Frame data processing method and device, equipment and storage medium

Abstract

The invention discloses a frame data processing method and device, equipment and a storage medium, belongs to the field of data processing, and is used for processing multiple paths of frame data with different rates. The method comprises the following steps: acquiring synchronous transmission module STM frame data sent by a plurality of first channels and byte writing numbers corresponding to the first channels; based on the byte write-in number, STM frame data sent by each first channel is written into the RAM to obtain a single write-in byte, and the single write-in byte is a byte written when the RAM performs a single write-in operation; reading a single write-in byte in the RAM through a preset configuration table, and determining whether the single write-in byte is frame header data of the STM frame data or not based on a preset frame header judgment rule; and if yes, respectively inputting the first bytes at each position in the single write-in bytes into the data processing channels corresponding to each position, so that the data processing channels process each first byte.

Description

Technical Field

[0001] This application belongs to the field of data processing, and specifically relates to a frame data processing method, apparatus, device and storage medium. Background Technology

[0002] The SDH frame structure is the core technical framework in the Synchronous Digital Hierarchy (SDH) system for realizing digital synchronous time-division multiplexing and ensuring reliable network operation. It carries information through a standardized frame format to meet the demands of high-speed, high-capacity transmission. SDH frames use STM-N as the basic unit, with each frame containing 9 lines × 270 × N bytes. Current technologies process multiple SDH frames at the same rate using a single circuit, which increases resource consumption.

[0003] Therefore, a frame data processing method is needed that can process multiple frames of different rates. Summary of the Invention

[0004] This application provides a frame data processing method that can process multiple frames of different rates.

[0005] In a first aspect, embodiments of this application provide a frame data processing method, the method comprising: acquiring STM frame data transmitted by a plurality of first channels and the number of bytes written corresponding to each first channel; each first channel transmitting the STM frame data according to its corresponding transmission rate; the number of bytes written is a preset number of bytes written in a single operation when writing STM frame data at different transmission rates into random access memory (RAM); based on the number of bytes written, writing the STM frame data transmitted by each first channel into the RAM to obtain a single-write byte, the single-write byte being the byte written when the RAM performs a single write operation; reading the single-write byte in the RAM through a preset configuration table, and determining whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule; if so, inputting the first byte at each position of the single-write byte into the data processing channel corresponding to each position, so that the data processing channel processes each first byte.

[0006] Secondly, embodiments of this application provide a frame data processing apparatus, comprising: a first acquisition module, configured to acquire STM frame data transmitted by multiple first channels and the number of bytes written corresponding to each first channel, wherein each first channel transmits the STM frame data according to its corresponding transmission rate, and the number of bytes written is a preset number of bytes written in a single operation when writing STM frame data at different transmission rates into random access memory (RAM); a first writing module, configured to write the STM frame data transmitted by each first channel into the RAM based on the number of bytes written, to obtain a single-write byte, wherein the single-write byte is the byte written when the RAM performs a single-write operation; a first reading module, configured to read the single-write byte in the RAM through a preset configuration table, and determine whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule; and a first processing module, configured to, when the single-write byte is the frame header data of the STM data, input the first byte at each position of the single-write byte to the data processing channel corresponding to each position, so that the data processing channel processes each first byte.

[0007] Thirdly, embodiments of this application provide an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method described in the first aspect.

[0008] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0009] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.

[0010] In this embodiment, the STM frame data transmitted by multiple first channels and the number of bytes written for each first channel are obtained. Based on the number of bytes written, the STM frame data transmitted by each first channel is written into RAM to obtain a single-write byte. The single-write byte is the byte written when RAM performs a single write operation. The single-write byte in RAM is read through a preset configuration table, and it is determined whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule. If so, the first byte at each position in the single-write byte is input to the data processing channel corresponding to each position, so that the data processing channel processes each first byte and can process multiple frames of different rates. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating a frame data processing method provided in an embodiment of this application; Figure 2 This is a schematic diagram of a RAM single-write byte structure provided in an embodiment of this application; Figure 3 This is a flowchart illustrating the second frame data processing method provided in the embodiments of this application; Figure 4 This is a flowchart illustrating the third frame data processing method provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of a frame data processing device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of a frame data processing device provided in an embodiment of this application. Detailed Implementation

[0012] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0013] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0014] The data processing provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings, through specific examples and application scenarios.

[0015] Figure 1 This illustration shows a frame data processing method provided by an embodiment of the present invention. The method can be executed by an electronic device, which may include a server and / or a terminal device, wherein the terminal device may be, for example, an in-vehicle terminal or a mobile phone terminal. In other words, the method can be executed by software or hardware installed on the frame data processing device, and the method includes the following steps: Step 102: Obtain the STM frame data of the synchronous transmission module sent by multiple first channels and the number of bytes written for each first channel.

[0016] Each of the first channels transmits the STM frame data according to its corresponding transmission rate, and the number of bytes written is a preset number of bytes written in a single operation when writing STM frame data at different transmission rates into the random access memory (RAM).

[0017] The execution entity of the frame data processing method described in this application can be a frame data processing system, frame data processing software, or other execution entities. This application embodiment will use a frame data processing system as an example for illustration.

[0018] The frame data processing system acquires the STM frame data sent by the synchronous transmission modules of multiple first channels and the number of bytes written corresponding to the first channel that sent the STM frame data. Each first channel sends STM frame data to the frame data processing system at its corresponding transmission rate, and the transmission rates corresponding to multiple first channels can be the same or different. The number of bytes written at one time is the number of bytes written to RAM at one time when the STM data is temporarily stored in RAM, which is pre-set.

[0019] Specifically, the structure of SDH frame data is represented by STM-N, such as STM-1, STM-10, etc. The transmission rate of STM data with different structures is different, and each type of STM data has a corresponding first channel for transmission. STM1 (i.e., STM-1) is the smallest unit in SDH frame data, consisting of 9 rows and 270 columns, totaling 2430 bytes. STM10 (i.e., STM-10) is obtained by interpolating 10 STM1 bytes. The transmission rate of STM1 is 155.52 Mbps, and the transmission rate of STM10 is 15.552 Mbps. Byte interpolation is a multiplexing technique that can multiplex multiple low-rate STM1 frame data into a higher-rate STM-N frame data. For example, 10 STM1 frame data can be multiplexed into one STM10 frame data. During the byte interpolation operation, the multiplexing is performed in a byte-interleaved manner, that is, the bytes of multiple STM1 frame data are inserted into the frame structure of the STM-N signal column by column in a certain order. For example, assuming there are 4 STM1 frame data, their bytes are aaaa, bbbb, cccc, and dddd, then the bytes obtained after byte interpolation are abcdabcdabcdabcd.

[0020] Data entering from the first channel needs to be written to the storage RAM first. The storage RAM has a fixed bit width, such as 8 bytes, so the maximum bit width for each storage operation is also fixed. The frame data processing system stores different numbers of bytes at a time when storing STM frame data at different transmission rates. For example, only 1 byte is stored at a time for STM1 frame data, 2 bytes for STM2 frame data, and 8 bytes for STM10 frame data. The reason for storing 8 bytes instead of 10 bytes for STM10 frame data is that the maximum number of bytes that the RAM can process at a time is 8, so 8 bytes need to be stored first, and then the remaining 2 bytes are stored.

[0021] Step 104: Based on the number of bytes written, write the STM frame data sent by each of the first channels into the RAM to obtain a single write byte.

[0022] The single write byte refers to the byte written during a single write operation of the RAM.

[0023] After determining the number of bytes to be written for each first channel, the frame data processing system writes the STM frame data sent by each first channel into RAM according to the corresponding number of bytes to be written, thereby obtaining the single-write bytes written to RAM in a single operation.

[0024] Specifically, data coming in from the high-speed port (i.e., the first channel) needs to be written to the RAM first. The RAM has a bit width of 8 bytes. The high-order address is the high-speed port chn_id[3:0] (a maximum of 16 STM1s are supported, requiring 16 high-order addresses), and the low-order address is accumulated each time data arrives from the corresponding high-speed port. If it is STM1 frame data, only the lowest byte is written, and the other 7 bytes are filled with 0. If it is STM10 frame data, 8 bytes are written the first time, 2 bytes are written the second time, and the other 6 bytes are filled with 0.

[0025] Step 106: Read the single-write byte in the RAM through the preset configuration table, and determine whether the single-write byte is the frame header data of the STM frame data based on the preset frame header judgment rule.

[0026] After storing the single-write byte in RAM, the frame data processing system will also read the single-write byte stored in RAM through a preset configuration table, and determine whether the obtained single-write byte is the frame header data of STM frame data based on the preset frame header judgment rules. The frame header data is used to characterize the starting position of STM frame data.

[0027] Specifically, the frame data processing system pre-establishes a configuration table. This table can have a depth of 16 addresses or 8 addresses; here, we'll use 16 addresses as an example. Each configured entry in the table represents a data read from the corresponding location in the RAM. The configuration table contains: chn_en: represents the enable for reading; chn_id[3:0]: represents which high-speed port's data needs to be read; stm_n[1:0]: the type of the currently read SDH frame, STM1 or STM10. One STM1 requires one entry, meaning a maximum of 16 STM1s are supported. One STM10 requires two entries, meaning a maximum of 8 STM10s are supported. In other words, 16 addresses are pre-configured through the pre-configuration table, and for any address, data can be read from RAM; each address can obtain a single byte of data written to RAM. For example, with a clock speed of 320MHz and a processing width of 8 bytes per clock cycle. At this point, the bandwidth of the entire system is 20G. With proper configuration, it can support a maximum of 16 STM1s or a maximum of 8 STM10s. For each additional STM10 frame, two STM1 frames will be reduced.

[0028] More specifically, when reading single-write bytes stored in RAM through the configuration table, it is necessary to ensure that the frequency at which the configuration table retrieves single-write bytes from RAM per unit time is greater than the frequency at which RAM stores single-write bytes. This ensures that single-byte data stored in RAM can be read normally during data processing. For example, with a clock speed of 320MHz and a total of 16 entries, if STM configures one entry and processes one byte at a time, the processing rate of this entry is 320MHz * 8 / 16 = 160MHz, which is greater than the rate of STM1 (155.52MHz).

[0029] After retrieving the single-write byte from RAM via the configuration table, the frame data processing system can determine whether the single-write byte is the frame header data of an STM frame based on a preset frame header judgment rule. This rule determines whether the retrieved single-write byte is the frame header of an STM frame. Specifically, it determines whether the retrieved single-write byte is a preset byte; if so, it identifies the single-write byte as frame header data. For example, the STM1 frame header consists of three fixed f6 bytes and three 28 bytes (i.e., f6f6f6282828). Therefore, when the frame data processing system detects that the single-write byte includes either an f6 byte or a 28 byte, it determines that the single-write byte includes either the preset f6 byte or 28 byte (i.e., it identifies the single-write byte as the frame header data of an STM frame).

[0030] Step 108: If so, the first byte at each position in the single-write byte is input to the data processing channel corresponding to each position, so that the data processing channel processes each first byte.

[0031] After determining that the single-write byte is the frame header data of the STM frame data, the frame data processing system can input the first byte of each position in the single-write byte into the data processing channel corresponding to each position, so that the data processing channel can process the first byte sent.

[0032] In other words, a single write byte can store a maximum of 8 bytes of information (i.e., 8 first bytes). Therefore, a single write byte can have 8 positions, and the frame data processing system sets up a data processing channel for each position. Thus, the frame data processing system can input the first byte of each position in a single write byte into the corresponding data processing channel.

[0033] Specifically, STM-N frame data is obtained by interpolating N STM-1 frame data into bytes. This method ensures that each byte of STM2 frame data comes from the corresponding byte of STM1 frame data. Therefore, the frame data processing system can acquire different numbers of bytes at a time for different STM-N frame data (e.g., 1 byte for STM1, 2 bytes for STM2, and 8 and 2 bytes for STM10 respectively). Different data processing channels are set for the first byte at different positions, so the first byte acquired at a time can be input into the corresponding data processing channel to complete the splitting operation of STM frame data. That is, it can split STM2 frame data into 2 STM1 frame data and STM10 frame data into 10 STM1 frame data, so that each data processing channel can process the split STM1 frame data.

[0034] The frame data processing provided in this embodiment of the invention obtains STM frame data transmitted by multiple first channels and the number of bytes written corresponding to each first channel; based on the number of bytes written, the STM frame data transmitted by each first channel is written into RAM to obtain single-write bytes, which are the bytes written when RAM performs a single write operation; the single-write bytes in RAM are read through a preset configuration table, and it is determined whether the single-write bytes are frame header data of STM frame data based on a preset frame header judgment rule; if so, the first byte at each position in the single-write bytes is input to the data processing channel corresponding to each position, so that the data processing channel processes each first byte, which can split the received STM frame data of different rates into STM frame data of a unified format (such as STM1 frame data), thereby processing multiple frames of different rates.

[0035] In one implementation, obtaining the STM frame data transmitted by multiple first channels (step 102) can be performed by step A: Step A: Obtain multiple first frame data, second frame data, third frame data, and fourth frame data sent by the first channel.

[0036] Wherein, the first frame data is the basic transmission data in the STM frame data, the second frame data is the frame data determined by byte interleaving multiplexing of four first frame data, the third frame data is the frame data determined by byte interleaving multiplexing of sixteen first frame data, and the fourth frame data is the frame data determined by byte interleaving multiplexing of sixty-four first frame data.

[0037] The frame data processing system acquires STM frame data at different rates through the first channel. Specifically, these can be first frame data, second frame data, third frame data, and fourth frame data. The first frame data is the basic transmission data in the STM frame data, i.e., STM1 frame data. The second frame data is the frame data determined by byte interleaving multiplexing of 4 first frame data, i.e., STM4 frame data. The third frame data is the frame data determined by byte interleaving multiplexing of 16 first frame data, i.e., STM16 frame data. The fourth frame data is the frame data determined by byte interleaving multiplexing of 64 frame data, i.e., STM64 frame data.

[0038] Specifically, the transmission rate of STM1 frame data is 155.52 Mbps, the transmission rate of STM4 frame data is four times that of STM1, i.e., 622.08 Mbps, the transmission rate of STM16 is sixteen times that of STM1, i.e., 2488.32 Mbps, and the transmission rate of STM64 is sixty-four times that of STM1 frame data, i.e., 9953.28 Mbps. Furthermore, based on the fact that the frame header of STM1 frame data is a fixed 6 bytes (f6f6f6282828), the frame header of STM4 is 12 f6 bytes plus 12 28-byte bytes; the frame header of STM16 is 48 f6 bytes plus 48 28-byte bytes; and the frame header of STM64 is 192 f6 bytes plus 192 28-byte bytes.

[0039] In one implementation, based on the number of bytes written, the STM frame data sent by each of the first channels is written into the RAM to obtain a single-write byte (step 104), and steps B1-B4 can be executed: Step B1: Write the first frame of data into the RAM to obtain the first single byte.

[0040] The RAM can process eight bytes, and the first single byte includes one byte.

[0041] RAM can store a maximum of 8 bytes at a time. Therefore, when processing STM frame data, a maximum of 8 bytes are stored. However, for STM frame data with different transmission rates, the frame data processing system can determine the number of bytes to write based on the specific transmission rate. Specifically, when the STM frame data is the first frame, i.e., STM1 frame data, the frame data processing system can write only the lowest byte, filling the other 7 bytes with 0s.

[0042] Step B2: Write the second frame data into the RAM to obtain the second single byte.

[0043] The second single byte consists of four bytes.

[0044] When the STM frame data is the second frame data, i.e. STM4 frame data, the frame data processing system can write only the lowest 4 bytes and fill the other 4 bytes with 0.

[0045] Step B3: Write the third frame of data into the RAM to obtain the third single byte.

[0046] The third single byte consists of eight bytes.

[0047] When the STM frame data is the third frame data, i.e. STM16 frame data, the frame data processing system can write all 8 bytes.

[0048] Step B4: Write the fourth frame of data into the RAM to obtain the fourth single byte.

[0049] The fourth single byte consists of eight bytes.

[0050] When the STM frame data is the fourth frame data, i.e. STM64 frame data, the frame data processing system can write all 8 bytes.

[0051] Specifically, when the first frame of data is STM1, the second frame is STM4, the third frame is STM16, and the fourth frame is STM64, taking a clock speed of 320MHz and a processing width of 8 bytes per clock cycle as an example, the bandwidth of the entire system is 20G. By appropriately configuring the configuration table (16 addresses deep) of the frame data processing system, it can support a maximum of 16 STM1 / STM4, a maximum of 8 STM16, or a maximum of 2 STM64. Mixed configurations are also supported; adding one STM16 reduces the configuration of 2 STM1 / STM4, and adding one STM64 reduces the configuration of 8 STM1 / STM4. The number of supported SDH frames can be changed by increasing the processing width or clock speed per clock cycle. Furthermore, for STM1, one entry is configured, using one byte at a time, resulting in 320m * 8 / 16 = 160m, which is greater than the STM1's speed of 155.52m. For STM4, one entry is configured, using four bytes at a time, resulting in 320m * 8 * 4 / 16 = 640m, which is greater than the STM4's speed of 622.08m. For STM16, two entries are configured, using eight bytes at a time, resulting in 320m * 8 * 8 * 2 / 16 = 2560m, which is greater than the STM16's speed of 2488.32m. For STM64, eight entries are configured, using eight bytes at a time, resulting in 320m * 8 * 8 * 8 / 16 = 10240m, which is greater than the STM64's speed of 9953.28m.

[0052] Figure 2 This is a schematic diagram of a single byte write structure for RAM provided in one embodiment of this specification, as shown below. Figure 2As shown, when the STM frame data is STM1 frame data, the RAM can acquire 1 byte of data each time as a single write byte. When the STM frame data is STM4 frame data, the RAM can acquire 4 bytes of data each time as a single write byte. When the STM frame data is STM16 or STM64, the RAM can acquire 8 bytes of data each time as a single write byte.

[0053] In one implementation, the step of reading the single-write byte from the RAM through a preset configuration table and determining whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule (step 106) can be executed via steps C1-C2: Step C1: Obtain the first and second write bytes in the RAM.

[0054] Wherein, the first written byte is data read from the RAM at a first time point, the second written byte is data read from the RAM at a second time point, and the second time point is the time point following the first time point.

[0055] When determining whether a single written byte is the frame header data of an STM frame, the frame data processing system can also obtain the first written byte and the second written byte in RAM, and determine whether the obtained written byte is the frame header data based on the first written byte and the second written byte. The first written byte is the data read from RAM at the first moment, and the second written byte is the data read from RAM at the second moment, and the second moment is the moment after the first moment.

[0056] In other words, the frame data processing system retrieves the write byte from RAM twice in a row, and determines the write byte read the first time as the first write byte and the write byte read the second time as the second write byte.

[0057] Step C2: When the first written byte and the second written byte include a preset frame header byte, determine that the first written byte and the second written byte are the frame header data.

[0058] After determining the first write byte and the second write byte, the frame data processing system can determine whether the first write byte and the second write byte include a preset frame header byte, and if the first write byte and the second write byte include the preset frame header byte, the system determines that the first write byte and the second write byte are frame header data.

[0059] Specifically, the number of frame header data (two bytes, f6 and 28) included in the STM frame data is multiple. Therefore, when determining whether a single write byte includes f6 or 28 bytes, it can only confirm the inclusion of frame header data; it cannot determine the position of the frame header data within its STM frame data. However, regardless of how many f6 or 28 bytes are included in the STM frame header data, two consecutive bytes, "f628", will always be generated between the f6 and 28 bytes. Therefore, the frame data processing system can read the single write byte twice consecutively and determine whether the single write byte includes the preset frame header bytes (e.g., two bytes, f6 and 28). If it determines that these two bytes are included, it identifies the first and second write bytes as frame header data.

[0060] In one implementation, the step of reading the single-write byte from the RAM through a preset configuration table and determining whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule (step 106) may also include steps D1-D8: Step D1: Continuously acquire a first number of the first single bytes, and determine whether there is a preset frame header byte in the first number of the first single bytes based on bit shifting operations.

[0061] Since the number of (f628) bytes in the frame header of STM frame data varies for different rates, and if each f6 and 28 byte of each STM16 or STM64 is detected and framed, the circuit would be more complex and would have higher requirements for circuit performance. Therefore, it is possible to perform unified detection on both bytes of f628.

[0062] Specifically, when the STM frame data is the first frame data, i.e., the STM1 frame data, the frame data processing system can continuously acquire a first number of first single bytes. This first number is a preset value, which can be 3 or 5. For example, the frame data processing system 1 reads 1 byte from the STM1 frame data each time and retains 3 consecutive times for a total of 3 bytes, i.e., STM1_merge[23:0] = {stm1_d3[7:0],stm1_d2[7:0],stm1_d1[7:0]}.

[0063] After acquiring the first number of first single bytes, the frame data processing system determines whether there is a preset frame header byte in the acquired first number of first single bytes based on bit shifting operations. The preset frame header byte can be f628.

[0064] Specifically, the frame data processor system compares each bit-shifted byte with f628. When f628 is detected, it transitions from the lost frame state to the predetermined frame state, that is, it determines the frame header data of the first frame data. Then, based on the data, it determines the starting data to be sent to the data processing channel so that the data processing channel can process the split and completed STM frame data.

[0065] For example, for STM1: stm1_merge[23:0] is split into eight 2-byte blocks, which are: stm1_tmp0[15:0]=stm1_merge[23:8]; stm1_tmp1[15:0]=stm1_merge[22:7]; stm1_tmp2[15:0]=stm1_merge[21:6; stm1_tmp3[15:0]=stm1_merge[20:5]; stm1_tmp4[15:0]=stm1_merge[19:4]; stm1_tmp5[15:0]=stm1_merge[18:3]; stm1_tmp6[15:0]=stm1_merge[17:2]; stm1_tmp7[15:0]=stm1_merge[16:1]; After determining the above 8 2-byte groups, the frame data processing system compares the above 8 groups of 2-byte groups with f628 to determine whether there is a frame header.

[0066] Step D2: If so, determine the frame header data based on the first number of the first single bytes.

[0067] After determining that a frame header byte exists among the multiple first single bytes obtained, the frame data processing system determines the frame header data based on the frame header byte in the first number of first single bytes, and then determines the starting data of the data to be sent, wherein the data to be sent is the data that needs to be sent to the data processing channel.

[0068] Specifically, after determining the starting data, the frame data processing system starts sending data to the data processing channel from the starting data, that is, sending the starting data and the data after the starting data, so that the data processing channel can process the completed STM frame data obtained by splitting. For example, if stm1_tmp0 matches f628, the data sent to the subsequent modules is the first 28 bytes of the three 28-byte sequences, that is, stm1_merge[16:8] is selected; if stm2_tmp0 matches f628, the data sent to the subsequent modules is all selected from stm1_merge[15:7].

[0069] Step D3: Continuously acquire a second number of the second single bytes, and determine whether there is a preset frame header byte in the second number of the second single bytes based on bit shifting operations.

[0070] Specifically, when the STM frame data is the second frame data, i.e., the STM4 frame data, the frame data processing system can continuously acquire a second number of second single bytes. This second number is a preset value, which can be 4 or 8 bytes. For example, the frame data processing system reads 4 bytes of STM4 frame data each time and needs to retain 3 consecutive times for a total of 12 bytes, i.e.: stm4_merge[95:0] ={stm4_d3[31:0], stm4_d2[31:0],stm4_d1[31:0]}.

[0071] After acquiring the second number of second single bytes, the frame data processing system determines whether a preset frame header byte exists in the acquired second number of second single bytes based on bit shifting operations. The frame header byte can be f628 bytes. Specifically, the frame data processing system compares each bit shifted byte with f628. When f628 is detected, it transitions from the lost frame state to the predetermined frame state, that is, it determines the frame header data of the second frame data. Then, based on the data, it determines the starting data to be sent to the data processing channel so that the data processing channel can process the split, completed STM frame data.

[0072] For example, for STM4: stm4_merge[95:0] is split into 32 2-byte blocks, which are: stm4_tmp0[15:0]=stm4_merge[95:80]; stm4_tmp1[15:0]=stm4_merge[94:79; ... stm4_tmp30[15:0]=stm4_merge[65:50]; stm4_tmp31[15:0]=stm4_merge[64:49].

[0073] After determining the initial 32 2-byte groups, the frame data processing system will compare these 32 groups of 2-byte groups with f628 to determine whether there is a frame header.

[0074] Step D4: If so, determine the frame header data based on the second number of the second single bytes.

[0075] After confirming the presence of a frame header byte among the acquired multiple second single bytes, the frame data processing system determines the frame header data, and then determines the starting data for the data to be sent. Specifically, after determining the starting data, the frame data processing system starts sending data to the data processing channel from the starting data, that is, sending the starting data and the data after the starting data, so that the data processing channel can process the completed STM frame data obtained by splitting. For example, if stm4_tmp0 matches f628, the data sent to the subsequent modules is initially the first 4 bytes of 28 bytes out of 12 bytes, that is, stm4_merge[87:56] is selected; if stm4_tmp1 matches f628, the data sent to the subsequent modules is stm4_merge[86:55]; if stm4_tmp31 matches f628, the data sent to the subsequent modules is stm4_merge[56:25].

[0076] Step D5: Continuously acquire the third number of the third single bytes, and determine whether there is a preset frame header byte in the third number of the third single bytes based on bit shifting operations.

[0077] Specifically, when the STM frame data is the third frame data, i.e., the STM16 frame data, the frame data processing system can continuously acquire the third number of single bytes, which is a preset value. For example, the frame data processing system acquires 8 bytes of STM16 frame data each time, and needs to retain 16 bytes in total from two consecutive acquisitions, i.e.: stm16_merge[191:0]={stm16_d3[63:0], stm16_d2[63:0],stm16_d1[63:0]}.

[0078] After acquiring the third single byte of the third number, the frame data processing system determines whether a preset frame header byte exists in the acquired third single byte based on bit shifting operations. Specifically, the frame data processing system compares each bit shifted byte with f628. When f628 is detected, it transitions from the lost frame state to the predetermined frame state, that is, it determines the frame header data of the third frame data. Then, based on the data, it determines the starting data to be sent to the data processing channel so that the data processing channel can process the split and completed STM frame data.

[0079] For example, for STM16: stm16_merge[191:0] is split into 64 2-byte blocks, which are: stm16_tmp0[15:0]=stm16_merge[191:176]; stm16_tmp1[15:0]=stm16_merge[190:175]; ... stm16_tmp63[15:0]=stm16_merge[128:113].

[0080] Step D6: If so, determine the frame header data based on the third number of the third single bytes.

[0081] After confirming the presence of a frame header byte among the acquired third single bytes, the frame data processing system determines the frame header data, and then determines the starting data to be sent. Specifically, after determining the starting data, the frame data processing system starts sending data to the data processing channel from the starting data, that is, sending the starting data and the data after the starting data, so that the data processing channel can process the split and completed STM frame data. For example, if stm16_tmp0 matches f628, the data sent to the subsequent modules is the first 8 bytes of the 28 bytes, that is, stm16_merge[183:120] is selected; if stm16_tmp1 matches f628, the data sent to the subsequent modules is stm16_merge[182:119]; if stm16_tmp63 matches f628, the data sent to the subsequent modules is stm16_merge[120:57].

[0082] Step D7: Continuously acquire the fourth number of the fourth single bytes, and determine whether there is a preset frame header byte in the fourth number of the fourth single bytes based on bit shifting operations.

[0083] Specifically, when the STM frame data is the fourth frame data, i.e., the STM64 frame data, the frame data processing system can obtain the fourth single byte of the fourth number, which is a preset value. For example, the frame data processing system obtains 8 bytes of STM64 frame data each time, and needs to retain 16 bytes in total from two consecutive times, i.e.: stm64_merge[191:0]={stm64_d3[63:0], stm64_d2[63:0],stm64_d1[63:0]}.

[0084] After acquiring the fourth single byte of the fourth number, the frame data processing system determines whether a preset frame header byte exists in the acquired fourth single byte based on bit shifting operations. Specifically, the frame data processing system compares each bit shifted byte with f628. When f628 is detected, it transitions from the lost frame state to the predetermined frame state, that is, it determines the frame header data of the fourth frame data. Then, based on the data, it determines the starting data to be sent to the data processing channel so that the data processing channel can process the split and completed STM frame data.

[0085] For example, for STM64 frame data: stm64_merge[191:0] is split into 64 2-byte blocks, which are: stm64_tmp0[15:0]=stm16_64_merge[191:176]; stm64_tmp1[15:0]=stm16_64_merge[190:175]; ... stm16_64_tmp63[15:0]=stm16_64_merge[128:113].

[0086] Step D8: If so, determine the frame header data based on the fourth single byte of the fourth number.

[0087] After confirming the presence of a frame header byte among the acquired multiple fourth single bytes, the frame data processing system determines the frame header data, and then determines the starting data to be sent. Specifically, after determining the starting data, the frame data processing system starts sending data to the data processing channel from the starting data, that is, sending the starting data and the data after the starting data, so that the data processing channel can process the split and completed STM frame data. For example, if stm64_tmp0 matches f628, the data sent to the subsequent modules is the first 8 bytes of the 28 bytes, that is, stm64_merge[183:120] is selected; if stm64_tmp1 matches f628, the data sent to the subsequent modules is stm64_merge[182:119]; if stm64_tmp63 matches f628, the data sent to the subsequent modules is stm64_merge[120:57].

[0088] Figure 3 This is a flowchart illustrating a second frame data processing method provided in an embodiment of this specification, as shown below. Figure 3 As shown, the schematic diagram includes: Step 302: Obtain multiple first frame data, second frame data, third frame data and fourth frame data sent by the first channel.

[0089] Wherein, the first frame data is the basic transmission data in the STM frame data, the second frame data is the frame data determined by byte interleaving multiplexing of four first frame data, the third frame data is the frame data determined by byte interleaving multiplexing of sixteen first frame data, and the fourth frame data is the frame data determined by byte interleaving multiplexing of sixty-four first frame data.

[0090] Step 304: Write the first frame data into the RAM to obtain the first single byte.

[0091] The RAM can process eight bytes, and the first single byte includes one byte.

[0092] Step 306: Write the second frame data into the RAM to obtain the second single byte.

[0093] The second single byte consists of four bytes.

[0094] Step 308: Write the third frame of data into the RAM to obtain the third single byte.

[0095] The third single byte consists of eight bytes.

[0096] Step 310: Write the fourth frame of data into the RAM to obtain the fourth single byte.

[0097] The fourth single byte consists of eight bytes.

[0098] Step 312: Continuously acquire a first number of the first single bytes, and determine whether there is a preset frame header byte in the first number of the first single bytes based on bit shifting operations.

[0099] Step 314: If so, determine the frame header data based on the first number of the first single bytes.

[0100] Step 316: Continuously acquire a second number of the second single bytes, and determine whether there is a preset frame header byte in the second number of the second single bytes based on bit shifting operations.

[0101] Step 318: If so, determine the frame header data based on the second number of second single bytes.

[0102] Step 320: Continuously acquire a third number of the third single bytes, and determine whether there is a preset frame header byte in the third number of the third single bytes based on bit shifting operations.

[0103] Step 322: If so, determine the frame header data based on the third number of the third single bytes.

[0104] Step 324: Continuously acquire the fourth number of the fourth single bytes, and determine whether there is a preset frame header byte in the fourth number of the fourth single bytes based on bit shifting operations.

[0105] Step 326: If so, determine the frame header data based on the fourth number of the fourth single byte.

[0106] Step 328: Determine the reassembled frame data corresponding to each position in the RAM based on the frame header data.

[0107] Step 330: Input the recombined frame data into the data processing channel corresponding to each position, so that the data processing channel processes each of the first bytes.

[0108] In the embodiments described in the specification, STM frame data with different transmission rates are written into RAM according to their corresponding writing methods and then read. The read data is then input into the corresponding data processing channels according to their positions. This allows STM frame data with different transmission rates (such as STM4 frame data, STM16 frame data, and STM64 frame data) to be split into STM1 frame data for processing. Thus, multiple channels of multi-rate STM frame data can be processed simultaneously through a single circuit.

[0109] In one implementation, the step of inputting the first byte at each position in the single-write byte to the data processing channel corresponding to each position, so that the data processing channel processes each first byte (step 108), can execute steps E1-E2: Step E1: Determine the fifth number corresponding to the single write byte based on the data type of the single write byte.

[0110] Wherein, the data type is one of the first frame data, the second frame data, the third frame data, and the fourth frame data, and the fifth number is the number of times that the STM data of the data type to which the single-write byte belongs needs to be stored through the RAM.

[0111] The frame data processing system determines the corresponding fifth number based on the data type of the bytes written in a single operation. The data type is one of the first frame data, the second frame data, the third frame data, and the fourth frame data. The fifth number is the number of times that STM frame data of this data type needs to be stored.

[0112] Before sending the first byte to the data processing channel, the frame data processing system can perform a framing operation on the first byte to ensure that the multiple consecutively sent first bytes are complete data. Therefore, the frame data processing system can first determine the number of times STM frame data of different data types needs to be sent to the data processing channel. For example, STM1 frame data has 2430 bytes, so it can continuously send 2430 bytes to the data processing channel, thereby sending the complete STM1 frame data to the data processing channel.

[0113] Different types of STM frame data have different byte counts; therefore, the number of times the frame data processing system sends the first byte to the data processing channel will vary depending on the STM frame data type. The frame data processing channel can determine the number of times it needs to send the complete STM frame data to the data processing channel, i.e., the fifth time, based on the data type of the first byte to be sent.

[0114] Step E2: Based on the fifth number, the first byte at the same position is acquired to determine the recombined frame data, and the recombined frame data is input into the data processing channel so that the data processing channel processes the recombined frame data.

[0115] After determining the fifth number, the frame data processing system can retrieve the first byte at the same position in a single write byte sequence using a configuration table, thereby identifying the complete split STM frame data, i.e., the reassembled frame data. The frame data processing system can then send the complete reassembled frame data to the corresponding data processing channel for processing.

[0116] Specifically, the frame data processing system can be configured with a frame fixing module. This module has a status indicator, which has three states: lost frame, pre-defined frame, and fixed frame, along with a frame counter cnt_frame[2:0]. Initially, the frame fixing module is in the lost frame state, and cnt_frame is 0 when in the lost frame state. In the pre-defined frame state, if a new frame indication is received from the verification module, the value is incremented by 1. The increment remains unchanged after reaching a maximum of 7. This value also remains unchanged in the fixed frame state. In the lost frame state, if the frame fixing module detects f628, the status indicator changes from lost frame to pre-defined frame state. In the pre-defined frame state, if cnt_frame is greater than or equal to 4 and the frame state of the verification module is NORM, the module enters the fixed frame state. In the fixed frame state, if the frame state of the verification module is LOF, the module enters the lost frame state.

[0117] In one implementation, steps F1-F3 can also be performed: Step F1: Number the first byte and determine the first number of the first byte.

[0118] After determining the first byte corresponding to each data processing channel, the frame data processing system can number the first byte that needs to be sent to the data processing channel and determine the first number of each first byte.

[0119] Step F2: When the first number is the first value, determine whether the first byte is a preset byte.

[0120] After determining the first number corresponding to each first byte, the frame data processing system determines whether the first byte corresponding to the first number of the first value is a preset byte when the first number is a first value. In other words, STM frame data has a fixed structure, and at certain fixed positions (i.e., the first number of the first value), it is a fixed byte (i.e., a preset byte). Therefore, the frame data processing system can detect whether the actual byte at the fixed position (i.e., the first number of the first value) that should theoretically be a fixed byte (i.e., a preset byte) is a preset byte.

[0121] Specifically, the position of the fixed byte varies across different types of STM frame data, but all types of STM frame data contain a fixed byte, only their positions differ. The frame data processing system can pre-set a counter cnt, and then use the counter cnt to number the first byte, thereby determining whether the first byte corresponding to the first number of the first value is the preset byte.

[0122] Step F3: If yes, then determine that the first byte is in normal transmission state.

[0123] After determining that the first byte at the first number of the first value is a preset byte, the frame data processing system can determine that the first byte is in normal transmission status; when the first byte at the first number of the first value is not a preset byte, the frame data processing system can determine that the first byte is transmitted incorrectly.

[0124] Specifically, the STM1 frame data consists of 9 x 270 = 2430 bytes, with 1 byte transmitted each time. The cnt count ranges from 0 to 2429, and is set to 3 when the frame header is indicated (the frame header is the first 28 bytes, preceded by 3 f6s). When cnt is 0-2, it checks if each input data is an f6; when cnt is 3-5, it checks if each input data is a 28. If both conditions are met, the frame status is indicated as normal (i.e., normal transmission status); otherwise, it is indicated as lof (i.e., a transmission error has occurred). The frame status only changes when cnt is 5, remaining unchanged at other times. The STM4 frame data consists of 9 x 270 x 4 = 9720 bytes, with 4 bytes transmitted each time. The cnt count ranges from 0 to 2429, and is set to 3 when the frame header is indicated (the frame header is the first 28 bytes, preceded by 12 f6s). When cnt is 0-11, it checks if each input data is f6; when cnt is 12-23, it checks if each input data is 28. If both conditions are met, the frame status is indicated as normal (i.e., normal transmission state); otherwise, it is indicated as lof (i.e., a transmission error has occurred). The frame status only changes when cnt is 23; otherwise, it remains unchanged. The STM16 frame data consists of a total of 9 x 270 x 16 = 38880 bytes, with 8 bytes transmitted each time. The cnt count ranges from 0 to 4859, and is set to 6 during frame header indication (the frame header is the first 28 bytes, preceded by 48 f6 bytes). When cnt is 0-47, it checks if each input data is f6; when cnt is 48-95, it checks if each input data is 28. If both conditions are met, the frame status is indicated as normal (i.e., normal transmission state); otherwise, it is indicated as lof (i.e., a transmission error has occurred). The frame status only changes when cnt is 95; otherwise, it remains unchanged. The STM64 frame data consists of a total of 9 x 270 x 64 = 155520 bytes, with 8 bytes transmitted each time. The cnt counter ranges from 0 to 19439, and is set to 24 during frame header indication (the frame header is the first 28 bytes, preceded by 192 f6s). When cnt is 0-191, it checks if each input data is an f6; when cnt is 192-383, it checks if each input data is a 28. If both conditions are met, the frame status is indicated as normal (i.e., normal transmission status); otherwise, it is indicated as lof (i.e., a transmission error has occurred). The frame status only changes when cnt is 383; otherwise, it remains unchanged.

[0125] Figure 4 This is a flowchart illustrating a third frame data processing method provided in an embodiment of this specification, as shown below. Figure 4 As shown, the schematic diagram includes: Step 402: Obtain the STM frame data of the synchronous transmission module sent by multiple first channels and the number of bytes written for each first channel.

[0126] Each of the first channels transmits the STM frame data according to its corresponding transmission rate, and the number of bytes written is a preset number of bytes written in a single operation when writing STM frame data at different transmission rates into the random access memory (RAM).

[0127] Step 404: Based on the number of bytes written, write the STM frame data sent by each of the first channels into the RAM to obtain a single write byte.

[0128] The single write byte refers to the byte written during a single write operation of the RAM.

[0129] Step 406: Read the single-write byte in the RAM through the preset configuration table, and determine whether the single-write byte is the frame header data of the STM frame data based on the preset frame header judgment rule.

[0130] Step 408: If so, the first byte at each position in the single-write byte is input to the data processing channel corresponding to each position, so that the data processing channel processes each first byte.

[0131] Step 410: Number the first byte and determine the first number of the first byte.

[0132] Step 412: When the first number is the first value, determine whether the first byte is a preset byte.

[0133] Step 414: If yes, then determine that the first byte is in normal transmission state.

[0134] In the embodiments described in the specification, by numbering the first byte sent to each data processing channel, and determining whether the first byte with the first number is a preset byte when the first number is a first value, it is possible to determine whether the first byte is in a normal transmission state. This enables monitoring of data during data transmission, thereby ensuring normal data transmission.

[0135] It should be noted that the frame data processing method provided in this application embodiment can be executed by a frame data processing device or a control module within that frame data processing device for executing the frame data processing method. This application embodiment uses the execution of the frame data processing method by a frame data processing device as an example to illustrate the frame data processing device provided in this application embodiment.

[0136] Figure 5 This is a schematic diagram of the structure of a frame data processing apparatus according to an embodiment of the present invention. Figure 5 As shown, the frame data processing device includes: a first acquisition module 502, a first writing module 504, a first reading module 506, and a first processing module 508.

[0137] The first acquisition module 502 is used to acquire the synchronous transmission module STM frame data sent by multiple first channels and the number of bytes written corresponding to each first channel. Each first channel sends the STM frame data according to its corresponding transmission rate. The number of bytes written is a preset number of bytes written in a single write when writing the STM frame data at different transmission rates into the random access memory RAM. The first writing module 504 is used to write the STM frame data sent by each of the first channels into the RAM based on the number of bytes written, to obtain a single write byte, wherein the single write byte is the byte written when the RAM performs a single write operation. The first reading module 506 is used to read the single-write byte in the RAM through a preset configuration table, and determine whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule. The first processing module 508 is configured to, when the frame header data of the single-write byte is the STM data, input the first byte of each position in the single-write byte to the data processing channel corresponding to each position, so that the data processing channel processes each first byte.

[0138] The frame data processing device in this application embodiment can be a device, or a component, integrated circuit, or chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. For example, mobile electronic devices can be mobile phones, tablets, laptops, PDAs, in-vehicle electronic devices, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc., while non-mobile electronic devices can be servers, network attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. This application embodiment does not impose specific limitations.

[0139] The frame data processing device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0140] The frame data processing device provided in this application embodiment can achieve... Figures 1 to 4The various processes implemented in the method embodiments are not described in detail here to avoid repetition.

[0141] Based on the same technical concept, embodiments of this application also provide an electronic device for performing the above-described frame data processing method. Figure 6 This is a schematic diagram of the structure of an electronic device to implement various embodiments of this application. The electronic device can vary significantly due to differences in configuration or performance, and may include a processor 602, a communications interface 604, a memory 606, and a communication bus 608. The processor 602, communications interface 604, and memory 606 communicate with each other via the communication bus 608. The processor 602 can call a computer program stored in the memory 606 and executable on the processor 602 to perform the following steps: The synchronous transmission module STM frame data sent by multiple first channels and the number of bytes written for each first channel are obtained. Each first channel sends the STM frame data according to its corresponding transmission rate. The number of bytes written is a preset number of bytes written in a single write when writing the STM frame data at different transmission rates into the random access memory RAM. Based on the number of bytes written, the STM frame data sent by each of the first channels is written into the RAM to obtain a single write byte, wherein the single write byte is the byte written when the RAM performs a single write operation; The single-write byte is read from the RAM by a preset configuration table, and it is determined whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule. If so, the first byte at each position in the single-write byte is input to the data processing channel corresponding to each position, so that the data processing channel processes each first byte.

[0142] In one implementation, acquiring the STM frame data transmitted by the multiple first channels includes: Acquire multiple first frame data, second frame data, third frame data, and fourth frame data sent by the first channel. The first frame data is the basic transmission data in the STM frame data. The second frame data is the frame data determined by byte interleaving multiplexing of four first frame data. The third frame data is the frame data determined by byte interleaving multiplexing of sixteen first frame data. The fourth frame data is the frame data determined by byte interleaving multiplexing of sixty-four first frame data.

[0143] In one implementation, the step of writing the STM frame data transmitted by each of the first channels into the RAM based on the number of bytes written, to obtain a single write byte, includes: The first frame of data is written into the RAM to obtain the first single byte. The RAM can process eight bytes, and the first single byte includes one byte. The second frame of data is written into the RAM to obtain a second single byte, which consists of four bytes. The third frame of data is written into the RAM to obtain a third single byte, which includes eight bytes. The fourth frame of data is written into the RAM to obtain the fourth single byte, which consists of eight bytes.

[0144] In one implementation, the step of reading the single-write byte from the RAM through a preset configuration table and determining whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule includes: Obtain the first write byte and the second write byte from the RAM, wherein the first write byte is data read from the RAM at a first time moment, and the second write byte is data read from the RAM at a second time moment, wherein the second time moment is the time moment following the first time moment; When the first written byte and the second written byte include a preset frame header byte, the first written byte and the second written byte are determined to be the frame header data.

[0145] In one implementation, the step of reading the single-write byte from the RAM through a preset configuration table and determining whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule includes: A first number of the first single bytes are continuously acquired, and a preset frame header byte is determined based on bit shifting operations. If so, the frame header data is determined based on the first number of the first single bytes; A second number of the second single bytes are continuously acquired, and a preset frame header byte is determined based on bit shifting operations. If so, the frame header data is determined based on the second number of the second single bytes; A third number of the third single bytes are continuously acquired, and a preset frame header byte is determined based on bit shifting operations. If so, the frame header data is determined based on the third number of the third single bytes; The fourth number of fourth single bytes are continuously acquired, and a preset frame header byte is determined based on bit shifting operations. If so, the frame header data is determined based on the fourth single byte of the fourth number.

[0146] In one implementation, the step of inputting the first byte at each position in the single-write byte to the data processing channel corresponding to each position, so that the data processing channel processes each first byte, includes: The fifth number corresponding to the single write byte is determined based on the data type of the single write byte. The data type is one of the first frame data, the second frame data, the third frame data, and the fourth frame data. The fifth number is the number of times the STM data of the data type to which the single write byte belongs needs to be stored through the RAM. Based on the fifth number, the first byte at the same position is acquired to determine the recombined frame data, and the recombined frame data is input into the data processing channel so that the data processing channel processes the recombined frame data.

[0147] In one implementation, the method further includes: The first byte is numbered, and the first number of the first byte is determined; When the first number is a first value, determine whether the first byte is a preset byte; If so, then the first byte is determined to be in a normal transmission state.

[0148] The specific execution steps can be found in the various steps of the above-described frame data processing method embodiments, and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0149] It should be noted that the electronic devices in the embodiments of this application include: servers, terminals, or other devices besides terminals.

[0150] The above electronic device structure does not constitute a limitation on the electronic device. An electronic device may include more or fewer components than illustrated, or combine certain components, or arrange them differently. For example, an input unit may include a Graphics Processing Unit (GPU) and a microphone, and a display unit may use a liquid crystal display (LCD), organic light-emitting diode (OLED), or other similar display panels. User input units include at least one of a touch panel and other input devices. A touch panel is also called a touchscreen. Other input devices may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be elaborated further here.

[0151] Memory can be used to store software programs and various data. Memory can primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area can store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, memory can include volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (Synchlink DRAM, SLDRAM), and direct memory bus RAM (DRRAM).

[0152] The processor may include one or more processing units; optionally, the processor integrates an application processor and a modem processor, wherein the application processor mainly handles operations related to the operating system, user interface, and applications, while the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into the processor.

[0153] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described frame data processing method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0154] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0155] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described frame data processing method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0156] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0157] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0158] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0159] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A frame data processing method, characterized in that, include: The synchronous transmission module STM frame data sent by multiple first channels and the number of bytes written for each first channel are obtained. Each first channel sends the STM frame data according to its corresponding transmission rate. The number of bytes written is a preset number of bytes written in a single write when writing the STM frame data at different transmission rates into the random access memory RAM. Based on the number of bytes written, the STM frame data sent by each of the first channels is written into the RAM to obtain a single write byte, wherein the single write byte is the byte written when the RAM performs a single write operation; The single-write byte is read from the RAM by a preset configuration table, and it is determined whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule. If so, the first byte at each position in the single-write byte is input to the data processing channel corresponding to each position, so that the data processing channel processes each first byte.

2. The method according to claim 1, characterized in that, The acquisition of STM frame data from multiple first channels includes: Acquire multiple first frame data, second frame data, third frame data, and fourth frame data sent by the first channel. The first frame data is the basic transmission data in the STM frame data. The second frame data is the frame data determined by byte interleaving multiplexing of four first frame data. The third frame data is the frame data determined by byte interleaving multiplexing of sixteen first frame data. The fourth frame data is the frame data determined by byte interleaving multiplexing of sixty-four first frame data.

3. The method according to claim 2, characterized in that, The step of writing the STM frame data sent by each of the first channels into the RAM based on the number of bytes written, to obtain a single write byte, includes: The first frame of data is written into the RAM to obtain the first single byte. The RAM can process eight bytes, and the first single byte includes one byte. The second frame of data is written into the RAM to obtain a second single byte, which includes four bytes. The third frame of data is written into the RAM to obtain a third single byte, which includes eight bytes. The fourth frame of data is written into the RAM to obtain the fourth single byte, which consists of eight bytes.

4. The method according to claim 1, characterized in that, The step of reading the single-write byte from the RAM through a preset configuration table and determining whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule includes: Obtain the first write byte and the second write byte from the RAM, wherein the first write byte is data read from the RAM at a first time moment, and the second write byte is data read from the RAM at a second time moment, wherein the second time moment is the time moment following the first time moment; When the first written byte and the second written byte include a preset frame header byte, the first written byte and the second written byte are determined to be the frame header data.

5. The method according to claim 3, characterized in that, The step of reading the single-write byte from the RAM through a preset configuration table and determining whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule includes: A first number of the first single bytes are continuously acquired, and a preset frame header byte is determined based on bit shifting operations. If so, the frame header data is determined based on the first number of the first single bytes; A second number of the second single bytes are continuously acquired, and a preset frame header byte is determined based on bit shifting operations. If so, the frame header data is determined based on the second number of the second single bytes; A third number of the third single bytes are continuously acquired, and a preset frame header byte is determined based on bit shifting operations. If so, the frame header data is determined based on the third number of the third single bytes; The fourth number of fourth single bytes are continuously acquired, and a preset frame header byte is determined based on bit shifting operations. If so, the frame header data is determined based on the fourth single byte of the fourth number.

6. The method according to claim 3, characterized in that, The step of inputting the first byte at each position in the single-write byte sequence to the data processing channel corresponding to each position, so that the data processing channel processes each first byte, includes: The fifth number corresponding to the single write byte is determined based on the data type of the single write byte. The data type is one of the first frame data, the second frame data, the third frame data, and the fourth frame data. The fifth number is the number of times the STM data of the data type to which the single write byte belongs needs to be stored through the RAM. Based on the fifth number, the first byte at the same position is acquired to determine the recombined frame data, and the recombined frame data is input into the data processing channel so that the data processing channel processes the recombined frame data.

7. The method according to claim 1, characterized in that, The method further includes: The first byte is numbered, and the first number of the first byte is determined; When the first number is a first value, determine whether the first byte is a preset byte; If so, then the first byte is determined to be in a normal transmission state.

8. A frame data processing apparatus, characterized in that, include: The first acquisition module is used to acquire the synchronous transmission module STM frame data sent by multiple first channels and the number of bytes written corresponding to each first channel. Each first channel sends the STM frame data according to its corresponding transmission rate. The number of bytes written is a preset number of bytes written in a single write when writing the STM frame data at different transmission rates into the random access memory RAM. The first write module is used to write the STM frame data sent by each of the first channels into the RAM based on the number of bytes written, to obtain a single write byte, wherein the single write byte is the byte written when the RAM performs a single write operation; The first reading module is used to read the single-write byte in the RAM through a preset configuration table, and determine whether the single-write byte is the frame header data of the STM frame data based on a preset frame header judgment rule. The first processing module is configured to, when the frame header data of the single-write byte is the STM data, input the first byte of each position in the single-write byte to the data processing channel corresponding to each position, so that the data processing channel processes each first byte.

9. A computer device, characterized in that, The device includes: Processor; and A memory configured to store computer-executable instructions configured to be executed by the processor, the executable instructions including steps for performing the method as described in any one of claims 1 to 7.

10. A storage medium, characterized in that, The storage medium is used to store computer-executable instructions that cause the computer to perform the method as described in any one of claims 1 to 7.

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