Patterned etching method
By employing a dual-layer SOC structure and adding an LTO layer as a protective layer in TiN patterning etching, the problem of difficult removal of Ti+/Ta+ residues was solved, achieving efficient etching results and improving product yield.
Patent Information
- Application Number
- CN202511066241.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-11-11
AI Technical Summary
Existing technologies have extremely small residual defects in the TiN patterning etching process, especially in the Barc open process, where Ti+/Ta+ adheres to or enters the photoresist and carbon coating, which is difficult to completely remove by existing methods.
A dual-layer SOC structure is adopted, with an LTO layer added in the middle as a protective layer. Stepwise plasma etching and wet etching processes are used to prevent residues from entering the SOC layer. Finally, DHF is used to remove the LTO layer to remove residues.
This effectively avoids defects caused by extremely small residues, improves product yield, and ensures the quality of patterned etching of the TiN layer.
Smart Images
Figure CN120933158A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a patterned etching method. Background Technology
[0002] In some processes, TiN needs to be patterned and etched. The patterning etching of TiN usually uses a double-layer photolithography process with carbon coating (SOC) and photoresist (PR). The opening process of the double-layer photolithography process is also called the bottom anti-reflective coating (Barc) opening process. In some process nodes, serious tiny residue problems have been found in the development of the barc opening process. The residue mainly occurs in the area where the barc is not opened. During the opening of the barc, the etching plasma bombards the TiN and TaN or high dielectric constant (HK) layer exposed in the opened area. This causes the generated Ti+ / Ta+ to adhere to or enter the PR / SOC. Subsequent processes cannot completely remove the SOC containing Ti+ / Ta+, forming serious residual defects.
[0003] In some processes, TiN needs to be patterned and etched. The patterning etching of TiN usually uses a double-layer photolithography process with carbon coating (SOC) and photoresist (PR). The opening process of the double-layer photolithography process is also called the bottom anti-reflective coating (Barc) opening process. In some process nodes, serious tiny residue problems have been found in the development of the barc opening process. The residue mainly occurs in the area where the barc is not opened. During the opening of the barc, the etching plasma bombards the TiN and TaN or high dielectric constant (HK) layer exposed in the opened area. This causes the generated Ti+ / Ta+ to adhere to or enter the PR / SOC. Subsequent processes cannot completely remove the SOC containing Ti+ / Ta+, forming serious residual defects.
[0004] The following is combined with Figures 1A to 1E Further explanation of existing patterning etching methods: Existing patterning etching methods include the following steps: like Figure 1A As shown, a TiN layer 104 is formed on the underlying structure 101.
[0005] Typically, the TiN layer 104 serves as the P-type work function layer of a PMOS.
[0006] A first TaN layer and a high dielectric constant layer are also formed at the bottom of the TiN layer 104.
[0007] The underlying structure 101 includes a semiconductor substrate. Semiconductor protrusions 102 are formed on the semiconductor substrate, and shallow trench isolation 103 is formed in the bottom region of the spacing area between the semiconductor protrusions 102. A portion of the semiconductor protrusions 102 is truncated and the truncated region is filled with a dielectric layer.
[0008] A coating process is performed to form the SOC layer 105.
[0009] Coating with photoresist 106.
[0010] like Figure 1B As shown, exposure is performed to open the first region, which is the area of the TiN layer 104 that needs to be removed. Typically, the first region is the formation region of the NMOS. The exposure process corresponds to PMG-PH, i.e., photolithography of a P-type metal gate.
[0011] like Figure 1C As shown, a plasma etching process is performed to remove the SOC layer 105 in the first region. This step corresponds to a Barc open.
[0012] In the plasma etching process, the photoresist 106 outside the first region will be partially consumed.
[0013] In the plasma etching process, after the TiN layer 104 is exposed, the plasma bombards the TiN layer 104, thus causing Ti ions to be deposited. + They will be bombarded out; similarly, the Ta ions in the Ta layer at the bottom of the TiN layer 104, i.e., Ta... + It will also be bombarded out, eventually forming a residue 107 containing Ti ions and Ta ions.
[0014] like Figure 1D As shown, the TiN layer 104 in the first region is removed (RM) using the SOC layer 105 as a mask. This step is called TiN RM. Typically, the TiN layer 104 is removed using SC2 cleaning solution, which is the standard No. 2 solution.
[0015] like Figure 1E As shown, the SOC layer 105 is removed, a step corresponding to Barc RM.
[0016] Typically, the SOC layer 105 is removed using an ashing process followed by a wet etching process. However, due to... Figure 1E As shown, outside the first region, after the process steps of removing the SOC layer 105 are completed, the residue 107 cannot be easily removed.
[0017] Adjusting the ashing and wet etching processes or repeating the ashing and wet etching processes twice still fails to remove the residue 107. Therefore, the existing method cannot eliminate the residue 107 by removing the SOC layer 105. Summary of the Invention
[0018] The technical problem to be solved by the present invention is to provide a patterned etching method that can avoid the formation of extremely small residual defects.
[0019] To solve the above-mentioned technical problems, the patterned etching method provided by the present invention includes the following steps: A first process layer is formed on the underlying structure, and the first process layer is the target layer for patterned etching.
[0020] The first SOC layer is coated to form the first SOC layer.
[0021] An LTO layer is grown on the surface of the first SOC layer, the LTO layer having a first thickness.
[0022] A second SOC layer is applied to form a second SOC layer on the surface of the LTO layer.
[0023] The first region is opened by applying photoresist and exposing it. The first region is the area of the first process layer that needs to be removed.
[0024] The first plasma etching process removes the second SOC layer in the first region and stops the etching on the LTO layer.
[0025] A second plasma etching process is performed to remove the LTO layer in the first region. After the LTO layer is removed, all the photoresist outside the first region is consumed, and part of the second SOC layer outside the first region is consumed.
[0026] A third plasma etching process is performed to remove the first SOC layer in the first region. After the third plasma etching process is completed, the second SOC layer outside the first region is completely consumed. The first thickness ensures that the LTO layer remains after the third plasma etching process. The third plasma etching process will generate plasma bombardment on the first process layer and form residues. Outside the first region, the LTO layer prevents the residues from entering the first SOC layer and keeps the residues on the surface of the LTO layer.
[0027] The LTO layer was removed using DHF to completely eliminate the residue.
[0028] The first process layer in the first region is removed using the first SOC layer as a mask.
[0029] Remove the first SOC layer.
[0030] A further improvement is that the material of the first process layer includes TiN.
[0031] A further improvement is that the first process layer serves as the P-type work function layer of the PMOS.
[0032] A further improvement is that the underlying structure completes the process of removing the pseudo-gate structure and forms a gate trench in the pseudo-gate structure removal area.
[0033] A further improvement is that the first SOC layer ensures that the gate trench is completely filled.
[0034] A further improvement is that a first TaN layer is formed at the bottom of the first process layer, and the first TaN layer is formed after the gate trench is formed.
[0035] A further improvement is that a high dielectric constant layer is formed at the bottom of the first TaN layer.
[0036] A further improvement is that the underlying structure further includes a semiconductor substrate, on which the high dielectric constant layer is formed; the high dielectric constant layer is formed before the dummy gate structure is removed.
[0037] A further improvement is to use a wet etching process to remove the TiN from the first process layer.
[0038] A further improvement is that the etching solution for removing the TiN from the first process layer includes SC2 cleaning solution.
[0039] A further improvement is to remove the first SOC layer using an ashing process combined with a wet etching process.
[0040] A further improvement is that semiconductor ridges are formed on the semiconductor substrate.
[0041] A further improvement is that the first region is the formation region of the NMOS.
[0042] In the dual-layer photolithography process using SOC plus PR, this invention further divides the SOC layer into a first SOC layer and a second SOC layer, and adds an LTO layer with a first thickness between them. After the photoresist is exposed, during the process of transferring the photoresist pattern downwards, the second SOC layer, the LTO layer, and the first SOC layer in the open area (i.e., the first region) are etched sequentially. The first plasma etching process to remove the second SOC layer uses the LTO layer as the stop layer. The second plasma etching process to remove the LTO layer simultaneously consumes all the photoresist outside the first region and part of the second SOC layer outside the first region. The third plasma etching process, which removes the first SOC layer, consumes all of the second SOC layer outside the first region and retains a portion of the LTO layer. The retained LTO layer protects the bottom first SOC layer, ensuring that any residue generated during the third plasma etching process is located on the surface of the LTO layer and does not enter the first SOC layer to form extremely small residue defects that are difficult to remove. Since the residue areas outside the first region are all located on the surface of the LTO layer and the first SOC layer does not contain extremely small residues, all residues can be removed when removing the LTO layer, thus avoiding the formation of extremely small residue defects and ultimately improving product yield.
[0043] This invention is particularly applicable to the patterning etching of the P-type work function layer of TiN layers such as PMOS. Attached Figure Description
[0044] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figures 1A-1E This is a schematic diagram of the device structure in each step of the existing patterning etching method; Figure 2 This is a flowchart of the graphical etching method according to an embodiment of the present invention; Figures 3A-3H This is a schematic diagram of the device structure in each step of the patterned etching method according to an embodiment of the present invention. Detailed Implementation
[0045] like Figure 2 The diagram shown is a flowchart of the patterned etching method according to an embodiment of the present invention; as shown Figures 3A to 3H The diagram shown is a schematic representation of the device structure in each step of the patterning etching method according to an embodiment of the present invention. The patterning etching method according to an embodiment of the present invention includes the following steps: Step S101, as follows Figure 3A As shown, a first process layer 204 is formed on the underlying structure 201, and the first process layer 204 is the target layer for patterned etching.
[0046] In this embodiment of the invention, the material of the first process layer 204 includes TiN.
[0047] The first process layer 204 serves as the P-type work function layer of the PMOS.
[0048] A first TaN layer is also formed at the bottom of the first process layer 204.
[0049] A further improvement is that a high dielectric constant layer is formed at the bottom of the first TaN layer.
[0050] In other embodiments, the material of the first process layer 204 can also be set to other materials as needed.
[0051] In this embodiment of the invention, the underlying structure 201 completes the removal process of the dummy gate structure and forms a gate trench in the dummy gate structure removal region. The first TaN layer is formed after the gate trench is formed.
[0052] In this embodiment of the invention, the underlying structure 201 further includes a semiconductor substrate, and the high dielectric constant layer is formed on the semiconductor substrate; the high dielectric constant layer is formed before the dummy gate structure is removed.
[0053] Semiconductor ridges 202 are formed on the semiconductor substrate, and shallow trench isolation 203 is formed at the bottom region of the spacer region between the semiconductor ridges 202. In some embodiments, a portion of the semiconductor ridges 202 is truncated and the truncated region is filled with a dielectric layer.
[0054] Step S102, as follows Figure 3A As shown, the first SOC layer is coated to form the first SOC layer 205.
[0055] In this embodiment of the invention, the first SOC layer 205 ensures that the gate trench is completely filled.
[0056] Step S103, as follows Figure 3A As shown, an LTO layer 206 is grown on the surface of the first SOC layer 205, and the LTO layer 206 has a first thickness.
[0057] In this application, LTO represents a low-temperature oxidation process, and the LTO layer represents a low-temperature oxidation layer. The low-temperature oxidation process typically uses silane (SiH4) and oxygen at a low temperature range of over 200°C. Compared with the oxidation process at over 1000°C, the temperature of the low-temperature oxidation process is lower.
[0058] Step S104, as follows Figure 3A As shown, a second SOC layer coating is performed to form a second SOC layer 207 on the surface of the LTO layer 206.
[0059] Step S105, as follows Figure 3AAs shown, photoresist 208 is applied.
[0060] like Figure 3B As shown, exposure is performed to open the first region 301, which is the region of the first process layer 204 that needs to be removed.
[0061] In this embodiment of the invention, the first region 301 is the formation region of the NMOS. In other embodiments, the first region 301 can also be configured according to actual needs.
[0062] Step S106, as follows Figure 3C As shown, the first plasma etching process removes the second SOC layer 207 of the first region 301 and stops on the LTO layer 206.
[0063] In the first plasma etching process, the photoresist 208 outside the first region 301 will be partially consumed.
[0064] Step S107, as follows Figure 3D As shown, a second plasma etching process is performed to remove the LTO layer 206 in the first region 301. After the LTO layer 206 is removed, all the photoresist 208 outside the first region 301 is consumed and part of the second SOC layer 207 outside the first region 301 is consumed.
[0065] Step S108, as follows Figure 3E As shown, a third plasma etching process removes the first SOC layer 205 in the first region 301. After the third plasma etching process is completed, the second SOC layer 207 outside the first region 301 is completely consumed. The first thickness ensures that the LTO layer 206 remains after the third plasma etching process. The third plasma etching process will generate plasma bombardment on the first process layer 204 and form residue 209. Outside the first region 301, the LTO layer 206 prevents the residue 209 from entering the first SOC layer 205 and keeps the residue 209 on the surface of the LTO layer 206.
[0066] Depend on Figure 3E As shown, the residue 209 is formed when the plasma formed in the third plasma etching process bombards the first process layer 204 under the condition that the first process layer 204 is exposed. In this way, the material of the first process layer 204, such as TiN, and the TaN at the bottom of TiN will be bombarded out to form Ti and Ta ions, such as Ti + / Ta + The residue 209 contains Ti and Ta ions ejected from the bombardment.
[0067] Step S109, as follows Figure 3F As shown, DHF is used to remove the LTO layer 206 and completely remove the residue 209.
[0068] Step S110, as follows Figure 3G As shown, the first process layer 204 in the first region 301 is removed using the first SOC layer 205 as a mask.
[0069] In this embodiment of the invention, a wet etching process is used to remove the TiN in the first process layer 204.
[0070] Preferably, the etching solution for removing TiN from the first process layer 204 includes SC2 cleaning solution, which is standard solution No. 2.
[0071] Step S111: Remove the first SOC layer 205.
[0072] In this embodiment of the invention, the first SOC layer 205 is removed by an ashing process combined with a humidification etching process.
[0073] In the dual-layer photolithography process using SOC plus PR, this embodiment of the invention further divides the SOC layer into a first SOC layer 205 and a second SOC layer 207, and adds an LTO layer 206 with a first thickness between them. After the photoresist 208 is exposed, during the process of transferring the pattern of the photoresist 208 downward, the second SOC layer 207, the LTO layer 206, and the first SOC layer 205 in the open area, i.e., the first region 301, are etched sequentially. The first plasma etching process to remove the second SOC layer 207 uses the LTO layer 206 as the stop layer. The second plasma etching process to remove the LTO layer 206 simultaneously consumes all the photoresist 208 outside the first region 301 and part of the second SOC layer 207 outside the first region 301. The third plasma etching process for removing the first SOC layer 205 will completely consume the second SOC layer 207 outside the first region 301 and retain a portion of the LTO layer 206. The retained LTO layer 206 can protect the bottom first SOC layer 205, so that the residue 209 generated in the third plasma etching process is located on the surface of the LTO layer 206 and will not enter the first SOC layer 205 to form a difficult-to-remove micro-residue 209 defect. Since the residue area outside the first region 301 is located on the surface of the LTO layer 206 and the first SOC layer 205 does not contain micro-residue 209, the residue 209 can be completely removed when removing the LTO layer 206, thus avoiding the formation of micro-residue 209 defects and ultimately improving the product yield.
[0074] The embodiments of the present invention are particularly applicable to the patterning etching of the P-type work function layer of TiN layers such as PMOS.
[0075] In this embodiment of the invention, the SOC is coated in two stages, with an LTO layer grown in between, followed by normal PR coating. The first step of the Barc-open process stops the coating on the LTO layer, then opens it for the second Barc-open step. During this second step, Ti+ / Ta+ ions from ET plasma bombardment remain on the LTO layer surface. The LTO layer is then removed using DHF, completely eliminating any Ti+ / Ta+ residues on the LTO layer surface. TiN RM (SC2) is then performed, and finally, the SOC is removed using a general process (Asher+WET). This method effectively solves the serious tiny residue problem caused by existing Barc-open processes.
[0076] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A patterned etching method, characterized in that, Includes the following steps: A first process layer is formed on the underlying structure, and the first process layer is the target layer for patterned etching. Perform the first SOC layer coating to form the first SOC layer; An LTO layer is grown on the surface of the first SOC layer, the LTO layer having a first thickness; A second SOC layer coating is applied to form a second SOC layer on the surface of the LTO layer; The first region is the area of the first process layer that needs to be removed by coating photoresist and exposing it. The first plasma etching process is performed to remove the second SOC layer in the first region and stop on the LTO layer; A second plasma etching process is performed to remove the LTO layer in the first region. After the LTO layer is removed, all the photoresist outside the first region is consumed and part of the second SOC layer outside the first region is consumed. A third plasma etching process is performed to remove the first SOC layer in the first region. After the third plasma etching process is completed, the second SOC layer outside the first region is completely consumed. The first thickness ensures that the LTO layer remains after the third plasma etching process. The third plasma etching process will generate plasma bombardment on the first process layer and form residues. Outside the first region, the LTO layer prevents the residues from entering the first SOC layer and keeps the residues on the surface of the LTO layer. The LTO layer was removed using DHF to completely eliminate the residue; The first process layer in the first region is removed using the first SOC layer as a mask. Remove the first SOC layer.
2. The patterned etching method as described in claim 1, characterized in that: The material of the first process layer includes TiN.
3. The patterned etching method as described in claim 2, characterized in that: The first process layer serves as the P-type work function layer of the PMOS.
4. The patterned etching method as described in claim 3, characterized in that: The underlying structure completes the process of removing the pseudo-gate structure and forms a gate trench in the pseudo-gate structure removal area.
5. The patterned etching method as described in claim 4, characterized in that: The first SOC layer ensures that the gate trench is completely filled.
6. The patterned etching method as described in claim 4, characterized in that: A first TaN layer is also formed at the bottom of the first process layer, and the first TaN layer is formed after the gate trench is formed.
7. The patterned etching method as described in claim 6, characterized in that: A high dielectric constant layer is also formed at the bottom of the first TaN layer.
8. The patterned etching method as described in claim 7, characterized in that: The underlying structure also includes a semiconductor substrate, on which the high dielectric constant layer is formed; the high dielectric constant layer is formed before the dummy gate structure is removed.
9. The patterned etching method as described in claim 2, characterized in that: The TiN in the first process layer was removed using a wet etching process.
10. The patterned etching method as described in claim 9, characterized in that: The etching solution used to remove the TiN from the first process layer includes SC2 cleaning solution.
11. The patterned etching method as described in claim 1, characterized in that: The first SOC layer was removed using an ashing process combined with a humidification etching process.
12. The patterned etching method as described in claim 8, characterized in that: Semiconductor convex strips are formed on the semiconductor substrate.
13. The patterned etching method as described in claim 3, characterized in that: The first region is the formation region of the NMOS.