Wafer structure and manufacturing method thereof
By creating a trench structure by slotting in the insulating layer beneath the RDL, the problem of copper atom migration and accumulation caused by increased current density is solved, thereby improving the reliability of the copper interconnect structure and preventing short circuits and interface separation.
Patent Information
- Application Number
- CN202511041495.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-28
- Publication Date
- 2025-11-11
AI Technical Summary
As the feature size of semiconductor devices shrinks, the linewidth and spacing of RDLs decrease, leading to an increase in current density. The potential difference between adjacent RDLs causes a temperature gradient, resulting in the migration and accumulation of copper atoms, which can cause short circuits or interface separation problems.
Grooves are created in the insulating layer beneath the RDL to form a trench structure. Copper atoms accumulate in the trenches during migration, preventing them from migrating to adjacent lines. The metal lines are isolated by filling the insulating layer with organic polymers or inorganic dielectric materials.
It effectively prevents short circuits between RDL lines, improves the reliability of copper interconnect structures, and reduces electromigration failures.
Smart Images
Figure CN120933265A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a wafer structure and its fabrication method for improving electromigration failure in copper interconnect structures. Background Technology
[0002] A redistribution layer (RDL) is a metal wiring layer in a chip package used to rearrange the original bond pads on the chip surface to more easily packaged locations. It solves the problem of insufficient pad spacing or irregular layout, enabling efficient connections to external circuits. Currently, RDLs typically use copper interconnect structures due to copper's advantages such as low resistivity, low parasitic capacitance, low resistance, and good resistance to electromigration.
[0003] As the feature size of semiconductor devices continues to shrink and chip area continues to increase, the linewidth and spacing of the RDL (Relational Domain Array) on the chip are correspondingly decreasing. With the increase in current density in the RDL, the potential difference between adjacent RDLs becomes large, leading to temperature gradients and ultimately causing reliability issues such as copper electromigration in the RDL. This is especially true for products with increasingly smaller RDL line spacing, where copper atoms accumulate at the RDL copper interconnect spacing, causing pin short circuits, or voids form at the original RDL locations, leading to interface separation between the passivation layer and the copper. Summary of the Invention
[0004] This application provides a structure and method for improving electromigration failure in copper interconnect structures. By slotting in the insulating layer between RDL lines below the RDL, a trench structure is formed, so that when copper atoms migrate on one side of the RDL line, they can accumulate in the trench and not migrate to the RDL line on the other side of the trench, effectively preventing short circuits between RDL lines.
[0005] According to one embodiment of the present invention, a wafer structure is provided, comprising: a wafer, a first insulating layer, and a metal layer. The first insulating layer covers one side of the wafer. The metal layer includes a plurality of metal lines distributed on the first insulating layer. A trench structure is formed on the surface of the first insulating layer facing the metal layer, located between the plurality of metal lines, and the trench structure extends along the metal lines on both sides of the trench structure.
[0006] In one embodiment, the aforementioned wafer structure further includes a second insulating layer that covers the first insulating layer and the metal layer and fills the trench structure of the first insulating layer.
[0007] In one embodiment, the materials of the first insulating layer and the second insulating layer in the aforementioned wafer structure are different.
[0008] In one embodiment, in the aforementioned wafer structure, the second insulating layer comprises an organic polymer.
[0009] In one embodiment, in the aforementioned wafer structure, the first insulating layer comprises an inorganic dielectric material.
[0010] In one embodiment, in the aforementioned wafer structure, the depth of the trench structure is greater than 3 μm and less than the spacing between adjacent metal lines minus 6 μm.
[0011] In one embodiment, in the aforementioned wafer structure, the depth of the trench structure is less than the thickness of the first insulating layer minus 0.5 μm.
[0012] In one embodiment, in the aforementioned wafer structure, the distance between the sidewall of the trench structure and the adjacent metal line is greater than 3 μm.
[0013] In one embodiment, the metal layer in the aforementioned wafer structure comprises copper.
[0014] According to an embodiment of the present invention, a method for fabricating a wafer structure is provided, comprising: providing a wafer; forming a first insulating layer on one of the surfaces of the wafer; forming a trench structure at a location of the first insulating layer below a region between metal lines of a predetermined metal layer; forming a metal layer on the first insulating layer, the metal layer including a plurality of metal lines; and forming a second insulating layer on the metal layer and the first insulating layer, the second insulating layer filling the trench structure. Attached Figure Description
[0015] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings:
[0016] Figure 1 This is a cross-sectional view of an existing semiconductor device 100 under a microscope after copper atom electromigration has occurred.
[0017] Figure 2 This is a partial cross-sectional schematic diagram of a wafer structure 200 according to an embodiment of this application;
[0018] Figure 3 This is a partial cross-sectional schematic diagram of a wafer structure 200 according to an embodiment of this application, showing copper atom migration.
[0019] Figure 4 A method 400 for fabricating a wafer structure according to an embodiment of this application is shown;
[0020] Figures 5A-5E Cross-sectional views of the wafer structure after each step 401 to 405 of the fabrication method 400 according to an embodiment of the present invention are shown. Detailed Implementation
[0021] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.
[0022] Throughout this specification, references to "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases "in an embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same elements have been designated by corresponding reference numerals in different drawings.
[0023] The terms “having,” “comprising,” “including,” “include,” etc., are open-ended, and these terms indicate the presence of the said structure, element, or feature, but do not exclude additional elements or features.
[0024] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.
[0025] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".
[0026] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.
[0027] Figure 1 This is a cross-sectional view of an existing semiconductor device 100 under a microscope after copper atom electromigration has occurred. Figure 1 As shown, copper wires 102a and 102b are distributed on the chip layer 101 of the semiconductor device 100. An insulating layer 103 covers the chip layer 101 and the copper wires 102a and 102b. Under the influence of a long-term high current, the potential difference generated between the copper wires leads to a temperature gradient, causing the semiconductor device 100 to exhibit phenomena such as… Figure 1 The void 104 is shown in the diagram. Some copper atoms migrate between copper lines 102a and 102b and stack in the region 105 between them. When enough copper atoms stack, copper lines 102a and 102b short-circuit, leading to device failure and other problems.
[0028] Figure 2 This is a partial cross-sectional schematic diagram of a wafer structure 200 according to an embodiment of this application. The wafer structure 200 includes a chip layer 201, a metal layer 202, and an insulating layer 203. The chip layer 201 includes a wafer 201a and an insulating layer 201b covering the wafer 201a. The metal layer 202 includes multiple metal lines distributed on the insulating layer 201b. It should be understood that, for clarity of illustration, Figure 2 Only a partial cross-section of wafer structure 200 is shown, thus only metal lines 202a and 202b are shown. In the actual wafer structure, metal layer 202 includes multiple metal lines. Among them, insulating layer 201b is also referred to as the first insulating layer, and insulating layer 203 is also referred to as the second insulating layer.
[0029] On the surface 201s of the first insulating layer 201b toward the metal layer 202, at a position between metal lines 202a and 202b, there is a trench structure 204. The trench structure 204 extends along the metal lines 202a and 202b on both sides of the trench structure 204.
[0030] The second insulating layer 203 covers the first insulating layer 201b and the metal layer 202, and fills the trench structure 204 of the first insulating layer 201b.
[0031] exist Figure 2 In the embodiment, when copper atoms migrate in metal lines 202a or 202b, the migrated copper atoms fall into the trench structure 204, such as... Figure 3 As shown. In other words, the trench structure 204 prevents the migration of copper atoms, avoiding a short circuit between metal lines 202a and 202b. Furthermore, electromigration failure generally occurs at a single point, i.e., concentrated at one or a few points. The trench structure 204, extending along the metal lines, has sufficient space to accommodate the migrating copper atoms, thus preventing short circuits.
[0032] exist Figure 2In this embodiment, the spacing between metal lines 202a and 202b is w1, the spacing between the sidewall of the trench structure 204 and the metal lines of the adjacent metal layer is w2, the width of the trench structure 204 is w3, and the depth of the trench structure 204 is d1. In one embodiment, to ensure sufficient space in the trench to accommodate copper atoms, the depth d1 of the trench structure 204 is greater than 3 μm. Since the metal layer is processed by electroplating, a sputtered layer covering the entire surface needs to be sputtered for conductivity before electroplating. Considering the capability of the sputtering machine, in one embodiment, the width w3 of the trench structure 204 is set to be greater than the depth d1. In some embodiments, the minimum value of the spacing w2 between the sidewall of the trench structure 204 and the metal lines of the adjacent metal layer is set to 3 μm, and the minimum value of the width w3 of the trench structure 204 is also set to 3 μm, while the maximum value is set to w1-6 μm. In some embodiments, the maximum value of the depth d1 of the trench structure 204 is set to w1-6 μm.
[0033] In one embodiment, to prevent copper atoms from penetrating the first insulating layer 201b beneath the trench structure 204 and causing a short circuit between the metal layer and the device surface of the wafer surface 201a, the thickness d2 of the first insulating layer 201b beneath the trench structure 204 is greater than 0.5 μm. That is, the depth d1 of the trench structure 204 is less than the maximum thickness (d1+d2) of the first insulating layer 201b minus 0.5 μm.
[0034] In one embodiment, the first insulating layer 201b comprises an inorganic dielectric material, such as silicon dioxide and silicon nitride, and covers the device surface of the wafer 201a to form a dielectric layer between the metal layer 202 and the device surface of the wafer 201a.
[0035] In one embodiment, the second insulating layer 203 comprises an organic polymer and covers the metal layer 202 and the first insulating layer 201b to provide electrical isolation for the device and prevent chip cracking.
[0036] In one embodiment, metal layer 202 comprises copper. It should be understood that other conductive metals suitable for electrical interconnect structures can also be used in this invention. The trench structure of this invention can be used in any application where electromigration of metal atoms would occur.
[0037] Figure 4 A method 400 for fabricating a wafer structure according to an embodiment of this application is shown. For example... Figure 4 As shown, the wafer structure fabrication method 400 includes steps 401 to 405. Figures 5A-5E Cross-sectional views of the wafer structure after each step 401 to 405 of the fabrication method 400 according to an embodiment of the present invention are shown. The following corresponds to... Figure 4 and Figures 5A-5EThis section details each step of the production method 400.
[0038] Step 401, provide wafer 201a. The cross-sectional view of the wafer structure corresponding to step 401 is shown below. Figure 5A As shown. Among them, in Figure 5A In the diagram, the upper surface of wafer 201a is the device surface.
[0039] Step 402: A first insulating layer 201b is formed on the upper surface (device surface) of wafer 201a. The wafer structure cross-sectional view corresponding to step 402 is shown below. Figure 5B As shown. The first insulating layer 201b can be formed using a process of coating, exposure, development, and curing. It should be understood that the first insulating layer 201b has partial openings for electrical connection between the metal layer 202 and a portion of the device surface of the wafer 201a.
[0040] Step 403: A trench structure 204 is formed at the location of the first insulating layer 201b below the region between metal lines 202a and 202b of the predetermined metal layer 202. The wafer structure cross-sectional view corresponding to step 403 is shown below. Figure 5C As shown. The trench structure 204 can be formed using photolithography.
[0041] Step 404: A metal layer 202 is formed on the first insulating layer 201b. The metal layer 202 includes multiple metal lines; metal lines 202a and 202b are shown in the figure for clarity. The wafer structure cross-sectional view corresponding to step 404 is shown below. Figure 5D As shown. The method for forming the metal layer 202 may include depositing a metal seed layer and pattern electroplating, specifically including sputtering a metal seed layer, photolithography patterning, electroplating a metal layer according to the photolithography pattern, removing the photoresist, etching the sputtered layer, etc.
[0042] Step 405: A second insulating layer 203 is formed on the metal layer 202 and the first insulating layer 201b, and this second insulating layer 203 simultaneously fills the trench structure 204. The wafer structure cross-sectional view corresponding to step 405 is shown below. Figure 5E As shown.
[0043] As described above, these embodiments of the present application do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to make good use of the present application and modifications based on it. The present application is limited only by the claims and their full scope and equivalents.
Claims
1. A wafer structure comprising: wafers; The first insulating layer covers one side of the wafer; as well as A metal layer, comprising multiple metal wires, is distributed on the first insulating layer; Among them, on the surface of the first insulating layer facing the metal layer, at the position between multiple metal lines of the metal layer, there is a trench structure, and the trench structure extends along the metal lines on both sides of the trench structure.
2. The wafer structure according to claim 1, further comprising: The second insulating layer covers the first insulating layer and the metal layer, and fills the trench structure of the first insulating layer.
3. The wafer structure according to claim 2, wherein the first insulating layer and the second insulating layer are made of different materials.
4. The wafer structure according to claim 2, wherein the second insulating layer comprises an organic polymer.
5. The wafer structure according to claim 1, wherein the first insulating layer comprises an inorganic dielectric material.
6. The wafer structure according to claim 1, wherein the depth of the trench structure is greater than 3 μm and less than the spacing between adjacent metal lines minus 6 μm.
7. The wafer structure according to claim 1, wherein the depth of the trench structure is less than the thickness of the first insulating layer minus 0.5 μm.
8. The wafer structure according to claim 1, wherein the distance between the sidewall of the trench structure and the adjacent metal line is greater than 3 μm.
9. The wafer structure according to claim 1, wherein the metal layer comprises copper.
10. A method for fabricating a wafer structure, comprising: Provide wafers; A first insulating layer is formed on one of the surfaces of the wafer; A trench structure is formed at the location of the first insulating layer below the region between the metal lines of the predetermined metal layer; A metal layer is formed on a first insulating layer, the metal layer comprising a plurality of metal lines; as well as A second insulating layer is formed on the metal layer and the first insulating layer, and the second insulating layer fills the trench structure.