Frequency jitter control circuit and switching power supply

Abstract

The application provides a frequency jitter control circuit and a switching power supply. The frequency jitter control circuit comprises a logic module and a delay output module, the logic module is electrically connected with the delay output module, and the delay output module is used for being electrically connected with a control module in the switching power supply. The logic module is used for outputting a control signal to the delay output module according to a preset signal; the delay output module is used for delaying a received first clock signal according to the control signal and outputting a second clock signal to the control module, so as to provide frequency jitter for the control module, wherein the first clock signal is a clock signal in the switching power supply. The application multiplexes and delays the internal existing clock signal, not only saves the hardware cost required by the newly added independent oscillator module, but also reduces the additional synchronization logic design cost and the switching power supply chip space occupation cost under the double clock architecture, thereby greatly saving the design cost of the switching power supply.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of switching power supply, and particularly relates to a frequency jitter control circuit and a switching power supply. BACKGROUND

[0002] In the field of switching power supply, especially in the scenes such as automotive electronics, LED (Light-Emitting Diode) backlight driving and the like which have strict requirements on EMI (Electromagnetic Interference) and control accuracy, the stable operation and function realization of a DC-DC switching power supply highly depend on the support of a clock signal. On the one hand, in order to accurately complete the detection of core parameters (such as the detection of the PWM (Pulse-Width Modulation) duty cycle input by the chip pin in LED backlight driving), a high-frequency clock needs to be integrated inside the power supply, and the clock must have the characteristic of no jitter. Once jitter is introduced, it will directly lead to the decrease of the detection accuracy of the duty cycle, and further cause functional abnormalities such as backlight brightness fluctuation. On the other hand, in order to suppress the electromagnetic interference generated when the DC-DC switching power supply works, a perturbation needs to be introduced at the high-frequency switching frequency point to realize spectrum dispersion, and this process needs to rely on a clock signal with jitter characteristic. In the prior art, since the high-frequency clock for detection cannot provide the jitter function, an independent oscillator module with clock jitter needs to be additionally added, forming a double-clock architecture of "no-jitter detection" and "jitter frequency suppression EMI". However, such a design will directly increase the design cost of the switching power supply. SUMMARY

[0003] The embodiments of the application provide a frequency jitter control circuit and a switching power supply, which can solve the problem that the existing switching power supply uses a double-clock architecture to increase the design cost.

[0004] In a first aspect, the embodiments of the application provide a frequency jitter control circuit, which comprises a logic module and a delay output module, the logic module is electrically connected with the delay output module, and the delay output module is used to be electrically connected with a control module in a switching power supply.

[0005] The logic module is used to output a control signal to the delay output module according to a preset signal; and the delay output module is used to delay a received first clock signal according to the control signal, and output a second clock signal to the control module, wherein the first clock signal is a clock signal in the switching power supply.

[0006] In a possible implementation manner of the first aspect, the delay output module comprises a switch unit and a plurality of first delay units, the switch unit is electrically connected with all the first delay units and the control module respectively, and each of the first delay units is electrically connected with the logic module and the control module.

[0007] The switch unit is configured to output a first voltage signal according to the first clock signal, and the first delay unit is configured to adjust a frequency of the first voltage signal according to the control signal to obtain the second clock signal.

[0008] In a possible implementation manner of the first aspect, the switch unit comprises a first switch tube and a second switch tube, a gate of the first switch tube and a gate of the second switch tube are configured to receive the first clock signal, a source of the first switch tube is electrically connected with a power supply, a drain of the first switch tube is electrically connected with a drain of the second switch tube, all the first delay units and the control module respectively, and a source of the second switch tube is grounded.

[0009] In a possible implementation manner of the first aspect, the first delay unit comprises a third switch tube, a fourth switch tube, a transmission gate and a first capacitor, a gate of the third switch tube is configured to receive the first clock signal, a source of the third switch tube is electrically connected with a power supply, a drain of the third switch tube is electrically connected with a source of the fourth switch tube, a gate of the fourth switch tube and a control end of the transmission gate are electrically connected with the logic module, a drain of the fourth switch tube is electrically connected with the switch unit, a first end of the transmission gate and the control module respectively, a first end of the first capacitor is electrically connected with a second end of the transmission gate, and a second end of the first capacitor is grounded.

[0010] In a possible implementation manner of the first aspect, the delay output module further comprises a first inverter and a second inverter, an input end of the first inverter is configured to receive the first clock signal, an output end of the first inverter is electrically connected with an input end of the second inverter, and an output end of the second inverter is electrically connected with the switch unit and all the first delay units respectively.

[0011] In a possible implementation manner of the first aspect, the delay output module further comprises a third inverter, an input end of the third inverter is electrically connected with all the first delay units and the switch unit respectively, and an output end of the third inverter is electrically connected with the control module.

[0012] In a possible implementation manner of the first aspect, the delay output module comprises a plurality of second delay units and a multiplexing unit, all the second delay units are electrically connected in sequence, and the multiplexing unit is electrically connected with all the second delay units and the logic module respectively, and the multiplexing unit is configured to be electrically connected with the control module.

[0013] Each of the second delay units is configured to output a corresponding delay clock signal, and the multiplexing unit is configured to output the second clock signal according to the control signal, the second clock signal being one of the plurality of delay clock signals.

[0014] In a possible implementation manner of the first aspect, the multiplexing unit comprises a multiplexer, a plurality of first input terminals of the multiplexer are electrically connected with the plurality of second delay units correspondingly, a second input terminal of the multiplexer is electrically connected with the logic module, and an output terminal of the multiplexer is configured to be electrically connected with the control module.

[0015] In a possible implementation manner of the first aspect, the second delay unit comprises a fourth inverter, an input terminal of the fourth inverter and an output terminal of the fourth inverter are electrically connected with the multiplexing unit.

[0016] In the second aspect, the embodiments of the present application provide a switching power supply comprising a control module and the frequency jitter control circuit of any one of the first aspect.

[0017] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0018] The frequency jitter control circuit provided by the embodiments of the present application comprises a logic module and a delay output module. The logic module can output a control signal to the delay output module according to a preset signal, and the delay output module delays a first clock signal received according to the control signal and outputs a second clock signal to the control module to provide frequency jitter for the control module. Since the first clock signal used in the embodiments of the present application is an internal clock signal integrated in the switching power supply, rather than an additional independent clock, the frequency jitter control circuit provided by the embodiments of the present application does not need to set a double clock architecture to meet the dual requirements of "non-jitter detection" and "frequency jitter suppression EMI". This design reuses the internal clock signal and performs delay processing, which not only saves the hardware cost of adding an independent oscillator module, but also reduces the additional synchronization logic design cost and the switching power supply chip space occupation cost, thereby greatly saving the design cost of the switching power supply. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0020] Figure 1 is a schematic diagram of a frequency jitter control circuit provided by an embodiment of the present application;

[0021] Figure 2 is a schematic diagram of a frequency jitter control circuit provided by another embodiment of the present application;

[0022] Figure 3 is a schematic diagram of a frequency jitter control circuit provided by an embodiment of the present application;

[0023] Figure 4 is a schematic diagram of a frequency jitter control circuit provided by another embodiment of the present application;

[0024] Figure 5 is a schematic diagram of a triangular wave output of digital logic provided by an embodiment of the present application;

[0025] Figure 6 is a schematic diagram of a frequency variation result of an oscillator output provided by an embodiment of the present application;

[0026] Figure 7 is a schematic diagram of a frequency jitter control circuit provided by another embodiment of the present application.

[0027] In the figure, 10, frequency jitter control circuit; 101, logic module; 102, delay output module; 1021, switch unit; 1022, first delay unit; 1023, multi-way selection unit; 1024, second delay unit; 20, control module. DETAILED DESCRIPTION

[0028] In the following description, specific details are set forth in order to provide a thorough understanding of embodiments of the present application. However, persons of ordinary skill in the art will readily recognize that embodiments of the present application can be practiced without these specific details, in other instances, well-known structures, devices, circuits, and methods have not been described in detail in order to avoid obscuring the present application.

[0029] It should be understood that when used in the specification and the appended claims, the term "comprise" indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0030] It should also be understood that, in the description of the present application and in the claims that follow, the term "and / or" means any combination of one or more of the associated listed items and includes all possible combinations.

[0031] As used in the description of the application and the appended claims, the term "if' can be interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting." Similarly, the phrase "if determined" or "if detected [a described condition or event]" can be interpreted to mean "upon determining" or "in response to determining" or "upon detecting [a described condition or event]" or "in response to detecting [a described condition or event]," as appropriate.

[0032] In addition, the description in the specification of the application and the appended claims, the terms "first," "second," "third," etc. are merely used to distinguish one element from another, and are not intended to imply or suggest relative importance.

[0033] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" or "in some embodiments" or "in other embodiments" or "in still other embodiments" in various places throughout this specification are not necessarily all referring to the same embodiment, unless otherwise indicated. Furthermore, the terms "comprises," "comprising," "includes," "including," "has," "having" and the like are intended to be open-ended terms that do not exclude additional, unrecited elements or methods. Thus, the term "comprising" or "comprises" as used in the specification and claims does not exclude the presence of unrecited elements or steps.

[0034] In the field of switching power supply, especially in the scenes of automotive electronics, LED backlight driving and other scenes with strict requirements on EMI and control accuracy, the stable operation and function realization of DC-DC switching power supply highly depend on the support of clock signal. On the one hand, in order to accurately complete the detection of core parameters (such as the detection of PWM duty cycle input by chip pin in LED backlight driving), a high-frequency clock (for example, 20 MHz) needs to be integrated inside the power supply, and the clock must maintain the characteristic of no jitter. Once jitter is introduced, it will directly lead to the decrease of the detection accuracy of duty cycle, and then cause functional abnormalities such as backlight brightness fluctuation. On the other hand, in order to suppress the electromagnetic interference generated by the DC-DC switching power supply during operation, a perturbation needs to be introduced at the high-frequency switching frequency point to realize spectrum dispersion, and this process needs to rely on the clock signal with jitter characteristic. In the prior art, since the high-frequency clock for detection cannot provide the jitter function, an independent oscillator module with clock jitter needs to be additionally added, forming a double clock architecture of "no jitter detection" and "jitter frequency suppression EMI". However, such design will directly increase the design cost of the switching power supply.

[0035] Based on the above problems, the jitter frequency control circuit provided by the embodiment of the present application includes a logic module and a delay output module. The logic module can output a control signal to the delay output module according to a preset signal, and the delay output module delays the received first clock signal according to the control signal and outputs a second clock signal to the control module to provide jitter frequency for the control module. Since the first clock signal used in the embodiment of the present application is the clock signal integrated inside the switching power supply, rather than an additional independent clock, the jitter frequency control circuit provided by the embodiment of the present application does not need to set a double clock architecture to meet the dual requirements of "no jitter detection" and "jitter frequency suppression EMI". This design reuses and delays the existing internal clock signal, which not only saves the hardware cost of adding an independent oscillator module, but also reduces the additional synchronization logic design cost and switching power supply chip space occupation cost under the double clock architecture, thereby greatly saving the design cost of the switching power supply.

[0036] In order to illustrate the technical solutions described in the present application, the following will be described by specific embodiments.

[0037] Figure 1 The principle diagram of the jitter frequency control circuit 10 provided by an embodiment of the present application is shown. Referring to Figure 1 As shown, the jitter frequency control circuit 10 includes a logic module 101 and a delay output module 102, the logic module 101 is electrically connected with the delay output module 102, and the delay output module 102 is used to be electrically connected with the control module 20 in the switching power supply.

[0038] Specifically, the logic module 101 can output a control signal to the delay output module 102 according to a preset signal, the delay output module 102 delays the received first clock signal according to the control signal, and outputs a second clock signal CLK_OUT to the control module 20 to provide frequency jitter for the control module 20. Since the first clock signal used in the embodiment of the present application is an internal clock signal integrated in the switching power supply, rather than an additional independent clock, the frequency jitter control circuit 10 provided by the embodiment of the present application does not need to set a double clock architecture to meet the dual requirements of "no jitter detection" and "jitter suppression EMI". This design reuses and delays the internal existing clock signal, which not only saves the hardware cost of adding an independent oscillator module, but also reduces the additional synchronization logic design cost and switching power supply chip space occupation cost under the double clock architecture, thereby greatly saving the design cost of the switching power supply.

[0039] It should be noted that the first clock signal, i.e. CLK0, is a high-frequency non-jitter clock (for example, a 20MHz clock) integrated in the switching power supply for precise parameter detection (such as PWM duty cycle detection of chip pin input in LED backlight driving) after frequency division, which is used as the input clock signal CLK_IN of the delay output module 102. The clock itself needs to be stable and non-jitter to ensure detection accuracy and cannot be directly used for frequency jitter. The present scheme only changes the output timing (produces jitter characteristics) by delaying it, without changing its non-jitter property, so it can reuse it as the basic clock source for frequency jitter without affecting the original detection function, thus avoiding the need for a double clock architecture.

[0040] Exemplarily, the preset signal can be a control reference signal with specific rules pre-set for different frequency jitter requirements. The specific form needs to be determined in combination with the application scenarios (such as LED backlight driving, automobile electronic power supply, etc.) and EMI suppression targets of the switching power supply, mainly covering the following types: it can be a rule signal set based on the frequency jitter mode, for example, a triangular wave mode signal for realizing smooth frequency fluctuation to adapt to the normal EMI suppression requirement. The signal drives the logic module 101 to output a control signal that changes in a fixed period (such as gradually increasing from 4-bit code 0000 to 1111 and then decreasing back to 0000), so that the delay time of the delay output module 102 linearly increases and decreases, and finally the frequency of the second clock signal CLK_OUT presents a triangular wave jitter. It can also be a pseudo-random mode signal set for improving EMI suppression effect and avoiding the continuous appearance of a single frequency point. The signal triggers the logic module 101 to generate a code (such as a 4-bit pseudo-random code) conforming to the pseudo-random algorithm, and through random selection of different delay time, the frequency of the second clock signal CLK_OUT fluctuates irregularly, further dispersing the frequency spectrum energy. In addition, it can also be a parameter adaptation signal set in combination with the actual working parameters of the switching power supply, such as a delay step control signal pre-set according to the PWM duty cycle detection accuracy requirement in LED backlight driving, the output power range of the switching power supply and other parameters, to ensure that the control signal output by the logic module 101 can match the frequency characteristics of the first clock signal, realizing the frequency jitter function while not affecting the original detection function of the first clock signal, and finally making the entire frequency jitter control circuit 10 neither need to rely on the double clock architecture, nor can accurately adapt to the actual working requirements of the switching power supply.

[0041] It should be noted that the logic module 101 can internally integrate multiple digital devices to realize the generation and output of the encoded signal.

[0042] For example, the logic module 101 can include a counter (such as a binary counter, a ring counter), generate a periodically changing encoding sequence through pre-designed counting periods or cyclic logic. The logic module 101 can also include a pseudo-random sequence generator, generate a pseudo-random code with irregular repetition through a specific algorithm, and provide a control signal for a pseudo-random dithering mode. The logic module 101 can also include a mode selector, switch the working state of the counter and the pseudo-random generator according to an external instruction (such as a mode control signal input by a chip pin), and realize flexible switching of multiple dithering modes. The logic module 101 can also include a register (such as a register group composed of D flip-flops), used for temporarily storing preset encoding parameters (such as encoding values corresponding to maximum delay time lengths), and ensuring that the encoding signal output by the logic module 101 is stable and reliable. In addition, the logic module 101 can also include logic gate circuits (such as AND gates, OR gates, XOR gates), shape, verify or bit width adjust (such as converting an 8-bit count signal into a 4-bit valid encoding) the output signal of the counter or the pseudo-random generator through combination logic, and finally output a control signal meeting the requirements of the delay output module 102.

[0043] The working principle of the delay output module 102 provided in an embodiment of the present application will be described in detail below in combination with the circuit schematic diagram shown in Figure 2 and Figure 3

[0044] In an embodiment of the present application, as shown in Figure 2 , the delay output module 102 includes a switching unit 1021 and a plurality of first delay units 1022, the switching unit 1021 is electrically connected with all the first delay units 1022 and the control module 20 respectively, each first delay unit 1022 is electrically connected with the logic module 101 and the control module 20, and all the first delay units 1022 are connected in parallel.

[0045] Specifically, the switching unit 1021 is used for receiving a first clock signal and outputting a first voltage signal according to the first clock signal. When the first clock signal is at a high level, the switching unit 1021 is in a first switching state. When the first clock signal is at a low level, the switching unit 1021 is in a second switching state. Thus, the switching unit 1021 can switch the switching state according to the first clock signal and obtain the first voltage signal. Each first delay unit 1022 receives a control signal output by the logic module 101, and selects whether to access the circuit to delay process the first voltage signal according to the control signal, thereby adjusting the frequency of the first voltage signal. After the delay processing of the plurality of first delay units 1022, a second clock signal CLK_OUT can be obtained.

[0046] ​For example, the delay output module 102 includes four first delay units 1022. The number of the first delay units 1022 can be increased or decreased according to actual requirements, which is not limited herein. In an embodiment of the present application, as shown in Figure 3 The switch unit 1021 includes a first switch tube PM10 and a second switch tube NM10. The gate of the first switch tube PM10 and the gate of the second switch tube NM10 are configured to receive the first clock signal. The source of the first switch tube PM10 is electrically connected to the power supply VDD. The drain of the first switch tube PM10 is electrically connected to the drain of the second switch tube NM10, all the first delay units 1022 and the control module 20. The source of the second switch tube NM10 is grounded.

[0047] Specifically, the first switch tube PM10 and the second switch tube NM10 are both used as switching devices, which are turned on or turned off according to the first clock signal received by the gate. When the first clock signal is at a high level, the first switch tube PM10 is turned off, and the second switch tube NM10 is turned on. The switch unit 1021 is in a first switch state. At this time, the first delay unit 1022 can be discharged through the turned-on second switch tube NM10. When the first clock signal is at a low level, the first switch tube PM10 is turned on, and the second switch tube NM10 is turned off. The switch unit 1021 is in a second switch state. At this time, the first delay unit 1022 can be charged through the turned-on first switch tube PM10. The first delay unit 1022 charges and discharges according to the change of the state of the switch unit 1021, so as to change the frequency of the first voltage signal, so as to obtain the second clock signal CLK_OUT.

[0048] For example, the designer can select the types of the first switch tube PM10 and the second switch tube NM10 according to actual conditions, that is, both can be full-controlled power devices such as metal oxide field effect transistors or insulated gate bipolar transistors. For example, the first switch tube PM10 can be selected as a PMOS tube, and the second switch tube NM10 can be selected as an NMOS tube.

[0049] In an embodiment of the present application, as shown in Figure 3As shown, the first delay unit 1022 includes a third switch tube, a fourth switch tube, a transmission gate and a first capacitor, the gate of the third switch tube is configured to receive the first clock signal, the source of the third switch tube is electrically connected with the power supply VDD, the drain of the third switch tube is electrically connected with the source of the fourth switch tube, the gate of the fourth switch tube and the control end of the transmission gate are electrically connected with the logic module 101, the drain of the fourth switch tube is electrically connected with the switching unit 1021, the first end of the transmission gate and the control module 20 respectively, the first end of the first capacitor is electrically connected with the second end of the transmission gate, and the second end of the first capacitor is grounded. Among them, PM11, PM13, PM15 and PM17 are the third switch tubes in the corresponding first delay unit 1022, and the gates of the third switch tubes receive the first clock signal; PM12, PM14, PM16 and PM18 are the fourth switch tubes in the corresponding first delay unit 1022, and the gates of the fourth switch tubes are connected with the logic module 101, and CTRL0-CTRL3 receive the control signals from the logic module 101. TG0-TG3 are the transmission gates in the corresponding first delay unit 1022, and C0, C1, C2 and C3 are the first capacitors in the corresponding first delay unit 1022.

[0050] Specifically, the third switch tube, the fourth switch tube, the transmission gate and the first capacitor are connected in series to form an RC delay loop. Among them, the third switch tube is configured to adjust the current flowing into the first delay unit 1022 according to the first clock signal, the fourth switch tube and the transmission gate both receive the control signal output by the logic module 101, and are turned on or turned off according to the control signal, when the fourth switch tube and the transmission gate are both turned on, the first capacitor is connected to the RC loop; when the fourth switch tube and the transmission gate are both turned off, the first capacitor is disconnected from the RC loop. The first capacitor as a core delay element, after being connected, changes the time constant of the RC loop through the charging and discharging process, the larger the capacitance value of the connected capacitor (or the larger the total capacitance value when multiple capacitors are connected in parallel), the longer the charging and discharging time, and the longer the delay time of the output signal. Ultimately, through the cooperation of the switching unit 1021 and other first delay units 1022, the frequency of the first voltage signal is stepwise adjusted, providing hardware support for generating the second clock signal CLK_OUT with jitter characteristics.

[0051] For example, the designer can select the types of the third switch tube and the fourth switch tube according to the actual situation, that is, both can be full-controlled power devices such as metal oxide field effect transistors or insulated gate bipolar transistors. For example, the third switch tube and the fourth switch tube can be PMOS tubes.

[0052] For example, if the control signal output by the setting logic module 101 is a 4-bit binary code (CTRL3-CTRL0), corresponding to four first delay units 1022 (each containing one transmission gate and one first capacitor, the capacitances of the four first capacitors can be set in binary weight form of C, 2C, 4C, and 8C, and the difference in capacitance allocation can achieve more flexible delay time adjustment), taking “1 indicates that the transmission gate is turned on and the capacitor is connected, and 0 indicates that the transmission gate is turned off and the capacitor is not connected” as an example, the specific correspondence is as follows:

[0053] The core logic of this binary weight design is to make the capacitance of each capacitor branch increase exponentially by 2, and each bit (from the lowest bit to the highest bit) of the 4-bit control signal controls the capacitor branch with a capacitance of C, 2C, 4C, and 8C, respectively. When a bit of the control signal is “1”, the corresponding weight capacitor is connected to the RC circuit, and the total capacitance is the sum of the capacitances of all “1” bits. For example, when the control signal is “0001”, only the capacitor with a capacitance of C is connected, the total capacitance is C, and the delay time is the reference value t (determined by the RC time constant); when the control signal is “0010”, the capacitor with a capacitance of 2C is connected, the total capacitance is 2C, and the delay time is 2t; when the control signal is “0101”, the capacitors with capacitances of C and 4C are connected, the total capacitance is 5C, and the delay time is 5t; when the control signal is “1111”, all four capacitors are connected, the total capacitance is C+2C+4C+8C=15C, and the delay time reaches 15t. Compared with the design with the same capacitance, this binary weight capacitance setting can achieve a wider delay adjustment range (4 paths can achieve 16 total capacitance combinations of 0-15C) with fewer capacitor branches, and can also adjust the connection state of capacitors with different weights to flexibly match the demand for jitter frequency step size in different scenarios (such as when small step adjustment is needed, control the low-weight capacitor branch switching; when large step adjustment is needed, control the high-weight capacitor branch switching), further improving the adaptability of the delay output module 102 to EMI suppression scenarios, and without additional hardware costs, only through the differential design of capacitance can expand the functional dimension.

[0054] For example, in addition to the 4-bit binary coding, the delay time length can also be adjusted in steps by using the thermometer code. The core logic is to ensure that the total capacitance of the RC circuit is always in a continuous accumulation state by adding a new capacitor branch for each progressive bit of the coding, thereby avoiding the non-continuous capacitance change problem that may occur in binary coding. Taking the thermometer code control of four first delay units 1022 (corresponding to four capacitor branches, each with the same capacitance value, such as 10 pF) as an example. When the logic module 101 outputs the thermometer code "0001", only the transmission gate of the first delay unit 1022 of the first path is turned on, corresponding to the access of a 10 pF capacitor, and the total capacitance of the RC circuit is 10 pF, and the delay time length is the reference value t (such as 10 ns); when the output is "0011", on the basis of the first path being turned on, the transmission gate of the second path is newly turned on, and the total capacitance of 10 pF+10 pF=20 pF is accessed, and the delay time length is increased to 2t (20 ns); when the output is "0111", the transmission gate of the third path is further newly turned on, and the total capacitance is accumulated to 30 pF, and the delay time length is increased to 3t (30 ns); if the maximum delay is required, the output "1111" turns on the transmission gate of the fourth path, and the total capacitance reaches 40 pF, and the delay time length is 4t (40 ns). In this coding mode, each change of the control signal only increases or decreases one capacitor branch, and does not have the jump change of first disconnecting the 2 capacitors that have been accessed and then accessing 1 capacitor, like binary coding (such as "0011" to "0100"). This can make the charging and discharging speed of the RC circuit more stable, thereby making the frequency jitter of the second clock signal CLK_OUT more linear and without sudden change, especially suitable for EMI suppression scenarios (such as scenarios in automotive electronics that need to avoid frequency jump interference with radio signals) that require higher timing stability, while maintaining the same core logic as binary coding, balancing the adjustment accuracy and timing smoothness.

[0055] In an embodiment of the present application, as shown in Figure 3 The delay output module 102 further includes a first inverter INV1 and a second inverter INV2. The input terminal of the first inverter INV1 is used to receive the first clock signal, the output terminal of the first inverter INV1 is electrically connected with the input terminal of the second inverter INV2, and the output terminal of the second inverter INV2 is respectively electrically connected with the switch unit 1021 and all the first delay units 1022.

[0056] Specifically, the first inverter INV1 and the second inverter INV2 constitute a two-stage inverting buffer structure, and the core function is to perform signal conditioning and driving capability enhancement on the input first clock signal, to provide a reliable timing reference for the stable operation of the subsequent switching unit 1021 and the first delay unit 1022. Specifically, the first inverter INV1 first receives the first clock signal inside the switching power supply, performs the first inversion of the signal while shaping the signal edge, and can filter out the slight noise or edge burr that the first clock signal may carry in the transmission process, to ensure that the signal has a steeper high / low level transition and more accurate timing, and to avoid affecting the working stability of the subsequent circuit due to the original signal quality problem. Subsequently, the signal shaped by the first inverter INV1 is input to the second inverter INV2, and the second inverter INV2 inverts the signal for the second time, so that the phase of the final output signal remains consistent with the original first clock signal (offsetting the phase flip of the first inverter INV1 to ensure that the timing logic is not disordered). On the other hand, through the cascade amplification of the two-stage inverter, the driving capability of the clock signal is significantly improved. Since the on / off of the subsequent switching unit 1021 requires sufficient signal driving strength, and multiple first delay units 1022 need to receive synchronous clock signals at the same time, the signal output by the two-stage inverter can provide stable current driving for these loads, avoid problems such as switching unit 1021 switching delay, poor clock synchronization of each first delay unit 1022, and finally ensure that the charge / discharge timing of the entire RC delay architecture is accurate, and each module works stably, to provide a reliable basic clock guarantee for the jitter characteristics of the second clock signal CLK_OUT.

[0057] In an embodiment of the present application, as shown in Figure 3 The delay output module 102 further includes a third inverter INV3, the input end of the third inverter INV3 is electrically connected with all the first delay units 1022 and the switching unit 1021 respectively, and the output end of the third inverter INV3 is electrically connected with the control module 20.

[0058] Specifically, the third inverter INV3 is used for final conditioning of the signal processed by the switching unit 1021 and the first delay unit 1022, to ensure that the second clock signal CLK_OUT output to the control module 20 meets the timing and level requirements. Specifically, the first voltage signal (charge-discharge waveform) processed by the RC delay adjustment may present a slowly varying analog characteristic or a noisy edge, and the third inverter INV3 shapes such slowly varying signals into steeply jumping digital pulse signals through its steep voltage flipping characteristic, clearly distinguishes the high / low level state, and eliminates the ambiguous area in signal transmission. At the same time, the output level of the third inverter INV3 can be accurately matched with the input level standard of the control module 20, avoiding signal recognition errors caused by incompatible levels. In addition, as the last stage of buffering before signal output, the third inverter INV3 can also enhance the driving capability of the second clock signal CLK_OUT, ensuring that it remains stable during transmission to the control module 20 and is not affected by load changes, and finally provides the control module 20 with a jitter clock signal that is clear in timing, adapted in level, and reliable in driving, ensuring the accurate execution of the entire dithering control logic.

[0059] The working principle of the delay output module 102 provided by another embodiment of the present application will be described in detail below in conjunction with the circuit schematic diagram shown in the figure. Figure 4 to Figure 7 The working principle of the delay output module 102 provided by another embodiment of the present application will be described in detail below in conjunction with the circuit schematic diagram shown in the figure.

[0060] In an embodiment of the present application, as shown in the figure, the delay output module 102 includes a multiplexing unit 1023 and a plurality of second delay units 1024, all of the second delay units 1024 are electrically connected in sequence, the multiplexing unit 1023 is electrically connected with all of the second delay units 1024 and the logic module 101 respectively, and the multiplexing unit 1023 is electrically connected with the control module 20. Figure 4 Specifically, the plurality of second delay units 1024 cooperates with the multiplexing unit 1023 to realize multi-gear delay and accurate gating of the clock signal, and provides flexible timing adjustment capability for the dithering function. Among them, the plurality of second delay units 1024 adopts a cascaded structure (i.e. the output end of a previous second delay unit 1024 is connected to the input end of a subsequent second delay unit 1024) electrically connected in sequence. After the first clock signal is input from the first second delay unit 1024, a fixed delay time length is added after passing through each second delay unit 1024. Finally, each second delay unit 1024 can output a delay clock signal corresponding to the delay time length (for example, the first unit outputs a signal with a delay of t1, the second unit outputs a signal with a delay of t1+t2, and so on, forming a multi-gear delay clock sequence). Through cascading design, the number of delay time length gears can be easily expanded to meet different dithering range requirements.

[0061]

[0062] ​The multiplexing unit 1023 is a gating hub for signal output, the input end of which is connected to the output end of all second delay units 1024 and the input end of the first second delay unit 1024 to obtain signals of all delay time lengths, and the control end is used for receiving a control signal. In operation, the multiplexing unit 1023 will accurately gate a signal meeting the current dithering frequency requirement from all delay clock signals as the second clock signal CLK_OUT according to the control signal (such as a binary coded signal or a thermometer code, wherein 4 bits correspond to the setting of 16 second delay units 1024 to realize 16 different frequencies of delay, and the number of second delay units 1024 can be increased / decreased according to actual needs) output by the logic module 101, and output it to the control module 20. This design can not only realize the stepwise coverage of the delay time length through the cascade of the second delay units 1024, but also make the delay time length of the second clock signal CLK_OUT change flexibly with the control signal through the rapid switching of the multiplexing unit 1023, so as to generate a clock signal with preset dithering characteristics, effectively support the dithering frequency control function, and at the same time, the circuit structure is simple, the adjustment precision is controllable, and it is suitable for the EMI suppression needs of switching power supplies in different scenes.

[0063] For example, through the design of the above-mentioned delay output module 102, the logic module 101 can have different ways of output, such as triangular wave mode or pseudo-random mode, etc.

[0064] If the triangular wave mode is selected, taking 4-bit output as an example, each period realizes from 0000 to 1111 and then back to 0000 as a complete period. The encoding method can also use other methods, such as thermometer code, etc. Through the encoding method, the number of delay modules is gradually increased from 0 to the maximum value, and then decreased to zero to complete a period. Figure 5

[0065] The final frequency change is shown in Figure 6 The oscillator output frequency is from fmin to fmax and then decreases to fmin according to the triangular wave. The key parameters of the design are fmin and fmax and the period Tmod of the triangular wave.

[0066] However, the triangular wave mode has the problem that each frequency point can only be maintained for one period, and if the next period has the same delay, the frequency value is equal to the input frequency. Therefore, in order to obtain better dithering frequency effect, a pseudo-random mode can be used, and a four-bit pseudo-random code is generated internally by the digital logic, which can better control the modulation frequency of the oscillator.

[0067] In an embodiment of the present application, as Figure 7 ​As shown, the multiplexing unit 1023 includes a multiplexer MUX, a plurality of first inputs of the multiplexer MUX are respectively connected to a plurality of second delay units 1024, a second input of the multiplexer MUX is connected to the logic module 101, and an output of the multiplexer MUX is configured to be connected to the control module 20.

[0068] Specifically, the multiplexer MUX as the core device of the multiplexing unit 1023 can accurately select the target signal from a plurality of delay clock signals, and is an important device for realizing the flexibility of the jitter control. The plurality of first inputs of the multiplexer MUX are connected to the plurality of second delay units 1024 one by one, and can synchronously receive clock signals of different delay time lengths (such as signals of delay t, 2t, 3t and 4t) output by the plurality of second delay units 1024, which cover all preset jitter levels. The second input of the multiplexer MUX is connected to the logic module 101 and receives a control signal for controlling the selection. In operation, the multiplexer MUX can quickly switch the internal path according to the control signal (such as encoding “00” corresponding to selecting the first path and “01” corresponding to selecting the second path) output by the logic module 101, select a signal meeting the current jitter requirement from the plurality of delay clock signals, and transmit the signal to the control module 20 as the second clock signal CLK_OUT through the output. This design can adjust the jitter level of the output clock only by the control signal of the logic module 101, ensure the rapidity and stability of the signal switching process, avoid the conflict caused by the parallel output of multiple signals, simplify the circuit structure (single output instead of multiple parallel outputs), reduce the complexity of the connection with the control module 20, and finally provide a precise and controllable jitter clock for the switching power supply, thereby efficiently supporting the EMI suppression function.

[0069] In an embodiment of the present application, as shown in Figure 7 The second delay unit 1024 includes a fourth inverter, an input of the fourth inverter and an output of the fourth inverter are connected to the multiplexing unit 1023, and INV4-1, INV4-2, …, INV4-n are the fourth inverters in the corresponding second delay units 1024.

[0070] Specifically, the fourth inverter, as the core delay and signal transmission device, achieves precise clock signal delay through its inherent transmission delay characteristics and provides a stable delayed clock signal for the multiplexer (MUX). Specifically, when the first clock signal is input to the fourth inverter, while performing signal logic inversion (high level to low level, low level to high level), the inverter generates a fixed transmission delay due to physical processes such as the charging and discharging of parasitic capacitances within the device (e.g., a delay duration of t0 introduced by each inverter stage). This delay characteristic causes the clock signal after the inverter to have a fixed time difference compared to the input signal, forming the delay duration corresponding to the second delay unit 1024. For multiple cascaded second delay units 1024, the output of each fourth inverter also serves as the input to the next stage of the second delay unit 1024. Through the cascading and superposition of multiple inverter stages, an increasing sequence of delay durations is formed (e.g., 2 stages of inverters correspond to a 2t0 delay, 3 stages correspond to a 3t0 delay). In addition, the digital logic characteristics of the fourth inverter can also shape the signal, ensuring that the delayed clock signal output to the multiplexer (MUX) has a steep edge and a clear level, providing a reliable signal foundation for subsequent gating logic. Finally, through the design of the number of cascaded inverters and the utilization of the inherent delay of the fourth inverter, precise control and flexible expansion of the delay duration can be achieved.

[0071] It should be noted that traditional solutions adjust the output frequency of an oscillator by periodically changing its resistance value, and achieve periodic modulation of the oscillator frequency by controlling the frequency change period. However, this method has significant limitations when a small jitter range (such as 1% frequency jitter) is required, namely, the jitter deviation of the resistor must be controlled within 1%, which is difficult to achieve precisely in actual manufacturing processes. This application, on the other hand, uses a delay control method to meet the low jitter range requirement. Not only is the circuit size much smaller than that of a conventional oscillator, but it also achieves frequency jitter by controlling the delay of the rising edge of the clock (which can be achieved using digital gate circuit delay or RC charging and discharging delay). The low jitter frequency target can be achieved by flexibly adjusting the delay duration, and the circuit implementation is simple and easy to adjust the modulation frequency.

[0072] Compared to Figure 4 The delay output module 102 shown is composed of a multiplexing unit 1023 and multiple (e.g., 16) second delay units 1024. Figure 2 and Figure 3 The delay output module 102 shown is composed of a switching unit 1021 and multiple (e.g., four) first delay units 1022. It can directly output the second clock signal CLK_OUT. Its 16 delay durations can be achieved by controlling the RC delay, and the overall circuit structure is more concise.

[0073] It should be noted that only two circuit structures of the delay output module 102 are shown in the embodiments provided in the present application, and it does not mean that only these two circuit structures can realize the function of the delay output module 102. Other circuit structures that can realize the function can also be replaced, and are not limited thereto.

[0074] The present application also discloses a switching power supply comprising a control module 20 and the above-mentioned frequency jitter control circuit 10, and the control module 20 is electrically connected with the delay output module 102 in the frequency jitter control circuit 10. By integrating the above-mentioned frequency jitter control circuit 10, the switching power supply can realize the jitter control of the high-frequency switching frequency by using the internal clock signal without increasing the cost of the independent oscillator hardware. Not only does it simplify the circuit structure, reduce the chip area occupation and production process cost, but also avoid the timing disorder problem caused by the double clock cooperation, ensure the stable output precision while realizing the EMI suppression, and balance the electromagnetic compatibility, cost advantage and working reliability, especially suitable for the scene (such as the power supply system of vehicle-mounted electronics and consumer smart devices) sensitive to EMI and strict cost control.

[0075] Since the processing and functions realized by the switching power supply in the present embodiment are basically corresponding to the embodiments, principles and examples of the above-mentioned frequency jitter control circuit, the description of the present embodiment is not detailed, and the related description in the above-mentioned embodiments can be referred to, and will not be repeated here.

[0076] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the above-mentioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the above-mentioned embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A dithering control circuit, characterized by, The logic module is electrically connected with the delay output module, and the delay output module is used for being electrically connected with a control module in a switching power supply; The logic module is used for outputting a control signal to the delay output module according to a preset signal; the delay output module is used for delaying a received first clock signal according to the control signal and outputting a second clock signal to the control module, wherein the first clock signal is a clock signal generated by frequency division of a high-frequency non-jitter clock integrated in the switching power supply for parameter detection; the delay processing of the delay output module on the first clock signal does not change the non-jitter attribute of the first clock signal; The delay output module comprises a switching unit and a plurality of first delay units, the switching unit is electrically connected with all the first delay units and the control module respectively, and each first delay unit is electrically connected with the logic module and the control module; The switching unit is used for outputting a first voltage signal according to the first clock signal; and the first delay unit is used for adjusting the frequency of the first voltage signal to obtain the second clock signal according to the control signal; The switching unit comprises a first switch tube and a second switch tube, the gate of the first switch tube and the gate of the second switch tube are used for receiving the first clock signal, the source of the first switch tube is electrically connected with a power supply, the drain of the first switch tube is electrically connected with the drain of the second switch tube, all the first delay units and the control module, and the source of the second switch tube is grounded; The first delay unit comprises a third switch tube, a fourth switch tube, a transmission gate and a first capacitor, the gate of the third switch tube is used for receiving the first clock signal, the source of the third switch tube is electrically connected with a power supply, the drain of the third switch tube is electrically connected with the source of the fourth switch tube, the gate of the fourth switch tube and the control end of the transmission gate are electrically connected with the logic module, the drain of the fourth switch tube is electrically connected with the switching unit, the first end of the transmission gate and the control module, the first end of the first capacitor is electrically connected with the second end of the transmission gate, and the second end of the first capacitor is grounded.

2. The dithering control circuit of claim 1, wherein, The delay output module further comprises a first inverter and a second inverter, the input end of the first inverter is used for receiving the first clock signal, the output end of the first inverter is electrically connected with the input end of the second inverter, and the output end of the second inverter is electrically connected with the switching unit and all the first delay units.

3. The dithered frequency control circuit of claim 1, wherein, The delay output module further comprises a third inverter, the input end of the third inverter is electrically connected with all the first delay units and the switching unit, and the output end of the third inverter is electrically connected with the control module.

4. A switching power supply, characterized by comprising: The delay output module further comprises a third inverter, the input end of the third inverter is electrically connected with all the first delay units and the switching unit, and the output end of the third inverter is electrically connected with the control module. The delay output module further comprises a third inverter, the input end of the third inverter is electrically connected with all the first delay units and the switching unit, and the output end of the third inverter is electrically connected with the control module.

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