Input channel expansion circuit and ADC circuit
By introducing gating decoding and switching circuits into the ADC circuit, dynamic configuration of the signal channel is achieved, which solves the signal distortion problem of the ADC circuit when processing signals of different frequencies and optimizes the transmission effect of low-frequency and high-frequency signals.
Patent Information
- Application Number
- CN202511044671.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-28
- Publication Date
- 2025-11-11
AI Technical Summary
Existing ADC circuits suffer from signal distortion when processing analog signals of different frequencies, especially the over-margin design for low-frequency signals, which leads to distortion of high-frequency signals.
By designing an input channel extension circuit, a dynamic configuration of the signal channel is achieved using a gating decoding circuit and a gating switch circuit. The signal channels are turned on individually for low-frequency signals and connected in parallel for high-frequency signals to reduce nonlinear on-resistance and meet the transmission requirements of signals of different frequencies.
The ADC circuit has been optimized for transmitting low-frequency and high-frequency analog signals, reducing the total harmonic distortion of high-frequency signals and meeting the application requirements of multiple input channels.
Smart Images
Figure CN120934518A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to an input channel extension circuit and an ADC circuit. Background Technology
[0002] Analog-to-digital converters (ADCs) are a commonly used functional module in SoCs. Common SoCs, such as MCUs, often have multi-channel ADC applications. For example, one channel is used to process temperature signals, and another channel is used to process dynamic signals such as motor speed. In design, it is common practice to design each input channel of the ADC to be identical. However, in the application stage, since temperature is a low-frequency analog signal and motor speed is a high-frequency analog signal, the same channel transmission circuit is over-marginalized for temperature signals and under-marginalized for motor speed signals, which will lead to signal distortion. Summary of the Invention
[0003] The purpose of this invention is to provide an input channel expansion circuit and an ADC circuit to solve the problem that current ADC circuits cannot meet the application requirements of different analog signal inputs.
[0004] To address the aforementioned technical problems, based on one aspect of the present invention, an input channel expansion circuit is provided, comprising:
[0005] The strobe decoding circuit has a first signal port and a second signal port. The first signal port is used to receive a control signal, the second signal port is used to receive an enable signal, and the output port is used to output a decoding signal.
[0006] The gating switch circuit has multiple signal channels. The input terminal of each signal channel receives an analog signal, and the output terminal of each signal channel is connected to a sampling circuit. When the signal channel is turned on, the analog signal is transmitted to the sampling circuit.
[0007] Specifically, when the enable signal is a first set signal, the strobe decoding circuit controls at least one of the signal channels to be turned on according to the control signal; when the enable signal is a second set signal, the strobe decoding circuit controls multiple of the signal channels to be turned on according to the control signal, and groups at least two of the signal channels together, controlling all the signal channels in a group to be connected in parallel.
[0008] Optionally, the first set signal is low and the second set signal is high.
[0009] Optionally, the gating decoding circuit further includes an output port, wherein the gating decoding circuit decodes the control signal into the decoded signal and outputs it from the output port to the gating switch circuit.
[0010] Optionally, when the enable signal is the second set signal, the gating decoding circuit controls the signal channels to be grouped in pairs and connected in parallel.
[0011] Optionally, the signal channel includes a CMOS switch, and the gating decoding circuit controls the CMOS switch to be turned on or off.
[0012] Optionally, the CMOS switch includes an NMOS transistor and a PMOS transistor, and the signal channel further includes an inverter. The gate of the NMOS transistor is connected to the gating and decoding circuit, the gate of the PMOS transistor is connected to the output terminal of the inverter, the input terminal of the inverter is connected to the gating and decoding circuit, the source of the NMOS transistor and the source of the PMOS transistor are connected as the input terminal of the signal channel, and the drain of the NMOS transistor and the drain of the PMOS transistor are connected as the output terminal of the signal channel.
[0013] According to another aspect of the present invention, the present invention also provides an ADC circuit, which includes a sampling circuit and an input channel extension circuit as described above.
[0014] Optionally, the sampling circuit includes a sampling capacitor.
[0015] Optionally, the signal channel of the input channel expansion circuit is connected to the sampling circuit via a sampling switch.
[0016] Optionally, the ADC circuit further includes a quantization circuit, which is connected to the sampling circuit.
[0017] As shown in the above input channel expansion circuit, when the enable signal is the first set signal, the corresponding signal channel can be selected to be turned on by the gating decoding circuit. At this time, the nonlinear on-resistance of the signal channel is the original default value, which can support the input of low-frequency analog signals. When the enable signal is the second set signal, the parallel signal channels in a group can be considered as combined into one channel for use, thereby transmitting the same analog signal. The parallel connection of at least two signal channels can reduce the overall nonlinear on-resistance of the signal channel, which can greatly optimize the total harmonic distortion of the input high-frequency analog signal. That is, the parallel connection of signal channels can support the input of high-frequency analog signals. Thus, the design of this invention can meet the requirements of multiple input channels of ADC, as well as the transmission requirements of low-frequency and high-frequency analog signals.
[0018] It should be noted that since the ADC circuit includes the input channel expansion circuit, it also has the technical effects brought by the input channel expansion circuit, which will not be repeated here. Attached Figure Description
[0019] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0020] Figure 1 This is a schematic diagram of an input channel expansion circuit according to an embodiment of the present invention;
[0021] Figure 2 This is a schematic diagram of a gating switch circuit according to an embodiment of the present invention;
[0022] Figure 3 This is a schematic diagram of an ADC circuit according to an embodiment of the present invention. Detailed Implementation
[0023] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.
[0024] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature. “One end” and “the other end,” as well as “proximal end” and “distal end,” generally refer to two corresponding parts, including not only endpoints. The terms “installed,” “connected,” and “joined” should be interpreted broadly, for example, as a fixed connection, a detachable connection, or an integral part; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or a connection within two elements or an interaction between two elements. Furthermore, as used in this invention, the phrase "one element is disposed on another element" generally only indicates that there is a connection, coupling, cooperation, or transmission relationship between the two elements, and the connection, coupling, cooperation, or transmission between the two elements can be direct or indirect through an intermediate element. It should not be construed as indicating or implying a spatial positional relationship between the two elements, i.e., one element can be located arbitrarily inside, outside, above, below, or to one side of the other element, unless otherwise explicitly stated. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0025] Figure 1 This is a schematic diagram of an input channel expansion circuit according to an embodiment of the present invention. (See attached diagram.) Figure 1 This invention schematically provides an input channel expansion circuit for an ADC circuit, including a decoder circuit (Decode) and a strobe switch circuit (MUX). The decoder circuit (Decode) has a first signal port and a second signal port. The first signal port is used to receive a control signal S<1:M>, and the second signal port is used to receive an enable signal HFIN. The output port is used to output a decoded signal CH<1:2N>. The strobe switch circuit (MUX) has multiple signal channels. The input terminal of each signal channel receives an analog signal Vin<1:2N>, and the output terminal of each signal channel is connected to a sampling circuit. When the signal channel is turned on, it transmits the analog signal Vin<1:2N> to the sampling circuit. (See reference...) Figure 1The analog signal transmitted through the gating switch circuit MUX is denoted as signal VS. When the enable signal HFIN is the first set signal, the gating decoder circuit Decode controls at least one of the signal channels to be turned on according to the control signal S<1:M>; when the enable signal HFIN is the second set signal, the gating decoder circuit Decode controls multiple signal channels to be turned on according to the control signal S<1:M>, and groups at least two signal channels together, controlling all signal channels in a group to be connected in parallel. In one embodiment, the first set signal is low level and the second set signal is high level.
[0026] As shown in the above input channel expansion circuit, when the enable signal HFIN is the first set signal, the corresponding signal channel can be selected to be turned on by the decoder circuit. At this time, the nonlinear on-resistance of the signal channel is the original default value, which can support the input of low-frequency analog signals. When the enable signal HFIN is the second set signal, the parallel signal channels in a group can be considered as combined into one channel for use, thereby transmitting the same analog signal. The parallel connection of at least two signal channels can reduce the overall nonlinear on-resistance of the signal channel, which can greatly optimize the total harmonic distortion of the input high-frequency analog signal. That is, the parallel connection of signal channels can support the input of high-frequency analog signals. Thus, the design of this invention can meet the requirements of multiple input channels of ADC, as well as the transmission requirements of low-frequency and high-frequency analog signals Vin<1:2N>.
[0027] Optionally, the strobe decoding circuit Decode further includes an output port. The strobe decoding circuit Decode decodes the control signal S<1:M> into the decoded signal CH<1:2N> and outputs it from the output port to the strobe switch circuit MUX. The strobe decoding circuit Decode controls the signal channel to be turned on or off according to the decoded signal CH<1:2N> converted from the control signal S<1:M>.
[0028] In one embodiment, when the enable signal HFIN is the second set signal, the decoder circuit Decode controls the signal channels to be grouped in pairs and connected in parallel. Thus, the number of signal channels can be set to an even number, controlling each pair to be grouped in parallel, thereby halving the number of effective signal channels.
[0029] Figure 2 This is a schematic diagram of a selection switch circuit according to an embodiment of the present invention. (See attached diagram.) Figure 2 The signal channel includes a CMOS switch, and the strobe decoding circuit Decode controls the CMOS switch to be turned on or off, thus using the CMOS switch as a signal channel.
[0030] In one embodiment, see Figure 2 When the ADC circuit is applied to low-frequency analog signal input, the enable signal HFIN is set to the first set signal. At this time, the gating switch circuit MUX has independent 2N signal channels. The decoded signal CH<1:2N> obtained by decoding S<1:M> determines which signal channel is connected to the sampling circuit. The decoded signal CH<1:2N> is divided into 2N signals, including signal CH <1> CH <2> CH<2N>, ..., CH<2N>, correspond to 2N signal channels, and each signal channel is controlled independently. When the ADC circuit is applied to a higher frequency analog signal input, the enable signal HFIN is set to the second set signal. At this time, logically, the decoded signal converted from the control signal S<1:M> generates N control signals. In application, Vin... <1> Connect to Vin <2> Vin <3> Connect to Vin <4> , ..., Vin<2N-1> connects to Vin<2N>, thereby halving the control signal. The input channels are connected in parallel to each other, which also halves the number of effective signal channels. The overall nonlinear on-resistance of the signal channels is reduced, which can greatly optimize the total harmonic distortion of the input high-frequency analog signal.
[0031] Continue reading Figure 2 The CMOS switch includes an NMOS transistor P1 and a PMOS transistor P2. The signal channel also includes an inverter INV. The gate of the NMOS transistor P1 is connected to the Decode strobe decoding circuit. The gate of the PMOS transistor P2 is connected to the output terminal of the inverter INV. The input terminal of the inverter INV is connected to the Decode strobe decoding circuit. The sources of the NMOS transistor P1 and the PMOS transistor P2 are connected as the input terminal of the signal channel. The drains of the NMOS transistor P1 and the PMOS transistor P2 are connected as the output terminal of the signal channel.
[0032] Figure 3 This is a schematic diagram of an ADC circuit according to an embodiment of the present invention. (See attached diagram.) Figure 3 Based on the above-mentioned input channel, the present invention also provides an ADC circuit, which includes a sampling circuit and an input channel extension circuit as described above.
[0033] Optionally, the sampling circuit includes a sampling capacitor C.
[0034] Optionally, the signal channel of the input channel expansion circuit is connected to the sampling circuit via a sampling switch Sx.
[0035] Optionally, the ADC circuit further includes a quantization circuit Quant, which is connected to the sampling circuit. The sampling circuit samples the analog signal Vin<1:2N> to obtain a discrete signal, and the quantization circuit Quant performs quantization processing on the discrete signal to obtain a digital signal.
[0036] While the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the scope of protection of the present invention.
Claims
1. An input channel expansion circuit, characterized in that, include: The strobe decoding circuit has a first signal port and a second signal port. The first signal port is used to receive a control signal, the second signal port is used to receive an enable signal, and the output port is used to output a decoding signal. The gating switch circuit has multiple signal channels. The input terminal of each signal channel receives an analog signal, and the output terminal of each signal channel is connected to a sampling circuit. When the signal channel is turned on, the analog signal is transmitted to the sampling circuit. Specifically, when the enable signal is a first set signal, the strobe decoding circuit controls at least one of the signal channels to be turned on according to the control signal; when the enable signal is a second set signal, the strobe decoding circuit controls multiple of the signal channels to be turned on according to the control signal, and groups at least two of the signal channels together, controlling all the signal channels in a group to be connected in parallel.
2. The input channel expansion circuit according to claim 1, characterized in that, The first set signal is at a low level, and the second set signal is at a high level.
3. The input channel expansion circuit according to claim 1, characterized in that, The gating decoding circuit also includes an output port, which decodes the control signal into the decoded signal and outputs it to the gating switch circuit from the output port.
4. The input channel expansion circuit according to claim 1, characterized in that, When the enable signal is the second set signal, the gating decoding circuit controls the signal channels to be grouped in pairs and connected in parallel.
5. The input channel expansion circuit according to claim 1, characterized in that, The signal channel includes a CMOS switch, and the gating decoding circuit controls the CMOS switch to be turned on or off.
6. The input channel expansion circuit according to claim 5, characterized in that, The CMOS switch includes an NMOS transistor and a PMOS transistor. The signal channel also includes an inverter. The gate of the NMOS transistor is connected to the gating and decoding circuit. The gate of the PMOS transistor is connected to the output terminal of the inverter. The input terminal of the inverter is connected to the gating and decoding circuit. The sources of the NMOS transistor and the PMOS transistor are connected as the input terminal of the signal channel. The drains of the NMOS transistor and the PMOS transistor are connected as the output terminal of the signal channel.
7. An ADC circuit, characterized in that, It includes a sampling circuit and an input channel expansion circuit as described in any one of claims 1-6.
8. The ADC circuit according to claim 7, characterized in that, The sampling circuit includes a sampling capacitor.
9. The ADC circuit according to claim 7, characterized in that, The signal channel of the input channel expansion circuit is connected to the sampling circuit via a sampling switch.
10. The ADC circuit according to claim 7, characterized in that, The ADC circuit also includes a quantization circuit, which is connected to the sampling circuit.