Decoding method and device, electronic equipment and storage medium

Abstract

Embodiments of the present disclosure provide a decoding method and device, electronic equipment and storage medium, relating to the technical field of decoding, and the method comprises: obtaining code word sequence data to be decoded; in the first iteration, if the syndrome of the code word sequence data is not a zero vector, flipping the first information bit in the code word sequence data; updating the syndrome of the code word sequence data according to the flipping change amount of the first information bit; if the updated syndrome of the code word sequence data is not a zero vector, updating the bit flipping threshold, determining the updated code word sequence data as the code word sequence data, updating I = I + 1, and returning to execute the step of flipping the first information bit in the code word sequence data until the syndrome of the code word sequence data is a zero vector or I = J. In this way, not only the decoding rate can be improved, but also the problem of large consumption of computing resources caused by global calculation can be avoided, and the resource consumption is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of decoding technology, and in particular to a decoding method, apparatus, electronic device and storage medium. Background Technology

[0002] In the hard-decision decoding of Low Density Parity Check Code (LDPC), bit-flipping algorithms can locate and correct erroneous bits generated during transmission using parity equations. However, existing bit-flipping algorithms suffer from problems such as low decoding speed and high resource consumption during the decoding process. Summary of the Invention

[0003] This disclosure provides a decoding method, apparatus, electronic device, and storage medium to at least solve the above-mentioned technical problems existing in the prior art.

[0004] In a first aspect, embodiments of this disclosure provide a decoding method, the method comprising:

[0005] Obtain the codeword sequence data to be decoded;

[0006] In the I-th iteration, when the checksum of the codeword sequence data is not a zero vector, the first information bit in the codeword sequence data is flipped. The number of non-zero checksums of the first information bit is greater than or equal to the bit flipping threshold. The number of non-zero checksums of the first information bit is determined based on the checksum of the codeword sequence data.

[0007] Update the checksum of the codeword sequence data according to the amount of flip change of the first information bit;

[0008] If the checksum of the updated codeword sequence data is not a zero vector, update the bit flipping threshold, determine the updated codeword sequence data as the codeword sequence data, update I=I+1, and return to the step of flipping the first information bit in the codeword sequence data until the checksum of the updated codeword sequence data is a zero vector, or I=J, where J is the preset iteration number, and I and J are both positive integers.

[0009] Secondly, embodiments of this disclosure provide a decoding apparatus, the apparatus comprising:

[0010] The acquisition module is used to acquire the codeword sequence data to be decoded;

[0011] The flipping module is used in the I-th iteration to flip the first information bit in the codeword sequence data when the checksum of the codeword sequence data is not a zero vector. The number of non-zero checksums of the first information bit is greater than or equal to the bit flipping threshold. The number of non-zero checksums of the first information bit is determined based on the checksum of the codeword sequence data.

[0012] The update module is used to update the checksum of the codeword sequence data according to the amount of flip change of the first information bit.

[0013] The update module is further configured to update the bit flipping threshold when the checksum of the updated codeword sequence data is not a zero vector, and determine that the updated codeword sequence data is the codeword sequence data, update I=I+1, and return to the step of performing the flipping of the first information bit in the codeword sequence data until the checksum of the codeword sequence data is a zero vector, or I=J, where J is a preset iteration number, and I and J are both positive integers.

[0014] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform any of the decoding methods.

[0015] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform any decoding method.

[0016] Based on the decoding method provided in this embodiment, the codeword sequence data to be decoded can be obtained. In I iterations, if the checksum of the codeword sequence data is not a zero vector, it indicates that the codeword sequence data has changed during transmission, i.e., the codeword sequence data is an erroneous codeword sequence data. Then, the first information bit in the codeword sequence data with a number of non-zero checksums greater than or equal to the bit flipping threshold can be flipped. The checksum of the codeword sequence data can be updated synchronously according to the flipping change of the first information bit. Thus, when the checksum of the updated codeword sequence data is not a zero vector, the bit flipping threshold can be updated, and the updated codeword sequence data can be determined to be the codeword sequence data. The iteration count is updated until the checksum of the updated codeword sequence data is a zero vector, or the iteration count reaches the preset maximum iteration count and stops, thus obtaining the final decoding result. In this way, not only can the convergence of codeword sequence data be accelerated by dynamically adjusting the bit flipping threshold of each information bit in real time during each iteration, thereby improving the decoding rate, but the checksum of the codeword sequence data can also be synchronously updated directly by flipping the information bits, avoiding the problem of large computational resource consumption caused by global calculation and reducing resource consumption.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a decoder provided in an embodiment of the present disclosure;

[0019] Figure 2 This is one of the flowcharts illustrating a decoding method provided in this embodiment of the present disclosure;

[0020] Figure 3 This is a schematic diagram illustrating the relationship between the SW value and the number of error information bits provided in an embodiment of this disclosure;

[0021] Figure 4 This is a second schematic flowchart of a decoding method provided in this embodiment of the present disclosure;

[0022] Figure 5 This is one of the performance comparison diagrams between the decoding method provided in this embodiment and the traditional decoding method.

[0023] Figure 6 This is the second schematic diagram comparing the performance of a decoding method provided in this embodiment of the present disclosure with that of a traditional decoding method;

[0024] Figure 7 This is a schematic diagram of the structure of a decoding device provided in an embodiment of the present disclosure;

[0025] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0026] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0027] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0030] Before providing a further detailed description of the embodiments of this disclosure, the nouns and terms involved in the embodiments of this disclosure will be explained, and the nouns and terms involved in the embodiments of this disclosure shall be interpreted as follows.

[0031] In the hard-decision decoding mechanism of LDPC codes, the sending end constructs a valid codeword sequence data based on the parity check matrix H. It needs to satisfy the linear constraint condition of the parity check matrix H, that is... This indicates that the codeword sequence data is error-free. However, due to the codeword sequence data... During channel transmission, noise interference may occur, causing the codeword sequence data received by the receiver to be affected. = The offset from the original state can be represented as = + .in, For error vectors, this interference will break The balance.

[0032] In related technologies, the bit-flipping algorithm is crucial for the hard-decision decoding process of LDPC. Traditional bit-flipping algorithms typically determine whether to flip the corresponding received bit by comparing the number of non-compliance checks in the corresponding parity check equation with a fixed bit-flipping threshold for each received bit. The setting of the bit-flipping threshold significantly impacts the decoding performance. Specifically, if the threshold is set too high, it significantly increases the number of decoding iterations, thus reducing the decoding rate. Conversely, if the threshold is set too low, it can easily lead to false flips, which also increases the number of decoding iterations, reducing the decoding rate, and in severe cases, may even cause decoding failure. Therefore, traditional bit-flipping algorithms have a low decoding rate and often require significant time, making them unsuitable for hardware implementation.

[0033] To address the aforementioned issues, some methods exist that dynamically adjust the bit-flipping threshold to improve decoding speed. However, existing methods cannot dynamically adjust the bit-flipping threshold for each received bit, resulting in persistently low decoding speeds. Furthermore, existing techniques require the product of the received vector and the transpose of the parity-check matrix (i.e., ...) in each iteration. Performing global verification results in significant consumption of computing resources.

[0034] To address the aforementioned issues, this disclosure provides a decoding method. Based on this method, a codeword sequence data to be decoded can be acquired. In I iterations, if the checksum of the codeword sequence data is not a zero vector, it indicates that the codeword sequence data has changed during transmission, meaning it is an erroneous codeword sequence data. In this case, the first information bit in the codeword sequence data, where the number of non-zero checksums is greater than or equal to a bit-flipping threshold, can be flipped. The checksum of the codeword sequence data can be updated synchronously based on the flipping change of the first information bit. Thus, even if the updated checksum of the codeword sequence data is not a zero vector, the bit-flipping threshold can be updated, and the updated codeword sequence data can be identified as the correct codeword sequence data. The iteration count is then updated until the updated checksum of the codeword sequence data is a zero vector, or until the iteration count reaches a preset maximum iteration count, at which point the final decoding result is obtained. In this way, not only can the convergence of codeword sequence data be accelerated by dynamically adjusting the bit flipping threshold of each information bit in real time during each iteration, thereby improving the decoding rate, but the checksum of the codeword sequence data can also be synchronously updated directly by flipping the information bits, avoiding the problem of large computational resource consumption caused by global calculation and reducing resource consumption.

[0035] Since the decoding method provided in this disclosure can be applied to a decoder, in order to describe the decoding method provided in this disclosure in more detail and accurately, the decoder provided in this disclosure will be introduced first before introducing the decoding method provided in this disclosure.

[0036] Figure 1 This is a schematic diagram of the structure of a decoder provided in an embodiment of this application.

[0037] like Figure 1 As shown, the decoder 100 may include a verification module 11, a Syndrome Weight (SW) value calculation module 12, a non-zero checksum statistics module 13, and a bit flipping module 14.

[0038] The verification module 11 is used to acquire codeword sequence data and verify the codeword sequence data to obtain the corresponding checksum. It should be noted that there are two methods for verifying the codeword sequence data: global calculation and incremental calculation. The global calculation method refers to the process of verifying the codeword sequence data during the first iteration. The codeword sequence data initially acquired is verified using the following method to obtain the corresponding checksum. Incremental calculation refers to the process in which, for information bits that have flipped, the verification results of several check equations corresponding to that information bit are locally updated during subsequent iterations to verify the codeword sequence data. It should be noted that the verification results of the several check equations corresponding to that information bit can be determined based on the checksum of the codeword sequence data obtained in the previous iteration. Alternatively, the codeword sequence data can also be verified using a global calculation method during subsequent iterations; this embodiment does not specifically limit this method. Thus, if the checksum of the codeword sequence data output by the verification module 11 is a zero vector, it indicates that the codeword sequence data has passed verification, and the decoding result, i.e., the verified codeword sequence data, can be directly output. If the checksum of the codeword sequence data output by the verification module 11 is not a zero vector, it indicates that the codeword sequence data has failed verification, and the codeword sequence data can be verified according to... Figure 1 The decoding process shown continues to iterate until the checksum of the codeword sequence data is a zero vector, or until the number of iterations equals the preset number of iterations. This preset number of iterations can be the maximum number of iterations pre-set based on actual experience or circumstances.

[0039] The aforementioned SW value calculation module 12 is used, during the first iteration, to calculate the number of codeword sequence data that do not meet the verification equation, i.e., the SW value, based on the checksum of the codeword sequence data output by the verification module 11, if the checksum of the codeword sequence data is not zero (i.e., the codeword sequence data verification fails). Since the SW value is positively correlated with the number of error information bits in the codeword sequence data, the number of error information bits in the codeword sequence data can be determined by comparing the SW value with the SW threshold. If the SW value is less than the SW threshold, it indicates that the number of error information bits in the codeword sequence data meets the decoding range of the decoder, and the subsequent decoding process can continue. Otherwise, the decoding of the next codeword sequence data will begin directly.

[0040] The non-zero checksum counting module 13 is used to count the number of check equations that are not true for each information bit in the codeword sequence data, i.e., the number of non-zero checksums. It can also determine the maximum number of non-zero checksums based on the number of non-zero checksums for each information bit, which is used to subsequently update the bit flip threshold.

[0041] The bit-flipping module 14 is used to determine whether to flip an information bit based on a comparison between the number of non-zero parity checkpoints in each information bit of the codeword sequence data and a bit-flipping threshold. Specifically, if the number of non-zero parity checkpoints in the information bit is greater than or equal to the bit-flipping threshold, the information bit needs to be flipped; if the number of non-zero parity checkpoints is less than the bit-flipping threshold, the information bit does not need to be flipped. It should be noted that the initial bit-flipping threshold used in the first iteration can be the maximum column weight of the parity check matrix. In subsequent iterations, the bit-flipping threshold can be either the maximum number of non-zero parity checkpoints in the codeword sequence data updated in the previous iteration or the maximum number of non-zero parity checkpoints in the codeword sequence data updated in the current iteration; no specific limitation is made here.

[0042] Based on such Figure 1 The decoder shown below, with reference to the accompanying drawings, will be described in detail with reference to specific embodiments of the present disclosure regarding the decoding method provided.

[0043] Figure 2 This is one of the flowcharts illustrating a decoding method provided in this embodiment.

[0044] like Figure 2 As shown, the execution entity of this method can be a decoder. Based on this, the method can specifically include the following steps:

[0045] S210, Obtain the codeword sequence data to be decoded.

[0046] The codeword sequence data can be the codeword sequence data that needs error correction. This codeword sequence data can be LDPC code or quasi-cyclic low-density parity-check code (QC-LDPC), without specific limitations here. It should be noted that if it is QC-LDPC, the information within the same submatrix can be processed in parallel during the following steps, which will not be elaborated further here.

[0047] S220, in the I-th iteration, if the checksum of the codeword sequence data is not a zero vector, flip the first information bit in the codeword sequence data.

[0048] The checksum of the codeword sequence data can be the product of the codeword sequence data and the transpose of the checksum matrix, i.e. The result is as follows. It should be noted that if the checksum of the codeword sequence data is a zero vector, it indicates that the codeword sequence data has not been altered by noise interference during transmission, meaning the codeword sequence data is correct. If the checksum of the codeword sequence data is not a zero vector, it indicates that the codeword sequence data has been altered due to noise interference during transmission, meaning the codeword sequence data is incorrect.

[0049] Furthermore, the aforementioned codeword sequence data may include multiple information bits, and the aforementioned first information bit may be an information bit among these multiple information bits whose number of non-zero checksums is greater than or equal to a bit-flipping threshold, that is, the number of non-zero checksums of the first information bit is greater than or equal to the bit-flipping threshold. The number of non-zero checksums of the information bits can be determined based on the checksums of the codeword sequence data, and correspondingly, the number of non-zero checksums of the first information bit can be determined based on the checksums of the codeword sequence data. Additionally, the aforementioned bit-flipping threshold may be preset based on practical experience or circumstances, and is not specifically limited here.

[0050] S230, update the checksum of the codeword sequence data according to the amount of flip change of the first information bit.

[0051] The amount of change in the first information bit can be the change between the bit value before and after the first information bit is flipped. It should be noted that since codeword sequence data is generally composed of binary data, if the first information bit is flipped, whether from "1" to "0" or from "0" to "1", the amount of change in the first information bit is always 1.

[0052] S240, if the checksum of the updated codeword sequence data is not a zero vector, update the bit flipping threshold, determine that the updated codeword sequence data is codeword sequence data, update I=I+1, and return to the step of performing the flipping of the first information bit in the codeword sequence data until the checksum of the codeword sequence data is a zero vector, or I=J.

[0053] Where J is the preset number of iterations, which can be the maximum number of iterations preset based on actual experience or circumstances, and is not specifically limited here. In addition, I and J are both positive integers.

[0054] Thus, the decoder can acquire the codeword sequence data to be decoded, and in the I-th iteration, it can determine whether the codeword sequence has changed during transmission by checking if the checksum of the codeword sequence data is a zero vector. Specifically, if the checksum of the codeword sequence data is not a zero vector, it indicates that the codeword sequence data has changed during transmission. At this time, it is necessary to flip the first information bit in the codeword sequence data whose number of non-zero checksums is greater than or equal to the bit flipping threshold. Based on the amount of flipping change of the first information bit, the checksum of the codeword sequence data can be directly and synchronously updated. Then, it can be determined whether the checksum of the updated codeword sequence data is a zero vector. If the checksum of the updated codeword sequence data is also not a zero vector, the bit flipping threshold is updated, and the updated codeword sequence data is determined to be codeword sequence data. I is updated to I+1, that is, the iteration count is updated, and the process of flipping the first information bit in the codeword sequence data is repeated until the checksum of the codeword sequence data is a zero vector, or I=J, that is, the iteration count reaches the preset iteration count and the loop stops, obtaining the final decoding result.

[0055] Based on the decoding method provided in this embodiment, the codeword sequence data to be decoded can be obtained. In I iterations, if the checksum of the codeword sequence data is not a zero vector, it indicates that the codeword sequence data has changed during transmission, i.e., the codeword sequence data is an erroneous codeword sequence data. Then, the first information bit in the codeword sequence data with a number of non-zero checksums greater than or equal to the bit flipping threshold can be flipped. The checksum of the codeword sequence data can be updated synchronously according to the flipping change of the first information bit. Thus, when the checksum of the updated codeword sequence data is not a zero vector, the bit flipping threshold can be updated, and the updated codeword sequence data can be determined to be the codeword sequence data. The iteration count is updated until the checksum of the updated codeword sequence data is a zero vector, or the iteration count reaches the preset maximum iteration count and stops, thus obtaining the final decoding result. In this way, not only can the convergence of codeword sequence data be accelerated by dynamically adjusting the bit flipping threshold of each information bit in real time during each iteration, thereby improving the decoding rate, but the checksum of the codeword sequence data can also be synchronously updated directly by flipping the information bits, avoiding the problem of large computational resource consumption caused by global calculation and reducing resource consumption.

[0056] In the above embodiments, the decoder needs to determine whether the codeword sequence data has changed during transmission and whether error correction decoding is required by checking whether the checksum of the codeword sequence data is a zero vector. Therefore, to comprehensively and thoroughly describe the decoding method provided by the embodiments of this disclosure, in one embodiment of this disclosure, before the step of flipping the first information bit in the codeword sequence data when the checksum of the codeword sequence data is not a zero vector, the decoding method provided by the embodiments of this disclosure may further include the following steps:

[0057] The codeword sequence data is verified using a check matrix to obtain the verification result of each check equation;

[0058] If the result of the target check equation is not zero in multiple check equations, the check vector of the codeword sequence data is determined to be non-zero.

[0059] The aforementioned parity check matrix can be pre-set or configured by the decoder based on the encoding matrix. The encoding matrix can be the matrix used by the transmitter to encode the original data to obtain the codeword sequence data; this will not be elaborated upon further here. It should be noted that the parity check matrix can include multiple parity check equations, each of which is a linear equation generated based on the elements of each row of the parity check matrix.

[0060] In addition, the target verification equation mentioned above may include at least one of multiple verification equations, without specific limitations here.

[0061] Thus, after acquiring the codeword sequence data, the decoder can verify the codeword sequence data using a pre-configured parity check matrix. Since the parity check matrix can include multiple parity check equations, the decoder can obtain the verification result of each parity check equation. If the verification result of the target parity check equation among these multiple parity check equations is not zero, it indicates that the codeword sequence data has failed the verification, and at this time, it can be determined that the parity check vector of the codeword sequence data is not zero.

[0062] In this embodiment, the codeword sequence data can be verified using a check matrix to obtain the verification result of each check equation. Then, by using the verification result of each check equation, it can be determined whether there is a target check equation among the multiple check equations with a non-zero verification result, so as to accurately determine whether the codeword sequence data has changed during transmission, thereby accurately determining whether the codeword sequence data is erroneous.

[0063] Furthermore, considering that the codeword sequence data acquired by the decoder may be affected by noise during transmission, thus disrupting the... If the parity is not balanced, at least one parity check equation will have a non-zero parity check, meaning the parity check equation is invalid. The number of invalid parity check equations is the SW value. For a specific parity check matrix, the SW value of the codeword sequence data reflects the number of error information bits in the codeword sequence data, specifically as follows: Figure 3 As shown, the SW value of the codeword sequence data is positively correlated with the number of error information bits in the codeword sequence data. That is, the larger the SW value, the more error information bits there are in the codeword sequence data, and vice versa.

[0064] Thus, the decoding method provided in this disclosure can evaluate the codeword sequence data based on the SW value of the codeword sequence data. If the SW value of the codeword sequence data is small, it indicates that the decoding process is within the decoding capability range of the decoder, and the subsequent decoding process can continue. Conversely, if the SW value of the codeword sequence data is large, it indicates that the decoding process has exceeded the decoding capability range of the decoder, and the decoding process of the codeword sequence can be terminated. This not only saves unnecessary latency but also significantly and effectively reduces power consumption. Based on this, in one embodiment of this disclosure, before the step of flipping the first information bit in the codeword sequence data, the decoding method provided in this disclosure may further include the following steps:

[0065] Based on the checksum of the codeword sequence data, determine the checksum weight SW value of the codeword sequence data.

[0066] The SW value of the codeword sequence data is positively correlated with the number of error information bits in the codeword sequence data.

[0067] Based on this, the step of flipping the first information bit of the codeword sequence data described above may specifically include the following steps:

[0068] If the SW value is less than the preset SW threshold, the first information bit in the codeword sequence data is flipped.

[0069] The preset SW threshold can be set in advance based on actual experience or circumstances. It can be used to characterize the decoding capability of the decoder, and no specific limitations are made here.

[0070] After obtaining the checksum of the codeword sequence data, the decoder can determine the SW value of the codeword sequence data based on the checksum. By comparing the SW value with a preset SW threshold, it can determine whether the decoding process of the codeword sequence data will exceed the decoder's decoding capability range. Specifically, if the SW value of the codeword sequence data is less than the preset SW threshold, it indicates that the decoding process of the codeword sequence data has not exceeded the decoder's decoding capability range, so the decoding process can continue, and the first information bit in the codeword sequence data can be flipped; conversely, if the SW value is greater than the preset SW threshold, the decoding process can continue, and the first information bit in the codeword sequence data can be flipped.

[0071] In this embodiment, by determining the SW value of the codeword sequence data and comparing the SW value with a preset SW threshold, it is possible to accurately determine whether the decoding process of the codeword sequence data is within the decoding capability range of the decoder. If the decoding process of the codeword sequence data is within the decoding capability range of the decoder, the decoding process of the codeword sequence data continues, thereby not only avoiding unnecessary delays but also significantly reducing resource consumption.

[0072] Based on this, in order to accurately and effectively flip the first information bit in the codeword sequence data, in one embodiment of this disclosure, the step of flipping the first information bit in the codeword sequence data may specifically include the following steps:

[0073] Based on the parity check matrix and the parity check results of each parity check equation, determine the number of non-zero parsers for each information bit.

[0074] Select the first information bit from multiple information bits, where the number of non-zero check bits is greater than or equal to the bit flipping threshold.

[0075] Flip the first information bit.

[0076] In some embodiments, the codeword sequence data may include multiple information bits, and the number of non-zero check bits for each information bit may represent the number of check equations in which the information bit participates where the check result is not zero.

[0077] Specifically, since the codeword sequence data can include multiple information bits, the decoder can determine the number of non-zero check bits for each information bit based on the parity check matrix and the parity check result of each parity check equation. Then, it can select the first information bit from the multiple information bits whose number of non-zero check bits is greater than or equal to the bit flipping threshold, and flip the first information bit.

[0078] In this embodiment, the number of non-zero checkers (i.e., non-satisfied check equations) in the check equations involving each information bit can be counted by using the check matrix and the check results of each check equation. This enables accurate location of error information bits in the codeword sequence data, and accurate error correction of the codeword sequence data can be achieved by flipping the corresponding error information bits.

[0079] In the decoding method provided in this embodiment, the checksum of the codeword sequence data can be synchronously updated according to the flipped information bits, thereby avoiding the use of... This addresses the problem of high computational resource consumption caused by the method of verifying codeword sequence data. Therefore, in order to accurately and synchronously update the checksum of the codeword sequence data, in one embodiment of this disclosure, as follows... Figure 4 As shown, the above S230 may specifically include the following steps:

[0080] S410, based on the check matrix and the check result of each check equation, determine the first check equation in which the check result of the first information bit is not zero.

[0081] S420, update the verification result of the first verification equation according to the amount of flip change of the first information bit.

[0082] Specifically, the decoder can determine the first check equation in which the check equation of the first information bit that has been flipped has a non-zero check result based on the check matrix and the check result of each check equation, and can update the check result of the first check equation according to the amount of flip change before and after the first information bit is flipped.

[0083] In this embodiment, by identifying the check equation that produces an erroneous result in the check equation involving the flipped first information bit, and then by locally updating the check result of the first check equation based on the amount of flipping of the first information bit, the checker of the codeword sequence data can be synchronously updated, avoiding errors caused by... The method of verifying codeword sequence data results in a large consumption of computational resources.

[0084] Based on this, in order to accurately update the checksum of the codeword sequence data synchronously by locally updating the checksum result of the first checksum equation, in one embodiment of this disclosure, the step of updating the checksum equation of the first checksum equation according to the flip change of the first information bit may specifically include the following steps:

[0085] The result is obtained by performing an XOR operation on the flip change of the first information bit and the verification result of the first check equation.

[0086] The updated calculation result is the verification result of the first verification equation.

[0087] Specifically, after determining the first check equation, the decoder can perform an XOR operation on the flip change of the first information bit and the check result of the first check equation to obtain the operation result, and then update the operation result to the check result of the first check equation, thereby realizing the local update of the check result of the first check equation.

[0088] In this embodiment, the result of the operation can be obtained by XORing the flip change of the first information bit with the verification result of the first check equation. This result can then be used to locally update the verification result of the first check equation, thereby achieving synchronous updating of the checksum of the codeword sequence data and avoiding errors caused by... The method of verifying codeword sequence data results in a large consumption of computational resources.

[0089] Furthermore, in order to describe the decoding method provided by the embodiments of this disclosure in a comprehensive and detailed manner, in one embodiment of this disclosure, the step of updating the bit flipping threshold may specifically include the following steps:

[0090] The maximum number of non-zero checksums is determined from the number of non-zero checksums in each information bit as the bit flipping threshold.

[0091] Specifically, since the codeword sequence data can include multiple information bits, after obtaining the number of non-zero checksums for each information bit, the largest number of non-zero checksums can be selected as the bit flipping threshold based on the number of non-zero checksums for each information bit.

[0092] In another embodiment of this disclosure, the step of updating the bit-flipping threshold described above may specifically include the following steps:

[0093] The maximum number of non-zero checksums is determined from the number of non-zero checksums in each information bit as the first threshold.

[0094] The maximum number of non-zero checksums is determined from the updated number of non-zero checksums for each information bit as the second threshold.

[0095] The larger of the first and second thresholds is determined as the bit flipping threshold.

[0096] The number of non-zero checksums for each updated information bit is determined based on the checksums of the updated codeword sequence data.

[0097] Specifically, since the codeword sequence data can include multiple information bits, the decoder can first select the largest number of non-zero checksums as a first threshold based on the number of non-zero checksums for each information bit. Furthermore, since the checksums of the codeword sequence data will be updated subsequently based on the information bits that have been flipped, the number of non-zero checksums for each information bit will also change accordingly. Therefore, a second threshold, representing the largest number of non-zero checksums, can be determined from the updated number of non-zero checksums for each information bit. Finally, the larger of the first and second thresholds can be selected as the bit-flipping threshold.

[0098] Furthermore, it should be noted that the number of non-zero checksums for each information bit refers to the number of checksum equations in which each information bit participates and whose checksum result is not zero. Since the checksum equation is a linear equation based on the elements of each row of the checksum matrix, the maximum number of checksum equations in which each information bit participates and whose checksum result is not zero can be equal to the column weight of the checksum matrix (the number of "1"s in each column of the checksum matrix). Based on this, considering the decoding method provided in this embodiment, the bit flipping threshold involved in the first iteration can be set to the maximum column weight of the checksum matrix. This avoids the situation in the prior art where the bit flipping threshold is set too high or too low, affecting the decoding rate.

[0099] In this embodiment, the bit-flipping threshold for the next iteration can be dynamically updated based on the number of non-zero checksums for each information bit in the current iteration. Furthermore, the bit-flipping threshold for the next iteration can also be updated based on the dynamic changes in the number of non-zero checksums for each information bit in the current iteration. This allows for accurate and effective updating of the bit-flipping threshold for each information bit, facilitating the decoding process of the subsequent convergent codeword sequence data and improving the decoding rate.

[0100] Based on the decoding method provided in the above embodiments of this disclosure, taking an example matrix with a code rate of 0.872 as an example, tests are conducted using the decoding method provided in the embodiments of this disclosure and a traditional decoding method, respectively. Figure 5 The performance comparison between the decoding method provided in this disclosure and traditional decoding methods is shown, such as... Figure 5 As shown, the decoding method provided in this embodiment can achieve a smaller frame error rate (FER) value at the same raw bit error rate compared to traditional decoding methods, which can significantly improve the error correction performance of the BF decoder.

[0101] also, Figure 6 The illustration shows a comparison of the number of iterations required between the decoding method provided in this disclosure and traditional decoding methods, such as... Figure 6As shown, the decoding method provided in this embodiment can achieve a smaller average number of iterations compared to traditional decoding methods under the same RBER. That is, the method provided in this embodiment can effectively reduce the number of iterations for decoding, thereby effectively reducing decoding latency.

[0102] Based on the same inventive concept, this disclosure provides a decoding device, which can be specifically described in conjunction with the appendix. Figure 7 A decoding apparatus provided in the embodiments of this disclosure will be described in detail.

[0103] Figure 7 This is a schematic diagram of the structure of a decoding device provided in an embodiment of this disclosure.

[0104] like Figure 7 As shown, the decoding device 700 may include:

[0105] The acquisition module 710 is used to acquire the codeword sequence data to be decoded;

[0106] The flipping module 720 is used in the I-th iteration to flip the first information bit in the codeword sequence data when the checksum of the codeword sequence data is not a zero vector. The number of non-zero checksums of the first information bit is greater than or equal to the bit flipping threshold. The number of non-zero checksums of the first information bit is determined based on the checksum of the codeword sequence data.

[0107] The update module 730 is used to update the checksum of the codeword sequence data according to the amount of flip change of the first information bit.

[0108] The update module 730 is further configured to update the bit flipping threshold when the checksum of the updated codeword sequence data is not a zero vector, and determine that the updated codeword sequence data is the codeword sequence data, and update I=I+1, and return to the step of performing the flipping of the first information bit in the codeword sequence data until the checksum of the codeword sequence data is a zero vector, or I=J, where J is a preset iteration number, and I and J are both positive integers.

[0109] In one embodiment of this disclosure, the decoding apparatus provided in this embodiment may further include:

[0110] The verification module is used to verify the codeword sequence data using a verification matrix, wherein the verification matrix includes multiple verification equations, and the verification result of each verification equation is obtained.

[0111] The determination module is used to determine that the checksum of the codeword sequence data is a non-zero vector when the checksum result of the target checksum is not zero among the plurality of checksums.

[0112] In one embodiment of this disclosure, the decoding apparatus provided in this embodiment may further include:

[0113] The determining module is also used to determine the check weight SW value of the codeword sequence data based on the check of the codeword sequence data, wherein the SW value is positively correlated with the number of error information bits in the codeword sequence data;

[0114] The flipping module is specifically used to flip the first information bit in the codeword sequence data when the SW value is less than a preset SW threshold.

[0115] In one embodiment of this disclosure, the codeword sequence data includes a plurality of information bits; the decoding apparatus provided in this embodiment may further include:

[0116] The determining module is further configured to determine the number of non-zero check pieces for each information bit based on the check matrix and the check result of each check equation, wherein the number of non-zero check pieces for each information bit represents the number of check equations in which the information bit participates whose check result is not zero;

[0117] The filtering module is used to filter out a first information bit from the plurality of information bits, wherein the number of non-zero check bits is greater than or equal to the bit flipping threshold.

[0118] The flipping module is specifically used to flip the first information bit.

[0119] In one embodiment of this disclosure, the decoding apparatus provided in this embodiment may include:

[0120] The determining module is further configured to determine, based on the verification matrix and the verification result of each of the verification equations, the first verification equation in which the first information bit participates has a non-zero verification result.

[0121] The update module is specifically used to update the verification result of the first verification equation based on the amount of flipping change of the first information bit.

[0122] In one embodiment of this disclosure, the decoding apparatus provided in this embodiment may include:

[0123] The arithmetic module is used to perform an XOR operation on the flip change of the first information bit and the verification result of the first verification equation to obtain the arithmetic result.

[0124] The update module is specifically used to update the calculation result to the verification result of the first verification equation.

[0125] In one embodiment of this disclosure, the decoding apparatus provided in this embodiment may include:

[0126] The determining module is further configured to determine the maximum number of non-zero checksums from the number of non-zero checksums for each of the information bits as the bit flipping threshold.

[0127] In one embodiment of this disclosure, the decoding apparatus provided in this embodiment may include:

[0128] The determining module is further configured to determine the maximum number of non-zero checksums from the number of non-zero checksums for each of the information bits as a first threshold.

[0129] The determining module is further configured to determine the maximum number of non-zero checksums from the updated number of non-zero checksums for each of the information bits as a second threshold, wherein the updated number of non-zero checksums for each of the information bits is determined based on the checksums of the updated codeword sequence data;

[0130] The determining module is further configured to determine the maximum threshold among the first threshold and the second threshold as the bit flipping threshold.

[0131] It is understood that, when implementing the corresponding decoding method, the decoding apparatus provided in the above embodiments can allocate the above processing to different program modules as needed to complete all or part of the processing described above. Furthermore, the apparatus and the corresponding method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0132] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a decoding method.

[0133] This application provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored and when executed by a processor, the processor will execute the decoding method provided in this application.

[0134] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0135] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0136] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0137] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0138] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure; as shown below. Figure 8 As shown, the electronic device 80 includes: a processor 801, and a memory 802 communicatively connected to the processor 801; the memory 802 stores instructions executable by the processor 801. The instructions are executed by the processor 801 to enable the processor 801 to perform:

[0139] Obtain the codeword sequence data to be decoded; in the I-th iteration, if the checksum of the codeword sequence data is not a zero vector, flip the first information bit in the codeword sequence data. The number of non-zero checksums of the first information bit is greater than or equal to the bit flipping threshold. The number of non-zero checksums of the first information bit is determined based on the checksum of the codeword sequence data; update the checksum of the codeword sequence data according to the amount of flipping of the first information bit; if the checksum of the updated codeword sequence data is not a zero vector, update the bit flipping threshold, determine the updated codeword sequence data as the codeword sequence data, update I=I+1, and return to execute the step of flipping the first information bit in the codeword sequence data until the checksum of the updated codeword sequence data is a zero vector, or, I=J, where J is the preset iteration number, and I and J are both positive integers.

[0140] The electronic devices and corresponding decoding methods provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0141] In practical applications, the electronic device 80 may further include at least one network interface 803. The various components of the electronic device 80 are coupled together via a bus system 804. It is understood that the bus system 804 is used to implement communication between these components. In addition to a data bus, the bus system 804 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 8 All buses are labeled as bus system 804. The number of processors 801 can be at least one, and the number of memories 802 can be at least one. Network interface 803 is used for wired or wireless communication between electronic device 80 and other devices.

[0142] The memory 802 in this embodiment is used to store various types of data to support the operation of the electronic device 80.

[0143] The methods disclosed in the above embodiments of this disclosure can be applied to or implemented by processor 801. Processor 801 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 801 or by instructions in software form. The processor 801 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 801 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 802. Processor 801 reads the information in memory 802 and, in conjunction with its hardware, completes the steps of the aforementioned decoding method.

[0144] In some embodiments, the electronic device 80 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0145] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0146] In the above description, the term "some embodiments" refers to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0147] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0148] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0149] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0150] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A decoding method, characterized in that, The method includes: Obtain the codeword sequence data to be decoded; In the I-th iteration, when the checksum of the codeword sequence data is not a zero vector, the first information bit in the codeword sequence data is flipped. The number of non-zero checksums of the first information bit is greater than or equal to the bit flipping threshold. The number of non-zero checksums of the first information bit is determined based on the checksum of the codeword sequence data. Update the checksum of the codeword sequence data according to the amount of flip change of the first information bit; If the checksum of the updated codeword sequence data is not a zero vector, update the bit flipping threshold, determine the updated codeword sequence data as the codeword sequence data, update I=I+1, and return to the step of flipping the first information bit in the codeword sequence data until the checksum of the updated codeword sequence data is a zero vector, or I=J, where J is the preset iteration number, and I and J are both positive integers; Before flipping the first information bit in the codeword sequence data when the checksum of the codeword sequence data is not a zero vector, the method further includes: The codeword sequence data is verified using a check matrix, which includes multiple check equations, and the verification result of each check equation is obtained. If the verification result of the target verification equation is not zero among the plurality of verification equations, the check vector of the codeword sequence data is determined to be non-zero. The step of updating the checksum of the codeword sequence data based on the flip change of the first information bit includes: Based on the verification matrix and the verification result of each verification equation, determine the first verification equation in which the first information bit participates and the verification result is not zero. Update the verification result of the first verification equation based on the amount of flip change of the first information bit. The step of updating the verification result of the first verification equation based on the flip change of the first information bit includes: The result is obtained by performing an XOR operation on the flip change of the first information bit and the verification result of the first verification equation. The calculation result is updated to the verification result of the first verification equation.

2. The method according to claim 1, characterized in that, Before flipping the first information bit in the codeword sequence data, the method further includes: Based on the checksum of the codeword sequence data, the checksum weight SW value of the codeword sequence data is determined. The SW value is positively correlated with the number of error information bits in the codeword sequence data. The flipping of the first information bit of the codeword sequence data includes: If the SW value is less than a preset SW threshold, the first information bit in the codeword sequence data is flipped.

3. The method according to claim 1, characterized in that, The codeword sequence data includes multiple information bits; flipping the first information bit in the codeword sequence data includes: Based on the verification matrix and the verification result of each verification equation, the number of non-zero check pieces for each information bit is determined. The number of non-zero check pieces for each information bit represents the number of verification equations in which the information bit participates whose verification result is not zero. Select a first information bit from the plurality of information bits whose number of non-zero check bits is greater than or equal to the bit flipping threshold; Flip the first information bit.

4. The method according to claim 3, characterized in that, The updating of the bit-flipping threshold includes: The maximum number of non-zero check elements is determined from the number of non-zero check elements in each of the information bits, and this is the bit flipping threshold. or, The largest number of non-zero checksums is determined from the number of non-zero checksums in each of the information bits and is set as a first threshold. The maximum number of non-zero checksums is determined from the updated number of non-zero checksums for each information bit as a second threshold, wherein the updated number of non-zero checksums for each information bit is determined based on the checksums of the updated codeword sequence data; The larger of the first threshold and the second threshold is determined as the bit flipping threshold.

5. A decoding device, characterized in that, The device includes: The acquisition module is used to acquire the codeword sequence data to be decoded; The flipping module is used in the I-th iteration to flip the first information bit in the codeword sequence data when the checksum of the codeword sequence data is not a zero vector. The number of non-zero checksums of the first information bit is greater than or equal to the bit flipping threshold. The number of non-zero checksums of the first information bit is determined based on the checksum of the codeword sequence data. The update module is used to update the checksum of the codeword sequence data according to the amount of flip change of the first information bit. The update module is further configured to update the bit flipping threshold when the checksum of the updated codeword sequence data is not a zero vector, and determine that the updated codeword sequence data is the codeword sequence data, and update I=I+1, and return to the step of performing the flipping of the first information bit in the codeword sequence data until the checksum of the codeword sequence data is a zero vector, or I=J, where J is a preset iteration number, and I and J are both positive integers; The device further includes: The verification module is used to verify the codeword sequence data using a verification matrix, wherein the verification matrix includes multiple verification equations, and the verification result of each verification equation is obtained. The determination module is used to determine the non-zero check vector of the codeword sequence data when the check result of the target check equation is not zero among the plurality of check equations; The device includes: The determining module is further configured to determine, based on the verification matrix and the verification result of each of the verification equations, the first verification equation in which the first information bit participates has a non-zero verification result. The update module is specifically used to update the verification result of the first verification equation based on the amount of flip change of the first information bit. The device further includes: The arithmetic module is also used to perform an XOR operation on the flip change of the first information bit and the verification result of the first verification equation to obtain the arithmetic result. The update module is specifically used to update the calculation result to the verification result of the first verification equation.

6. The apparatus according to claim 5, characterized in that, The device further includes: The determining module is also used to determine the check weight SW value of the codeword sequence data based on the check of the codeword sequence data, wherein the SW value is positively correlated with the number of error information bits in the codeword sequence data; The flipping module is specifically used to flip the first information bit in the codeword sequence data when the SW value is less than a preset SW threshold.

7. The apparatus according to claim 5, characterized in that, The codeword sequence data includes multiple information bits; the device further includes: The determining module is further configured to determine the number of non-zero check pieces for each information bit based on the check matrix and the check result of each check equation, wherein the number of non-zero check pieces for each information bit represents the number of check equations in which the information bit participates whose check result is not zero; The filtering module is used to filter out a first information bit from the plurality of information bits, wherein the number of non-zero check bits is greater than or equal to the bit flipping threshold. The flipping module is specifically used to flip the first information bit.

8. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the decoding method according to any one of claims 1 to 4.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the decoding method according to any one of claims 1 to 4.

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