Communication terminal tester, interface timing parameter determination method thereof, electronic device, chip, storage medium and program product

Abstract

Provided are a communication terminal tester, a method for determining interface timing parameters of the communication terminal tester, an electronic device, a chip, a storage medium, and a program product, and relate to the technical field of communication. The method for determining interface timing parameters of the communication terminal tester comprises: obtaining respective values of a first parameter, a second parameter, and a third parameter corresponding to a target subcarrier spacing; obtaining a first value range of a fourth parameter, a second value range of a fifth parameter, and a third value range of a sixth parameter according to the respective values of the first parameter, the second parameter, and the third parameter; and outputting the first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter, so as to determine, by debugging the communication terminal tester, a value of the fourth parameter within the first value range, a value of the fifth parameter within the second value range, and a value of the sixth parameter within the third value range.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of communication, and in particular to a communication terminal tester, a method for determining interface timing parameters of the communication terminal tester, an electronic device, a chip, a storage medium and a program product. BACKGROUND

[0002] The communication terminal tester is an instrument for detecting and evaluating the performance of a communication terminal, which can be applied to the research and development, production, quality inspection and maintenance of the communication terminal. The interface timing of the communication terminal tester is one of the key factors affecting the accuracy of the test results of the communication terminal. By precisely controlling the interface timing, the communication terminal tester can verify the performance of the communication terminal in the dimensions of standard compatibility, throughput and latency.

[0003] At present, the setting of the interface timing of the communication terminal tester is usually from the basic planning under the non-millimeter wave scene, and the timing offset is based on the preset value of the master unit and the upper layer. Through the timing reading and writing of the register, the data interaction with the algorithm module is realized. Such interface timing planning is not standardized and systematic, and has poor scalability. The adaptation complexity is high for new scene requirements (such as the scene of subcarrier spacing under a large parameter set), which affects the test efficiency. SUMMARY

[0004] To alleviate, mitigate or eliminate at least one of the above technical problems, the present disclosure provides a communication terminal tester, a method for determining interface timing parameters of the communication terminal tester, an electronic device, a chip, a storage medium and a program product.

[0005] In a first aspect, the present disclosure provides a method for determining interface timing parameters of a communication terminal tester, the communication terminal tester comprising a first processor, a second processor and a radio frequency circuit, the first processor being configured to run a scheduler program and an L1 layer control plane program, the scheduler program being used for scheduling control of air interface time-frequency resources, the L1 layer control plane program being used for performing resource control and interface interaction of the L1 layer, the second processor being configured to run a signal processing algorithm program and interact with the first processor and the radio frequency circuit, the first processor being configured with a shared memory for interface interaction with the second processor, and the method comprising:

[0006] obtaining respective values of a first parameter, a second parameter and a third parameter corresponding to a target subcarrier spacing, wherein the first parameter is a number of basic time units required by a maximum processing duration of the L1 layer control plane procedure, the second parameter is a number of basic time units required by a maximum processing duration of the signal processing algorithm procedure, and the third parameter is a number of basic time units required for delaying after the L1 layer control plane procedure finishes writing the first partition of the shared memory and before the second processor reads the first partition in a transmission timing, wherein the basic time unit is a length of a single time slot corresponding to a maximum subcarrier spacing in a scenario supported by the communication terminal tester;

[0007] obtaining a first value range of a fourth parameter, a second value range of a fifth parameter and a third value range of a sixth parameter according to the respective values of the first parameter, the second parameter and the third parameter, wherein the fourth parameter is a number of basic time units required for advancing before the scheduler procedure issues a schedule relative to the radio frequency circuit transmitting a radio frequency signal in the transmission timing, the fifth parameter is a number of basic time units required for advancing before the L1 layer control plane procedure writes the first partition relative to the radio frequency circuit transmitting a radio frequency signal in the transmission timing, and the sixth parameter is a number of basic time units required for delaying before the L1 layer control plane procedure reads a second partition of the shared memory relative to the radio frequency circuit receiving a radio frequency signal in a reception timing; and

[0008] outputting the first value range of the fourth parameter, the second value range of the fifth parameter and the third value range of the sixth parameter for determining a value of the fourth parameter within the first value range, a value of the fifth parameter within the second value range and a value of the sixth parameter within the third value range by debugging the communication terminal tester.

[0009] In a second aspect, the present disclosure provides a communication terminal tester, comprising:

[0010] a radio frequency circuit;

[0011] a first processor configured to run a scheduler procedure and an L1 layer control plane procedure, wherein the scheduler procedure is used for scheduling control of air interface time-frequency resources, and the L1 layer control plane procedure is used for performing resource control and interface interaction of the L1 layer; and

[0012] a second processor configured to run a signal processing algorithm procedure and interact with the first processor and the radio frequency circuit, wherein the first processor is configured with a shared memory for interface interaction with the second processor;

[0013] The radio frequency circuit, the first processor and the second processor operate according to the interface timing parameter determined by the method of the first aspect.

[0014] In a third aspect, the present disclosure provides an electronic device. The electronic device includes one or more processors; and one or more memories coupled to the one or more processors and storing instructions thereon. When the instructions are executed by the one or more processors alone or collectively, the electronic device performs the method of the first aspect.

[0015] In a fourth aspect, the present disclosure provides a chip. The chip includes circuitry configured to perform the method of the first aspect.

[0016] In a fifth aspect, the present disclosure provides a non-transitory computer-readable storage medium storing machine executable instructions. The machine executable instructions, when executed by one or more processors of a machine, cause the machine to perform the method of the first aspect.

[0017] In a sixth aspect, the present disclosure provides a computer program product including machine executable instructions. The machine executable instructions, when executed by one or more processors of a machine, cause the machine to perform the method of the first aspect.

[0018] It should be understood that the summary section is not intended to identify key or essential features of embodiments of the present disclosure or to limit the scope of the present disclosure. Other features of the present disclosure will be readily apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1 An exemplary communication network in which exemplary embodiments of the present disclosure can be implemented is shown;

[0021] Figure 2 A structural schematic diagram of a communication terminal tester according to some embodiments of the present disclosure is shown;

[0022] Figure 3 A flowchart of a method of determining interface timing parameters of a communication terminal tester according to some embodiments of the present disclosure is shown;

[0023] Figure 4 A transmission timing diagram of a communication terminal tester according to some embodiments of the present disclosure is shown;

[0024] Figure 5A receive timing diagram of a communication terminal tester is shown in accordance with some embodiments of the present disclosure.

[0025] Figure 6 A simplified block diagram of a device suitable for implementing example embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0026] The principles of the present disclosure will now be described with reference to some embodiments. It should be understood that the description of these embodiments is merely intended to illustrate the present disclosure and to help the skilled person understand and implement the present disclosure, without imposing any limitation on the scope of the present disclosure. The disclosure described herein can be implemented in a manner different from that described below.

[0027] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0028] Reference herein to "one embodiment", "an embodiment", "example embodiment" and the like means that a particular feature, structure, or characteristic described in connection with that embodiment can be included in that embodiment, but not necessarily in other embodiments. The appearance of the phrases "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0029] It should be understood that although the terms "first" and "second" and the like can be used herein to describe various objects, these objects are not necessarily limited by these terms. These terms are only used to distinguish one object from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of example embodiments. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed terms.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, elements and / or components etc. but do not preclude the presence or addition of one or more other features, elements, components and / or combinations thereof.

[0031] As used herein, the term "circuitry" can refer to one or more or all of the following:

[0032] (a) hardware-only circuit implementations (such as implementations in only analog and / or digital circuitry)

[0033] (b) combinations of hardware circuits and software, such as (as applicable):

[0034] (i) a combination of analog and / or digital hardware circuit(s) with software / firmware

[0035] (ii) any portions of hardware processor(s) with software (including digital signal processors); and

[0036] (c) hardware circuit(s) and or processor(s), such as a microprocessor(s) or a portion of microprocessor(s), that requires software (e.g., firmware) for operation, but need not necessarily have such software present.

[0037] This definition of circuit applies to all uses of this term herein, including in any claims. As a further example, as used herein, the term circuitry also includes an implementation that is a combination of hardware circuits and software (or firmware), such as (as applicable): a combination of a general purpose hardware circuit(s) with software / firmware (such as a microprocessor(s) or a portion of a microprocessor(s), or a combination of application-specific circuits and software / firmware (such as a combination of a digital-signal-processor hardware circuit implementation with software / firmware). The term circuitry also includes implementations such as (or similar to) the hardware circuit(s) in the mobile device's baseband integrated circuit or the baseband processor integrated circuit, or the like. For example, the circuitry can include a processor of any type usually found in a computing device or other electronic devices, such as a microprocessor, a digital signal processor, a microcontroller, a central processing unit, or the like. The circuitry can further include by way of example any customary electrical processor components, such as one or more phase-locked loops, oscillators, modulators, demodulators, encoders, decoders, amplifiers, repeaters, filters, voltage regulators, and the like.

[0038] As used herein, the term “communication network” refers to a network that follows any appropriate communication standard, such as Long Term Evolution (LTE), LTE-Advanced (LTE-A), Wideband Code Division Multiple Access (WCDMA), High Speed Packet Access (HSPA), Narrow Band Internet of Things (NB-IoT), New Radio (NR), Non-Terrestrial Network (NTN), etc. In addition, communication between terminal devices and network devices in the communication network can be performed according to any appropriate generation communication protocol, including but not limited to first generation (1G), second generation (2G), 2.5G, 2.75G, third generation (3G), fourth generation (4G), 4.5G, fifth generation (5G), future sixth generation (6G) communication protocols, and / or any other protocols that are currently known or that will be developed in the future. Embodiments of the present disclosure can be applied in a satellite communication system. In view of the rapid development in communications, there will of course also be future communication technologies and systems that can be implemented with the embodiments of the present disclosure. The scope of the present disclosure should not be limited to the aforementioned systems.

[0039] The term “satellite network equipment” refers to a node in a satellite communication network that is set up on a satellite or a ground segment. Terminal equipment accesses the network and receives services therefrom through this node. Depending on the terminology and technology applied, satellite network equipment can refer to a base station (BS) or access point (AP) as a satellite payload, such as a Node B (NodeB or NB), an evolved Node B (eNodeB or eNB), an NR NB (also known as gNB), a remote radio unit (RRU), a radio head (RH), a remote radio head (RRH), a relay node. An example of a relay node can be an integrated access and backhaul (IAB) node. The distributed unit (DU) part of an IAB node can perform the functions of “satellite network equipment” and thus can operate as network equipment. In the following description, the terms “satellite network equipment”, “BS” and “node” can be used interchangeably.

[0040] The term “terminal equipment” refers to any terminal equipment capable of wireless communication. By way of example and not limitation, terminal equipment can also be referred to as a communication terminal, a communication device, a user equipment (UE), a subscriber station (SS), a portable user station, a mobile station (MS), or an access terminal (AT). The terminal equipment can include, but is not limited to, a mobile phone, a cellular phone, a smartphone, a voice over IP (VoIP) phone, a wireless local loop phone, a tablet, a wearable terminal device, a personal digital assistant (PDA), a portable computer, a desktop computer, an image capture terminal equipment such as a digital camera, a gaming terminal device, a music storage and playback appliance, a car kit, a wireless endpoint, a mobile station, a laptop embedded equipment (LEE), a laptop mounted equipment (LME), a USB dongle, a smart device, a wireless customer premises equipment (CPE), an Internet of Things (loT) device, a watch or other wearable device, a head-mounted display (HMD), a vehicle, a drone, medical equipment and applications (e.g., remote surgery), industrial equipment and applications (e.g., robots in industrial and / or

[0041] The term “L1” refers to layer 1 of a protocol stack. Exemplarily, L1 refers to the physical layer.

[0042] The term "L2" refers to Layer 2 of the protocol stack. Exemplarily, L2 can include a Media Access Control (MAC) layer, a Radio Link Control (RLC) layer, a Packet Data Convergence Protocol (PDCP) layer, a Service Data Adaptation Protocol (SDAP) layer, responsible for scheduling, segment reassembly, encryption and integrity protection, etc.

[0043] The term "Communication Processor (CP)" refers to a dedicated processor for processing the communication protocol stack, commonly found in base stations, routers, etc., responsible for protocol stack management, carrying L1 and L2 of the protocol stack.

[0044] The term "Field-Programmable Gate Array (FPGA)" is responsible for the algorithm part of channel coding, modulation, resource mapping, etc. of the signal.

[0045] The term "shared memory" refers to a block of memory units that can be accessed by multiple different devices at the same time.

[0046] The term "Sub-Carrier Spacing (SCS)" refers to the sub-carrier spacing of the beam, which is the smallest unit of the signal in the frequency domain.

[0047] The term "slot" refers to the time domain basic unit of the beam, each slot contains a certain number of symbols.

[0048] Although the functions described herein can be performed in various exemplary embodiments in fixed and / or wireless network nodes, in other exemplary embodiments, the functions can be implemented in a user equipment device, such as a cellular phone, or a tablet computer, or a laptop computer, or a desktop computer, or a mobile Internet of Things device, or a fixed Internet of Things device. For example, the user equipment device can suitably have the respective capabilities described in relation to the fixed and / or wireless network nodes. The user equipment device can be a user equipment and / or a control device, e.g. a chipset or a processor, configured to control the user equipment when the user equipment is installed therein. Examples of these functions include a bootstrap server function and / or a home subscriber server, which can be implemented in the user equipment device by providing the user equipment device with software configured to cause the user equipment device to perform from the perspective of these functions / nodes.

[0049] Figure 1An exemplary communication network 100 in which embodiments of the present disclosure may be implemented is shown. The communication network 100 includes a satellite network device 110 and terminal devices 120A and 120B served by the satellite network device 110. Terminal devices 120A and 120B may also be collectively referred to as terminal device 120. The communication network 100 may provide a service cell 130 to serve terminal devices 120A and 120B. Figure 1 In the example, as a satellite communication network, communication network 100 also includes ground station 140, gNB 150, next-generation core network NGC 160, and data network 170. The satellite communication network may include low-Earth orbit (LEO), medium-Earth orbit (MEO), or geostationary orbit (GEO) satellites.

[0050] Ground station 140 acts as a gateway, connecting non-terrestrial networks and public data networks. gNB 150 acts as an access network, connecting ground station 140 to the core network NGC 160. NGC 160 can also connect to data network 170 to provide, for example, internet content services. It will be understood that communication network 100 is not required to include... Figure 1 The communication network 100 may also include all the elements shown in the diagram. Figure 1 Other elements not shown in the text.

[0051] In some embodiments, the satellite network device 110 can function as a base station to communicate with terminal devices 120A and 120B, or it can function as a transparent forwarding node to transmit signals sent by the ground station 140 to the terminal devices 120A and 120B. In the former case, the satellite network device 110 possesses all or part of the functions of a base station. For example, the satellite network device 110 can be a gNB or a gNB-DU, and the satellite network device 110 with gNB functionality can have an inter-satellite link (ISL) or not. In the case of a transparent forwarding node, the satellite network device 110 only performs transparent forwarding.

[0052] It should be understood that the number of satellite network devices 110, terminal devices 120A and 120B, and serving cell 130 is for illustrative purposes only and is not intended to impose any limitation. Communication network 100 may include any suitable number of satellite network devices, terminal devices, and serving cells suitable for implementing embodiments of this disclosure. It should be noted that the terms "cell" and "serving cell" are used interchangeably herein.

[0053] In the communication network 100, the satellite network device 110 can transmit data and control information to the terminal devices 120A and 120B, and the terminal devices 120A and 120B can also transmit data and control information to the satellite network device 110. The link from the satellite network device 110 to the terminal devices 120A and 120B is called the downlink (DL) or forward link, while the link from the terminal devices 120 to the satellite network device 110 is called the uplink (UL) or reverse link.

[0054] The communication in the communication network 100 can comply with any suitable standard, but is not limited to Long Term Evolution (LTE), LTE Evolution, LTE-Advanced (LTE-A), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), etc. In addition, the communication can be performed according to any generation of communication protocol known at present or developed in the future. Examples of the communication protocol include, but are not limited to, first generation (1G), second generation (2G), 2.5G, 2.75G, third generation (3G), fourth generation (4G), 4.5G, fifth generation (5G), sixth generation (6G) communication protocol.

[0055] In the development, production, quality inspection and maintenance of a communication terminal (such as the terminal device 120 in Figure 1 , it is usually necessary to use a communication terminal tester to detect and evaluate the corresponding performance of the communication terminal. According to the technology and test scenario of the communication terminal being tested, there are various types of instruments. Common communication terminal testers include comprehensive testers, production testers, Bluetooth / Wi-Fi testers, etc.

[0056] Figure 2 A structural schematic diagram of a communication terminal tester according to some embodiments of the present disclosure is shown. As shown in Figure 2 , the communication terminal tester 200 includes a first processor 210, a second processor 220 and a radio frequency circuit 230. The first processor 210 is configured to run a scheduler program 211 and an L1 layer control plane program 212. The scheduler program 211 is used for scheduling control of air interface time-frequency resources. The L1 layer control plane program 212 is used for performing resource control and interface interaction of the L1 layer. The second processor 220 is configured to run a signal processing algorithm program and interact with the first processor 210 and the radio frequency circuit 230. The first processor 210 is configured with a shared memory 213 for interface interaction with the second processor 220. It will be understood that the communication terminal tester 200 does not necessarily have to include all the elements shown in Figure 2 , the communication terminal tester 200 can also include other elements not shown in Figure 2 .

[0057] In one example embodiment, the first processor 210 is a CP, and the second processor 220 is an FPGA. The CP and the FPGA interface and interact through a shared memory 213 having a total length of L partitions. For example, the CP writes data to a partition idx2 of the shared memory 213, and the FPGA reads data from the partition idx2 of the shared memory 213.

[0058] The interface timing of the communication terminal tester is one of the key factors affecting the accuracy of the test results of the communication terminal. The embodiments of the present disclosure distinguish different satellite communication application scenarios such as frequency range FR1 / FR2, high and low orbits by subcarrier spacing SCS, balance the business logic requirements, chip processing performance and interface read-write capability, standardize the interface timing between the scheduler program, the L1 layer control plane program and the second processor, reduce the internal processing delay of the communication terminal tester, and improve the test efficiency.

[0059] Figure 3 A flowchart of a method for determining interface timing parameters of a communication terminal tester according to some embodiments of the present disclosure is shown. It should be understood that the method 300 for determining interface timing parameters of a communication terminal tester can include additional steps not shown and / or some of the shown steps can be omitted, and the embodiments of the present disclosure are not limited in this regard.

[0060] In step S310, the respective values of a first parameter N proc , a second parameter N algo and a third parameter N send_delay corresponding to a target subcarrier spacing are obtained. The first parameter N proc is the number of basic time units T ext_IRQ required for the maximum processing duration of the L1 layer control plane program, and the first parameter N proc is an integer. The second parameter N algo is the number of basic time units T ext_IRQ required for the maximum processing duration of the signal processing algorithm program, and the second parameter N algo is an integer. The third parameter N send_delay is the number of basic time units T ext_IRQ required for the delay before the second processor reads the first partition after the L1 layer control plane program writes the first partition of the shared memory in the transmission timing, and the third parameter N send_delay is an integer. The basic time unit T ext_IRQ is the length of a single time slot corresponding to the maximum subcarrier spacing in the application scenarios supported by the communication terminal tester. The length of a single time slot T scs corresponding to the target subcarrier spacing is n x T ext_IRQ, n = 1, 2, 4, … (n is a non-negative integer power of 2). In an exemplary embodiment, the system timing of the communication terminal tester is controlled by external interrupts of the first processor, and the basic time unit T ext_IRQ is equal to the period of the external interrupts of the first processor.

[0061] In some embodiments, the respective values of the first parameter N proc , the second parameter N algo , and the third parameter N send_delay corresponding to the target subcarrier spacing are determined according to the chip characteristics of the first processor and the second processor and the target application scenario of the communication terminal tester. It can be understood that the method for obtaining the respective values of the first parameter N proc , the second parameter N algo , and the third parameter N send_delay corresponding to the target subcarrier spacing is not limited in the embodiments of the present disclosure, and exemplaryly, the respective values can be obtained directly from a cloud or a remote server, or obtained locally.

[0062] In some embodiments, the index number of the first partition is determined based on the time slot number in which the radio frequency circuit transmits the radio frequency signal. The index number of the second partition is determined based on the time slot number in which the radio frequency circuit receives the radio frequency signal. In such embodiments, the index number x of the shared memory partition is determined by the current time slot number s. Exemplarily, x = f_buf_idx(s), where f_buf_idx(s) represents a mapping relationship function between the time slot number s and the index number x of the shared partition, and the specific mapping relationship can be determined according to the chip and business requirements.

[0063] In step S320, a first value range of a fourth parameter N sche_ext , a second value range of a fifth parameter N send_para , and a third value range of a sixth parameter N recv_para are obtained according to the respective values of the first parameter N proc , the second parameter N algo , and the third parameter N send_delay . The fourth parameter N sche_ext is the number of basic time units T ext_IRQ that the scheduler program needs to advance in the sending timing to schedule the radio frequency circuit to transmit the radio frequency signal, and the fourth parameter N sche_ext is an integer. The fifth parameter N send_para is the number of basic time units T ext_IRQ that the L1 layer control plane program needs to advance in the sending timing to write the first partition, and the fifth parameter N send_para is an integer. The sixth parameter N recv_parais a basic time unit T ext_IRQ , the number of the second partition of the shared memory that the L1 layer control plane program reads in the receiving timing needs to be delayed relative to the radio frequency circuit receiving the radio frequency signal recv_para is an integer.

[0064] In some embodiments, the fourth parameter N sche_ext is obtained according to a first constraint condition. The first constraint condition includes: the difference between the product of the fourth parameter N sche_ext and the basic time unit T ext_IRQ and the sum of the product of the first parameter N proc and the basic time unit T ext_IRQ , the product of the second parameter N algo and the basic time unit T ext_IRQ , and the product of the third parameter N send_delay and the basic time unit T ext_IRQ is greater than zero, or the difference between the fourth parameter N sche_ext and the sum of the first parameter N proc , the second parameter N algo , and the third parameter N send_delay is greater than zero. Exemplarily, the first constraint condition can be expressed by formula (1) or formula (2), and formula (1) and formula (2) are respectively shown as follows:

[0065] N sche_ext ×T ext_IRQ -N proc ×T ext_IRQ -N algo ×T ext_IRQ -N send_delay ×T ext_IRQ >0 (1)

[0066] N sche_ext -N proc -N algo -N send_delay >0 (2)

[0067] In some embodiments, the fifth parameter N send_para is obtained according to a second constraint condition. The second constraint condition includes: the difference between the product of the fifth parameter N send_para and the basic time unit and the sum of the product of the second parameter N algo and the basic time unit T ext_IRQ , and the product of the third parameter N send_delay and the basic time unit T ext_IRQ is greater than zero; or the difference between the fifth parameter N send_para and the sum of the second parameter N algo and the third parameter N send_delayThe difference between the sums is greater than zero. For example, such a second constraint can be expressed by formula (3) or formula (4), which are illustrated below:

[0068] N send_para ×T ext_IRQ -N algo ×T ext_IRQ -N send_delay ×T ext_IRQ >0 (3)

[0069] N send_para -N algo -N send_delay >0 (4)

[0070] In some embodiments, the sixth parameter N is obtained according to the third constraint condition. recv_para The third range of values. The third constraint includes: the sixth parameter N. recv_para and basic time unit T ext_IRQ The product minus the second parameter N algo and basic time unit T ext_IRQ The difference between the products is greater than zero; or the sixth parameter N recv_para Subtract the second parameter N algo The difference is greater than zero. For example, such a third constraint can be expressed by formula (5) or formula (6), with examples of formula (5) and formula (6) as follows:

[0071] N recv_para ×T ext_IRQ -N algo ×T ext_IRQ >0 (5)

[0072] N recv_para -N algo >0 (6)

[0073] In step S330, the fourth parameter N is output. sche_ext The first range of values, the fifth parameter N send_para The second range of values ​​and the sixth parameter N recv_para The third value range is used to determine the fourth parameter N by debugging the communication terminal tester. sche_ext Values ​​within the first range, and the fifth parameter N send_para The values ​​within the second range and the sixth parameter N recv_para The value within the third range.

[0074] The fourth parameter N is determined by debugging the communication terminal tester. sche_ext Values ​​within the first range, and the fifth parameter N send_para The values ​​within the second range and the sixth parameter Nrecv_para Within the third range of values, the interaction stability and internal latency of the communication terminal tester are balanced. In some embodiments, during debugging, the result on the left side of the formula corresponding to the above constraints is made as small as possible to more effectively balance the interaction stability and internal latency of the communication terminal tester.

[0075] In some embodiments, the fifth parameter N can also be used. send_para The sixth parameter N recv_para The seventh parameter N is determined by the corresponding value of the total length L of the shared memory partition. clr The value of . Among them, the seventh parameter N clr The basic time unit T is the interval between the first partition being written to and cleared. ext_IRQ The number of, the seventh parameter N clr L is an integer, where L is the total number of partitions in the shared memory.

[0076] In one exemplary embodiment, the seventh parameter N is determined according to the fourth constraint condition. clr The value of . Among them, the fourth constraint condition includes: the seventh parameter N clr Greater than the fifth parameter N send_para and the sixth parameter N recv_para The largest of the four values ​​is less than the total length L of the shared memory partition. For example, such a fourth constraint can be expressed by formula (7), as exemplified below:

[0077] max(N send_para , N recv_para ) <N clr <L (7)

[0078] This disclosure quantifies and standardizes the interface timing within the communication terminal tester to form a set of independently configurable interface timing parameters for various application scenarios, making it suitable for a wide range of applications. For example, for low-speed scenarios, larger values ​​can be taken within the range of interface timing parameters, while for high-speed scenarios, smaller values ​​can be taken within the range of interface timing parameters. Furthermore, the interface timing parameter determination method of the communication terminal tester in this disclosure has good scalability and can adapt to constantly changing technical requirements and different application scenarios.

[0079] After determining the values ​​of the interface timing parameters of the communication terminal tester, these values ​​are configured into the first and second processors of the tester. The radio frequency circuit, the first processor, and the second processor of the tester can then operate according to the determined interface timing parameters. For example, the determined first parameter N... proc The second parameter N algo The third parameter N send_delay, fourth parameter N sche_ext , fifth parameter N send_para , sixth parameter N recv_para , and seventh parameter N clr are configured into the first processor 210 and the second processor 220 of the communication terminal tester 200 shown in Figure 2 . The transmission timing and the reception timing of the communication terminal tester 200 are exemplarily explained below with reference to Figure 4 and Figure 5 respectively.

[0080] Assuming that there is downlink scheduling on the time slot m, and the next time slot is the time slot l, the exemplary transmission timing 400 of the communication terminal tester 200 is shown in Figure 4 , wherein the time unit in Figure 4 is T ext_IRQ .

[0081] In the embodiment shown in Figure 4 , the scheduler program 211 issues the scheduling in advance by N sche_ext × T ext_IRQ , to ensure that the subsequent processing unit has sufficient processing time. After receiving the scheduling from the scheduler program 211, the L1 layer control plane program 212 processes for N proc × T ext_IRQ , and then sends the scheduling information to the second processor 220 in advance by N send_para × T ext_IRQ , i.e., writes the required interface parameters into the first partition of the shared memory 213 in advance by N send_para × T ext_IRQ . The second processor 220 reads the first partition of the shared memory 213 after a delay of N send_delay × T ext_IRQ , to ensure the integrity of writing and reading, and processes the scheduling, which takes N algo × T ext_IRQ . It can be understood that the maximum processing time of the L1 layer control plane program 212 under all scheduling scenarios supported by the L1 layer control plane program 212 does not exceed N proc × T ext_IRQ .

[0082] Assuming that there is downlink scheduling on the time slot l, the exemplary reception timing of the communication terminal tester 200 is shown in Figure 5 , wherein the time unit in Figure 5 is T ext_IRQ .

[0083] In the embodiment shown in Figure 5 , when the L1 layer control plane program 212 receives the interface data returned by the second processor 220, the L1 layer control plane program 212 is delayed by N recv_para × T ext_IRQThe time length reads the second partition of the shared memory, and then performs subsequent processing. After the processing is completed, the processing result is reported to the scheduler program 211.

[0084] In Figure 4 and Figure 5 In the embodiment shown, the index number x of the partition of the shared memory 213 is determined by the current time slot number s. The index number of the first partition is determined based on the time slot number in which the radio frequency circuit transmits the radio frequency signal. The index number of the second partition is determined based on the time slot number in which the radio frequency circuit receives the radio frequency signal. Within the total length L of the shared memory 213, the storage space of the partition x of the shared memory 213 is emptied after completing one read-write, N clr ×T ext_IRQ times, thereby improving the utilization rate of the shared memory 213 and preventing data loss.

[0085] Embodiments of the present disclosure also provide a chip. The chip includes circuitry configured to perform any of the processes discussed with reference to the disclosed. Figures 3-5

[0086] Figure 6 is a simplified block diagram of a device 600 suitable for implementing embodiments of the present disclosure. For example, the satellite network device 110, the terminal device 120, the electronic device can be implemented by the device 600. As shown, the device 600 includes one or more processors 610, one or more memories 620 coupled to the processors 610, and one or more communication modules 640 coupled to the processors 610. Figure 6

[0087] The communication module 640 is used for bidirectional communication. The communication module 640 has at least one antenna to facilitate communication. The communication interface can represent any interface necessary for communication with other network elements.

[0088] The processor 610 can be any type suitable for the local technology network and can include one or more of the following as non-limiting examples: general purpose computer, special purpose computer, microprocessor, digital signal processor (DSP), and processor based on multi-core processor architecture. The device 600 can have multiple processors, for example, an application specific integrated circuit chip that is time-slaved to a clock that synchronizes the main processor.

[0089] ​​The memory 620 can include one or more non-transitory memories and one or more transitory memories. Examples of non-transitory memories include, but are not limited to, read only memories (ROM) 624, electrically programmable read only memories (EPROM), flash memories, hard disks, compact disks (CDs), digital video disks (DVDs), and other magnetic storage devices and / or optical storage devices. Examples of transitory memories include, but are not limited to, random access memories (RAM) 622 and other volatile memories that do not persist for more than a duration of power.

[0090] The computer program 630 includes computer executable instructions that are executed by the associated processor 610. The computer program 630 can be stored in the ROM 624. The processor 610 can perform any appropriate action and processing by loading the computer program 630 into the RAM 622.

[0091] Embodiments of the present disclosure can be implemented by the program 630 so that the device 600 can perform any process of the disclosed Figures 3-5 Embodiments of the present disclosure can also be implemented by hardware or by a combination of software and hardware.

[0092] In some embodiments, the computer program 630 can be tangibly embodied in a computer readable medium, which can be included in the device 600 (e.g., the memory 620) or other storage medium accessible by the device 600. The device 600 can load the computer program 630 from the computer readable medium into the RAM 622 for execution. The computer readable medium can include any type of tangible non-transitory memory, such as ROM, EPROM, flash memory, hard disk, CD, DVD, and the like. The computer program 630 is stored on the computer readable medium.

[0093] In general, the various embodiments of the present disclosure can be implemented in hardware or special-purpose circuits, software, logic or any combination thereof. Some aspects can be implemented in hardware, while other aspects can be implemented in firmware or software which can be executed by a controller, microprocessor or other computing device. While various aspects of embodiments of the present disclosure are illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein can be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controler or other computing devices, or some combination thereof.

[0094] Embodiments of the present disclosure also provide at least one computer program product tangibly stored on a non-transitory computer readable storage medium. The computer program product includes computer executable instructions, for example, instructions included in program modules, executed by devices at a target real or virtual processor to perform any process described above with reference toFigures 3-5 Any processes discussed in the disclosure. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various embodiments, the functionality of the program modules can be combined or split between program modules as desired. Machine executable instructions for program modules can be executed within the local or distributed device. In a distributed device, program modules can be located in local and remote storage media.

[0095] Program code for carrying out methods of embodiments of the disclosure can be written in any combination of one or more programming languages. The program code can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor of the computer or other programmable data processing apparatus, enables the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code can execute entirely on a machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

[0096] In the context of this document, a computer program code or related data can be carried by any suitable carrier for enabling a device, apparatus, or processor to perform various processes and operations as described above. Examples of carriers include signals, computer readable media, etc.

[0097] The computer readable medium can be a computer readable signal medium or a computer readable storage medium. The computer readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the computer readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0098] Furthermore, while operations are depicted in a particular order, this should not be understood as requiring such order nor that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing can be advantageous. Likewise, while several specific implementation details are contained in the above discussion, these should not be construed as limiting the scope of the disclosure, but merely as providing an overview of specific embodiments thereof. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination.

[0099] While the disclosure has been described in terms of specific embodiments thereof, it is to be understood that the disclosure is not necessarily limited to the specific features or acts described, but rather that the intention is to be broadly construed encompassing numerous alternatives, equivalents, and modifications not specifically set forth herein. Particularly, while the disclosure has been described in terms of specific embodiments thereof, it is to be understood that the disclosure is not necessarily limited to the specific features or acts described, but rather that the intention is to be broadly construed encompassing numerous alternatives, equivalents, and modifications not specifically set forth herein.

[0100] It should be fully appreciated that the use of personally identifiable information should follow privacy practices that are commonly considered to meet or exceed industry or governmental requirements for maintaining the privacy of users. In particular, personally identifiable information data should be managed and processed so as to minimize the risk of inadvertent or unauthorized access or use, and the nature of authorized use should be clearly indicated to users.

Claims

1. A method for determining interface timing parameters of a communication terminal tester, characterized in that, The communication terminal tester includes a first processor, a second processor, and an radio frequency circuit. The first processor is configured to run a scheduler program and an L1 layer control plane program. The scheduler program is used to schedule and control air interface time-frequency resources, and the L1 layer control plane program is used to perform L1 layer resource control and interface interaction. The second processor is configured to run a signal processing algorithm program and interact with the first processor and the radio frequency circuit. The first processor is configured with shared memory for interface interaction with the second processor. The method includes: The values ​​of the first, second, and third parameters corresponding to the target subcarrier interval are obtained. The first parameter is the number of basic time units required for the maximum processing time of the L1 layer control plane program. The second parameter is the number of basic time units required for the maximum processing time of the signal processing algorithm program. The third parameter is the number of basic time units that need to be delayed in the transmission timing after the L1 layer control plane program has finished writing the first partition of the shared memory and before the second processor reads the first partition. The basic time unit is the single time slot length corresponding to the maximum subcarrier interval in the application scenario supported by the communication terminal tester. Based on the corresponding values ​​of the first, second, and third parameters, the first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter are obtained respectively. The fourth parameter is the number of basic time units that the scheduler program needs to advance the scheduling relative to the RF circuit's transmission of the RF signal in the transmission timing sequence; the fifth parameter is the number of basic time units that the L1 layer control plane program needs to advance the writing of the first partition relative to the RF circuit's transmission of the RF signal in the transmission timing sequence; and the sixth parameter is the number of basic time units that the L1 layer control plane program needs to delay in reading the second partition of the shared memory relative to the RF circuit's reception of the RF signal in the reception timing sequence. The first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter are output so that the value of the fourth parameter in the first value range, the value of the fifth parameter in the second value range, and the value of the sixth parameter in the third value range can be determined by debugging the communication terminal tester.

2. The method as described in claim 1, characterized in that, The step of obtaining the first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter based on the corresponding values ​​of the first parameter, the second parameter, and the third parameter includes: The first value range of the fourth parameter is obtained according to the first constraint condition, wherein the first constraint condition includes: the difference between the product of the fourth parameter and the basic time unit and the sum of the products of the first parameter and the basic time unit, the second parameter and the basic time unit, and the third parameter and the basic time unit is greater than zero; or the difference between the fourth parameter and the sum of the first parameter, the second parameter, and the third parameter is greater than zero.

3. The method as described in claim 1, characterized in that, The step of obtaining the first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter based on the corresponding values ​​of the first parameter, the second parameter, and the third parameter includes: The second range of values ​​for the fifth parameter is obtained according to the second constraint condition, wherein the second constraint condition includes: the difference between the product of the fifth parameter and the basic time unit and the sum of the product of the second parameter and the basic time unit and the product of the third parameter and the basic time unit is greater than zero; or the difference between the fifth parameter and the sum of the second parameter and the third parameter is greater than zero.

4. The method as described in claim 1, characterized in that, The step of obtaining the first value range of the fourth parameter, the second value range of the fifth parameter, and the third value range of the sixth parameter based on the corresponding values ​​of the first parameter, the second parameter, and the third parameter includes: The third range of values ​​for the sixth parameter is obtained based on the third constraint condition, wherein the third constraint condition includes: the difference between the product of the sixth parameter and the basic time unit and the product of the second parameter and the basic time unit is greater than zero; or the difference between the sixth parameter and the second parameter is greater than zero.

5. The method according to any one of claims 1-4, characterized in that, Also includes: The value of the seventh parameter is determined based on the corresponding values ​​of the fifth parameter, the sixth parameter, and the total length of the shared memory partition. The seventh parameter is the number of basic time units required for the first partition to be written to and cleared.

6. The method as described in claim 5, characterized in that, The step of determining the value of the seventh parameter based on the corresponding values ​​of the fifth parameter, the sixth parameter, and the total length of the shared memory partition includes: The value of the seventh parameter is determined according to the fourth constraint, wherein the fourth constraint includes: the seventh parameter is greater than the largest of the fifth and sixth parameters, and less than the total length of the shared memory partition.

7. The method according to any one of claims 1-4, characterized in that, The values ​​of the first, second, and third parameters corresponding to the target subcarrier interval are determined based on the chip characteristics of the first and second processors and the target application scenario for which the communication terminal tester is used.

8. The method according to any one of claims 1-4, characterized in that, The index number of the first partition is determined based on the time slot number of the radio frequency circuit transmitting radio frequency signals; the index number of the second partition is determined based on the time slot number of the radio frequency circuit receiving radio frequency signals.

9. The method according to any one of claims 1-4, characterized in that, The basic time unit is equal to the period of the external interrupt of the first processor.

10. The method as described in claim 5, characterized in that, Also includes: The corresponding values ​​of the first parameter, the second parameter, the third parameter, the fourth parameter, the fifth parameter, the sixth parameter, and the seventh parameter are configured into the first processor and the second processor.

11. A communication terminal tester, characterized in that, include: Radio frequency circuits; The first processor is configured to run a scheduler program and an L1 control plane program. The scheduler program is used to schedule and control air interface time and frequency resources, and the L1 control plane program is used to perform L1 layer resource control and interface interaction. as well as The second processor is configured to run signal processing algorithm programs and interact with the first processor and the radio frequency circuit, wherein the first processor is configured with shared memory for interfacing with the second processor. The radio frequency circuit, the first processor, and the second processor operate according to the interface timing parameters determined by the method as described in any one of claims 1-10.

12. An electronic device, characterized in that, include: One or more processors; as well as One or more memories coupled to the one or more processors and storing instructions thereon, which, when executed individually or jointly by the one or more processors, cause the electronic device to perform the method of any one of claims 1-10.

13. A chip, characterized in that, Includes a circuit system configured to perform the method of any one of claims 1-10.

14. A non-transitory computer-readable storage medium storing machine-executable instructions, which, when executed by one or more processors of a machine, cause the machine to perform the method of any one of claims 1-10.

15. A computer program product comprising machine-executable instructions, which, when executed by one or more processors of a machine, cause the machine to perform the method of any one of claims 1-10.

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