A scale out network backup path fast switching notification system and method

Abstract

The application relates to a scale out network backup path fast switching notification system and method, and aims to solve the problem that the switching time of an existing VRRP / BFD protocol cannot meet the high real-time requirement of an AI server scale out network; the scheme is realized through a cooperative architecture of CPU + inspection FPGA + power supply monitoring; the CPU runs a VRRP / BFD protocol stack and maintains a state table, the FPGA is responsible for real-time detection of power failure, port failure and GPU alarm, and a preloaded message is generated and sent within 1 main frequency cycle; the power supply monitoring module ensures that the power supply is maintained for greater than or equal to 5 ms after sudden power failure through an energy storage capacitor, and the complete sending of the fault message is guaranteed. The advantages are as follows: the system supports multi-scale out interface redundancy, adopts a low-power consumption switching chip and an independent minimum power supply domain design, realizes end-to-end delay of fault detection and backup path switching of less than or equal to 1 ms, significantly improves the fault response speed and reliability of the AI server scale out network, and is suitable for network continuity guarantee of a high-density AI training cluster.

Description

TECHNICAL FIELD

[0001] The application belongs to the computer system and relates to the field of AI server network communication technology, in particular to a scale out network backup path fast switching notification system and method. BACKGROUND

[0002] With the rapid development of artificial intelligence technology, AI server clusters (especially scale out horizontal expansion architecture) are widely used in distributed training, deep learning inference and other high-performance computing scenarios. Such clusters usually build high-speed interconnection networks through RoCE V2 or IB protocols, and nodes need to maintain microsecond-level communication delay to ensure task continuity. However, network link or node failure may cause training data transmission interruption, and even cause task failure, so the fast switching capability of the backup path becomes a key technical bottleneck.

[0003] In the existing Ethernet field, VRRP (Virtual Router Redundancy Protocol) and BFD (Bidirectional Forwarding Detection Protocol) are the mainstream solutions to realize path redundancy and fault detection. Among them:

[0004] The VRRP protocol realizes master-slave node switching through a virtual IP address and priority mechanism, solving the single point failure problem, but relying on CPU software to process protocol packets, the switching delay is usually 50-100 ms;

[0005] The BFD protocol monitors the link state by periodically sending detection packets, and the detection time can be configured to be millisecond-level, but the packet generation and judgment still need CPU participation, and in extreme scenarios (such as node power failure) may cause packet loss due to power interruption.

[0006] In the AI server scale out network, the above-mentioned technologies have significant limitations:

[0007] 1. Switching delay cannot meet the needs: AI training tasks usually have a tolerance for network interruption of less than 1 ms, while the 100 ms level switching delay of VRRP / BFD will cause problems such as waste of GPU computing power and gradient synchronization failure;

[0008] 2. Loss of instructions in power failure scenarios: traditional solutions rely on CPU and switch chip power supply, when the device suddenly powers off, the switching instruction packet (such as VRRP Pri=0 announcement) cannot be sent in time, causing the upstream node to fail to trigger the backup path switching;

[0009] 3. State synchronization lag: the state information (such as port link state, whole machine health) between CPU and hardware modules is synchronized through software scheduling, which has a delay, which may cause state mismatch and cause false switching or missed switching.

[0010] In addition, the prior art is not optimized for the hardware characteristics of the AI server, such as DPU integration and multi-scale out port design, and is difficult to adapt to high-density node interconnection scenarios. Therefore, there is an urgent need for a fast switching scheme that can break through the CPU processing bottleneck and ensure reliable transmission of instructions in extreme scenarios. SUMMARY

[0011] The purpose of the present application is to solve the above-mentioned problems existing in the prior art, and to provide a scale out network backup path fast switching notification system.

[0012] To achieve the above-mentioned purpose, the technical solution adopted by the present application is:

[0013] A scale out network backup path fast switching notification system comprises:

[0014] A CPU module configured to run a VRRP / BFD protocol stack, generate and maintain a state maintenance table containing port ID, link state and whole machine state, and generate a pre-installed switching instruction packet based on the state maintenance table;

[0015] An inspection FPGA module in communication connection with the CPU module and configured to detect power failure, scale out port failure and GPU end failure in real time, synchronously store the state maintenance table, and determine whether to send the pre-installed switching instruction packet according to a preset strategy;

[0016] A device power supply monitoring module configured to monitor the device power supply state, test the discharge maintenance time of the whole machine or part of the module after power failure, and ensure the complete sending of the pre-installed switching instruction packet in the power failure scenario;

[0017] A switching module connected with the CPU module and the inspection FPGA module and configured to support link switching of multiple scale out ports;

[0018] The inspection FPGA module sends the pre-installed switching instruction packet to the upstream device through the switching module when detecting a failure, triggers backup path switching, and the response time of the switching does not exceed 1ms.

[0019] Preferably, the inspection FPGA module is further configured to receive VRRP priority and BFD initial state information sent by the CPU module, and has a state maintenance table that is updated synchronously with the CPU module, the state maintenance table comprising port ID, link state and whole machine state.

[0020] Preferably, the device power supply monitoring module comprises:

[0021] A power input filtering monitoring unit configured to output power input abnormality alarm;

[0022] A holding capacitor unit is configured to provide energy storage when a power input is abnormal, to maintain power supply of the patrol FPGA module and the switching module;

[0023] A power domain management unit is configured to prolong the discharge time after power failure by minimum power domain design in a high-power consumption scenario of the device.

[0024] Preferably, the switching module is an external low-power consumption switching chip configured to maintain the sending capability of the preloaded switching instruction packet when the device is powered off.

[0025] Another object of the present application is to provide a scale out network backup path fast switching notification method.

[0026] To achieve the above-mentioned second object, the technical scheme adopted by the present application is:

[0027] A scale out network backup path fast switching notification method comprises the following steps:

[0028] S1, state detection: the patrol FPGA module detects the power state, the scale out port link state and the GPU end state in real time;

[0029] S2, state synchronization: the CPU module generates a state maintenance table containing port ID, link state and whole machine state, and synchronizes to the patrol FPGA module;

[0030] S3, fault decision: the patrol FPGA module decides whether to send a preloaded switching instruction packet according to a preset strategy and the detected fault state, in combination with the state maintenance table;

[0031] S4, fast switching: if it is decided to send the preloaded switching instruction packet, the preloaded switching instruction packet is sent to the upstream device through the switching module to trigger backup path switching, and the response time of the switching does not exceed 1ms;

[0032] S5, power failure guarantee: the power supply of the whole machine or part of the module after power failure is maintained through the device power supply monitoring module to ensure the successful sending of the preloaded switching instruction packet in step S4.

[0033] Preferably, in step S3, the preset strategy includes that the patrol FPGA module immediately triggers the sending process of the preloaded switching instruction packet when detecting power failure, scale out port link failure or GPU end failure.

[0034] Preferably, in step S5, the device power supply monitoring module determines the energy storage capacity of the holding capacitor by testing the discharge time, ensuring that the power supply time of the patrol FPGA module and the switching module after power failure is not less than the sending period of the preloaded switching instruction packet.

[0035] Preferably, the preloaded switching instruction packet is a customized packet based on the VRRP / BFD protocol, containing a fault node identifier, a backup path identifier and a switching execution instruction.

[0036] As the above technical solutions are adopted, the application has the following beneficial effects:

[0037] 1. The application accelerates fault detection and packet sending through FPGA hardware, and combines hardware forwarding of a low-power switching chip to shorten the backup path switching time from 100 ms in the prior art to ≤1 ms, meeting the microsecond-level tolerance requirement of AI training tasks on network interruption.

[0038] 2. The application adopts a minimum power domain (only FPGA and switching module power supply) and a holding capacitor design to ensure that the switching instruction packet can be completely sent when the device suddenly loses power, solve the packet loss problem caused by power interruption in the traditional scheme, and effectively improve the switching success rate.

[0039] 3. The application synchronizes the state table of the CPU and the FPGA in real time and adopts a hardware logic decision mechanism to avoid state mismatch caused by software scheduling, effectively reducing the false switching rate. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a structural flowchart of an embodiment of the scale out network backup path fast switching notification system in the application.

[0041] Figure 2 is a functional configuration structural diagram of an embodiment of the CPU module and the patrol FPGA module in the application.

[0042] Figure 3 is a structural flowchart of an embodiment of the device power supply monitoring module in the application.

[0043] Figure 4 is a structural flowchart of an embodiment of the software decision in the application.

[0044] Figure 5 is a structural flowchart of an embodiment of the scale out network backup path fast switching notification method in the application.

[0045] The reference signs are shown as follows:

[0046] 1. CPU module; 2. Patrol FPGA module; 3. Device power supply monitoring module;

[0047] 4. The exchange module. DETAILED DESCRIPTION

[0048] Referring to the drawings Figures 1-5 The present application mainly relates to a scale out network backup path fast switching notification scheme, mainly applied to an AI server. Although the existing VRRP and BFD protocols can solve the backup and switching problems, the switching time is in the 100 ms level, which cannot meet the needs of the AI server, especially when the response is not fast enough in the case of sudden power failure or path failure. Based on this, the present application provides a scale out network backup path fast switching notification system, which comprises:

[0049] The CPU module 1 is configured to run the VRRP / BFD protocol stack, generate and maintain a state maintenance table containing port ID, link state and whole machine state, and generate a pre-installed switching instruction message based on the state maintenance table. Specifically, the VRRP / BFD protocol stack can be run by using a multi-core processor, and the exchange module integrated by the DPU (data processing unit) is used to realize the fast forwarding of the protocol message. The state maintenance table can adopt a hash table structure, and the port ID, link state and whole machine state are updated every 10 μs. The switching instruction message containing VRRP Pri=0 and BFD Down state is pre-generated and stored in the cache of the FPGA.

[0050] The inspection FPGA module 2 is in communication connection with the CPU module 1 and is configured to detect power failure, scale out port failure and GPU end failure in real time, synchronously store the state maintenance table, and determine whether to send the pre-installed switching instruction message according to the preset strategy.

[0051] During the period, the communication protocol between the FPGA and the CPU generally adopts a high-speed communication protocol, and the PCIE is the most commonly used high-speed communication interface of the CPU and is widely used for fast access and state synchronization between the FPGA and the CPU. Therefore, the communication protocol conforms to the high-speed PCIE IO standard, and the interrupt can also adopt an in-band interrupt mode.

[0052] In this embodiment, the CPU needs to run the VRRP and BFD protocol stacks at the same time, and the protocol stack itself mainly interacts with the FPGA through the PORT / LINK maintenance table corresponding to the VRRP / BFD parameter table (PRI / STA field definition). The main content is the state of the PORT and the state of the whole machine. The PORT state needs to be corresponded to the scale out port of the device.

[0053] The state maintenance table is used for the FPGA to determine to which port or link partner to send a message. The message can be an emergency highest priority message or a low priority state report message. However, the message itself needs to conform to the frame format of VRRP / BFD. Of course, the PORT ID and the LINK state need to be finally converted into the frame structure definition of VRRP / BFD.

[0054] The following briefly describes the above two protocols, but the focus of the present application is not on the two protocols, and only serves as background knowledge. VRRP is a protocol for providing gateway redundancy backup, mainly solving the problem of single point failure of the default gateway; and BFD is a mechanism for quickly detecting network link failure, which can complete detection within milliseconds. BFD itself does not perform switching actions, and only notifies the associated upper layer protocol, such as VRRP / OSPF, to trigger fault processing. The common VRRP+BFD linkage scheme can improve the fault switching performance. BFD can make up for the deficiency of VRRP's second-level detection, and compress the fault switching time to within 200 ms. The typical scenario is when the uplink fails, BFD notifies VRRP to directly trigger the master-slave switching, avoiding the default 3-second waiting of VRRP.

[0055] The detection of the port state is related to the deployment of VRRP / BFD. The PORT state represents different outlets of the Scaleout network. For example, the device has four scale out network ports. The state of these ports is usually monitored by the FPGA, such as port los or flash-off. In this way, the CPU protocol stack can be notified of the PORT state, and the VRRP protocol stack can quickly switch to the standby port.

[0056] In addition, the FPGA module will determine that the device is about to power off when it detects the interruption of the power abnormal alarm. Therefore, the interruption signal is used to directly trigger the message sending, and after one clock cycle, the preloaded message sending module will be triggered to start the message sending process and send the preloaded message to the FPGA message sending module.

[0057] Furthermore, regarding message transmission in emergency situations, there are generally very stringent time requirements. Therefore, FPGAs are used to pre-install messages and then send them with a single click, directly to scale-out ports or switching modules. The most important field in the pre-installed message is the Priority field in the VRRP frame structure definition. The protocol stipulates that when this field is 0, it means that the device has stopped parsing VPPR messages, indicating that the node has failed. Previously, a field value of 0 was used to indicate that the device had experienced an emergency power condition and was about to go offline; after the peer device's VRRP protocol stack received this message, it could switch to the backup device. Device power monitoring module 3 is configured to monitor the device's power supply status and test the discharge sustaining time of the entire machine or some modules after a power outage, ensuring the complete transmission of the pre-installed switching command message in a power outage scenario.

[0058] In this embodiment, the device power monitoring module includes:

[0059] The power input filtering monitoring unit uses an LC filter circuit to suppress input ripple and monitors the voltage through a comparator. When the input voltage is less than the threshold, it outputs a low-level alarm signal to the FPGA.

[0060] The holding capacitor unit is configured to provide energy storage in the event of a power input abnormality, thereby maintaining the power supply to the inspection FPGA module and the switching module;

[0061] The power domain management unit is configured to extend the discharge time after power failure through a minimum power domain design in high power consumption scenarios of the device.

[0062] Furthermore, such as Figure 3 As shown, the power supply monitoring scheme in this embodiment is as follows:

[0063] 1. The Input stage is the first-level input of the power supply, mainly responsible for power input filtering and monitoring, and can output power input abnormality alarms.

[0064] 2. Hold-up capacitor is a power holding capacitor, mainly used to provide power storage to ensure the stability of power input. It can also be used to maintain normal power output for a period of time when the power input is abnormal, so as to complete some log recording or last words tasks.

[0065] 3. The On-Board Power Rail Active is the device's Level 2 power supply, primarily responsible for powering various hardware components. When the device requires significant power consumption, a dedicated minimum power domain needs to be designed to ensure that the minimum system can utilize hold-up time to operate for extended periods to complete its intended tasks.

[0066] 4. Power monitor is the power supply working state monitoring of the device, and can report the interruption of power supply anomaly to FPGA to start the fast packet assembly and sending process.

[0067] 5. FPGA / Packet / ports is the minimum packet sending path of the device, which needs to be considered to complete the composition and sending of the message within 1 ms.

[0068] In the present embodiment, the hardware subsystem of the general AI server adopts a 48V bus power supply design, and the secondary power supply in the later stage works based on a 48V input voltage. Therefore, the power supply detection circuit detects the voltage based on 48V; when the 48V bus voltage abnormally drops, such as to 36V, the secondary power supply will not work normally and cannot output a normal voltage. Therefore, the power supply detection circuit will detect the voltage and start warning if the voltage is lower than 42V, prompting the system to stop working after T time. Through the power consumption measurement value of the above-mentioned typical system, the T time is generally 2-10 ms. If a longer holding time is required, a holding capacitor circuit will be used to prolong the voltage holding time.

[0069] The size of the Hold up cap power holding capacitor can be calculated according to the formula: C = 2PΔt / (U1² - U2²), wherein P is the load power, Δt is the required holding time, U1 is the initial voltage, and U2 is the minimum working voltage. The formula is based on the principle of energy conservation, and the energy stored by the capacitor is E = ½C(U1² - U2²), and the energy consumed by the load is PΔt. For example, when the load power is 375W (considering 85% conversion efficiency) and the holding time is 9ms, the total series capacitance minimum value is calculated to be 820μF.

[0070] In addition, the standard signal interruption protocol is usually used between the FPGA and the power supply monitoring module. The power supply monitoring module is generally an ADC voltage acquisition module, which can pre-configure the abnormal voltage threshold through configuration resistance or internal ROM or I2C bus, such as setting the abnormal voltage to be below 42V. The lower the abnormal voltage setting, the less time left for the system to react abnormally, and the higher the abnormal voltage setting, the more likely it is to cause false detection of voltage fluctuations and cause the system to malfunction. Therefore, after the power supply monitoring module detects the abnormal bus voltage, it will report a hardware interruption signal to the FPGA, and the signal is generally high, and the low state is an abnormal alarm; and the FPGA recognizes the power supply abnormal interruption, and can directly send the pre-installed VRRP Priority=0 protocol message, which is generally for all ports; this is the highest priority.

[0071] Further, it can ensure that the device can still send the switching instruction message completely after sudden power failure through the multi-level power management design, solve the problem of message loss caused by power failure in the traditional scheme, and improve the system stability in extreme scenarios.

[0072] In the embodiment, the switching module 4 is connected with the CPU module and the inspection FPGA module, and is configured to support link switching of multiple scale out ports. Specifically, a low-power consumption switching chip can be selected to support multiple scale out ports, and the hardware forwarding engine is used to realize the line-speed forwarding of the preloaded switching instruction message. The external low-power consumption switching chip is configured to maintain the sending capability of the preloaded switching instruction message when the device is powered off. The low-power consumption switching chip is combined with the power-off retention design to avoid message forwarding interruption when the device is powered off, guarantee the reliable transmission of the backup path switching instruction, and improve the switching success rate.

[0073] The inspection FPGA module 2 sends the preloaded switching instruction message to the upstream device through the switching module to trigger the backup path switching when a fault is detected, and the response time of the switching is not more than 1 ms. Further, the FPGA is used to accelerate the fault detection and message sending, and the low-power consumption component and the minimum power domain design are combined to shorten the backup path switching time from the 100 ms level in the prior art to ≤1 ms, solve the problem of training task interruption caused by fault switching delay in the AI server scale out network, and improve the system reliability.

[0074] As shown in FIG. 1, Figure 2 In the embodiment, the inspection FPGA module 2 is further configured to receive the VRRP priority and BFD initial state information sent by the CPU module, and has a state maintenance table which is updated synchronously with the CPU module. The state maintenance table includes port ID, link state and whole machine state. Specifically, the FPGA receives the VRRP priority (Pri=0 indicates forced switching) and BFD initial state sent by the CPU through the UART interface, and stores these parameters in the on-chip BRAM. The state maintenance table adopts a dual-port RAM design. The CPU writes the PORT ID, link state and whole machine state through the AXI bus, and the FPGA reads the updated data every 500 ns to ensure seamless synchronization with the CPU state information, avoid state mismatch caused by software delay, effectively shorten the fault detection response time, and further guarantee the immediacy of the switching instruction.

[0075] In the embodiment, the FPGA in the test system can select the A7-100T series of XLINK, the main frequency can reach 250M, the Serdes rate can reach 6.25Gbps, and the power consumption is generally 5-8W.

[0076] The power supply monitoring circuit is generally selected from an ADC detection circuit of TI / ADI, which is provided with a hardware configuration resistor or an I2C control interface to preset a detection threshold and participation, and a hardware interrupt signal to quickly report an exception.

[0077] The actually measured test results are as follows:

[0078] The VRRP / BFD without the application of the application does not have a fast processing for the power supply exception, and the time interval for detecting the exception is generally 50ms-100ms.

[0079] The switching time of the VRRP / BFD adopting the fast detection processing mechanism of the application is 5-20ms (considering the corresponding time of the opposite VRRP, the time period is within the expectation).

[0080] In the embodiment, the scale out network backup path fast switching notification method comprises the following steps:

[0081] S1, state detection: the power supply state, the scale out port link state and the GPU end state are detected in real time through the patrol FPGA module, and the detection results are written into the state maintenance table in real time;

[0082] S2, state synchronization: the CPU module generates the state maintenance table containing the port ID, the link state and the whole machine state according to the preset VRRP / BFD strategy (such as port priority, fault retry times), and synchronizes to the patrol FPGA module;

[0083] S3, fault decision: the patrol FPGA module decides whether to send the pre-installed switching instruction packet according to the preset strategy and the detected fault state in combination with the state maintenance table; specifically, the FPGA built-in decision logic (based on a combination logic circuit) calls the pre-installed switching instruction packet immediately when detecting the power supply fault, the port link Down or the GPU alarm, and sends the VRRP Pri=0 packet or the BFD fault packet through the port module; the standardized fault notification packet format can ensure that the upstream device quickly identifies the switching intention and avoids protocol analysis delay.

[0084] S4, fast switching: if it is decided to send the pre-installed switching instruction packet, the pre-installed switching instruction packet is sent to the upstream device through the switching module to trigger the backup path switching, and the response time of the switching does not exceed 1ms;

[0085] S5, power failure guarantee: the power supply of the whole machine or part of the module after power failure is maintained through the device power supply monitoring module to ensure the successful sending of the pre-installed switching instruction packet in step S4; specifically, when detecting that the input voltage drop is less than a preset value, the power supply monitoring module immediately notifies the FPGA through an interrupt, and the FPGA starts the pre-installed switching instruction packet sending within a certain time, and automatically powers off after the sending is completed by using the holding capacitor power supply.

[0086] Further, through the hardware-accelerated detection, decision and sending process, the end-to-end switching time is reduced from the traditional 100 ms level to the 1 ms level, which is effectively improved compared with the traditional CPU software processing, and meets the needs of low-delay switching of the AI server scale-out network.

[0087] In the present embodiment, the preset strategy in step S3 includes: the inspection FPGA module triggers the sending process of the preloaded switching instruction packet immediately when detecting power failure, scale-out port link failure or GPU end failure; the fine fault triggering condition avoids misjudgment, and the decision mechanism realized by hardware logic compresses the response time to the microsecond level, solving the problem of large delay of traditional software strategy decision.

[0088] In step S5, the device power supply monitoring module determines the energy storage capacity of the holding capacitor by testing the discharge time, ensuring that the power supply time of the inspection FPGA module and the switching module after power failure is not less than the sending period of the preloaded switching instruction packet; through scientific discharge time testing and capacitor configuration, it ensures 100% sending success rate of the switching instruction packet in the power failure scenario, eliminating the risk of switching failure caused by insufficient power supply.

[0089] In the present embodiment, the preloaded switching instruction packet is a customized packet based on VRRP / BFD protocol, containing fault node identification, backup path identification and switching execution instruction; the structured packet format ensures that the upstream device quickly analyzes the switching instruction, and realizes end-to-end fault recovery within 1 ms in combination with hardware-level path switching, guaranteeing the continuity of AI training tasks.

[0090] It should be noted that: through hardware acceleration and system collaborative design, three core technical effects of AI server scale-out network backup path switching are realized:

[0091] 1. Switching time is reduced from 100 ms to 1 ms: FPGA hardware logic replaces traditional CPU software processing to compress the end-to-end delay of fault detection, packet generation and sending to ≤1 ms, meeting the high real-time needs of AI training / inference tasks for network link continuity.

[0092] 2. Reliable notification capability under sudden failure: the power supply monitoring module in combination with the energy storage capacitor design ensures that the device can maintain ≥5 ms power supply after sudden power failure, guarantees the complete sending of VRRP / BFD switching packets, and avoids the loss of switching notification caused by power failure.

[0093] 3. Adaptive processing of multi-scenario faults: Support scale out port fault, GPU alarm, whole machine power failure and other multi-type fault detection, through the state maintenance table and preloaded message strategy of FPGA and CPU cooperation, realize single port switching, whole machine offline and other differentiated response, improve the stability in complex network environment.

[0094] The above related descriptions and the descriptions of the embodiments are for the convenience of the ordinary skilled in the art to understand and apply the present application. Those skilled in the art can easily make various modifications to these contents, and apply the general principles described herein to other embodiments without creative labor. Therefore, the present application is not limited to the above related descriptions and the descriptions of the embodiments, and the improvements and modifications made by those skilled in the art without departing from the scope of the present application should be within the protection scope of the present application.

Claims

1. A scale-out network backup path fast switching notification system, characterized in that, include: The CPU module is configured to run the VRRP / BFD protocol stack, generate and maintain a state maintenance table containing port ID, link status and overall system status, and generate pre-installed handover instruction messages based on the state maintenance table. The inspection FPGA module is communicatively connected to the CPU module and is configured to detect power failures, scale-out port failures, and GPU failures in real time. It synchronously stores the status maintenance table and determines whether to send the pre-installed switching instruction message according to a preset strategy. The inspection FPGA module reads updated data every 500ns to ensure seamless synchronization with the CPU status information. The equipment power monitoring module is configured to monitor the power supply status of the equipment, test the discharge maintenance time of the whole machine or some modules after power failure, and ensure the complete transmission of the pre-installed switching instruction message in the power failure scenario. The switching module, connected to the CPU module and the inspection FPGA module, is configured to support link switching with multiple scale-out ports; When the inspection FPGA module detects a fault, it sends the pre-installed switching instruction message to the upstream device through the switching module to trigger the backup path switching, and the switching response time does not exceed 1ms.

2. The system according to claim 1, characterized in that, The inspection FPGA module is also configured to receive VRRP priority and BFD initial state information sent by the CPU module, and to have a built-in state maintenance table that is updated synchronously with the CPU module. The state maintenance table includes port ID, link status and overall system status.

3. The system according to claim 1, characterized in that, The device power monitoring module includes: The power input filter monitoring unit is configured to issue an alarm for abnormal power input at the output. The holding capacitor unit is configured to provide energy storage in the event of a power input abnormality, thereby maintaining the power supply to the inspection FPGA module and the switching module; The power domain management unit is configured to extend the discharge time after power failure through a minimum power domain design in high-power scenarios of the device.

4. The system according to claim 1, characterized in that, The switching module is an external low-power switching chip, which is configured to maintain the ability to send the pre-installed switching instruction message when the device loses power.

5. A method for fast switching notification of scale-out network backup paths based on the system described in any one of claims 1-4, characterized in that, Includes the following steps: S1. Status Detection: Real-time detection of power status, scale-out port link status, and GPU status via FPGA inspection module; S2. Status Synchronization: The CPU module generates a status maintenance table containing port ID, link status, and overall system status, and synchronizes it to the inspection FPGA module. S3. Fault Judgment: The inspection FPGA module determines whether to send a pre-installed switching instruction message based on the preset strategy and the detected fault status, combined with the status maintenance table. S4. Fast switching: If the decision is made to send the pre-installed switching instruction message, the pre-installed switching instruction message is sent to the upstream device through the switching module to trigger the backup path switching, and the response time of the switching does not exceed 1ms; S5. Power Failure Protection: The power supply to the whole machine or some modules is maintained through the equipment power monitoring module after a power failure, ensuring the successful transmission of the pre-installed switching instruction message mentioned in step S4.

6. The method according to claim 5, characterized in that, In step S3, the preset strategy includes: when the inspection FPGA module detects a power failure, a scale-out port link failure, or a GPU failure, it immediately triggers the sending process of a pre-installed switching instruction message.

7. The method according to claim 5, characterized in that, In step S5, the device power monitoring module determines the energy storage capacity of the holding capacitor by testing the discharge time, ensuring that the power supply time of the inspection FPGA module and the switching module after power failure is not less than the sending cycle of the pre-installed switching instruction message.

8. The method according to claim 5, characterized in that, The pre-installed switchover instruction message is a customized message based on the VRRP / BFD protocol, which includes the fault node identifier, backup path identifier, and switchover execution instruction.

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