Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductors. The manufacturing method of the semiconductor device comprises the steps that a plurality of semiconductor columns arranged in an array mode are formed on a substrate, each semiconductor column comprises a first electrode region, a channel region and a second electrode region which are sequentially distributed in the direction perpendicular to the substrate, and the first electrode regions are close to the substrate; and sequentially forming a gate dielectric layer and a gate which at least partially surround the semiconductor column on the side wall of the semiconductor column, wherein the gate dielectric layer comprises an insulating layer and a ferroelectric layer. According to the semiconductor device and the manufacturing method thereof, the manufacturing process can be effectively simplified, and the device performance can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] This application provides a semiconductor device and its fabrication method, as well as an electronic device, which can effectively simplify the manufacturing process and improve device performance.

[0005] This application provides a method for fabricating a semiconductor device, including: A plurality of semiconductor pillars are formed on a substrate in an array, the semiconductor pillars including a first electrode region, a channel region and a second electrode region distributed sequentially along a direction away from the substrate; A gate dielectric layer and a gate electrode, at least partially surrounding the semiconductor pillar, are sequentially formed on the sidewall of the semiconductor pillar, the gate dielectric layer comprising a ferroelectric layer.

[0006] In some embodiments, after forming the gate dielectric layer and the gate, the method further includes: The second electrode region of the semiconductor pillar is doped to form an electrical contact layer; A source line is formed on the side of the electrical contact layer away from the substrate, and the source line is connected to the electrical contact layer.

[0007] In some embodiments, a plurality of semiconductor pillars arranged in an array are formed on the substrate, including: A plurality of first trenches extending along a first direction are formed on the substrate, and a first dielectric layer is filled in the first trenches; A plurality of second trenches extending along a second direction are formed on the substrate, the first trenches and the second trenches defining a plurality of semiconductor pillars; a second dielectric layer is deposited in the second trenches; A gate dielectric layer and a gate electrode, at least partially surrounding the semiconductor pillar, are sequentially formed on the sidewall of the semiconductor pillar, including: The second dielectric layer covering one sidewall of the second trench is removed, the second dielectric layer on the other sidewall is retained, and a third dielectric layer is formed in the second trench, the third dielectric layer filling the second trench and contacting the second dielectric layer, the first dielectric layer and the semiconductor pillar respectively; A portion of the retained second dielectric layer is removed, exposing only the second electrode region and the channel region of the semiconductor pillar, forming a first cavity in the region where the second dielectric layer is removed; and the first dielectric layer between two adjacent semiconductor pillars in the second direction is removed, forming a second cavity in the region where the first dielectric layer is removed; each of the first cavities and each of the second cavities in the second trench are connected and extend in the second direction; An insulating layer, a ferroelectric layer, and a word line are formed sequentially in the connected first and second cavities. The insulating layer, ferroelectric layer, and word line only surround the channel region, exposing the second electrode region. The gate is a part of the word line.

[0008] In some embodiments, before forming a plurality of arrayed semiconductor pillars on the substrate, the method further includes: A first substrate is provided, and a plurality of bit lines extending along a first direction are formed on the first substrate; A second substrate is provided, and an epitaxial layer is fabricated on the second substrate. The epitaxial layer includes a first doped region, a channel region, and a second doped region in sequence along a direction perpendicular to the second substrate. The first substrate on which the bit line is formed is bonded to the second substrate on which the epitaxial layer is formed, such that the bit line is in contact with the epitaxial layer; The second substrate is thinned to expose the epitaxial layer, and the substrate comprises the bonded first substrate and the epitaxial layer.

[0009] In some embodiments, a plurality of first trenches extending along a first direction are formed on the substrate, and a first dielectric layer is filled in the first trenches; a plurality of second trenches extending along a second direction are formed on the substrate, and the first trenches and the second trenches define a plurality of semiconductor pillars; a second dielectric layer is deposited in the second trenches; comprising: The epitaxial layer is patterned using a patterning process to form the first trench extending in a first direction, and the first trench exposes the bit line; A first dielectric layer is formed, which fills the first trench and covers the exposed bit line; The epitaxial layer and the first dielectric layer are patterned by a patterning process to form the second trench. The epitaxial layer includes a plurality of semiconductor pillars arranged in an array between the first trench and the second trench. The semiconductor pillars include a first electrode region located in the first doped region and a second electrode region located in the second doped region. A second dielectric layer is formed, which covers the sidewalls and bottom wall of the second trench, as well as the two sidewalls of the semiconductor pillar facing each other in the first direction.

[0010] In some embodiments, the sequential formation of the insulating layer, ferroelectric layer, and word line within the interconnected first and second cavities includes: An initial gate dielectric layer is formed, which covers the sidewalls and bottom wall of the first cavity and the sidewalls and bottom wall of the second cavity, and the initial gate dielectric layer does not completely fill the first cavity and the second cavity; An initial word line is formed, which fills the first cavity and the second cavity; By etching back a portion of the initial gate dielectric layer and the initial word line, the gate dielectric layer and the word line located in the channel region of the semiconductor pillar are formed, exposing the second electrode region.

[0011] In some embodiments, a plurality of semiconductor pillars arranged in an array are formed on the substrate, including: A substrate is provided, and a patterning process is performed on the substrate to form the first trenches that extend along a first direction and are spaced apart along a second direction; A first dielectric layer is formed, which fills the first trench and covers the substrate, and the substrate is doped to sequentially form a first doped region, a channel region, and a second doped region in a direction away from the substrate. The substrate and the first dielectric layer are patterned by a patterning process to form a plurality of second trenches extending along a second direction and arranged along a first direction. The substrate includes a plurality of semiconductor pillars arranged in an array between the first trenches and the second trenches. The semiconductor pillars include a first electrode region located in the first doped region and a second electrode region located in the second doped region. A second dielectric layer is formed, which covers the sidewalls and bottom wall of the second trench, as well as the two sidewalls of the semiconductor pillar; The portion of the substrate near the first electrode region is removed by a patterning process to form a cavity, and bit lines are formed within the cavity. The bit lines extend along a first direction and are spaced apart along a second direction.

[0012] In some embodiments, prior to the sequential formation of a gate dielectric layer and a gate electrode that at least partially surround the semiconductor pillar on the sidewalls of the semiconductor pillar, the following steps are included: A fourth dielectric layer is formed, which fills the second trench and contacts both the second dielectric layer and the first dielectric layer. By removing part of the second dielectric layer through a patterning process, the second electrode region and channel region of the semiconductor pillar are exposed, forming a first cavity with two sidewalls facing each other in the first direction exposed, and removing the first dielectric layer between two adjacent semiconductor pillars in the second direction to form a second cavity, the first cavity and the second cavity are connected. A gate dielectric layer and a gate electrode, at least partially surrounding the semiconductor pillar, are sequentially formed on the sidewall of the semiconductor pillar, including: The insulating layer, the ferroelectric layer, and the word line are formed successively in the first cavity and the second cavity, and the gate is a part of the word line.

[0013] In some embodiments, the doping treatment of the second electrode region of the semiconductor pillar to form an electrical contact layer includes: The surface of the second electrode region is doped with phosphorus or arsenic. A conductive layer comprising nickel, cobalt, or titanium is formed on the side of the semiconductor pillar away from the substrate using a patterning process. The orthographic projection of the conductive layer onto the substrate coincides with the orthographic projection of the semiconductor pillar onto the substrate, and the conductive layer serves as the electrical contact layer.

[0014] In some embodiments, forming a source line on the side of the electrical contact layer away from the substrate includes: A source line is formed on the side of the electrical contact layer away from the substrate, and the source line covers the entire substrate; Alternatively, a patterning process can be used to form source lines on the side of the electrical contact layer away from the substrate. The source lines extend along a first direction and are spaced apart along a second direction, and the source lines are in contact with the electrical contact layer.

[0015] This application provides a semiconductor device, including: Substrate; A plurality of ferroelectric transistors are located on one side of the substrate and include a plurality of semiconductor pillars arranged in an array, a gate dielectric layer and a gate, wherein the semiconductor pillars include a first electrode region, a channel region and a second electrode region distributed sequentially in a direction away from the substrate; The gate dielectric layer and the gate electrode at least partially surround the channel region, and the gate dielectric layer includes a ferroelectric layer.

[0016] In some embodiments, the following are included: A plurality of bit lines, the bit lines extending along a first direction and spaced apart along a second direction, the bit lines being located below the semiconductor pillar and connected to the first electrode region; An electrical contact layer is located on the side of the semiconductor pillar away from the substrate and is connected to the second electrode region. The orthographic projection of the electrical contact layer on the substrate overlaps with the orthographic projection of the semiconductor pillar on the substrate. The source line is located on the side of the electrical contact layer away from the substrate, and the source line is connected to the electrical contact layer.

[0017] In some embodiments, logic circuitry is also disposed on the substrate; The logic circuit is located below the bit line, and the bit line is connected to the first electrode region by bonding.

[0018] In some embodiments, the source lines cover the entire substrate; or, the source lines extend along a first direction and are spaced apart along a second direction, and the orthographic projection of the source lines on the substrate overlaps with the orthographic projection of the semiconductor pillars on the substrate.

[0019] In some embodiments, word lines are also included; The character lines extend along the second direction and are spaced apart along the first direction; The gate at the corresponding position of each of the semiconductor pillars is part of the word line; The gate portion surrounds the channel region, and the gates at corresponding positions of the semiconductor pillars in the same row are connected to the same word line.

[0020] In some embodiments, each of the semiconductor pillars includes two sidewalls opposite each other in a first direction, and each word line is located in the region corresponding to only one of the two sidewalls.

[0021] In some embodiments, the word lines extend in a second direction and are periodically spaced in a first direction; The distance between the gates corresponding to two adjacent word lines in the first direction is not less than the sum of the first distance and the second distance. The first distance is the thickness of the semiconductor pillar in the first direction, and the second distance is the distance between the adjacent sidewalls of two adjacent semiconductor pillars in the first direction.

[0022] This application provides an electronic device, including the semiconductor device described in any of the above embodiments.

[0023] The technical solution provided in this application has at least the following beneficial effects: The semiconductor device and its fabrication method provided in this application have the advantage that the threshold voltage can be changed by the polarization state of the FeFET because the gate dielectric layer in the semiconductor device and the fabrication method contains a ferroelectric material layer. Thus, the storage function can be realized without a capacitor, which effectively simplifies the structure of the semiconductor device and reduces the manufacturing difficulty.

[0024] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0025] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the structure of ferroelectric memory in related technologies; Figure 2 This is a schematic diagram of the structure of a ferroelectric transistor in related technologies; Figure 3a and Figure 3b This is a schematic diagram of the polarization reversal of a ferroelectric transistor. Figure 4 A flowchart illustrating a method for manufacturing a memory according to an embodiment of this application; Figure 5 This is a schematic diagram of a planar structure of a memory provided in an embodiment of this application; Figures 6-21 The structural diagrams of the single-sided gate structure memory provided in the embodiments of this application are shown in different manufacturing processes. Figures 22-35 The structural diagrams of the ring gate structure memory provided in the embodiments of this application are shown in different manufacturing processes. Figure 36 A schematic diagram of the circuit connection relationship of a memory provided in an embodiment of this application; Figure 37 This is a schematic diagram of the circuit connection relationship of another memory provided in an embodiment of this application.

[0026] Figure label: 110 - Substrate; 111 - First electrode region; 112 - Second electrode region; 113 - Gate insulating layer; 114 - Word line; 115 - Bit line; 116 - Ferroelectric capacitor; 117 - Driver line; 118 - Lead; 211 - Silicon dioxide layer; 212 - Ferroelectric material layer; 311-First substrate; 312-Logic circuit; 313-First insulating layer; 314-Bit line; 3141-First conductive layer; 3142-Second conductive layer; 315-Second substrate; 316-Epipolar layer; 3161-First doped region; 3162-Channel region; 3163-Second doped region; 317-First trench; 318-First dielectric layer; 319-Second trench; 320-Semiconductor pillar; 3201-First electrode region; 3202-Channel region; 3 203 - Second electrode region; 321 - Second dielectric layer; 322 - Third dielectric layer; 323 - First cavity; 324 - Second cavity; 325 - Second cavity; 326 - Gate dielectric layer and gate electrode; 3261 - Interface oxide layer; 3262 - Ferroelectric material layer; 3263 - Gate electrode; 327 - Fifth dielectric layer; 328 - Electrical contact layer; 329 - Source line; 330 - Second insulating layer; 331 - Electrical connection structure; 332 - Third insulating layer; 333 - Pad; 411-Substrate; 412-Oxide layer; 413-Hard mask layer; 414-BARC layer; 415-Photoresist layer; 416-First trench; 417-First dielectric layer; 4111-First doped region; 4112-Channel region; 4113-Second doped region; 418-Second trench; 419-Semiconductor pillar; 4191-First electrode region; 4192-Channel region; 4193-Second electrode region; 420-Second dielectric layer; 421-Cavity; 422-Bit line; 423-Fourth dielectric layer; 424-Gate dielectric layer and gate; 4241-Initial gate dielectric layer; 4242-Initial gate; 425-Fifth dielectric layer; 426-Electrical contact layer; 427-Source line; 428-Sixth dielectric layer. Detailed Implementation

[0027] This application is described in detail below. Examples of embodiments of this application are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. Furthermore, detailed descriptions of known technologies that are unnecessary for the features of this application are omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0028] Those skilled in the art will understand that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0029] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0030] Currently, the relevant technologies include semiconductor devices with VCT structures. The memory cell array first forms embedded bit lines (BL), then word lines (WL), and then storage capacitors (storage nodes) are formed on the VCT. The fabrication process of this semiconductor device can be further simplified, and the structure can be further simplified and miniaturized.

[0031] This application provides a semiconductor device comprising a 1T0C memory cell, wherein the memory cell is a ferroelectric memory cell, and the semiconductor device can be a memory or other type of integrated circuit. Taking the memory as an example, the transistor in this memory is a ferroelectric field effect transistor (FeFET), which can change the threshold voltage (Vt) through the polarization state of the FeFET, thereby achieving the storage function without the need for a capacitor. The structure and manufacturing process of this semiconductor device are relatively simple.

[0032] The relevant technologies are explained below: Ferroelectric materials are materials that exhibit spontaneous polarization within a certain temperature range, and whose polarization direction can be altered by an applied electric field. These materials possess spontaneous polarization characteristics, and this spontaneous polarization can be redirected under the influence of an external electric field, exhibiting excellent hysteresis loop properties. Ferroelectric materials can be used in ferroelectric transistors and ferroelectric memories.

[0033] Figure 1 This is a schematic diagram of the FeRAM memory structure, as shown below. Figure 1As shown, the FeRAM memory includes a substrate 110, a ferroelectric capacitor 116 disposed on the substrate 110, and a transistor. The transistor includes a first electrode region 111, a second electrode region 112, a channel region located between the first electrode region 111 and the second electrode region 112, a gate insulating layer 113, and a gate, which is part of a word line 114. One end of the ferroelectric capacitor 116 is connected to the bit line 115 through the transistor, and the other end is connected to the drive line 117. When the FeRAM memory reads information 1, the polarization of the ferroelectric capacitor reverses, destroying the original storage state, which is a destructive storage.

[0034] Figure 2 This is a schematic diagram of the FeFET structure. Figure 3a and Figure 3b This is a schematic diagram of the polarization reversal of a FeFET, as shown below. Figure 2 As shown, the FeFET includes a substrate 110, a first electrode region 111 and a second electrode region 112 disposed on the substrate 110, a channel region located between the first electrode region 111 and the second electrode region 112, a gate insulating layer, and a gate. The gate is part of a word line 114. The gate insulating layer includes a silicon dioxide layer 211 and a ferroelectric material layer 212. The first electrode region 111 is connected to the bit line 115, and the second electrode region 112 is connected to an external device via a lead 118.

[0035] like Figure 2 , Figure 3a and Figure 3b As shown, when a high-voltage pulse is applied to word line 114, the ferroelectric material layer 212 is polarized (state 1), and when a low-voltage pulse is applied to word line 114, the ferroelectric material layer 212 is reverse polarized (state 0), thus enabling writing and erasing. When reading information, a voltage of approximately 0.1V is applied to word line 114, and the current magnitude is determined to determine whether information is stored.

[0036] The embodiments of this application will now be described with reference to the accompanying drawings.

[0037] This application provides a method for fabricating a semiconductor device, such as... Figure 4 As shown, it includes: S101. A plurality of semiconductor pillars arranged in an array are formed on a substrate. The semiconductor pillars include a first electrode region, a channel region and a second electrode region distributed sequentially along the direction away from the substrate. S102. A gate dielectric layer and a gate electrode, which at least partially surround the semiconductor pillar, are sequentially formed on the sidewall of the semiconductor pillar. The gate dielectric layer includes a ferroelectric layer.

[0038] The semiconductor device fabrication method provided in this application changes the threshold voltage by altering the polarization state of the FeFET, thereby achieving storage functionality without the need for a capacitor, effectively simplifying the structure of the semiconductor device and reducing manufacturing difficulty.

[0039] Taking a semiconductor device as an example, the transistors in the above memory are ferroelectric transistors with vertical channel regions, which will be described in detail below with reference to the accompanying drawings.

[0040] In the above embodiments, the gate of the transistor may at least partially surround the semiconductor pillar, for example, only surrounding a portion of the region; The semiconductor pillar has four sides, with two opposing sidewalls in the first direction and two opposing sidewalls in the second direction.

[0041] When the gate surrounds two opposing sidewalls of the semiconductor pillar, the transistor has a double-gate structure; when it surrounds only one sidewall, the transistor has a single-gate structure.

[0042] In an optional embodiment, the ferroelectric transistor provided in this application has a single-gate structure. The transistor and the bit line can be formed on different substrates, and then the two substrates are bonded together using a bonding process. See [link to relevant documentation]. Figures 5 to 21 As shown. Figure 5 This is a cross-sectional schematic diagram of a memory, including several bit lines BL extending along a first direction (the column direction of the semiconductor pillar array) and several word lines WL extending along a second direction (the row direction of the semiconductor pillar array). The semiconductor pillars distributed in the array are located near the intersection of the bit lines BL and the word lines WL.

[0043] In one specific embodiment, prior to step S101, the method further includes: providing a first substrate and forming a plurality of bit lines extending along a first direction on the first substrate; providing a second substrate and fabricating an epitaxial layer on the second substrate, the epitaxial layer sequentially including a first doped region, a channel region, and a second doped region along a direction perpendicular to the second substrate; bonding the first substrate with the bit lines formed to the second substrate with the epitaxial layer formed, such that the bit lines are in contact with the epitaxial layer; thinning the second substrate to expose the epitaxial layer, the substrate comprising the bonded first substrate and the epitaxial layer.

[0044] Specifically, such as Figure 6 As shown, the first substrate 311, which has bit lines 314, can also have logic circuits 312. The bit lines 314 are located above the logic circuits and exposed, facilitating electrical connection with the second substrate. The bit lines can be single-layer or multi-layer conductive layers; for example, the bit lines may include a first conductive layer 3141 and a second conductive layer 3142.

[0045] In specific implementation, the method for forming bit line 314 includes: depositing a tungsten (W) film or a nickel (Ni) film on the first insulating layer 313, and patterning the W film or Ni film to form a first conductive layer 3141; then depositing an oxide layer (e.g., silicon oxide) and performing chemical mechanical polishing (CMP) to make the oxide layer flush with the surface of the first conductive layer 3141 and expose the first conductive layer 3141; then depositing a cobalt (Co) film on the first conductive layer 3141, and patterning the Co film to form a second conductive layer 3142; then depositing an oxide layer (e.g., silicon oxide) and performing CMP to make the oxide layer flush with the surface of the second conductive layer 3142 and expose the second conductive layer 3142; the first conductive layer 3141 and the second conductive layer 3142 form bit line 314. The specific arrangement of the formed bit line 314 is described in [reference needed]. Figure 5 As shown; the patterning process includes the coating, exposure, development, etching, and partial or complete removal of the photoresist. Figure 6 a is a schematic diagram of the cross-sectional structure of the first substrate 311 after the bit line is formed. Figure 6 b is the corresponding top view. Alternatively, the material of the first conductive layer 3141 can also be copper (Cu), and a Cu film with bit line patterns can be formed using Cu-related processes.

[0046] like Figure 7 As shown, a second substrate 315 (such as a silicon substrate) is provided, and an epitaxial layer 316 is fabricated on the silicon substrate. The epitaxial layer 316 is a composite layer, which includes a first doped region 3161, a channel region 3162, and a second doped region 3163 in sequence along a direction perpendicular to the second substrate 315. These three regions correspond to three films of different materials. In specific implementations, the channel region and the doped region are doped with different concentrations.

[0047] like Figure 8 As shown, a first substrate 311 with bit lines 314 and a second substrate 315 with an epitaxial layer 316 are bonded together.

[0048] In a specific implementation, the second substrate 315 is flipped so that the epitaxial layer 316 faces the first substrate 311. Then, the epitaxial layer 316 and the first substrate 311 are hybrid bonded, so that the first doped region 3161 of the epitaxial layer 316 contacts the bit line 314. In this embodiment, the second substrate 315 can be a silicon substrate. The bit line 314 on the first substrate 311 includes a double-layer metal structure, and the metal in contact with the epitaxial layer 316 is formed of Co, which can improve the bonding strength after bonding. Co silicide is formed at the bonding interface. Co silicide has high stability and low resistivity, which can reduce the contact resistance between the bit line 314 and the epitaxial layer 316.

[0049] In one specific embodiment, for the memory cell array region, the above-mentioned S101 forms a plurality of arrayed semiconductor pillars on the substrate, including: forming a plurality of first trenches extending along a first direction on the substrate, filling the first trenches with a first dielectric layer; forming a plurality of second trenches extending along a second direction on the substrate, the first trenches and the second trenches defining a plurality of semiconductor pillars; depositing a second dielectric layer in the second trenches; wherein the substrate includes a bonded first substrate and an epitaxial layer.

[0050] Specifically, a plurality of first trenches extending in a first direction are formed on a substrate, and a first dielectric layer is filled in the first trenches. A plurality of second trenches extending in a second direction are formed on the substrate. The first trenches and second trenches define a plurality of semiconductor pillars. A second dielectric layer is deposited in the second trenches. The method includes: patterning an epitaxial layer using a patterning process to form first trenches extending in the first direction, with bit lines exposed at the bottom of the first trenches; forming a first dielectric layer that fills the first trenches and covers the exposed bit lines; patterning the epitaxial layer and the first dielectric layer using a patterning process to form second trenches, the epitaxial layer including a plurality of semiconductor pillars arranged in an array between the first trenches and the second trenches, the semiconductor pillars including a first electrode region located in a first doped region and a second electrode region located in a second doped region; and forming a second dielectric layer that covers the sidewalls and bottom wall of the second trenches, and covers the two sidewalls of the semiconductor pillars facing each other in the first direction.

[0051] Specifically, such as Figure 5 , Figure 8 and Figure 9 As shown, Figure 9 The diagram only shows the structure of the memory cell array region. The epitaxial layer 316 is patterned using a patterning process to form several structures along the first direction (e.g., ...). Figure 5 Extending in the direction shown and along the second direction (such as...) Figure 5 The first trench 317, arranged in the direction shown, exposes the bit line at the bottom of the first trench 317 (specifically, exposes the second conductive layer 3142). The cross-sectional structure formed after this step is as follows: Figure 9 As shown, where, Figure 9 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 9 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 9 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 9 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0052] Specifically, patterning the epitaxial layer 316 includes: depositing a hard mask on the epitaxial layer 316, and then forming a plurality of first trenches 317 extending along a first direction using photolithography and etching. The epitaxial layer 316 between adjacent first trenches in the AA direction is completely preserved, the epitaxial layer 316 in the BB direction (located in the first trench region) is completely etched away to expose the first substrate, and the epitaxial layers 316 in the CC and DD directions are partially removed. Alternatively, SADP (self-aligned double patterning) or SAQP (self-aligned quadruple patterning) methods can be used to create the first trenches 317 with smaller linewidths and smaller spacing.

[0053] like Figure 5 and Figure 10 As shown, a first dielectric layer 318 is then formed, filling the first trench 317 and covering the exposed bit lines. Specifically, after forming the first trench 317, an oxide layer (e.g., silicon oxide) is deposited using atomic layer deposition (ALD) and a spin-on-dielectric (SOD) method. The deposited oxide layer is then mechanically polished using CMP to form a smooth surface of the first dielectric layer 318. The cross-sectional structure after forming the first dielectric layer 318 is shown below. Figure 10 As shown, where, Figure 10 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 10 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 10 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 10 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0054] like Figure 5 and Figure 11 As shown, next, the epitaxial layer 316 and the first dielectric layer 318 are patterned using a patterning process to form a plurality of second trenches 319 extending along the second direction and spaced apart along the first direction. The epitaxial layer 316 is covered by the first trenches 317 ( Figure 11 c and Figure 11The first dielectric layer 318 is filled in d), and the second trench 319 is separated into several arrayed semiconductor pillars 320. The semiconductor pillars 320 include a first electrode region 3201 corresponding to the first doped region, a channel region 3202 corresponding to the channel region, and a second electrode region 3203 corresponding to the second doped region. The cross-sectional structure formed after this step is as follows: Figure 11 As shown, where, Figure 11 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 11 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 11 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 11 d corresponds to Figure 5 A cross-sectional view of the structure in the DD direction. In one specific embodiment, the depth of the second trench is less than the depth of the first trench, and the second trench does not expose the bit line; the second trench exposes the channel region 3202 and the second electrode region 3203, but does not expose the first electrode region 3201.

[0055] like Figure 5 and Figure 12 As shown, next, a second dielectric layer 321 is formed. The second dielectric layer 321 covers the sidewalls and bottom wall of the second trench 319, and covers the surface of the exposed semiconductor pillar 320 of the second trench, but does not fill the second trench. The second dielectric layer 321 is used to protect the semiconductor pillar 320, and the material of the second dielectric layer 321 can be the same as the material of the first dielectric layer 318. The cross-sectional structure formed after this step is shown in the figure. Figure 12 As shown, where, Figure 12 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 12 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 12 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 12 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0056] The second trench extends along a second direction and has two sidewalls facing each other in a first direction and a bottom wall connecting the two sidewalls. The two sidewalls of the second trench expose the sidewalls of corresponding regions of the two rows of semiconductor pillars. Each second trench exposes the two sidewalls facing each other in the first direction of each semiconductor pillar. The two sidewalls facing each other in the second direction of each semiconductor pillar are covered by the dielectric material in the first trench.

[0057] In one specific embodiment, a gate dielectric layer and a gate electrode are sequentially formed on the sidewalls of a semiconductor pillar, at least partially surrounding the semiconductor pillar. This includes: removing a second dielectric layer covering one of the two sidewalls of the second trench, retaining the second dielectric layers on the bottom wall and the other sidewall; forming a third dielectric layer in the second trench, filling the second trench and contacting the second dielectric layer, the first dielectric layer, and the semiconductor pillar; removing a portion of the retained second dielectric layer through a patterning process, exposing only the second electrode region and the channel region of the semiconductor pillar; forming a first cavity in the region where the second dielectric layer was removed; and removing the first dielectric layer between two adjacent semiconductor pillars in a second direction, forming a second cavity in the region where the first dielectric layer was removed; each first cavity and each second cavity within the second trench are connected and extend in a second direction; an insulating layer, a ferroelectric layer, and a word line are sequentially formed within the connected first and second cavities, the insulating layer, the ferroelectric layer, and the word line only surrounding the channel region, exposing the second electrode region; the gate electrode is a portion of the word line.

[0058] Specifically, the second trench 319 includes a bottom wall and two opposing sidewalls. The second dielectric layer of one of the sidewalls in each second trench 319 is removed by a micro-sculpting process or an electron beam etching process, exposing the semiconductor pillar 320 and the first dielectric layer 318 between adjacent semiconductor pillars 320 in the second direction. The locations where the second dielectric layer is removed are the same in adjacent second trenches 319.

[0059] It's important to note that the core of the Centura Sculpta process is its ability to perform a novel step called pattern shaping. Unlike photolithography scanners, Centura Sculpta uses a tilted reactive ion beam to precisely sculpt patterned material stacks. Because Centura Sculpta does not use any photomasks, alignment errors are less likely to occur during material removal. The ion beam can be adjusted to etch one side of the pattern while leaving the other side unetched.

[0060] Specifically, such as Figure 13 As shown, after the second dielectric layer 321 is formed, a micro-sculpting process is used to remove the second dielectric layer on one of the two opposing sidewalls covering the second trench 319, while retaining the second dielectric layer on the other sidewall and the bottom wall. Figure 13 The diagonal lines in the diagram indicate the irradiation direction of the ribbon ion beam. Figure 13 The second dielectric layer 321 on the sidewall of the second trench 319 that was not irradiated by the ribbon ion beam was retained, while the second dielectric layer 321 on the sidewall of the second trench 319 that was irradiated by the ribbon ion beam was removed.

[0061] like Figure 5 and Figure 14As shown, after forming the second dielectric layer 321, a micro-sculpting process or an electron beam etching process is used to remove the second dielectric layer 321 from one sidewall of each second trench 319. The removal locations of the second dielectric layer in adjacent second trenches 319 are the same. The cross-sectional structure formed after this step is as follows: Figure 14 As shown, where, Figure 14 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 14 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 14 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 14 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0062] In this embodiment of the application, each of the semiconductor pillars includes two sidewalls opposite to each other in a first direction, and each word line is located in the region corresponding to only one of the two sidewalls.

[0063] In this embodiment of the application, the character lines extend in the second direction and are periodically spaced in the first direction; The distance between the gates corresponding to two adjacent word lines in the first direction is not less than the sum of the thickness of the semiconductor pillar in the first direction and the width of the second trench. The thickness of the semiconductor pillar in the first direction can be measured as the distance between two opposing contours of the semiconductor pillar's cross-section in the first direction. The width of the second trench can be measured as the distance between two sidewall contours in the cross-section of the second trench.

[0064] like Figure 5 and Figure 15 As shown above, Figure 14 The structure shown forms a third dielectric layer 322, which fills the second trench 319 and contacts the second dielectric layer 321, the first dielectric layer 318, and the semiconductor pillar 320. Specifically, after removing the second dielectric layer 321 covering one sidewall of the second trench 319 using a microsculpting or electron beam etching process, a silicon nitride (SiN) film is deposited to fill the second trench 319. Then, CMP processing is performed to make the surface of the SiN film flush with the surface of the semiconductor pillar 320, or to make the surface of the SiN film flush with the surface of the second dielectric layer 321, thus forming the third dielectric layer 322. The cross-sectional structure formed after this step is shown below. Figure 15 As shown, where, Figure 15 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 15 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 15 c corresponds to Figure 5Cross-sectional structure diagram in the CC direction. Figure 15 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0065] In one specific embodiment, an insulating layer, a ferroelectric layer, and word lines are sequentially formed in a first cavity and a second cavity that are connected to each other. This includes: forming an initial gate dielectric layer that covers the sidewalls and bottom wall of the first cavity and the sidewalls and bottom wall of the second cavity, and the initial gate dielectric layer does not completely fill the first cavity and the second cavity; forming an initial word line that fills the first cavity and the second cavity; and removing part of the initial gate dielectric layer and the initial word line by etching back to form a gate dielectric layer and word line located in the channel region of the semiconductor pillar, and exposing the second electrode region.

[0066] Specifically, such as Figure 5 and Figure 16 As shown, after forming the third dielectric layer 322, a wet etching or dry etching process is used to remove a portion of the first dielectric layer 318 in the first trench and a portion of the second dielectric layer 321 in the second trench, so that the first dielectric layer 318 and the second dielectric layer 321 are recessed to a suitable depth, ensuring that the channel region 3202 of the semiconductor pillar 320 is exposed, but preferably not exposing the first electrode region 3201; specifically, a portion of the second dielectric layer 321 on the sidewall of the remaining second trench is removed, exposing the semiconductor pillar 320 but preferably not exposing the first electrode region 3201, forming a first cavity 323, and the first dielectric layer 318 between two adjacent semiconductor pillars 320 in the second direction is removed, forming second cavities 324 and 325. The first cavity and the second cavity are connected, and word lines are subsequently formed in the first cavity and the second cavity; the cross-sectional structure formed after this step is as follows. Figure 16 As shown, where, Figure 16 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 16 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 16 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 16 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0067] like Figure 5 , Figure 17 and Figure 18 As shown, a gate dielectric layer and a gate 326 are then formed, with the upper surfaces of both the gate dielectric layer and the gate 326 flush with the upper surface of the channel region 3202; the cross-sectional structure formed after this step is shown in the figure. Figure 17 As shown, Figure 18 for Figure 17 An enlarged view of the area within the dashed box in section a, where... Figure 17 a corresponds to Figure 5Cross-sectional structural diagram along the AA direction. Figure 17 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 17 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 17 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0068] In a specific implementation, the formation of a gate dielectric layer and a gate 326 includes: sequentially growing an interface oxide layer (e.g., silicon oxide) and a ferroelectric material layer (e.g., HfZrO2) to form an initial gate dielectric layer. The initial gate dielectric layer covers the sidewalls and bottom walls of the first cavity of adjacent semiconductor pillars in each row, and covers the sidewalls and bottom walls of the second cavity between adjacent first cavities. The initial gate dielectric layer does not completely fill the first and second cavities. Next, titanium (Ti) and titanium nitride (TiN) are deposited in the first and second cavities, followed by the deposition of molybdenum (Mo) or tungsten (W) to form an initial gate. The initial gate fills the first and second cavities. Finally, a patterning process (e.g., dry or wet etching) is used to remove part of the initial gate dielectric layer and the initial gate to form a gate dielectric layer and a gate 3263. The gate dielectric layer includes an interface oxide layer 3261 and a ferroelectric material layer 3262. Specifically, the initial gate dielectric layer and the initial gate are etched back to the second electrode region 3203 of the exposed semiconductor pillar 320 using a back-etching method. The positions of the formed gate dielectric layer and gate correspond to the positions of the channel region. The back-etching process disconnects the word lines connected between adjacent rows of semiconductor pillars 320. Each row of semiconductor pillars 320 is connected to only one word line. The conductive materials in the first cavity and the second cavity corresponding to each row of semiconductor pillars 320 can form a word line with an integrated structure.

[0069] It should be noted that ferroelectric materials may include any suitable composition or combination of compositions; and may include one or more materials, composed of one or more materials selected from the group consisting of: transition metal oxides, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconate titanate, tantalum oxide, and barium strontium titanate, and wherein dopants are present, including one or more of silicon, aluminum, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and rare earth elements. Gate materials may include any suitable composition or combination of compositions. For example, gate materials may include metallic elements (e.g., titanium, tungsten, ruthenium, etc.), metal alloys, or other compositions (e.g., metal nitrides, metal carbides, metal silicides, etc.). In some embodiments, gate materials may include one or more of titanium nitride, tungsten, ruthenium, and ruthenium silicide.

[0070] In one specific embodiment, after forming the gate dielectric layer and the gate electrode, the method further includes: planarizing the substrate; wherein, planarizing the substrate includes: forming a fifth dielectric layer, the fifth dielectric layer filling the uneven regions of the substrate, the surface of the fifth dielectric layer being flush with the surface of the semiconductor pillar, or the fifth dielectric layer covering the surface of the semiconductor pillar.

[0071] Specifically, such as Figure 5 and Figure 19 As shown, after forming the gate dielectric layer and gate 326, trenches remain above the gate dielectric layer and gate 326 due to the etching back of the initial gate dielectric layer and gate. At this point, the substrate is not flat. To facilitate subsequent processes, a fifth dielectric layer 327 needs to be formed above the gate dielectric layer and gate 326 to planarize the substrate. Specifically, after forming the gate dielectric layer and gate 326, an oxide layer (e.g., silicon oxide) is formed using SOD (Surface Mount Technology). The oxide layer fills the trenches above the gate dielectric layer and gate 326. Then, the oxide layer is mechanically polished to an appropriate thickness using CMP (Chemical Mechanical Polishing) to form the fifth dielectric layer 327. The surface of the fifth dielectric layer 327 can be flush with the surface of the semiconductor pillar 320, or it can cover the surface of the semiconductor pillar 320. The cross-sectional structure formed after this step is shown in the figure. Figure 19 As shown, where, Figure 19 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 19 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 19 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 19 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0072] In one specific embodiment, if the surface of the fifth dielectric layer is flush with the surface of the semiconductor pillar, and the surface of the second electrode region is doped to form an electrical contact layer, the method includes: doping the surface of the second electrode region with phosphorus or arsenic; forming a silicide conductive layer containing nickel, cobalt, or titanium on the side of the semiconductor pillar away from the substrate using a patterning process, wherein the orthographic projection of the conductive layer on the substrate coincides with the orthographic projection of the semiconductor pillar on the substrate, and the conductive layer serves as the electrical contact layer, and the conductive layer is a silicide conductive layer; if the fifth dielectric layer covers the surface of the semiconductor pillar, and the surface of the second electrode region is doped to form an electrical contact layer, the method includes: removing the fifth dielectric layer on the surface of the semiconductor pillar using a patterning process to expose the surface of the semiconductor pillar; doping the surface of the second electrode region with phosphorus or arsenic; forming a silicide conductive layer containing nickel, cobalt, or titanium on the side of the semiconductor pillar away from the substrate using a patterning process, wherein the orthographic projection of the silicide conductive layer on the substrate coincides with the orthographic projection of the semiconductor pillar on the substrate, and the silicide conductive layer serves as the electrical contact layer.

[0073] like Figure 5 and Figure 20 As shown, after the fifth dielectric layer 327 is formed, in a specific embodiment of this application, taking the fifth dielectric layer 327 covering the surface of the semiconductor pillar 320 as an example, the surface of the second electrode region 3203 is doped to form an electrical contact layer. This includes: removing the fifth dielectric layer 327 from the surface of the semiconductor pillar 320 using a patterning process to expose the surface of the semiconductor pillar 320; doping the exposed surface of the second electrode region 3203 with phosphorus (P) or arsenic (As); forming a silicide conductive layer containing nickel (Ni), cobalt (Co), or titanium (Ti) on the side of the semiconductor pillar 320 away from the substrate using a patterning process; the orthographic projection of the conductive layer on the substrate coincides with the orthographic projection of the semiconductor pillar 320 on the substrate; the conductive layer and the semiconductor pillar 320 form a silicide; and the conductive layer serves as the electrical contact layer 328.

[0074] In one specific embodiment, after forming the electrical contact layer, the method further includes forming a source line on the side of the electrical contact layer away from the substrate, the source line being connected to the electrical contact layer, wherein: forming the source line includes: forming a source line on the side of the electrical contact layer away from the substrate, the source line covering the entire substrate; or, using a patterning process to form a source line on the side of the electrical contact layer away from the substrate, the source line extending along a first direction and spaced apart along a second direction, and the source line contacting the electrical contact layer.

[0075] Specifically, such as Figure 5 and Figure 20 As shown, after forming the electrical contact layer 328, a conductive layer is deposited on the side of the electrical contact layer 328 away from the substrate (i.e., away from the first insulating layer 313). This conductive layer covers the entire substrate to form the source line 329. When the source line 329 covers the entire substrate, it serves as the common source line of the memory array. The cross-sectional structure formed after this step is shown in the figure. Figure 20 As shown, where, Figure 20 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 20 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 20 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 20 d corresponds to Figure 5 A cross-sectional view of the structure in the DD direction. Of course, in some other embodiments, the conductive layer can also be patterned so that the conductive layer is discontinuously distributed, forming multiple source lines 329 extending along the first direction and spaced apart along the second direction.

[0076] In one specific embodiment, after forming the source line as described above, the method further includes: forming a second insulating layer on the side of the source line away from the first substrate, the second insulating layer covering the first substrate; forming an electrical connection structure on the side of the second insulating layer away from the first substrate through a patterning process, the electrical connection structure being located in the peripheral region and connected to the logic circuit; and forming a third insulating layer on the side of the electrical connection structure away from the first substrate, the third insulating layer covering the electrical connection structure and the second insulating layer.

[0077] Specifically, such as Figure 21 As shown, after forming the source line 329, through-silicon via (TSV) technology (i.e., the technology of interconnecting chips by creating vertical conductions between chips and wafers) and metal interconnection processes are used to form the final memory. In specific implementation, a second insulating layer 330 is formed on the side of the source line 329 away from the first substrate 311. The second insulating layer covers the first substrate 311 on which the source line 329 is formed. Then, an electrical connection structure 331 is formed (for example, using TSV process and metal interconnection process). The electrical connection structure 331 is connected to the logic circuit 312. Then, a third insulating layer 332 is formed to cover the electrical connection structure 331. The third insulating layer 332 can play a role in planarization and insulation. Finally, a pad 333 can be formed to receive external electrical signals. Figure 21 The structure within the dashed box has been described in detail above and will not be repeated here.

[0078] In a specific embodiment of this application, a single-gate memory structure with 1T0C is fabricated using the above method. Since this memory structure does not include capacitors, it can effectively simplify the structure of semiconductor devices and reduce the manufacturing difficulty of semiconductor devices. Furthermore, a portion of the channel region surrounding the gate of the semiconductor pillar can increase the distance between adjacent word lines in the periodically distributed word lines, thereby reducing the parasitic capacitance generated between word lines. Additionally, the bit lines are fabricated using a hybrid bonding process, and the fabricated bit lines do not have the problem of poor conductivity.

[0079] In another alternative embodiment, the ferroelectric transistor fabricated according to the embodiments of this application has a double-gate structure. Specifically, see [link to relevant documentation]. Figure 5 , Figures 22 to 35 As shown. Figure 5 A schematic diagram of a portion of the formed memory structure, such as... Figure 5 As shown, the memory fabricated in this embodiment includes a plurality of bit lines BL extending along a first direction and a plurality of word lines WL extending along a second direction, with arrayed semiconductor pillars near the intersection of the bit lines BL and word lines WL.

[0080] In one specific embodiment, forming a plurality of arrayed semiconductor pillars on a substrate in S101 includes: providing a substrate; performing a patterning process on the substrate to form first trenches extending along a first direction and spaced apart along a second direction; forming a first dielectric layer that fills the first trenches and covers the substrate, and doping the substrate to sequentially form a first doped region, a channel region, and a second doped region in a direction away from the substrate; patterning the substrate and the first dielectric layer through a patterning process to form a plurality of second trenches extending along the second direction and arranged along the first direction, the substrate including a plurality of arrayed semiconductor pillars between the first trenches and the second trenches, the semiconductor pillars including a first electrode region located in the first doped region and a second electrode region located in the second doped region; forming a second dielectric layer that covers the sidewalls and bottom wall of the second trenches, and covers the two sidewalls of the semiconductor pillars; removing the portion of the substrate near the first electrode region through a patterning process to form a cavity, and forming a conductive layer in the cavity, the conductive layer serving as bit lines, the bit lines extending along the first direction and spaced apart along the second direction.

[0081] Specifically, such as Figure 5 and Figure 22 As shown, a substrate 411 is provided, and the material of the substrate 411 can be silicon (Si). An oxide layer 412 (e.g., a silicon oxide layer), a hard mask layer 413, a BARC layer 414 (bottom anti-reflection coating), and a photoresist layer 415 are sequentially formed on the substrate 411. The photoresist layer 415 is patterned, and the cross-sectional structure formed after patterning is shown below. Figure 22 As shown, where, Figure 22 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 22 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 22 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 22 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0082] like Figure 5 and Figure 23 As shown, the substrate 411 is then patterned to form first grooves 416 extending along a first direction and spaced apart along a second direction. The cross-sectional structure formed after this step is as follows. Figure 23 As shown, where, Figure 23 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 23 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 23 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 23 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0083] like Figure 5 and Figure 24 As shown, next, an oxide layer is deposited, filling the first trench 416 and covering the substrate 411. The oxide layer is then subjected to CMP mechanical polishing, which smooths the surface and ensures the oxide layer thickness on the silicon substrate is greater than 1 nanometer (nm) to protect the silicon substrate 411. The oxide layer after CMP mechanical polishing forms the first dielectric layer 417. Next, the substrate 411 is doped (e.g., by ion implantation) to sequentially form a drain region 4111, a channel region 4112, and a source region 4113 within a certain depth (perpendicular to the substrate direction) of the substrate 411. Finally, the entire substrate 411 undergoes a spike annealing process. The cross-sectional structure formed after this step is shown below. Figure 24 As shown, where, Figure 24 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 24 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 24 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 24 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0084] like Figure 5 and Figure 25 As shown, the substrate 411 and the first dielectric layer 417 are then patterned using a patterning process to form a plurality of second trenches 418 extending along the second direction and spaced apart along the first direction. Specifically, the patterning method can employ a method similar to... Figure 22 and Figure 23 The same patterning method can also be used, such as SADP or SAQP patterning. After the second trench 418 is formed, the substrate is divided into several arrayed semiconductor pillars 419 by the first trench 416 and the second trench 418. A portion of the substrate drain region 4111 is the first electrode region 4191 of the semiconductor pillar, a portion of the substrate channel region 4112 is the channel region 4192 of the semiconductor pillar, and a portion of the substrate source region 4113 is the second electrode region 4193 of the semiconductor pillar.

[0085] Next, a second dielectric layer 420 is formed. The material of the second dielectric layer 420 can be silicon oxide. The second dielectric layer 420 covers the sidewalls and bottom wall of the second trench 418, but does not completely fill the second trench 418, and also covers the surface of the semiconductor pillar 419. Then, a cavity 421 is formed by a patterning process (e.g., lateral etching). Specifically, a lateral etching process can be used to remove part of the first electrode region 4191 and part of the substrate 411 below the first electrode region 4191 to form the cavity 421. The cross-sectional structure formed after this step is as follows: Figure 25 As shown, where, Figure 25 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 25 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 25 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 25 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0086] like Figure 5 and Figure 26 As shown, a conductive layer is then formed within the receiving cavity 421, serving as a bit line 422. Specifically, forming the conductive layer within the receiving cavity 421 includes: firstly, forming a silicide layer within the receiving cavity 421, covering the cavity wall of the receiving cavity 421; for example, first forming titanium (Ti) silicide, or nickel (Ni) silicide, or cobalt (Co) silicide; then, forming a metal layer that fills the entire receiving cavity 421, for example, filling with tungsten (W) or molybdenum (Mo); the silicide layer and the metal layer form the bit line 422, and the cross-sectional structure after forming the bit line 422 is as shown. Figure 26 As shown, where, Figure 26 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 26 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 26 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 26 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0087] In one specific embodiment, before forming at least partially surrounding the gate dielectric layer and gate electrode on the sidewalls of the semiconductor pillar, the method includes: forming a fourth dielectric layer, the fourth dielectric layer filling a second trench and contacting the second dielectric layer and the first dielectric layer respectively; removing a portion of the second dielectric layer by a patterning process to expose the second electrode region and the channel region of the semiconductor pillar, forming a first cavity exposing two opposing sidewalls of the semiconductor pillar in a first direction; and removing the first dielectric layer between two adjacent semiconductor pillars in a second direction to form a second cavity; the first cavity and the second cavity are connected; and forming at least partially surrounding the gate dielectric layer and gate electrode on the sidewalls of the semiconductor pillar includes: forming an insulating layer, a ferroelectric layer, and a word line successively in the first cavity and the second cavity, wherein the gate electrode is part of the word line.

[0088] like Figure 5 and Figure 27 As shown, the formation of the fourth dielectric layer, which fills the second trench and contacts both the second and first dielectric layers, includes: depositing a silicon nitride (SiN) layer; filling the second trench 418 with the silicon nitride layer; and mechanically polishing the silicon nitride layer using CMP to make its surface smooth and flush with the surface of the second dielectric layer 420. The silicon nitride layer after CMP treatment forms the fourth dielectric layer 423. The cross-sectional structure after this step is shown in the figure. Figure 27 As shown, where, Figure 27 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 27 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 27 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 27 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0089] Specifically, such as Figure 5 and Figure 28 As shown, after forming the fourth dielectric layer 423, the process includes: removing a portion of the second dielectric layer 420 in the second trench and a portion of the first dielectric layer 417 in the first trench using a patterning process. Specifically, the patterning process causes the second dielectric layer 420 and the first dielectric layer 417 to be recessed to a suitable depth. In practice, the upper surface of the second dielectric layer 420 can be flush with the lower surface of the channel region 4192, and the upper surface of the first dielectric layer 417 can be flush with the lower surface of the channel region 4192. Removing a portion of the second dielectric layer 420 forms the first cavity, and removing a portion of the first dielectric layer forms the second cavity. The first cavity and the second cavity are connected. The cross-sectional structure after this step is shown in the figure. Figure 28 As shown, where, Figure 28 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 28 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 28 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 28 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0090] like Figure 5 , Figure 29 , Figure 30 and Figure 31 As shown, Figure 30 for Figure 29 a. Enlarged view of the area within the dashed box. Figure 31 To illustrate the top view after the gate dielectric layer and gate are formed, after the first cavity and the second cavity are formed, an oxide layer with a thickness of 1 nm to 10 nm is first grown, covering the sidewalls and bottom walls of the first cavity and the second cavity. Then, a ferroelectric material layer is grown, covering the sidewalls and bottom walls of the first cavity and the second cavity. The oxide layer and the ferroelectric material layer form the initial gate dielectric layer 4241. The initial gate dielectric layer 4241 does not fill the first cavity and the second cavity. The ferroelectric material layer can be selected, for example, hafnium oxide (HfO) doped with silicon (Si), zirconium (Zr), aluminum (Al), yttrium (Y), lanthanum (La), gadolinium (Gd), strontium (Sr) and other elements. Then, titanium nitride (TiN) is deposited, followed by tungsten (W) or molybdenum (Mo) or other metals to form the initial gate 4242. The initial gate 4242 fills the first cavity and the second cavity and surrounds the semiconductor pillar and the initial gate dielectric layer. The initial gate 4242 surrounding the semiconductor pillar subsequently serves as the gate of the transistor, while the initial gate 4242 at other locations subsequently serves as the word line of the memory.

[0091] Next, a portion of the initial gate dielectric layer 4241 and a portion of the initial gate 4242 are removed using a patterning process (e.g., by etching back), so that the upper surfaces of both the initial gate dielectric layer 4241 and the initial gate 4242 are flush with the upper surface of the channel region 4192, thereby forming the gate dielectric layer and the gate 424. The cross-sectional structure formed after this step is as follows: Figure 29 As shown, where, Figure 29 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 29 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 29 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 29 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0092] In one specific embodiment, after forming the gate dielectric layer and the gate electrode, the method further includes: planarizing the substrate; wherein, planarizing the substrate includes: forming a fifth dielectric layer, the fifth dielectric layer filling the uneven regions of the substrate, the surface of the fifth dielectric layer being flush with the surface of the semiconductor pillar, or the fifth dielectric layer covering the surface of the semiconductor pillar; the specific embodiment of this application is illustrated by taking the surface of the formed fifth dielectric layer being flush with the surface of the semiconductor pillar as an example.

[0093] Specifically, such as Figure 32 As shown, after forming the gate dielectric layer and gate 424, trenches remain above the gate dielectric layer and gate 424 due to the etching back of the initial gate dielectric layer and initial gate. At this point, the substrate is not flat. To facilitate subsequent processes, a fifth dielectric layer 425 needs to be formed above the gate dielectric layer and gate 424 to planarize the substrate. Specifically, after forming the gate dielectric layer and gate 424, an oxide layer (e.g., a silicon oxide layer) is deposited using atomic layer deposition (ALD), and the oxide layer is mechanically polished using CMP to form the fifth dielectric layer 425. The surface of the fifth dielectric layer 425 is flush with the surface of the semiconductor pillar 419. The cross-sectional structure formed after this step is shown in the figure. Figure 32 As shown, where, Figure 32 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 32 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 32 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 32 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0094] In one specific embodiment, after forming the fifth dielectric layer 425, the surface of the second electrode region is doped to form an electrical contact layer, including: doping the surface of the second electrode region with phosphorus or arsenic; and forming a conductive layer containing nickel, cobalt, or titanium on the side of the semiconductor pillar away from the substrate using a patterning process, wherein the orthogonal projection of the conductive layer on the substrate coincides with the orthogonal projection of the semiconductor pillar on the substrate, and the conductive layer serves as the electrical contact layer.

[0095] Specifically, such as Figure 5 and Figure 33As shown, after forming the fifth dielectric layer 425, in this specific embodiment, the surface of the fifth dielectric layer 327 is flush with the surface of the semiconductor pillar 419. The surface of the second electrode region 4193 is doped to form an electrical contact layer, including: doping the surface of the second electrode region 3203 with phosphorus (P) or arsenic (As); forming a silicide conductive layer containing nickel (Ni), cobalt (Co), or titanium (Ti) on the side of the semiconductor pillar 320 away from the substrate using a patterning process, the orthographic projection of the conductive layer on the substrate coincides with the orthographic projection of the semiconductor pillar 419 on the substrate, the conductive layer and the semiconductor pillar 419 form a silicide, and the conductive layer serves as the electrical contact layer 426; the cross-sectional structure formed after this step is as follows. Figure 33 As shown, where, Figure 33 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 33 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 33 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 33 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0096] In one specific embodiment, after forming the electrical contact layer, a source line is formed on the side of the electrical contact layer away from the substrate, including: forming a source line on the side of the electrical contact layer away from the substrate, the source line covering the entire substrate; or, using a patterning process to form a source line on the side of the electrical contact layer away from the substrate, the source line extending along a first direction and spaced apart along a second direction, and the source line contacting the electrical contact layer.

[0097] Specifically, such as Figure 5 , Figure 34 and Figure 35 As shown, after forming the electrical contact layer 426, a conductive layer is deposited on the side of the electrical contact layer 426 away from the substrate 411. This conductive layer covers the entire substrate 411 to form the source line 427. When the source line 427 covers the entire substrate 411, the source line 427 serves as the common source line of the memory array. The corresponding circuit diagram is shown below. Figure 36 As shown; the cross-sectional structure formed after this step is as follows. Figure 34 As shown, where, Figure 34 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 34 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 34 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 34 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0098] Of course, in some other embodiments, after forming the electrical contact layer 426, a conductive layer is deposited on the side of the electrical contact layer 426 away from the substrate 411. The conductive layer is patterned using a patterning process, so that the conductive layer is discontinuously distributed, forming multiple source lines 427 extending along the first direction and spaced apart along the second direction. Then, an oxide layer (e.g., silicon oxide) is deposited to fill the gaps in the substrate 411, and the oxide layer is mechanically polished using CMP to form the sixth dielectric layer 428. The corresponding circuit diagram is shown below. Figure 37 As shown; the cross-sectional structure formed after this step is as follows. Figure 35 As shown, where, Figure 35 a corresponds to Figure 5 Cross-sectional structural diagram along the AA direction. Figure 35 b corresponds to Figure 5 Cross-sectional structural diagram in the BB direction. Figure 35 c corresponds to Figure 5 Cross-sectional structure diagram in the CC direction. Figure 35 d corresponds to Figure 5 Cross-sectional structure diagram in the DD direction.

[0099] In this embodiment, the source line 427 can be made of tungsten (W), molybdenum (Mo), or other metals. After the source line 427 is fabricated, the word line, bit line, and source line are connected to the logic circuit to complete the fabrication of the memory. The memory fabricated using this embodiment only includes one ferroelectric transistor and does not require the fabrication of capacitors, saving a lot of complex processes.

[0100] The circuit diagram of the memory fabricated according to the embodiments of this application is as follows: Figure 36 and Figure 37 As shown, the memory includes several ferroelectric transistors arranged in an array, several bit lines BL, several word lines WL, and several source lines SL. The gates of the ferroelectric transistors are connected to the word lines WL, the first electrode region is connected to the bit lines BL, and the second electrode region is connected to the source lines SL. The source lines can be the common source lines of the entire memory array, such as... Figure 36 As shown, a source line can also be connected to only one column of transistors, such as... Figure 37 As shown.

[0101] The following is combined Figure 36 and Figure 37 The read / write method of the memory formed in the embodiments of this application will be introduced.

[0102] Specifically, in the ferroelectric transistors included in the memory embodiments of this application, the ferroelectric material layer is Hf 0.5 Zr 0.5 Taking O2 as an example, the voltage selection for the word line, bit line, and source line connected to the ferroelectric transistor can be based on the voltages in Table 1 below.

[0103] Table 1

[0104] First, let's introduce the write operation phase, using the selected storage unit in the diagram (i.e., Figure 36 Taking the memory cell at the location of the dashed box as an example. During a write operation, a voltage of, for example, -4V is applied to the gate of the selected WL1, a voltage of 0V is applied to the adjacent unselected WL0 and WL2, a voltage of 0V is applied to the selected BL1, a voltage of 0V is applied to the unselected BL0 and BL2, and a voltage of, for example -2V is applied to all SLs. Under these conditions, the ferroelectric material in the selected memory cell is polarized under the voltage difference.

[0105] During the erasure phase, with Figure 36 Taking the selected memory cell as an example. The gate of the selected WL1 is applied with a voltage of, for example, 4V, the adjacent unselected WL0 and WL2 are applied with a voltage of 0V, the selected BL1 is applied with a voltage of 0V, the unselected BL0 and BL2 are applied with a voltage of, for example, 2V, and all SL are connected to 0V. Under these conditions, the ferroelectric material in the selected memory cell is reverse polarized under the reverse voltage difference.

[0106] During the read phase, the selected WL1 gate is applied with a voltage of, for example, -0.1V, the selected BL1 gate is applied with a voltage of, for example, 0.5V, the unselected adjacent WL0 and WL2 are applied with a voltage of 0V, the unselected BL0 and BL2 are applied with a voltage of 0V, and all SLs are connected to 0V. In this case, if the current between the source and drain is greater than a preset reference value, it is considered to be in a "0" state; if the current between the source and drain is less than the preset reference value, it is considered to be in a "1" state.

[0107] Based on the same inventive concept, embodiments of this application provide a semiconductor device, such as... Figure 5 , Figure 20 , Figure 21 , Figure 34 , Figure 35 , Figure 36 and Figure 37 As shown, the semiconductor device includes: a substrate and several ferroelectric transistors; several ferroelectric transistors (arrangement shown in [reference]). Figure 36 and Figure 37 Located on one side of the substrate, it includes several arrayed semiconductor pillars, a gate dielectric layer, and a gate electrode. The semiconductor pillars ( Figure 20 Semiconductor pillar 320 in Figure 34 and Figure 35 The semiconductor pillar 419 includes a first electrode region sequentially distributed along a direction perpendicular to the substrate. Figure 20 The first electrode region 3201 in Figure 34 and Figure 35 The first electrode region 4191 and the channel region ( Figure 20 3202, in the middle of the ditch area Figure 34 and Figure 35 The channel region 4192) and the second electrode region ( Figure 20 The second electrode region 3203 in Figure 34 and Figure 35 The second electrode region 4193 in the middle), the first electrode region is close to the substrate; the gate dielectric layer and the gate at least partially surround the channel region, the gate dielectric layer includes an insulating layer and a ferroelectric layer.

[0108] The semiconductor device provided in this application embodiment changes the threshold voltage by the polarization state of the FeFET, thereby achieving storage function without the need for a capacitor, effectively simplifying the structure of the semiconductor device.

[0109] In one specific embodiment, the semiconductor device includes: a plurality of bit lines, an electrical contact layer, and a source line; the plurality of bit lines ( Figure 21 The first conductive layer 3141 and the second conductive layer 3142 in Figure 34 and Figure 35 Bit lines 422 extend along a first direction and are spaced apart along a second direction. The bit lines are located below the semiconductor pillars and are connected to the first electrode region; electrical contact layer ( Figure 20 Electrical contact layer 328 in Figure 34 and Figure 35 The electrical contact layer 426 is located on the side of the semiconductor pillar away from the substrate and is connected to the second electrode region. The orthographic projection of the electrical contact layer on the substrate overlaps with the orthographic projection of the semiconductor pillar on the substrate; the source line ( Figure 20 Source line 329 in Figure 34 and Figure 35 The source line 427 is located on the side of the electrical contact layer away from the substrate, and the source line is connected to the electrical contact layer.

[0110] In one specific embodiment, if a gate dielectric layer and a gate are sequentially arranged around a portion of the circumferential region of the channel region of the semiconductor, i.e., the gate surrounds a portion of the channel region surrounding the semiconductor pillar, a logic circuit is also disposed on the substrate; such as Figure 5 , Figure 20 and Figure 21As shown, a logic circuit 312 is also disposed on the substrate; the logic circuit 312 is located in the peripheral region and below the bit line, the bit line 314 (including the first conductive layer 3141 and the second conductive layer 3142 in the figure) is located in the memory cell array region, and a first insulating layer 313 is disposed between the bit line 314 and the logic circuit 312; the memory also includes a second insulating layer 330 and a third insulating layer 332; the second insulating layer 330 is located on the side of the source line 329 away from the bit line 314 and covers the substrate (first substrate 311); the electrical connection structure 331 is located on the side of the second insulating layer 330 away from the bit line 314 and is located in the peripheral region, and is connected to the logic circuit 312; the third insulating layer 332 is located on the side of the electrical connection structure 331 away from the bit line 314 and covers the second insulating layer 330.

[0111] In one specific embodiment, such as Figure 5 , Figure 20 , Figure 21 , Figure 34 , Figure 35 , Figure 36 and Figure 37 As shown, the source line ( Figure 20 Source line 329 and Figure 34 In this case, source line 427 covers the entire substrate. As a common source line, source line 427 can save a photolithography step during fabrication, thus reducing costs; alternatively, the source line (… Figure 35 The source lines (427) extend along a first direction and are spaced apart along a second direction. The orthogonal projection of the source lines on the substrate overlaps with the orthogonal projection of the semiconductor pillars on the substrate. The source lines of this structure can operate a single column of memory cells, which can reduce write interference or erase interference.

[0112] In one specific embodiment, the semiconductor device further includes word lines that extend along a second direction and are spaced apart along a first direction; the gate at the corresponding position of each semiconductor pillar is a part of the word line; The gate portion surrounds the channel region, and the gates at corresponding positions of the semiconductor pillars in the same row are connected to the same word line.

[0113] In one specific embodiment, each semiconductor pillar includes two sidewalls opposite each other in a first direction, and each word line is located in the region corresponding to only one of the two sidewalls. The word lines extend in a second direction and are arranged at periodic intervals in the first direction; the distance between the gates corresponding to two adjacent word lines in the first direction is not less than the sum of a first distance and a second distance, where the first distance is the thickness of the semiconductor pillar in the first direction, and the second distance is the distance between adjacent sidewalls of two adjacent semiconductor pillars in the first direction; thus, the distance between adjacent word lines in the periodically distributed word lines can be increased, thereby reducing the parasitic capacitance generated between word lines.

[0114] Based on the same inventive concept, embodiments of this application provide an electronic device, including a semiconductor device as provided in any of the above embodiments.

[0115] The electronic device includes the aforementioned semiconductor device, and therefore has the same beneficial effects as the aforementioned semiconductor device, which will not be repeated here.

[0116] Specifically, electronic devices include storage devices, smartphones, computers, tablets, artificial intelligence devices, wearable devices, or power banks.

[0117] In summary, by applying the embodiments of this application, at least the following beneficial effects can be achieved: The semiconductor device and its fabrication method provided in this application have the advantage that the threshold voltage can be changed by the polarization state of the FeFET because the gate dielectric layer of the semiconductor device contains a ferroelectric material layer, thus achieving storage function without the need for a capacitor, effectively simplifying the structure and fabrication process of the semiconductor device.

[0118] In addition, in a method for manufacturing a semiconductor device provided in this application embodiment, a portion of the area around the channel region of the gate surrounding the semiconductor pillar is used to increase the distance between adjacent word lines in the periodically distributed word lines, thereby reducing the parasitic capacitance generated between word lines and improving the read and write operation speed of the memory.

[0119] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in the prior art that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0120] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0121] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0122] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A plurality of semiconductor pillars are formed on a substrate in an array, the semiconductor pillars including a first electrode region, a channel region and a second electrode region distributed sequentially along a direction away from the substrate; A gate dielectric layer and a gate electrode, at least partially surrounding the semiconductor pillar, are sequentially formed on the sidewall of the semiconductor pillar, the gate dielectric layer comprising a ferroelectric layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, After forming the gate dielectric layer and the gate, the method further includes: The second electrode region of the semiconductor pillar is doped to form an electrical contact layer; A source line is formed on the side of the electrical contact layer away from the substrate, and the source line is connected to the electrical contact layer.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The formation of a plurality of semiconductor pillars arranged in an array on the substrate includes: A plurality of first trenches extending along a first direction are formed on the substrate, and a first dielectric layer is filled in the first trenches; A plurality of second trenches extending along a second direction are formed on the substrate, the first trenches and the second trenches defining a plurality of semiconductor pillars; a second dielectric layer is deposited in the second trenches; The step of sequentially forming a gate dielectric layer and a gate electrode, at least partially surrounding the semiconductor pillar, on the sidewall of the semiconductor pillar includes: The second dielectric layer covering one sidewall of the second trench is removed, the second dielectric layer on the other sidewall is retained, and a third dielectric layer is formed in the second trench, the third dielectric layer filling the second trench and contacting the second dielectric layer, the first dielectric layer and the semiconductor pillar respectively; A portion of the retained second dielectric layer is removed, exposing only the second electrode region and the channel region of the semiconductor pillar, forming a first cavity in the region where the second dielectric layer is removed; and the first dielectric layer between two adjacent semiconductor pillars in the second direction is removed, forming a second cavity in the region where the first dielectric layer is removed; each of the first cavities and each of the second cavities in the second trench are connected and extend in the second direction; An insulating layer, a ferroelectric layer, and a word line are formed sequentially in the connected first and second cavities. The insulating layer, ferroelectric layer, and word line only surround the channel region, exposing the second electrode region. The gate is a part of the word line.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, Before forming a plurality of arrayed semiconductor pillars on the substrate, the method further includes: A first substrate is provided, and a plurality of bit lines extending along a first direction are formed on the first substrate; A second substrate is provided, and an epitaxial layer is fabricated on the second substrate. The epitaxial layer includes a first doped region, a channel region, and a second doped region in sequence along a direction perpendicular to the second substrate. The first substrate on which the bit line is formed is bonded to the second substrate on which the epitaxial layer is formed, such that the bit line is in contact with the epitaxial layer; The second substrate is thinned to expose the epitaxial layer, and the substrate comprises the bonded first substrate and the epitaxial layer.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The process includes forming a plurality of first trenches extending along a first direction on the substrate, filling the first trenches with a first dielectric layer, forming a plurality of second trenches extending along a second direction on the substrate, the first trenches and the second trenches defining a plurality of semiconductor pillars, and depositing a second dielectric layer in the second trenches, comprising: The epitaxial layer is patterned using a patterning process to form the first trench extending in the first direction, and the first trench exposes the bit line; A first dielectric layer is formed, which fills the first trench and covers the exposed bit line; The epitaxial layer and the first dielectric layer are patterned by a patterning process to form the second trench. The epitaxial layer includes a plurality of semiconductor pillars arranged in an array between the first trench and the second trench. The semiconductor pillars include a first electrode region located in the first doped region and a second electrode region located in the second doped region. A second dielectric layer is formed, which covers the sidewalls and bottom wall of the second trench, as well as the two sidewalls of the semiconductor pillar facing each other in the first direction.

6. The method for fabricating a semiconductor device according to claim 3, characterized in that, The process of sequentially forming an insulating layer, a ferroelectric layer, and word lines within the interconnected first and second cavities includes: An initial gate dielectric layer is formed, which covers the sidewalls and bottom wall of the first cavity and the sidewalls and bottom wall of the second cavity, and the initial gate dielectric layer does not completely fill the first cavity and the second cavity; An initial word line is formed, which fills the first cavity and the second cavity; By removing part of the initial gate dielectric layer and the initial word line through an etch-back process, the gate dielectric layer and the word line are formed in the channel region of the semiconductor pillar, exposing the second electrode region.

7. The method for fabricating a semiconductor device according to claim 1 or 2, characterized in that, The formation of a plurality of semiconductor pillars arranged in an array on the substrate includes: A substrate is provided, and a patterning process is performed on the substrate to form first trenches that extend along a first direction and are spaced apart along a second direction. A first dielectric layer is formed, which fills the first trench and covers the substrate, and the substrate is doped to sequentially form a first doped region, a channel region, and a second doped region in a direction away from the substrate. The substrate and the first dielectric layer are patterned by a patterning process to form a plurality of second trenches extending along a second direction and arranged along a first direction. The substrate includes a plurality of semiconductor pillars arranged in an array between the first trenches and the second trenches. The semiconductor pillars include a first electrode region located in the first doped region and a second electrode region located in the second doped region. A second dielectric layer is formed, which covers the sidewalls and bottom wall of the second trench, as well as the two sidewalls of the semiconductor pillar; The portion of the substrate near the first electrode region is removed by a patterning process to form a cavity, and bit lines are formed within the cavity. The bit lines extend along a first direction and are spaced apart along a second direction.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, Before the formation of a gate dielectric layer and a gate electrode that at least partially surround the semiconductor pillar in sequence on the sidewall of the semiconductor pillar, the process includes: A fourth dielectric layer is formed, which fills the second trench and contacts both the second dielectric layer and the first dielectric layer. By removing part of the second dielectric layer through a patterning process, the second electrode region and channel region of the semiconductor pillar are exposed, forming a first cavity with two sidewalls facing each other in the first direction exposed, and removing the first dielectric layer between two adjacent semiconductor pillars in the second direction to form a second cavity; the first cavity and the second cavity are connected. A gate dielectric layer and a gate electrode, at least partially surrounding the semiconductor pillar, are sequentially formed on the sidewall of the semiconductor pillar, including: An insulating layer, a ferroelectric layer, and a word line are formed successively in the first cavity and the second cavity, and the gate is a part of the word line.

9. The method for fabricating a semiconductor device according to claim 2, characterized in that, The step of doping the second electrode region of the semiconductor pillar to form an electrical contact layer includes: The surface of the second electrode region is doped with phosphorus or arsenic. A conductive layer comprising nickel, cobalt, or titanium is formed on the side of the semiconductor pillar away from the substrate using a patterning process. The orthographic projection of the conductive layer onto the substrate coincides with the orthographic projection of the semiconductor pillar onto the substrate, and the conductive layer serves as the electrical contact layer.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The formation of a source line on the side of the electrical contact layer away from the substrate includes: A source line is formed on the side of the electrical contact layer away from the substrate, and the source line covers the entire substrate; Alternatively, a patterning process can be used to form source lines on the side of the electrical contact layer away from the substrate. The source lines extend along a first direction and are spaced apart along a second direction, and the source lines are in contact with the electrical contact layer.

11. A semiconductor device, characterized in that, include: Substrate; A plurality of ferroelectric transistors are located on one side of the substrate and include a plurality of semiconductor pillars arranged in an array, a gate dielectric layer and a gate, wherein the semiconductor pillars include a first electrode region, a channel region and a second electrode region distributed sequentially in a direction away from the substrate; The gate dielectric layer and the gate electrode at least partially surround the channel region, and the gate dielectric layer includes a ferroelectric layer.

12. The semiconductor device according to claim 11, characterized in that, include: A plurality of bit lines, the bit lines extending along a first direction and spaced apart along a second direction, the bit lines being located below the semiconductor pillar and connected to the first electrode region; An electrical contact layer is located on the side of the semiconductor pillar away from the substrate and is connected to the second electrode region. The orthographic projection of the electrical contact layer on the substrate overlaps with the orthographic projection of the semiconductor pillar on the substrate. The source line is located on the side of the electrical contact layer away from the substrate, and the source line is connected to the electrical contact layer.

13. The semiconductor device according to claim 12, characterized in that, The substrate is also provided with logic circuits; The logic circuit is located below the bit line, and the bit line is connected to the first electrode region by bonding.

14. The semiconductor device according to claim 12, characterized in that, The source lines cover the entire substrate; or, the source lines extend along a first direction and are spaced apart along a second direction, and the orthogonal projection of the source lines on the substrate overlaps with the orthogonal projection of the semiconductor pillars on the substrate.

15. The semiconductor device according to claim 11, characterized in that, It also includes word lines; The character lines extend along the second direction and are spaced apart along the first direction; The gate at the corresponding position of each of the semiconductor pillars is part of the word line; The gate portion surrounds the channel region, and the gates at corresponding positions of the semiconductor pillars in the same row are connected to the same word line.

16. The semiconductor device according to claim 15, characterized in that, Each of the semiconductor pillars includes two sidewalls opposite each other in a first direction, and each word line is located in the region corresponding to only one of the two sidewalls.

17. The semiconductor device according to claim 16, characterized in that, The character lines extend in the second direction and are periodically spaced in the first direction; The distance between the gates corresponding to two adjacent word lines in the first direction is not less than the sum of the first distance and the second distance. The first distance is the thickness of the semiconductor pillar in the first direction, and the second distance is the distance between the adjacent sidewalls of two adjacent semiconductor pillars in the first direction.

18. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 11 to 17.

Images