Storage device and manufacturing method thereof, memory and electronic equipment

Abstract

The invention provides a storage device and a manufacturing method thereof, a memory and electronic equipment, relates to the technical field of semiconductors, and can shorten the transmission distance of signals. The storage device comprises a storage array chip and a logic chip which are bonded. The logic chip comprises a first transistor and a first metal wire which are arranged on the front side of the first substrate, and a power supply network arranged on the back side of the first substrate. The first metal wire is located on the side, away from the first substrate, of the first transistor. The first metal wire comprises a plurality of wire layers, and the plurality of wire layers comprise a first wire layer closest to the first substrate. The power supply network is connected with the first wiring layer through the first silicon through hole and is connected to the front surface of the first transistor through the first wiring layer; or, the power supply network is connected to the back surface of the first transistor through the first silicon through hole, and the power supply signal does not need to enter a high wiring layer in the metal wiring and enters the transistor through a plurality of wiring layers from top to bottom, so that the transmission distance of the power supply signal is shortened.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a storage device and its manufacturing method, a memory, and an electronic device. Background Technology

[0002] The rapid development of technologies such as cloud computing, metaverse, autonomous driving, and artificial intelligence has not only spurred massive data processing demands but also led to a continuous increase in the demand for high-performance memory products. In particular, high-capacity, high-bandwidth memory has become an essential component of almost all types of processors. However, traditional dynamic random access memory (DRAM) faces the challenge of miniaturization, with the continuous reduction in device size resulting in performance losses. Therefore, the industry is gradually shifting its focus to three-dimensional (3D) storage.

[0003] refer to Figure 1 As shown, the prior art provides a 3D-DRAM (dynamic random access memory) in which the peripheral logic circuit is fabricated in a logic die 1 and the memory array is fabricated in a memory die 2. The two chips are then bonded face to face, thereby achieving the purpose of increasing the storage capacity per unit area (i.e., storage density).

[0004] However, the above method results in excessively long signal traces (e.g.) Figure 1 The problem is that the signal travels from the package substrate (as indicated by the dashed arrow in the image). Figure 1 After being fed into the logic chip 1 (not shown), the signal first enters the higher metal trace layer through a through-silicon via (TSV), then is transmitted from top to bottom through a metal network to the lower device layer. After processing and conversion, it is transmitted from low to high through the metal network to the bonding interface 3. Subsequently, it is transmitted from high to low (i.e., from the side away from the substrate to the side closer to the substrate) through the metal network of the memory array chip 2 to the memory array located in the lower layer of the memory array chip 2. After read / write operations, the required data or signal is returned to the packaging substrate along the original path. This results in an excessively long signal transmission distance, which affects the data read / write rate and accuracy. Summary of the Invention

[0005] This application provides a storage device and its manufacturing method, a memory, and an electronic device that can shorten the signal transmission distance.

[0006] This application provides a storage device including a storage array chip and a logic chip, with the front sides of the storage array chip and the logic chip connected via a bonding interface. The logic chip includes: a first substrate, a first transistor and a first metal trace disposed on the front side of the first substrate, and a power supply network disposed on the back side of the first substrate. The first transistor forms a first logic circuit. A plurality of first through-silicon vias (TSVs) are disposed in the first substrate. The first metal trace is located on the side of the first transistor away from the first substrate, and the first transistor is electrically connected to the storage array chip via the first metal trace. The first metal trace includes multiple trace layers, with one trace layer being the first trace layer closest to the first substrate. The power supply network is connected to the first trace layer via the first TSVs and to the front side of the first transistor via the first trace layer.

[0007] In this scenario, the external power supply can be transmitted to the power supply network via an external interface. The power supply network then transmits the power signal through the first through-silicon via to the bottom layer (i.e., the first trace layer) of the first metal trace, and then through the first trace layer to the first transistor (device layer). In this way, the power signal does not need to enter the upper trace layers of the metal trace and pass through multiple trace layers from top to bottom to enter the transistor, thereby shortening the transmission distance of the power signal and improving the data read / write speed and accuracy.

[0008] As another possible implementation, the aforementioned power supply network can be directly connected to the back side of the first transistor via a first through-silicon via (TSV). In this way, external power can be transmitted to the power supply network via an external interface. The power supply network then transmits the power signal directly to the first transistor through the TSV. The power signal does not need to pass through multiple layers of traces from top to bottom in the metal traces to reach the transistor, thus shortening the transmission distance and improving data read / write speed and accuracy.

[0009] In some possible implementations, a plurality of second through-silicon vias (TSVs) are also provided in the first substrate. A signal network is also provided on the back side of the first substrate. The signal network is connected to the first wiring layer through the second TSVs and to the front side of the first transistor through the first wiring layer. In this way, an external data signal source can be transmitted to the signal network through an external interface, and then the data signal is directly input into the first wiring layer through the second TSVs, and then input into the first transistor (device layer) for processing and conversion. In this case, the data or command signal does not need to enter the higher wiring layers in the metal wiring and pass through multiple wiring layers from top to bottom to enter the transistor, thereby shortening the transmission distance of the data or command signal and thus improving the data read / write speed and accuracy.

[0010] In some possible implementations, a plurality of second through-silicon vias (TSVs) are also provided in the first substrate. A signal network is also provided on the back side of the first substrate. The signal network is connected to the back side of the first transistor through the second TSVs. In this way, an external data signal source can be transmitted to the signal network through an external interface, and then the data signal can be directly input to the first transistor (device layer) for processing and conversion through the second TSVs. In this case, the data or command signal does not need to pass through multiple layers of the metal traces from top to bottom to enter the transistor, thereby shortening the transmission distance of the data or command signal and thus improving the data read / write speed and accuracy.

[0011] In some possible implementations, the first logic circuit includes at least one of a peripheral circuit, an interface circuit, a power supply unit, or a computing unit. Thus, the peripheral circuit enables functions such as address decoding, data driving, data amplification, and data gating of the memory array; the interface circuit enables connection to external devices; the power supply unit provides power; and the computing unit enables functions such as in-memory computation.

[0012] In some possible implementations, the memory array chip includes a second substrate, a memory array disposed on the front side of the second substrate, and a second metal trace. The second metal trace is located on the side of the memory array away from the second substrate and is electrically connected to the memory array. The second metal trace is bonded to a first metal trace at a bonding interface. Data storage and retrieval are achieved through the memory array in the memory array chip.

[0013] In some possible implementations, the memory array chip also includes a second transistor disposed on the front side of the second substrate. The second transistor is connected to a second metal trace to form a second logic circuit connecting different memory arrays. This shortens the signal transmission distance between memory arrays, improving data read / write speeds and accuracy. Furthermore, it reduces the density of bonding pads at the bonding interface between the memory array chip and the logic chip, thereby simplifying the fabrication process.

[0014] In some possible implementations, the second logic circuitry includes at least one of a sensitive amplifier circuit or a word line driver circuit. In this way, data processing and conversion between memory arrays can be achieved within the memory chip via the second logic circuitry.

[0015] This application also provides a method for fabricating a memory device, which may include: fabricating a first transistor on the front side of a first wafer, and then fabricating a first metal trace connected to the first transistor; wherein the first transistor is used to form a first logic circuit. A plurality of first through-silicon vias (TSVs) are fabricated on the back side of the first wafer; wherein the bottom of the first TSVs is connected to the back side of the first transistor; or, the bottom of the first TSVs is connected to the front side of the first transistor through a first wiring layer, the first wiring layer being the wiring layer closest to the first wafer among the first metal traces. A power supply network is fabricated on the back side of the first wafer, and the power supply network is connected to the first TSVs. A memory array chip is provided. The front side of the memory array chip is bonded to the side of the first wafer with the first metal traces.

[0016] Using the above fabrication method, a power supply network is fabricated on the back side of the first wafer, and the power supply network is connected to the first wiring layer through the first through-silicon via (TSV), and then connected to the front side of the first transistor through the first wiring layer. Alternatively, the power supply network can be directly connected to the back side of the first transistor through the first TSV. In this way, external power can be transmitted to the power supply network through an external interface, and the power supply network transmits the signal through the first TSV to the bottom wiring layer (i.e., the first wiring layer) in the first metal wiring, and then through the first wiring layer to the first transistor (device layer). Alternatively, the power supply network can directly transmit the power signal to the first transistor through the first TSV. The power signal does not need to enter the upper wiring layers in the metal wiring and pass through multiple wiring layers from top to bottom to enter the transistor, thereby shortening the transmission distance of the power signal and improving the data read / write speed and accuracy.

[0017] In some possible implementations, the aforementioned memory array chip may include: first fabricating the memory array on the front side of a second wafer, and then fabricating a second metal trace layer connected to the memory array. The memory array fabricated in the memory array chip enables the storage and retrieval of data.

[0018] In some possible implementations, the aforementioned memory array chip may further include: fabricating a second transistor on the front side of a second wafer; wherein the second transistor is connected to a second metal trace layer to form a second logic circuit connecting different memory arrays. This approach, on the one hand, shortens the signal transmission distance between memory arrays, which is beneficial for improving data read / write speeds and accuracy; on the other hand, it reduces the density of bonding pads at the bonding interface between the memory array chip and the logic chip, thereby reducing the difficulty of the fabrication process.

[0019] This application also provides a memory that includes a storage device and a controller as provided in any of the aforementioned possible implementations, wherein the controller is electrically connected to the storage device.

[0020] This application also provides an electronic device, including a memory and a circuit board provided in any of the foregoing possible implementations, wherein the memory and the circuit board are electrically connected. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a DRAM provided in the prior art;

[0022] Figure 2 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application;

[0023] Figure 3 A circuit diagram of a logic chip provided in an embodiment of this application;

[0024] Figure 4 This is a partial structural diagram of a logic chip provided in an embodiment of this application;

[0025] Figure 5 A memory framework diagram of a memory array chip provided in this application embodiment;

[0026] Figure 6 A schematic diagram of a storage array provided in an embodiment of this application;

[0027] Figure 7 This is a schematic diagram of the structure of a storage array chip provided in an embodiment of this application;

[0028] Figure 8 A schematic diagram illustrating the distribution of bonding pads in a logic chip, provided as an embodiment of this application;

[0029] Figure 9 This is a schematic diagram of the structure of a storage array chip provided in an embodiment of this application;

[0030] Figure 10 A flowchart illustrating a method for manufacturing a storage device according to an embodiment of this application;

[0031] Figure 11 This application provides a schematic diagram of the structure of a logic chip during its fabrication process.

[0032] Figure 12 This application provides a schematic diagram of the structure of a logic chip during its fabrication process.

[0033] Figure 13 This application provides a schematic diagram of the structure of a logic chip during its fabrication process.

[0034] Figure 14 This is a schematic diagram of the structure of a memory array chip during the manufacturing process, provided in an embodiment of this application.

[0035] Figure 15 This is a schematic diagram of the structure of a memory array chip during the manufacturing process, as provided in an embodiment of this application. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0037] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or order. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can indicate three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item)" refers to one or more, and "more" refers to two or more. "Installation," "connection," "linking," etc., should be interpreted broadly, for example, it can be an electrical connection or a mechanical connection; it can be a fixed connection or a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium, or a connection within two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, including a series of steps or units. Methods, systems, products, or equipment are not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or equipment. Terms such as “up,” “down,” “left,” and “right” are used only with respect to the orientation of components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification and may vary accordingly depending on the orientation of the components in the drawings.

[0038] This application provides an electronic device that employs a novel storage device. This storage device uses a rear-side power supply method, where the power signal is directly input to the lower layer via a through-silicon via (TSV) through a rear-side power supply network. The signal is then input to the device layer for processing and conversion via the lower layer. Alternatively, the power signal can be directly input to the device layer via a TSV through a rear-side power supply network for processing and conversion. This eliminates the need for the signal to first pass through a higher layer via a TSV and then travel through multiple layers from top to bottom to reach the device layer, thus shortening the transmission distance of the power signal.

[0039] This application does not limit the form of the aforementioned electronic device. The electronic device can be any electronic product equipped with a storage device, such as consumer electronics, home electronics, automotive electronics, financial terminal products, communication electronic products, etc.

[0040] As illustrated, the aforementioned consumer electronics products can include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products can include smart door locks, televisions, smart speakers, refrigerators, robot vacuum cleaners, etc. In-vehicle electronics products can include in-vehicle navigation systems, in-vehicle displays, etc. Financial terminal products can include automated teller machines (ATMs), self-service electronic devices, etc. Communication electronics products can include servers, radar, base stations, and other communication equipment.

[0041] This application does not limit the configuration of the above-mentioned storage device, and the storage device can be applied to any product with storage function.

[0042] For example, in some possible implementations, the above-mentioned storage device can be applied to independent storage devices, such as dynamic random access memory (DRAM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM or ReRAM), magnetic random access memory (MRAM), phase change memory (PCM), etc.

[0043] For example, in some possible implementations, the aforementioned storage device can be applied to embedded storage devices, such as central processing units (CPUs) and micro-controller units (MCUs).

[0044] In addition, the storage device provided in the embodiments of this application can be a single storage chip or a system on chip (SOC), and this application does not limit it in this regard.

[0045] Depending on actual needs, the above-mentioned electronic devices may also include other devices electrically connected to the storage device, such as printed circuit boards (PCBs), input / output devices, etc. This application does not impose any restrictions on this.

[0046] The following embodiments in this application are all described using the application of a storage device in dynamic random access memory (DRAM) as an example. Of course, as a memory, it may also include other devices electrically connected to the storage device (or storage module), such as a controller.

[0047] Figure 2 This is a schematic diagram of a DRAM structure provided in an embodiment of this application.

[0048] For illustrative purposes only, please refer to the following: Figure 2As shown, this application embodiment provides a DRAM, which includes a logic die 1 and a memory die 2. The front sides of the logic die 1 and the memory die 2 are connected through a bonding interface 3, that is, the logic die 1 and the memory die 2 are bonded face to face, thereby ensuring that the logic die 1 and the memory die 2 can achieve signal interconnection and communication through the bonding interface 3.

[0049] This application does not impose any restrictions on the bonding method between logic chip 1 and memory array chip 2; in practice, the method can be selected and set as needed.

[0050] As illustrated, in some possible implementations, logic chip 1 and memory array chip 2 are bonded using a hybrid bonding method.

[0051] It should be understood that the front side of a chip refers to the side on which the device is located. For example, the front side of logic chip 1 refers to the side on which the logic circuit is formed by transistors, and the front side of memory array chip 2 refers to the side on which the memory array is located.

[0052] The DRAM provided in the embodiments of this application will be further described below with reference to logic chip 1.

[0053] For illustrative purposes only, please refer to the following: Figure 2 As shown, in the DRAM provided in this embodiment, the logic chip 1 includes a substrate 10 (also referred to as a first substrate) and a transistor T1 (also referred to as a first transistor) disposed on the front side of the substrate 10, i.e., a device layer. A metal trace 11 (also referred to as a first metal trace) connected to the transistor T1 is provided on the device layer. The transistor T1 is fabricated using a front end of line (FEOL) process and is used to form the first logic circuit; the metal trace 11 is fabricated using a back end of line (BEOL) process. Of course, in addition to satisfying the interconnection between the transistors T1 in the logic chip 1, the metal trace 11 also needs to achieve interconnection with the memory array chip 2 through the bonding interface 3.

[0054] As illustrated, in some possible implementations, the aforementioned transistor T1 can be a CMOS (complementary metal-oxide-semiconductor) transistor, and multiple CMOS transistors (T1) are connected by metal traces 11 to form a CMOS logic circuit. The following embodiments are all illustrated using this example.

[0055] This application does not limit the configuration of transistor T1; it can be configured as needed in practice. Indicatively, transistor T1 can be a planar transistor, a fin field-effect transistor (FinFET), a gate all-around field-effect transistor (GAA), a complementary field-effect transistor (CFET), etc.

[0056] The CMOS logic circuit (i.e., the first logic circuit) formed by the transistor T1 described above may include one or more functional circuits, and this application does not impose any restrictions on this.

[0057] For illustrative purposes only, please refer to the following: Figure 3 As shown, in some possible implementations, the CMOS logic circuit in logic chip 1 may include peripheral circuits to implement functions such as address decoding, data driving, data amplification, and data gating of the memory array; it may also include interface circuits such as input / output (I / O) units and memory controllers connected to the outside; it may also include power supply units such as charge pumps and LDOs; and it may also include circuit modules such as processing units that implement in-memory computing functions.

[0058] Of course, in some other possible implementations, the CMOS logic circuit in logic chip 1 may only include a portion of the aforementioned peripheral circuits, interface circuits, power supply units, or computing units.

[0059] Based on this, continue to refer to Figure 2As shown, the logic chip 1 also includes a power supply network 12 located on the back side of the substrate 10, which can also be called a backside power delivery network (BSPDN), and a through silicon via (TSV1) (also called a first through silicon via) connected to the power supply network 12 is provided in the substrate 10.

[0060] In addition, the metal trace 11 includes multiple trace layers, among which the first trace layer M0 is closest to the substrate 10. That is, the first trace layer M0 is the trace layer closest to the CMOS transistor in the metal trace 11. The power supply network 12 is connected to the first trace layer M0 through the through silicon via TSV1.

[0061] In this way, the external power supply can be transmitted to the power supply network 12 through the external interface, and then directly input to the first trace layer M0 through the through silicon via TSV1, and input to the transistor T1 (device layer) through the first trace layer M0 for processing and conversion.

[0062] Compared to existing technologies where signals first enter the trace layer through silicon vias and then travel through multiple trace layers from top to bottom to the transistor (device layer), resulting in excessively long signal transmission distances (see reference...), this presents a significant improvement in signal transmission efficiency. Figure 1 In the DRAM provided in this application embodiment, the logic chip 1 adopts a back-side power supply method. The signal is transmitted through the power supply network 12 via the through-silicon via (TSV1) to the bottom trace layer (i.e., the first trace layer M0) in the metal trace 11, and then transmitted to the transistor T1 (device layer) through the first trace layer M0. The signal does not need to enter the upper trace layer in the metal trace 11 and enters the transistor from top to bottom through multiple trace layers, thereby shortening the signal transmission distance and improving the data read / write speed and accuracy.

[0063] For the connection between the first routing layer M0 and the CMOS transistor (T1): (Refer to...) Figure 4 As shown, the CMOS transistor (T1) located on the front side of the substrate 10 includes a source S (i.e., the source terminal), a drain D (i.e., the drain terminal), and a gate G. The first wiring layer M0 is the wiring layer closest to the CMOS transistor in the metal wiring 11 and is located above the CMOS transistor (T1). The first wiring layer M0 can be connected to the front side of the source S or drain D of the CMOS transistor (T1) through a via V0. The via V0 can also be called a contact hole.

[0064] Compared to the above-mentioned method of shortening the power signal transmission distance by connecting the first trace layer M0 to the front side of transistor T1, this application embodiment also provides another technical solution to shorten the signal transmission distance. In some possible implementations, transistor T1 can be a vertical transistor, and the source (or drain) of the vertical transistor is embedded in the substrate. The through-silicon via TSV1 penetrates the substrate and connects to the back side of the source (or drain) of the vertical transistor. In this way, the power supply network 12 transmits the power signal directly to the transistor through the through-silicon via TSV1. The power supply does not need to enter the high-level trace layer in the metal trace 11 and pass through multiple trace layers from top to bottom to enter the transistor, thereby shortening the power signal transmission distance and improving the data read / write speed and accuracy.

[0065] To enhance power transmission performance, in some possible implementations, the power supply network 12 can be configured to use metal wires with wider and thicker traces.

[0066] As illustrated, in some possible implementations, the width and thickness of the metal traces in the power supply network 12 are both greater than the width and thickness of the metal traces in the metal traces 11.

[0067] In addition to inputting a power signal to transistor T1, logic chip 1 also requires input of other signals, such as data or command signals. To shorten the transmission distance of these data or command signals, refer to... Figure 2 As shown, in some possible implementations, the logic chip 1 may also include a signal network 13 located on the back side of the substrate 10, and the substrate 10 is provided with a through-silicon via (TSV2) (also referred to as a second TSV). The signal network 13 is connected to the first wiring layer M0 through the TSV2, and is connected to the front side of the source or drain of the transistor T1 through the first wiring layer M0 (see reference). Figure 4 (Connection method of TSV1 in the middle). In this way, the external data signal source can be transmitted to the signal network 13 through the external interface, and then the data or command signal is directly input into the first trace layer M0 through the through silicon via TSV2. The data or command signal is then input to the transistor T1 (device layer) through the first trace layer M0 for processing and conversion. In this case, the data signal does not need to enter the higher trace layers in the metal trace 11 and enter the transistor from top to bottom through multiple trace layers, thereby shortening the transmission distance of the data or command signal and thus improving the data read and write speed and accuracy.

[0068] Of course, as another possible implementation, the signal network 13 can also be directly connected to the back of the source or drain of the transistor T1 through the through-silicon via (TSV2). In this way, the signal network 13 can directly transmit the data signal to the transistor through the TSV2. The data signal does not need to enter the upper layer of the metal trace 11 and pass through multiple trace layers from top to bottom to enter the transistor, thereby shortening the transmission distance of the data or command signal and thus improving the data read / write speed and accuracy.

[0069] It should be understood that, in this application, all other wiring layers in the metal trace 11, except for the first wiring layer M0, can be used to transmit other data or command signals, thereby reducing wiring density and reducing process difficulty.

[0070] It should be noted that the power supply network 12 and the signal network 13 can be one or more layers of metal wiring. The power supply network 12 and the signal network 13 can be distributed on the same layer or on different layers. This application does not impose any restrictions on this.

[0071] Furthermore, this application does not impose any restrictions on the configuration of the external interface on the back of the logic chip 1.

[0072] For example, such as Figure 2 As shown, in some possible implementations, the DRAM can be in flip chip packaging, in which case the external interface on the back of logic chip 1 can be a ball grid array (BGA).

[0073] For example, in some possible implementations, the DRAM can be packaged using wire bonding, in which case the external interface on the back of logic chip 1 can be a bonding pad.

[0074] The following is a brief description of the configuration of the storage array chip 2 in the DRAM provided in the embodiments of this application.

[0075] For illustrative purposes only, please refer to the following: Figure 5 As shown, the storage array chip 2 contains multiple banks 201, and each bank 201 includes multiple storage arrays 202. (Reference) Figure 6As shown, the storage array 202 includes multiple storage cells a arranged in an array. Storage cell a can be a 1T1C structure formed by a selection transistor T and a storage capacitor C, but is not limited to this. Of course, the storage array 202 also includes signal lines such as word line WL and bit line BL connected to each storage cell a. By receiving control levels from one or more control circuits on the word line WL and bit line BL, the storage cell a to be read or written is selected and located, thereby changing the amount of stored charge in the storage capacitor C, thus realizing data read and write operations.

[0076] refer to Figure 7 As shown, in the memory array chip 2, the gate transistor T in memory cell a is disposed on the front side of the substrate 20 (also referred to as the second substrate), the memory capacitor C is disposed on the side of the gate transistor T away from the substrate 20, and the metal trace 21 (also referred to as the second metal trace) is disposed on the side of the memory capacitor C away from the substrate 20, that is, the metal trace 21 is located on the side of the memory array 202 away from the substrate 20. The metal trace 21 can have multiple trace layers. The metal trace 21 in the memory array chip 2 is bonded to the metal trace 21 in the logic chip 1 at the bonding interface 3 (see reference). Figure 2 ).

[0077] For illustrative purposes only, please refer to the following: Figure 8 As shown, logic chip 1 has a bonding pad P1 (also called the first bonding pad) at bonding interface 3, which is connected to the metal trace 11; similarly, memory array chip 2 has a bonding pad P2 (also called the second bonding pad) at bonding interface 3, which is connected to the metal trace 21. The bonding pad P1 in logic chip 1 and the bonding pad P2 in memory array chip 2 are bonded together at bonding interface 3, thus ensuring signal interconnection and communication between logic chip 1 and memory array chip 2. The bonding pads (P1, P2) can also be called bonding pads or bonding contacts.

[0078] It should be understood that the bonding pads (P1, P2) set at the bonding interface 3 of the logic chip 1 and the memory array chip 2 can be evenly arranged at equal intervals or staggered at unequal intervals. This application does not impose any restrictions on this, as long as the interconnection and communication between the logic chip 1 and the memory array chip 2 can be guaranteed.

[0079] Furthermore, it should be understood that, based on actual functional requirements, the peripheral circuits used in DRAM can be divided into large peripheral circuits and small peripheral circuits. Large peripheral circuits may include functional modules such as command conversion units, data buffer units, word line decoders, and bit line decoders. Small peripheral circuits may include functional modules such as sense amplifiers and word line drive circuits, and multiple functional modules are connected between the memory array 202.

[0080] In some possible implementations, the entire peripheral circuitry (including large and small peripheral circuitry) can be integrated into logic chip 1.

[0081] In some possible implementations, one or more functional modules of the small peripheral circuitry, such as the sensor amplifier, word line driver, word line decoder, or bit line decoder, can be integrated into the memory array chip 2, while other parts are integrated into the logic chip 1.

[0082] Taking the integration of small peripheral circuits in memory array chip 2 as an example, refer to Figure 9 As shown, in some possible implementations, in the memory array chip 2, a transistor T2 (also referred to as a second transistor) can be disposed on the front side of the substrate 20, and the transistor T2 is connected to the metal trace 21 to form a logic circuit connected between the memory arrays 202. The logic circuit may include one or more functional modules from the aforementioned small peripheral circuit.

[0083] As illustrated, the aforementioned transistor T2 may be a CMOS transistor, which, together with the connecting metal trace 21, forms one or more functional modules, such as a sense amplifier, a word line driver circuit, a word line decoder, or a bit line decoder.

[0084] Compared to integrating small peripheral circuits into logic chip 1, integrating them into memory array chip 2 allows some data signals between memory arrays to be directly processed and converted within memory array chip 2, eliminating the need for processing and conversion through logic chip 1. This shortens the signal transmission distance between memory arrays, improving data read / write speeds and accuracy. Furthermore, it reduces the density of bonding pads at the bonding interface 3 between memory array chip 2 and logic chip 1, thus simplifying the manufacturing process.

[0085] It should be understood that when the entire small peripheral circuit is integrated into the memory array chip 2, the interconnection signal between the logic chip 1 and the memory array chip 2 is not a signal on the word line and bit line, but a signal connected to the small peripheral circuit (such as a sensitive amplifier circuit and a word line drive circuit).

[0086] The DRAM provided in the embodiments of this application will be further described below in conjunction with the manufacturing method.

[0087] As illustrated, this application provides a method for manufacturing DRAM, such as... Figure 10 As shown, the manufacturing method may include:

[0088] Step 10, Reference Figure 11 As shown, a first transistor T1 is fabricated on the front side of the first wafer W1, and a first metal trace 11 connected to the first transistor T1 is fabricated; wherein, the first transistor T1 is used to form a first logic circuit.

[0089] As shown in the illustration, among some possible implementation methods, see reference. Figure 11 As shown, step 10 above may include: providing a first wafer W1 (i.e., a first substrate 10), which may be a silicon wafer. A plurality of first transistors T1 for forming a first logic circuit are fabricated on the front side of the first wafer W1 using a front-end process (FEOL), i.e., a device layer is formed; then, a back-end process (BEOL) is used to fabricate first metal traces 11 electrically connected to the device layer. Of course, a bonding pad P1 can be fabricated after the first metal traces 11 to lead them out.

[0090] Step 20, Reference Figure 12 As shown, a plurality of first through-silicon vias (TSV1) are fabricated from the back side of the first wafer W1; wherein, the bottom of the first through-silicon vias (TSV1) is connected to the front side of the transistor T1 through a first wiring layer M0, and the first wiring layer M0 is the wiring layer closest to the first wafer among the first metal wirings 11.

[0091] As shown in the illustration, among some possible implementation methods, see reference. Figure 12 As shown, step 20 may include: fabricating a plurality of first through-silicon vias (TSVs) 1 penetrating the first wafer W1 from the back side of the first wafer W1, and the bottom of the first TSVs 1 is connected to the first wiring layer M0 located on the front side of the first wafer W1. The first wiring layer M0 is the bottom wiring layer in the first metal wiring 11, that is, the wiring layer closest to the device layer in the first metal wiring 11, and the first wiring layer M0 is connected to the front side of the first transistor T1.

[0092] Of course, as another possible implementation, the first through-silicon via TSV1 formed in step 20 can be directly connected to the back side of the first transistor T1, as can be seen in the relevant description above.

[0093] Additionally, among some possible implementation methods, refer to Figure 12As shown, while forming multiple first through-silicon vias (TSV1) in step 20, multiple second through-silicon vias (TSV2) can be fabricated. The multiple second through-silicon vias (TSV2) are connected to the front side of the first transistor T1 through the first wiring layer M0, or directly connected to the back side of the first transistor T1. For details, please refer to the relevant description above.

[0094] Step 30: Fabricate a power supply network 12 on the back side of the first wafer W1, and connect the power supply network 12 to the first through-silicon via (TSV1).

[0095] As shown in the illustration, among some possible implementation methods, see reference. Figure 13 As shown, step 30 may include: thinning the back side of the first wafer W1 on which the first through-silicon via (TSV1) is formed to expose the first TSV1, and fabricating a power supply network 12 connected to the first TSV1 on the back side of the first wafer W1.

[0096] Of course, in some possible implementations, if a second through-silicon via (TSV2) is fabricated in the first wafer W1, a signal network 13 can be fabricated at the same time as the power supply network 12 is formed in step 30, and the signal network 13 is connected to the second through-silicon via (TSV2).

[0097] This completes logic chip 1.

[0098] Step 40, Reference Figure 14 As shown, a storage array chip 2 is provided.

[0099] Illustratively, in some possible implementations, step 40 above may include: referencing Figure 14 As shown, a second wafer W2 (i.e., a second substrate 20) is provided, which can be a silicon wafer (Si wafer). A memory array 202 is first fabricated on the front side of the second wafer W1, and then a second metal trace layer 21 connected to the memory array 202 is fabricated. (Refer to...) Figure 7 As shown, the fabrication of the memory array 202 may include: firstly, using a front-end process (FEOL), fabricating the gate transistor (T) in memory cell a on the front side of the second wafer W1, and then fabricating the memory capacitor C in memory cell a on the gate transistor (T).

[0100] Of course, in some possible implementations, step 40 may also include: fabricating a second transistor T2 on the front side of the second wafer W1 using a front-end process (FEOL), the second transistor T2 being connected to a second metal trace layer 21 located using a back-end process (BEOL) to form a second logic circuit. The second logic circuit may be one or more functional modules in small peripheral circuits connected between different memory arrays 202, as detailed in the preceding description.

[0101] Step 50, Reference Figure 15 As shown, the front side of the storage array chip 2 is bonded to the side of the first wafer W1 on which the first metal trace 11 is fabricated (i.e., the front side of the logic chip 1).

[0102] Illustratively, in some possible implementations, step 50 above may include: referencing Figure 15 As shown, the memory array chip 2 and the logic chip 1 are bonded together using a face-to-face bonding method, forming a bonding interface 3 between them. In this case, the second bonding pad P1 on the front of the logic chip 1 and the second bonding pad P2 on the front of the memory array chip 2 are bonded together at the bonding interface 3, thereby realizing signal interconnection and communication between the logic chip 1 and the memory array chip 2.

[0103] It should be noted that the bonding between the storage array chip 2 and the logic chip 1 can be wafer-to-wafer, chip-to-wafer, or chip-to-chip. This application does not impose any restrictions on this, and it can be set according to the requirements in practice.

[0104] To illustrate, taking logic chip 1 as a wafer and memory array chip 2 as a chip as an example, in the manufacturing process, the memory wafer needs to be cut into memory array chip 2 first, and then memory array chip 2 is bonded to the logic wafer; after that, the logic wafer is cut into logic chip 1, thus completing the bonding between memory array chip 2 and logic chip 1.

[0105] Of course, after step 50, other subsequent manufacturing processes can be carried out according to the actual product requirements.

[0106] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0107] For example, in some possible implementations, steps 20 and 30 may also be performed after the bonding process in step 50.

[0108] For example, in some possible implementations, step 20 can be performed before the first transistor T1 is fabricated via step 10.

[0109] In addition, for other related contents in the above manufacturing method, you can refer to the corresponding parts in the above structural embodiments, which will not be repeated here; for other settings in the above structural embodiments, you can refer to the above manufacturing method and related manufacturing methods for adjustment, which will not be repeated here.

[0110] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage device, characterized in that, It includes a storage array chip and a logic chip, and the front sides of the storage array chip and the front sides of the logic chip are connected by a bonding interface; The logic chip includes: A first substrate, wherein a plurality of first through-silicon vias are provided in the first substrate; A first transistor disposed on the front side of the first substrate, the first transistor being used to form a first logic circuit; The first metal trace is located on the side of the first transistor away from the first substrate, and the first transistor is electrically connected to the memory array chip through the first metal trace; The power supply network is located on the back side of the first substrate; The first metal trace includes multiple trace layers, and the multiple trace layers include a first trace layer that is closest to the first substrate; the power supply network is connected to the first trace layer through the first through-silicon via, and is connected to the front side of the first transistor through the first trace layer; Alternatively, the power supply network is connected to the back side of the first transistor through the first through-silicon via.

2. The storage device according to claim 1, characterized in that, The first substrate also has a plurality of second through-silicon vias; A signal network is also provided on the back side of the first substrate; The signal network is connected to the first wiring layer through the second through-silicon via, and is connected to the front side of the first transistor through the first wiring layer; Alternatively, the signal network can be connected to the back side of the first transistor via the second through-silicon via.

3. The storage device according to claim 1 or 2, characterized in that, The first logic circuit includes at least one of peripheral circuits, interface circuits, power supply units, or computing units.

4. The storage device according to any one of claims 1-3, characterized in that, The memory array chip includes: a second substrate and a memory array and a second metal trace disposed on the front side of the second substrate; The second metal trace is located on the side of the memory array away from the second substrate and is electrically connected to the memory array; The second metal trace is bonded to the first metal trace at the bonding interface.

5. The storage device according to claim 4, characterized in that, The memory array chip also includes a second transistor disposed on the front side of the second substrate; The second transistor is connected to the second metal trace to form a second logic circuit connected between different memory arrays.

6. The storage device according to claim 5, characterized in that, The second logic circuit includes at least one of a sensitive amplifier circuit or a word line driver circuit.

7. A method for manufacturing a storage device, characterized in that, include: A first transistor is fabricated on the front side of a first wafer, and then a first metal trace connected to the first transistor is fabricated; wherein, the first transistor is used to form a first logic circuit; Multiple first through-silicon vias are fabricated on the back side of the first wafer; wherein the bottom of the first through-silicon via is connected to the back side of the first transistor; or, the bottom of the first through-silicon via is connected to the front side of the first transistor through the first wiring layer, wherein the first wiring layer is the wiring layer closest to the first wafer among the first metal wirings. A power supply network is fabricated on the back side of the first wafer, and the power supply network is connected to the first through-silicon via; Provides storage array chips; The front side of the memory array chip is bonded to the side of the first wafer on which the first metal trace is formed.

8. The method for manufacturing a storage device according to claim 7, characterized in that, The provided storage array chip includes: First, a memory array is fabricated on the front side of the second wafer, and then a second metal trace layer connected to the memory array is fabricated.

9. The method for manufacturing a storage device according to claim 8, characterized in that, The storage array chip also includes: A second transistor is fabricated on the front side of the second wafer; wherein the second transistor is connected to the second metal trace layer to form a second logic circuit connected between different memory arrays.

10. A memory, characterized in that, The invention includes the storage device as described in any one of claims 1-6 and a controller, wherein the controller is electrically connected to the storage device.

11. An electronic device, characterized in that, The device includes the memory of claim 10 and a circuit board, wherein the memory is electrically connected to the circuit board.

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