Semiconductor power device and manufacturing method thereof

Abstract

The invention discloses a semiconductor power device. The semiconductor power device comprises a semiconductor layer, a plurality of grooves, a plurality of buried layers and a plurality of doped regions, the semiconductor layer has a first surface and a second surface. A plurality of trenches are located in the semiconductor layer, extend from a first surface of the semiconductor layer to an interior of the semiconductor layer, and extend along a first direction on the first surface of the semiconductor layer. The plurality of buried layers are located below the plurality of grooves and connected with the bottoms of the plurality of grooves. The plurality of doped regions extend inwards from the first surface of the semiconductor layer, and the bottom of each doped region is connected with the corresponding buried layer. And the buried layer and the doped region have the same conduction type. The buried layer is arranged at the bottom of the groove, and the doped region is arranged on the side edge, so that the problem of electric field concentration at the bottom angle of the groove is solved, and the withstand voltage of the semiconductor power device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to the structure and manufacturing method of a trench semiconductor power device. Background Technology

[0002] The technological development trend of semiconductor power devices is to reduce device size and improve device performance, thereby reducing device cost. Trench-type semiconductor power devices replace traditional planar structures with vertical trenching, achieving shorter current paths and better electric field distribution, effectively reducing on-resistance and increasing current density. With the application of wide-bandgap materials, wide-bandgap semiconductor power devices combined with trench device structures have further reduced device size and on-resistance. However, the manufacturing process of such wide-bandgap trench-type semiconductor power devices is complex, and the electric field concentrates near the bottom corners of the trench, making them prone to breakdown. Summary of the Invention

[0003] This application provides a structure for a semiconductor power device. By setting a buried layer at the bottom of the trench and a doped region on the side, the problem of electric field concentration at the bottom corner of the trench is solved, thereby improving the breakdown voltage of the semiconductor power device.

[0004] According to an embodiment of the present invention, a semiconductor power device is provided, comprising: a semiconductor layer having a first surface and a second surface opposite to the first surface; a first trench located in the semiconductor layer and extending from the first surface of the semiconductor layer into the semiconductor layer; a first plateau region located on a first side of the first trench; a second plateau region located on a second side of the first trench; a buried layer enclosing one bottom corner of the first trench, the buried layer having a first side surface, a second side surface, an upper surface, and a lower surface, wherein the first side surface is located below the first trench, the second side surface is located on a second side of the first trench, the distance between the upper surface and the first surface of the semiconductor layer is less than the distance between the bottom of the first trench and the first surface of the semiconductor layer, and the distance between the lower surface and the first surface of the semiconductor layer is greater than the distance between the bottom of the first trench and the first surface of the semiconductor layer; and a doped region located in the second plateau region and extending from the first surface of the semiconductor layer into the semiconductor layer, the bottom of the doped region being in contact with the buried layer; wherein the buried layer and the doped region have the same conductivity type, and the doping concentration of the buried layer is greater than the doping concentration of the doped region.

[0005] According to an embodiment of the present invention, a semiconductor power device is provided, comprising a semiconductor layer having a first surface and a second surface; a first trench located in the semiconductor layer and extending inward from the first surface of the semiconductor layer; a second trench located in the semiconductor layer and extending inward from the first surface of the semiconductor layer; a buried layer located below the first trench and the second trench and in contact with the bottom of the first trench and the second trench; and a doped region located in the semiconductor layer and extending inward from the first surface of the semiconductor layer, the doped region being located between the first trench and the second trench, the bottom of the doped region being in contact with the buried layer.

[0006] According to an embodiment of the present invention, a semiconductor power device is provided, comprising a semiconductor layer having a first surface and a second surface opposite to the first surface; a plurality of trenches located in the semiconductor layer extending from the first surface of the semiconductor layer into the interior of the semiconductor layer, and the plurality of trenches extending along a first direction on the first surface of the semiconductor layer; a plurality of buried layers located below the plurality of trenches and connected to the bottom of the plurality of trenches; and a plurality of doped regions extending from the first surface of the semiconductor layer into the interior of the semiconductor layer, and the bottom of each doped region being connected to a corresponding buried layer; wherein the buried layer and the doped region have the same conductivity type. Attached Figure Description

[0007] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings:

[0008] Figure 1 This is a schematic diagram of a partial cross-sectional structure of a semiconductor power device 100 according to an embodiment of this application, perpendicular to the device surface;

[0009] Figure 2 This is a schematic diagram of a partial cross-sectional structure of a semiconductor power device 200 according to an embodiment of this application, perpendicular to the device surface;

[0010] Figure 3 This is a schematic diagram of a partial cross-sectional structure of a semiconductor power device 300 according to an embodiment of this application, perpendicular to the device surface;

[0011] Figure 4 This is a schematic diagram of the planar structure 400 of a semiconductor power device 300 according to an embodiment of this application;

[0012] Figure 5 This is a schematic diagram of the planar structure 500 of a semiconductor power device 300 according to an embodiment of this application;

[0013] Figure 6This is a schematic diagram of a partial cross-sectional structure of a semiconductor power device 600 according to an embodiment of this application, perpendicular to the device surface;

[0014] Figure 7 This is a schematic diagram of the planar structure 700 of a semiconductor power device 600 according to an embodiment of this application;

[0015] Figure 8 This is a schematic diagram of a partial cross-sectional structure of a semiconductor power device 800 according to an embodiment of this application, perpendicular to the device surface;

[0016] Figure 9 A schematic diagram of a partial cross-sectional structure of a semiconductor power device 900 according to an embodiment of this application, perpendicular to the device surface, is shown.

[0017] Figure 10 This is a schematic diagram of a partial cross-sectional structure of a semiconductor power device 1000 according to an embodiment of this application, perpendicular to the device surface.

[0018] Figure 11 This is a schematic diagram of the planar structure 1100 of a semiconductor power device 1000 according to an embodiment of this application;

[0019] Figure 12 This is a schematic diagram of a partial cross-sectional structure of a semiconductor power device 1200 according to an embodiment of this application, perpendicular to the device surface;

[0020] Figure 13 This is a schematic diagram of a partial cross-sectional structure of a semiconductor power device 1300 according to an embodiment of this application, perpendicular to the device surface;

[0021] Figure 14 This is a schematic diagram of a partial cross-sectional structure of a semiconductor power device 1400 according to an embodiment of this application, perpendicular to the device surface. Detailed Implementation

[0022] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0023] Throughout this specification, references to "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases "in an embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale. The same reference numerals indicate the same elements. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. The drawings are not drawn to scale and are for illustrative purposes only. For clarity, unless otherwise stated, the same elements have been designated by corresponding reference numerals in different drawings.

[0024] The terms “having,” “comprising,” “including,” “include,” etc., are open-ended, and these terms indicate the presence of the said structure, element, or feature, but do not exclude additional elements or features.

[0025] When describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that it contains other layers or regions between it and another layer or region. Furthermore, if the device is flipped, the layer or region will be located "below" or "under" another layer or region.

[0026] To describe a situation where it is located directly on another layer or another area, this article will use the expressions "directly on top of" or "on and adjacent to".

[0027] In some of the accompanying figures, relative doping concentrations are indicated by a "-" or "+" sign next to the doping type "n" or "p". For example, "n-" indicates a lower doping concentration than the "n" doped region, while the "n" doped region has a higher doping concentration than the "n-" doped region. Doped regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-type doped regions may have the same or different absolute doping concentrations.

[0028] In this embodiment of the invention, each semiconductor layer or region has a first conductivity type or a second conductivity type. The first conductivity type refers to either n-type or p-type, and the second conductivity type is the other. That is, a semiconductor layer with the first conductivity type can be an n-type semiconductor layer or a p-type semiconductor layer. When the semiconductor layer with the first conductivity type is an n-type semiconductor layer, the semiconductor layer with the second conductivity type is a p-type semiconductor layer. The n-type semiconductor layer is formed by doping the semiconductor layer with n-type impurities. The n-type impurities can be pentavalent elements such as phosphorus and arsenic. The p-type semiconductor layer is formed by doping the semiconductor layer with p-type impurities. The p-type impurities can be trivalent elements such as boron, indium, and gallium.

[0029] Figure 1 This is a schematic cross-sectional view of a semiconductor power device 100 according to an embodiment of this application, perpendicular to the device surface. Figure 1 As shown, the semiconductor power device 100 includes a semiconductor layer 101, a first trench 105, a buried layer 108, and a doped region 109.

[0030] Semiconductor layer 101 has a first surface 1013 and a second surface 1014. The first surface 1013 and the second surface 1014 are opposite to each other in the vertical direction. Semiconductor layer 101 includes a substrate layer 1011 and an epitaxial layer 1012 covering the substrate layer 1011. The first surface 1013 of semiconductor layer 101 is also a surface of epitaxial layer 1012 that is not in contact with the substrate layer 1011, and the second surface 1014 is a surface of substrate layer 1011 that is not in contact with epitaxial layer 1012. The first surface 1013 and the second surface 1014 are opposite to each other. The substrate layer 1011 and the epitaxial layer 1012 have the same doping type, and the doping concentration of the substrate layer 1011 is greater than the doping concentration of the epitaxial layer 1012. In one embodiment, the substrate layer 1011 and the epitaxial layer 1012 have n-type doping. It should be understood that the epitaxial layer 1012 can be a single-layer structure with uniform doping concentration or a multilayer structure with different doping concentrations.

[0031] A first trench 105 is located in the semiconductor layer 101 and extends from the first surface 1013 of the semiconductor layer 101 into the interior of the semiconductor layer 101. More specifically, the first trench 105 is located in the epitaxial layer 1012. In one embodiment, a gate electrode 106 is provided within the first trench 105, and an insulating layer 107 isolates the gate electrode 106 from the inner wall of the first trench 105. The gate electrode 106 is electrically connected to the gate potential of the semiconductor power device 100.

[0032] The first trench 105 isolates the portion of the semiconductor layer 101 near the first surface 1013 into multiple platform regions 110. Among them, the first platform region 1101 is located on the first side of the first trench 105, and the second platform region 1102 is located on the second side of the first trench 105.

[0033] The buried layer 108 covers the bottom corner of the first trench 105 located on the second side. The buried layer 108 has a first side surface 1081, a second side surface 1082, an upper surface 1083, and a lower surface 1084. The first side surface 1081 is located below the first trench 105, and the second side surface 1082 is located on the second side of the first trench 105, meaning the first side surface 1082 extends towards the second side of the first trench 105 and horizontally extends beyond the sidewall of the first trench 105. The distance between the upper surface 1083 and the first surface 1013 of the semiconductor layer 101 is less than the distance between the bottom of the first trench 105 and the first surface 1013 of the semiconductor layer 101, and the distance between the lower surface 1084 and the first surface 1013 of the semiconductor layer 101 is greater than the distance between the bottom of the first trench 105 and the first surface 1013 of the semiconductor layer 101. In other words, the buried layer 108 covers the bottom of the first trench 105 and at least one bottom corner of the first trench 105. Figure 1 In one embodiment, the first side 1081 of the buried layer 108 is located at the bottom of the first trench 105, and the second side 1082 extends horizontally beyond the sidewall of the first trench 105, meaning the buried layer 108 covers one of the two bottom corners of the first trench 105. In some embodiments, the first side 1081 may also extend horizontally toward the first platform region 1101, either flush with or extending beyond the sidewall of the first trench 105 and the adjacent first platform region 1101, i.e., the buried layer 108 includes the two bottom corners of the first trench 105. In one embodiment, the thickness h1 of the buried layer 108 is between 0.3 μm and 0.6 μm, and the distance h2 between the upper surface 1083 of the buried layer 108 and the upper surface 1013 of the semiconductor layer 101 is between 0.6 μm and 1.2 μm.

[0034] The doped region 109 is located in the second plateau region 1102 and extends from the first surface 1013 of the semiconductor layer 101 into the interior of the semiconductor layer 101. The bottom of the doped region 109 is in contact with the buried layer 108. In one embodiment, the width w1 of the doped region 109 is between 0.5 μm and 2.0 μm.

[0035] The buried layer 108 and the doped region 109 have the same doping type. In one embodiment, both the buried layer 108 and the doped region 109 are p-type doped. The doping concentration of the buried layer 108 is greater than the doping concentration of the doped region 109. In one embodiment, the doping concentration of the buried layer 108 is more than 10 times the doping concentration of the doped region 109.

[0036] The doped region 109 has a first sidewall 1091, a second sidewall 1092, an upper surface 1093, and a lower surface 1094. Figure 1 In this embodiment, the first sidewall 1091 is connected to the sidewall of the first trench 105, the upper surface 1093 is exposed to the upper surface 1013 of the semiconductor layer 101, and the lower surface 1094 is connected to the buried layer 108 and flush with the lower surface 1084 of the buried layer 108. In some embodiments, the lower surface 1094 of the doped region 109 may be further deeper than the lower surface 1084 of the buried layer 108, that is, the distance from the lower surface 1094 of the doped region 109 to the upper surface 1013 of the semiconductor layer 101 may be greater than the distance from the lower surface 1084 of the buried layer 108 to the upper surface 1013 of the semiconductor layer 101.

[0037] like Figure 1 As shown in the embodiment, the semiconductor power device 100 further includes a body region 103 and a source region 104. The body region 103 and source region 104 are distributed in the region of the semiconductor layer 101 near the first surface 1013. Specifically, the body region 103 is distributed in the first plateau region 1101 and the second plateau region 1102, extending inward from the first surface 1013 of the semiconductor layer 101, with a depth less than the depth of the first trench 105. The source region 104 is distributed within the body region 103, with a depth less than the depth of the body region 103. The sidewalls of the body region 103 and the source region 104 are in contact with the sidewalls of the first trench 105 and the sidewalls of the doped region 109. When the semiconductor power device 100 is operating, a current channel is generated in the region where the body region 103 is in contact with the sidewall of the first trench 105.

[0038] Figure 2 This is a schematic cross-sectional view of a semiconductor power device 200 according to an embodiment of this application, perpendicular to the device surface. Figure 1 Compared to the previous examples, in Figure 2 In this embodiment, the buried layer 208 further extends horizontally toward the second platform region 1102. A certain spacing w2 is maintained between the doped region 109 and the first trench 105, while the bottom of the doped region 109 remains connected to one side of the buried layer 208. In one embodiment, the spacing w2 is between 0.3 μm and 1.0 μm.

[0039] Figure 3 This is a schematic cross-sectional view of a semiconductor power device 300 according to an embodiment of this application, perpendicular to the device surface. Figure 1Compared to the previous embodiment, the semiconductor power device 300 further includes a second trench 305 located in the semiconductor layer 101, extending inward from the first surface 1013 of the semiconductor layer 101. The second trench 305 is located in the first plateau region 1101, dividing the first plateau region 1101 into two regions 1101A and 1101B. A buried layer 308 extends horizontally into the second trench 305 to the bottom of the second trench 305. That is, the first side surface 3081 of the buried layer 308 is located at the bottom of the second trench 305. Figure 3 In this embodiment, both bottom corners of the first trench 105 are covered by a buried layer. The bottom corner of the second trench 305 near the first trench is covered by a buried layer 308. In some embodiments, the buried layer 308 may further extend to a portion 1101A of the second platform region 1101, where the first sidewall 3081 is flush with or even exceeds the sidewall of the second trench 305. That is, both bottom corners of the second trench 305 may be covered by the buried layer 308.

[0040] Figure 4 This is a schematic diagram of the planar structure 400 of a semiconductor power device 300 according to an embodiment of this application, corresponding to the first surface 1013 of the semiconductor layer 101. Along Figure 4 Cutting the AA' line shown in the figure in a direction perpendicular to the first surface 1013 will yield the following result: Figure 3 The cross-section of the semiconductor power device 300 shown.

[0041] like Figure 4 As shown, a plurality of parallel trenches, such as a first trench 105 and a second trench 305, are distributed along a first direction y on the first surface 1013 of the semiconductor layer 101. These trenches extend from the first surface 1013 into the interior of the semiconductor layer 101. A plurality of buried layers 308 are located at the bottom of the trenches. Figure 2 In this embodiment, each buried layer 308 connects the bottom of two adjacent trenches, and a certain spacing is maintained between two adjacent buried layers 308 along the first direction. Further, to ensure uniform current channel distribution, such as... Figure 4 As shown, in the first direction y, the buried layers in the same column are staggered with the buried layers in adjacent columns. Specifically, as... Figure 4 As shown, cells 401 and 403 are located in the same column in the first direction y, while cell 402 is located in an adjacent column in the first direction y. Cells 401, 402, and 403 are staggered, so that the buried layers corresponding to the cells are also staggered. The second trench 305 in cells 401 and 403 serves as the first trench in cell 402. Figure 4In this embodiment, in the first direction y, the buried layers 308 of one column are staggered with the buried layers of the adjacent columns. It should be understood that in other embodiments, the staggered distribution of buried layers in adjacent columns may also be that two buried layers of one column are staggered with two first layers of the adjacent column, or that two or more buried layers of one column are staggered with two or more first layers of the adjacent column.

[0042] like Figure 4 As shown, multiple doped regions 109 are connected one-to-one with multiple buried layers 308, and each doped region 109 is located on one side of two trenches (first trench 105 and second trench 305) connected by the corresponding buried layer 308. Figure 4 In this embodiment, the doped region 109 is in contact with the sidewall of the adjacent first trench 105. Although in Figure 4 In this embodiment, the length of the buried layer 308 is greater than the length of the doped region 109 in the first direction y. It should be understood that this application does not limit this, and the lengths of the buried layer 308 and the doped region 109 in the first direction y can be adjusted according to application needs.

[0043] Figure 5 This is a schematic diagram of the planar structure 500 of a semiconductor power device 300 according to an embodiment of this application, corresponding to the first surface 1013 of the semiconductor layer 101. Along Figure 5 Cutting the AA' line shown in the figure in a direction perpendicular to the first surface 1013 will yield the following result: Figure 3 The cross-section of the semiconductor power device 300 shown.

[0044] and Figure 4 Compared to the previous examples, in Figure 5 In the embodiment, each buried layer 308 extends further in the first direction y and connects with other adjacent buried layers in the first direction. Figure 5 In this embodiment, because the buried layers 308 between adjacent columns are staggered, the buried layer 308 in one column is connected to the buried layer 308 in the adjacent column. In other embodiments, if the buried layers 308 between adjacent columns are staggered in pairs, then the buried layer 308 in one column may be connected to a continuous buried layer 308 in the adjacent column, or it may be connected to the buried layer 308 in the same column.

[0045] Figure 6 This is a schematic cross-sectional view of a semiconductor power device 600 according to an embodiment of this application, perpendicular to the device surface. Figure 3Compared to the previous embodiment, the semiconductor power device 600 further includes a contact region 612. The contact region 612 is distributed within the source region 104 and the body region 103, with a depth less than the depth of the body region 103 and greater than or equal to the depth of the source region 104. That is, the contact region 612 penetrates the source region 104 and connects to the body region 103, with the bottom of the contact region 612 either flush with or lower than the bottom of the source region 104. The doping type of the contact region 612 is the same as that of the body region 103. In one embodiment, the source region 104 is n-type doped, the body region 103 is p-type doped, and the contact region 612 is p-type doped, with a higher doping concentration in the contact region 612 than in the body region 103. The contact region 612 is connected to the source potential of the device, which can equalize the potential of the body region 103 in the first direction y, thereby improving the performance of the device.

[0046] Figure 7 This is a schematic diagram of the planar structure 700 of a semiconductor power device 600 according to an embodiment of this application, corresponding to the first surface 1013 of the semiconductor layer 101. Along Figure 7 Cutting the AA' line shown in the figure in a direction perpendicular to the first surface 1013 will yield the following result: Figure 6 The cross-section of the semiconductor power device 600 is shown.

[0047] like Figure 7 As shown, the contact region 612 is discontinuously distributed along the first direction y in the body region 103 and the source region 104. It should be understood that the discontinuous distribution of the contact region 612 is due to the distribution of the doped regions 109. In some embodiments, if the trenches have a sufficiently large distance in the second direction x, i.e., the trench spacing is large, the contact region 612 can be continuously distributed along the continuous direction y to form an elongated structure.

[0048] Figure 8 This is a schematic cross-sectional view of a semiconductor power device 800 according to an embodiment of this application, perpendicular to the device surface. Figure 3 Compared to the previous embodiment, the semiconductor power device 800 further includes a third trench 805 located in the semiconductor layer 101, extending inward from the first surface 1013 of the semiconductor layer 101. The third trench 805 is located between the first trench 105 and the second trench 305, and the bottom of the third trench 805 is connected downward to the buried layer 808.

[0049] Figure 8 Implementation examples in Figure 3Based on the previous embodiment, a third trench 805 was added between the first trench 105 and the second trench 305. That is, the embedded layer 808 connects the bottoms of the three trenches in the second direction x. In other embodiments, two or more third trenches 805 may be added between the first trench 105 and the second trench 305. That is, the embedded layer 808 may connect the bottoms of multiple trenches in the second direction x.

[0050] The planar structure of the semiconductor power device 800 and Figure 4 and Figure 5 The planar structures shown are similar, the difference being the number of trenches connected to the buried layer. For the sake of brevity, this will not be elaborated further here.

[0051] Figure 9 A schematic cross-sectional view of a semiconductor power device 900 according to an embodiment of this application, perpendicular to the device surface, is shown. Figure 9 In this embodiment, the buried layer 908 is located within the semiconductor layer 101, below the first trench 105 and the second trench 905, and connects to the bottom of the first trench 105 and the second trench 905. The doped region 109 is located between the first trench 105 and the second trench 905, and the bottom of the doped region 109 is connected to the buried layer 908.

[0052] exist Figure 9 In this embodiment, the doped region 109 has a spacing w3 between itself and the first trench 105, and a spacing w4 between itself and the second trench 905, and w3 = w4. In some embodiments, the spacing w3 and the spacing w4 may not be equal.

[0053] Figure 10 This is a schematic cross-sectional view of a semiconductor power device 1000 according to an embodiment of this application, perpendicular to the device surface. Figure 9 Compared to the previous embodiment, the semiconductor power device 1000 further includes a contact region 612. The contact region 612 is distributed within the source region 104 and the body region 103, with a depth less than the depth of the body region 103 and greater than or equal to the depth of the source region 104. That is, the contact region 612 penetrates the source region 104 and connects to the body region 103, with the bottom of the contact region 612 either flush with or lower than the bottom of the source region 104. The doping type of the contact region 612 is the same as that of the body region 103. In one embodiment, the source region 104 is n-type doped, the body region 103 is p-type doped, and the contact region 612 is p-type doped, with a higher doping concentration in the contact region 612 than in the body region 103. The contact region 612 is connected to the source potential of the device, which can equalize the potential of the body region 103 in the first direction y, thereby improving the performance of the device.

[0054] Figure 11This is a schematic diagram of the planar structure 1100 of a semiconductor power device 1000 according to an embodiment of this application, corresponding to the first surface 1013 of the semiconductor layer 101. Along Figure 11 Cutting the AA' line shown in the figure in a direction perpendicular to the first surface 1013 will yield the following result: Figure 10 The cross-section of the semiconductor power device 1000 is shown.

[0055] like Figure 11 As shown, the contact region 612 is discontinuously distributed along the first direction y in the body region 103 and the source region 104, and is separated by the doped region 109.

[0056] Figure 12 This is a schematic cross-sectional view of a semiconductor power device 1200 according to an embodiment of this application, perpendicular to the device surface. Figure 3 Compared to the previous embodiment, in the semiconductor power device 1200, the doped region 109 maintains a certain distance from the adjacent first trench 105. That is, the sidewall of the doped region 109 is not in contact with the sidewall of the first trench 105.

[0057] Figure 13 This is a schematic cross-sectional view of a semiconductor power device 1300 according to an embodiment of this application, perpendicular to the device surface. Figure 12 Compared to the previous embodiment, the semiconductor power device 1300 further includes a contact region 612. The contact region 612 is distributed within the source region 104 and the body region 103, with a depth less than the depth of the body region 103 and greater than or equal to the depth of the source region 104. That is, the contact region 612 penetrates the source region 104 and connects to the body region 103, with the bottom of the contact region 612 either flush with or lower than the bottom of the source region 104. The doping type of the contact region 612 is the same as that of the body region 103. In one embodiment, the source region 104 is n-type doped, the body region 103 is p-type doped, and the contact region 612 is p-type doped, with a higher doping concentration in the contact region 612 than in the body region 103. The contact region 612 is connected to the source potential of the device, which can equalize the potential of the body region 103 in the first direction y, thereby improving the performance of the device.

[0058] Figure 14 This is a schematic cross-sectional view of a semiconductor power device 1400 according to an embodiment of this application, perpendicular to the device surface. Figure 12 Compared to the previous embodiment, the semiconductor power device 1400 further includes a third trench 805 located in the semiconductor layer 101, extending inward from the first surface 1013 of the semiconductor layer 101. The third trench 805 is located between the first trench 105 and the second trench 305, and the bottom of the third trench 805 is connected downward to the buried layer 808.

[0059] Figure 14 Implementation examples in Figure 12 Based on the previous embodiment, a third groove 805 was added between the first groove 105 and the second groove 305.

[0060] The planar structure of semiconductor power devices 1200, 1300 and 1400 Figure 4 and Figure 5 The planar structures shown are similar, the difference being whether there is a spacing between the doped region 109 and the first trench 105, and the number of trenches connected by the buried layer. For the sake of brevity, these will not be elaborated here.

[0061] It should be understood that the embodiments of this application only show the device structure related to the technical solution of the present invention. At the same time, the structure in the embodiments of this application is only a partial structural schematic of the semiconductor power device. In order to more clearly and concisely explain the technical solution of the present invention, some areas of the device are not shown in the figure. For example, in order to prevent short circuits between the source metal layer, the guard ring metal layer and a part of the upper surface of the epitaxial layer, the interlayer dielectric layer between the upper surface of the epitaxial layer and the metal layer is not shown in the figure. For example, the well contact area is also not shown in the figure.

[0062] It should be understood that semiconductor layer 101 can be made of any semiconductor material suitable for manufacturing semiconductor devices. Examples of such materials include, but are not limited to: basic semiconductor materials such as silicon (Si) or germanium (Ge); group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanide (SiGe); binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), gallium indium aluminum nitride (AlGaInN), or gallium indium arsenide phosphide (InGaAsP); and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe) (to name just a few). The semiconductor materials mentioned above are also known as "homogeneous junction semiconductor materials." When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-gallium indium aluminum nitride (AlGaInN), indium gallium nitride (InGaN)-gallium indium aluminum nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe heterojunction semiconductor materials. For power semiconductor device applications, Si, SiC, GaAs, and GaN materials are currently the primary materials used.

[0063] As described above, these embodiments of the present application do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to make good use of the present application and modifications based on it. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor power device, comprising: A semiconductor layer having a first surface and a second surface opposite to the first surface; The first trench is located in the semiconductor layer and extends from the first surface of the semiconductor layer into the interior of the semiconductor layer. The first platform area is located on the first side of the first trench; The second platform area is located on the second side of the first trench; A buried layer surrounds one bottom corner of the first trench. The buried layer has a first side surface, a second side surface, an upper surface, and a lower surface. The first side surface is located below the first trench, and the second side surface is located on a second side of the first trench. The distance between the upper surface and the first surface of the semiconductor layer is less than the distance between the bottom of the first trench and the first surface of the semiconductor layer, and the distance between the lower surface and the first surface of the semiconductor layer is greater than the distance between the bottom of the first trench and the first surface of the semiconductor layer. as well as The doped region, located in the second plateau region, extends from the first surface of the semiconductor layer into the interior of the semiconductor layer, and the bottom of the doped region is connected to the buried layer; The buried layer and the doped region have the same conductivity type, and the doping concentration of the buried layer is greater than that of the doped region.

2. The semiconductor power device as described in claim 1, further comprising: The second trench is located in the semiconductor layer and extends inward from the first surface of the semiconductor layer, and the second trench is located in the first plateau region; There is a certain distance between the first trench and the second trench, and the buried layer extends into the second trench to the bottom of the second trench on the first side surface of the buried layer.

3. The semiconductor power device as described in claim 2, further comprising: At least one third trench is located in the semiconductor layer and extends inward from the first surface of the semiconductor layer. The at least one third trench is located between the first trench and the second trench, and the bottom of the at least one third trench is covered by the buried layer.

4. The semiconductor power device according to any one of claims 1-3, wherein: The doped region includes a first side surface, a second side surface, an upper surface, and a lower surface; and The first side of the doped region is in contact with the sidewall of the first trench.

5. The semiconductor power device according to any one of claims 1-3, wherein: The doped region includes a first side surface, a second side surface, an upper surface, and a lower surface; and The first side of the doped region maintains a certain distance from the sidewall of the first trench.

6. The semiconductor power device according to any one of claims 1-3, further comprising: The body region is distributed in the first platform region and the second platform region, and extends from the first surface of the semiconductor layer inward. The depth of the body region is less than the depth of the first trench. as well as The source region is distributed within the body region, and the depth of the source region is less than the depth of the body region.

7. The semiconductor power device of claim 6, further comprising: The contact area is distributed within the source region and the body region, wherein the depth of the contact area is less than the depth of the body region and greater than or equal to the depth of the source region.

8. A semiconductor power device, comprising: The semiconductor layer has a first surface and a second surface; The first trench is located in the semiconductor layer and extends inward from the first surface of the semiconductor layer; The second trench is located in the semiconductor layer and extends inward from the first surface of the semiconductor layer. The buried layer is located below the first trench and the second trench, and is in contact with the bottom of the first trench and the second trench; as well as A doped region is located in the semiconductor layer and extends from the first surface of the semiconductor layer into the interior of the semiconductor layer. The doped region is located between the first trench and the second trench, and the bottom of the doped region is connected to the buried layer.

9. The semiconductor power device as claimed in claim 8, wherein: The buried layer has a first side, a second side, an upper surface, and a lower surface, wherein the first side is located below the first trench, the second side is located below the second trench, the distance between the upper surface and the first surface of the semiconductor layer is less than the distance between the bottom of the first trench and the second trench and the first surface of the semiconductor layer, and the distance between the lower surface and the first surface of the semiconductor layer is greater than the distance between the bottom of the first trench and the second trench and the first surface of the semiconductor layer.

10. The semiconductor power device of claim 8, wherein, The distance between the doped region and the first trench is the same as the distance between the doped region and the second trench.

11. The semiconductor power device according to any one of claims 8-10, further comprising: The body region is distributed in the semiconductor layer, extends from the first surface of the semiconductor layer inward, is adjacent to the first trench, the second trench and the doped region, and the depth of the body region is less than the depth of the first trench and the second trench. as well as The source region is distributed in the body region, adjacent to the first trench, the second trench and the doped region, and the depth of the source region is less than the depth of the body region.

12. The semiconductor power device of claim 11, further comprising: The contact area is distributed within the source region and the body region, wherein the depth of the contact area is less than the depth of the body region and greater than or equal to the depth of the source region.

13. A semiconductor power device, comprising: A semiconductor layer having a first surface and a second surface opposite to the first surface; Multiple trenches are located in the semiconductor layer, extending from a first surface of the semiconductor layer into the interior of the semiconductor layer, and on the first surface of the semiconductor layer, the multiple trenches extend along a first direction; Multiple buried layers are located below the multiple trenches and are connected to the bottom of the multiple trenches; as well as Multiple doped regions extend from the first surface of the semiconductor layer into the interior of the semiconductor layer, and the bottom of each doped region is in contact with a corresponding buried layer; The buried layer and the doped region have the same conductivity type.

14. The semiconductor power device of claim 13, wherein, Each buried layer connects the bottom of two or more trenches.

15. The semiconductor power device of claim 14, wherein, Each buried layer is connected to a doped region that is connected to one end of the buried layer and located on one side of the trench connected by the buried layer. The side of the doped region is connected to the sidewall of the trench adjacent to the doped region in the trench connected by the buried layer.

16. The semiconductor power device of claim 14, wherein, Each doped region connected to the buried layer is connected to one end of the buried layer and located on one side of the trench connected by the buried layer, and there is a certain distance between the doped region and the trench adjacent to the doped region in the trench connected by the buried layer.

17. The semiconductor power device of claim 14, wherein, Each buried layer is connected to a doped region located between trenches connected by the buried layer, and the doped region has the same spacing with the adjacent trenches on both sides.

18. The semiconductor power device of claim 13, wherein, The buried layers in the same column in the first direction are staggered with the buried layers in the adjacent columns, and two adjacent buried layers in the first direction maintain a certain distance.

19. The semiconductor power device of claim 13, wherein, The buried layers in the same column in the first direction are staggered with the buried layers in the adjacent columns, and two adjacent buried layers in the first direction are connected.

20. The semiconductor power device of claim 13, wherein, The doping concentration of the buried layer is greater than the doping concentration of the doped region.

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