Semiconductor device and manufacturing method thereof
By setting a stepped structure in the active region of the semiconductor device and forming heavily doped regions on both sides of the gate dielectric layer and the gate, the problems of low breakdown voltage and large leakage current of the semiconductor device are solved, and the device performance is improved.
Patent Information
- Application Number
- CN202510972920.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-14
- Publication Date
- 2025-11-11
AI Technical Summary
In the prior art, semiconductor devices have low breakdown voltage and large leakage current. Especially under the limitation of sidewall thickness in high-voltage and low-voltage semiconductor devices, it is difficult to effectively improve the breakdown voltage and reduce the leakage current.
By setting a stepped structure in the active region of a semiconductor device and forming heavily doped regions on both sides of the gate dielectric layer and the gate, the top of the heavily doped region is lower than the bottom of the gate dielectric layer, thereby improving the breakdown voltage of the device and reducing the leakage current.
This structural design improves the device's breakdown voltage, reduces leakage current, and enhances the device's electrical performance.
Smart Images
Figure CN120936078A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology
[0002] With the development of semiconductor integrated circuit manufacturing technology, more and more devices are integrated per unit area, the size of the devices is getting smaller and smaller, and the gates of the devices are getting thinner and thinner. The excessively thin gate thickness limits the energy of lightly doped drain (LDD) implantation in self-aligned ion implantation of semiconductor devices (the greater the implantation energy, the greater the damage to the excessively thin gate), which in turn limits the breakdown voltage (BV) of the device.
[0003] Therefore, related technologies provide a non-self-aligned LDD implantation process (LDD implantation performed before gate formation), which eliminates the limitation of LDD implantation energy on the thickness of the gate material. However, while the lateral overlap between the LDD region formed by non-self-aligned implantation and the gate is increased, the breakdown voltage and leakage current of the high-voltage semiconductor device are still limited by the sidewall thickness because the sidewalls of the high-voltage and low-voltage semiconductor devices on the wafer are formed in the same process. Summary of the Invention
[0004] This application provides a semiconductor device and a method for manufacturing the same, which can solve the problems of low breakdown voltage and large leakage current in semiconductor devices provided in related technologies.
[0005] On one hand, embodiments of this application provide a semiconductor device, including:
[0006] A substrate on which high-voltage devices and low-voltage devices are formed, wherein the operating voltage of the high-voltage devices is greater than the operating voltage of the low-voltage devices;
[0007] The upper surface of the active region of the high voltage device is a stepped structure, a first gate dielectric layer is formed on the top layer of the stepped structure, and a first gate is formed on the first gate dielectric layer.
[0008] A first well region is formed in the active region of the high-voltage device, and a first LDD region and a second LDD region are formed in the substrates on both sides of the first gate. A first heavily doped region is formed in the first LDD region, and a second heavily doped region is formed in the second LDD region.
[0009] The tops of the first heavily doped region and the second heavily doped region are lower than the bottom of the first gate dielectric layer, and the impurity concentrations in the first heavily doped region and the second heavily doped region are greater than the impurity concentrations in the first well region, the first LDD region, and the second LDD region.
[0010] In some embodiments, a first sidewall and a second sidewall are formed sequentially from the inside to the outside on the periphery of the first gate.
[0011] In some embodiments, the length of the first gate in the lateral direction is less than the length of the top layer of the stepped structure, the bottom of the first sidewall contacts the top layer, the bottom of the second sidewall contacts the bottom layer of the stepped structure, and the bottom of the first sidewall is higher than the bottom of the second sidewall.
[0012] In some embodiments, a second well region is formed in the active region of the low-voltage device, a second gate dielectric layer is formed on the active region of the low-voltage device, and a second gate is formed on the second gate dielectric layer.
[0013] A third LDD region and a fourth LDD region are formed in the substrate on both sides of the second gate. A third heavily doped region is formed in the third LDD region, and a fourth heavily doped region is formed in the fourth LDD region.
[0014] The impurity concentrations in the third and fourth doped regions are greater than those in the second well region, the third LDD region, and the fourth LDD region.
[0015] In some embodiments, a third sidewall and a fourth sidewall are formed sequentially from the inside to the outside on the periphery of the second gate.
[0016] On the other hand, embodiments of this application provide a method for fabricating a semiconductor device, including:
[0017] A substrate is provided, wherein the regions on the substrate for forming devices include a first region and a second region, the first region is used to form a high-voltage device, the second region is used to form a low-voltage device, the operating voltage of the high-voltage device is greater than the operating voltage of the low-voltage device, a first well region is formed in the substrate of the first region, and a second well region is formed in the substrate of the second region.
[0018] A first LDD region and a second LDD region are formed in the first well region;
[0019] An insulating layer and a polycrystalline silicon layer are sequentially formed on the substrate;
[0020] The insulating layer and polysilicon are etched by photolithography. The remaining insulating layer in the first region forms the first gate dielectric layer, the remaining polysilicon layer in the first region forms the first gate, the remaining insulating layer in the second region forms the second gate dielectric layer, and the remaining polysilicon layer in the second region forms the second gate. The first LDD region and the second LDD are located on both sides of the first gate.
[0021] A groove is formed in the substrate on the periphery of the first gate by photolithography, so that the upper surface of the active region of the high voltage device in the first region presents a stepped structure.
[0022] A third LDD region and a fourth LDD region are formed, wherein the third LDD region and the fourth LDD region are located in the substrate on both sides of the second gate;
[0023] A first heavily doped region and a second heavily doped region are formed, the top of the first heavily doped region and the second heavily doped region are lower than the bottom of the first gate dielectric layer, the first heavily doped region is located in the first LDD region, the second heavily doped region is located in the second LDD region, and the impurity concentration in the first heavily doped region and the second heavily doped region is greater than the impurity concentration in the first well region, the first LDD region and the second LDD region.
[0024] A third doped region and a fourth doped region are formed, wherein the third doped region is located in the third LDD region and the fourth doped region is located in the fourth LDD region. The impurity concentrations in the third doped region and the fourth doped region are greater than the impurity concentrations in the second well region, the third LDD region and the fourth LDD region.
[0025] In some embodiments, the lateral length of the first gate is less than the length of the top layer of the stepped structure.
[0026] In some embodiments, after forming a groove in the substrate surrounding the first gate by photolithography, and before forming the third LDD region and the fourth LDD region, the method further includes:
[0027] A first sidewall and a third sidewall are formed, wherein the first sidewall is located on the periphery of the first gate and the third sidewall is located on the periphery of the second gate.
[0028] In some embodiments, after forming the third LDD region and the fourth LDD region and before forming the first heavily doped region and the second heavily doped region, the method further includes:
[0029] A second side wall and a fourth side wall are formed, with the second side wall located around the periphery of the first side wall and the fourth side wall located around the periphery of the third side wall.
[0030] The technical solution of this application has at least the following advantages:
[0031] By setting the active region of the semiconductor device as a stepped structure, and placing the gate dielectric layer and gate on the top layer of the first-level stepped structure, the heavily doped tops on both sides are lower than the bottom of the gate dielectric layer. When the device is working, the source and drain are lower than the channel region on the horizontal plane, thereby improving the breakdown voltage of the device and reducing the leakage current of the device. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0033] Figure 1 This is a flowchart of a method for fabricating a semiconductor device according to an exemplary embodiment of this application;
[0034] Figures 2 to 8 This is a schematic diagram illustrating the fabrication process of a semiconductor device provided in an exemplary embodiment of this application;
[0035] Figure 9 This is a schematic cross-sectional view of a semiconductor device provided in an exemplary embodiment of this application. Detailed Implementation
[0036] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0037] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0038] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0039] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0040] refer to Figure 1 It illustrates a flowchart of a method for fabricating a semiconductor device according to an exemplary embodiment of this application, such as... Figure 1 As shown, the method includes:
[0041] Step S1: Provide a substrate, the regions on the substrate for forming devices include a first region and a second region, the first region is used to form a high-voltage device, the second region is used to form a low-voltage device, a first well region is formed in the substrate of the first region, and a second well region is formed in the substrate of the second region.
[0042] Step S2: A first LDD region and a second LDD region are formed in the first well region.
[0043] refer to Figure 2 It shows a schematic cross-sectional view after the formation of the first LDD region and the second LDD region. For example, as shown... Figure 2 As shown, the regions on the substrate 100 used for forming devices include a first region and a second region. The first region is used to form a high-voltage device, and the second region is used to form a low-voltage device (the operating voltage of the high-voltage device is greater than the operating voltage of the low-voltage device). A first well region 102 is formed in the substrate 100 of the first region, and a second well region 202 is formed in the substrate 100 of the second region.
[0044] A shallow trench isolation (STI) structure 101 is formed in the substrate 100. When viewed from a top view, the area surrounded by the STI structure 101 is the active area (AA) of each semiconductor device. The accompanying drawings of this application use cross-sectional views of the active area 1001 of the high voltage device in the first region and the active area 1002 of the low voltage device in the second region as examples.
[0045] For example, a first LDD region 1031 and a second LDD region 1032 can be formed on the substrate 100 in the first region by a non-self-aligned ion implantation process, that is, photoresist is covered on the substrate 100. Figure 2 (not shown in the image), the photoresist in the target area is removed by exposure and development in sequence. The remaining photoresist forms a barrier layer (the area covered by the remaining photoresist corresponds to the top layer of the stepped structure formed by subsequent etching). Ion implantation is performed using the barrier layer as a mask to form a first LDD region 1031 and a second LDD region 1032 in the substrate 100 on both sides of the barrier layer.
[0046] Step S3: An insulating layer and a polycrystalline silicon layer are sequentially formed on the substrate.
[0047] refer to Figure 3 It shows a schematic cross-sectional view after the formation of the insulating layer and the polysilicon layer. For example, such as... Figure 3 As shown, a silicon dioxide (SiO2) layer can be generated on the surface of the substrate 100 through a thermal oxidation process to form an insulating layer (insulating layer 104 in the first region and insulating layer 204 in the second region), and a polycrystalline silicon layer 105 can be deposited on the insulating layer through a deposition process in a furnace tube.
[0048] Step S4: The insulating layer and polysilicon are etched by photolithography. The remaining insulating layer in the first region forms the first gate dielectric layer, the remaining polysilicon layer in the first region forms the first gate, the remaining insulating layer in the second region forms the second gate dielectric layer, and the remaining polysilicon layer in the second region forms the second gate.
[0049] refer to Figure 4 It shows a schematic cross-sectional view after the formation of the first and second gates. For example, as shown... Figure 4 As shown, photoresist can be covered on the polysilicon layer 205. Figure 4 (Not shown in the image) The photoresist in the target area is removed by exposure and development in sequence. The remaining photoresist covers the areas corresponding to the first gate 1051 and the second gate 1052. Etching is then performed to remove the polysilicon layer 205 and the insulating layer in the target area. The remaining insulating layer in the first area forms the first gate dielectric layer 1041, the remaining polysilicon layer in the first area forms the first gate 1051, the remaining insulating layer in the second area forms the second gate dielectric layer 2041, and the remaining polysilicon layer in the second area forms the second gate 1052. The first LDD region 1031 and the second LDD region 1032 are located on both sides of the first gate 1051.
[0050] Step S5: A groove is formed in the substrate on the periphery of the first gate using photolithography, so that the upper surface of the active region of the high voltage device in the first region presents a stepped structure.
[0051] refer to Figure 5 It shows a cross-sectional view after the groove is formed; Reference Figure 9 This illustrates a schematic cross-sectional view of a semiconductor device provided in an exemplary embodiment of this application. For example, as shown... Figure 5 and Figure 9 As shown, photoresist 501 can be covered on the substrate 100. The photoresist in the first region is removed by exposure and development in sequence, and etching is performed to form grooves on both sides of the first gate 1051. Figure 5 The first groove 301 or Figure 9 The second groove 302, viewed from a top view, shows that both grooves 301 and 302 are rectangular, but their shapes are not limited to this (the upper surface of the active region of the high-voltage device can present a stepped structure). This allows the upper surface of the active region of the high-voltage device in the first region to present a stepped structure. This stepped structure can be... Figure 5 The top layer has the same length as the first gate 1051, which can also be... Figure 9 The top layer has a length greater than that of the first gate 1051.
[0052] Step S6: Form the third LDD region and the fourth LDD region, which are located in the substrate on both sides of the second gate.
[0053] Optionally, after step S5 and before step S6, the method further includes: forming a first side wall and a third side wall; after step S6, the method further includes: forming a second side wall and a fourth side wall.
[0054] refer to Figure 6 It shows a schematic cross-sectional view after the formation of the third and fourth LDD regions. For example, as shown... Figure 6 As shown, a silicon dioxide (SiO2) layer can be deposited by chemical vapor deposition (CVD) and etched until the first gate 1051, the second gate 1052 and the substrate 100 are exposed. Then, a first sidewall 1071 is formed on the periphery of the first gate 1051 and a second sidewall 1072 is formed on the periphery of the second gate 1052 (the first sidewall 1071 is higher than the third sidewall 1072). Photoresist 502 is covered on the substrate 100. The photoresist 502 in the second region is removed by exposure and development in sequence. Ion implantation is performed to form a third LDD region 2061 and a fourth LDD region 2062 in the substrate 100 on both sides of the second gate 1052.
[0055] refer to Figure 7 It shows a schematic cross-sectional view after the formation of the second and fourth side walls. For example, as shown... Figure 7As shown, a silicon dioxide layer can be deposited by CVD process and etched until the first gate 1051, the second gate 1052 and the substrate 100 are exposed. A second sidewall 1081 is formed on the surface of the first sidewall 1051 and a fourth sidewall 1082 is formed on the surface of the third sidewall 1052.
[0056] Step S7: A first heavily doped region and a second heavily doped region are formed. The top of the first heavily doped region and the second heavily doped region are lower than the bottom of the first gate dielectric layer. The first heavily doped region is located in the first LDD region, and the second heavily doped region is located in the second LDD region.
[0057] Step S8: A third doped region and a fourth doped region are formed. The third doped region is located in the third LDD region, and the fourth doped region is located in the fourth LDD region.
[0058] refer to Figure 8 The diagram shows a cross-sectional view after the formation of the first, second, third, and fourth doped regions. The impurity concentrations in the first and second doped regions 1091 and 1092 are greater than those in the first well region 102, the first LDD region 1031, and the second LDD region 1032. Similarly, the impurity concentrations in the third and fourth doped regions 2091 and 2092 are greater than those in the second well region 202, the third LDD region 2061, and the fourth LDD region 2062.
[0059] In this embodiment, the impurities doped in the first well region 102 and the second well region 202 are impurities of the first conductivity type, and the impurities doped in the first LDD region 1031, the second LDD region 1032, the third LDD region 2061, the fourth LDD region 2062, the first heavily doped region 1091, the second heavily doped region 1092, the third heavily doped region 2091, and the fourth heavily doped region 2092 are impurities of the second conductivity type. In this embodiment, if the impurity of the first conductivity type is a P (positive) type impurity, then the impurity of the second type is an N (negative) type impurity; if the impurity of the first conductivity type is an N type impurity, then the impurity of the second type is a P type impurity.
[0060] refer to Figure 8 and Figure 9 This illustration shows a cross-sectional schematic diagram of a semiconductor device provided in an exemplary embodiment of this application. This semiconductor device can be fabricated using the above embodiments, for example, as shown below. Figure 8 and Figure 9 As shown, the device includes:
[0061] A substrate 100 is formed thereon with a high-voltage device and a low-voltage device, wherein the operating voltage of the high-voltage device is greater than the operating voltage of the low-voltage device.
[0062] The upper surface of the active region of the high voltage device has a stepped structure. A first gate dielectric layer 1041 is formed on the top layer of the stepped structure, and a first gate 1051 is formed on the first gate dielectric layer 1041.
[0063] A first well region 102 is formed in the active region of the high voltage device. A first LDD region 1031 and a second LDD region 1032 are formed in the substrate 100 on both sides of the first gate 1051. A first heavily doped region 1091 is formed in the first LDD region 1031, and a second heavily doped region 1092 is formed in the second LDD region 1032.
[0064] The top of the first heavily doped region 1091 and the second heavily doped region 1092 are lower than the bottom of the first gate dielectric layer 1041, and the impurity concentration in the first heavily doped region 1091 and the second heavily doped region 1092 is greater than the impurity concentration in the first well region 102, the first LDD region 1031 and the second LDD region 1032.
[0065] Optionally, a first sidewall 1071 and a second sidewall 1081 are formed sequentially from the inside to the outside on the periphery of the first gate 1051; optionally, as... Figure 9 As shown, the lateral length of the first gate 1051 is less than the length of the top layer of the stepped structure. The bottom of the first sidewall 1071 contacts the top layer of the stepped structure, and the bottom of the second sidewall 1081 contacts the bottom layer of the stepped structure. The bottom of the first sidewall 1071 is higher than the bottom of the second sidewall 1081 (e.g., ...). Figure 9 (The area shown in the dashed line).
[0066] A second well region 202 is formed in the active region of the low-voltage device, a second gate dielectric layer 2041 is formed on the active region of the low-voltage device, and a second gate 1052 is formed on the second gate dielectric layer 2041.
[0067] A third LDD region 2061 and a fourth LDD region 2062 are formed in the substrate 100 on both sides of the second gate 1052. A third heavily doped region 2091 is formed in the third LDD region 2061, and a fourth heavily doped region 2092 is formed in the fourth LDD region 2062.
[0068] The impurity concentrations in the third doped region 2091 and the fourth doped region 2092 are greater than the impurity concentrations in the second well region 202, the third LDD region 2061, and the fourth LDD region 2062.
[0069] Optionally, a third sidewall 1072 and a fourth sidewall 1082 are formed sequentially from the inside to the outside on the periphery of the second gate 1052; optionally, the third sidewall 1072 is lower than the first sidewall 1071, and the fourth sidewall 1082 is lower than the second sidewall 1081.
[0070] The impurities doped in the first well region 102 and the second well region 202 are impurities of a first conductivity type, and the impurities doped in the first LDD region 1031, the second LDD region 1032, the third LDD region 2061, the fourth LDD region 2062, the first heavily doped region 1091, the second heavily doped region 1092, the third heavily doped region 2091, and the fourth heavily doped region 2092 are impurities of a second conductivity type. In the embodiments of this application, if the impurity of the first conductivity type is a P-type impurity, then the impurity of the second type is an N-type impurity; if the impurity of the first conductivity type is an N-type impurity, then the impurity of the second type is a P-type impurity.
[0071] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A semiconductor device, characterized in that, include: A substrate on which high-voltage devices and low-voltage devices are formed, wherein the operating voltage of the high-voltage devices is greater than the operating voltage of the low-voltage devices; The upper surface of the active region of the high voltage device is a stepped structure, a first gate dielectric layer is formed on the top layer of the stepped structure, and a first gate is formed on the first gate dielectric layer. A first well region is formed in the active region of the high-voltage device, and a first LDD region and a second LDD region are formed in the substrates on both sides of the first gate. A first heavily doped region is formed in the first LDD region, and a second heavily doped region is formed in the second LDD region. The tops of the first heavily doped region and the second heavily doped region are lower than the bottom of the first gate dielectric layer, and the impurity concentrations in the first heavily doped region and the second heavily doped region are greater than the impurity concentrations in the first well region, the first LDD region, and the second LDD region.
2. The device according to claim 1, characterized in that, The first gate has a first sidewall and a second sidewall formed sequentially from the inside to the outside.
3. The device according to claim 2, characterized in that, The length of the first gate in the lateral direction is less than the length of the top layer of the stepped structure, the bottom of the first sidewall is in contact with the top layer, the bottom of the second sidewall is in contact with the bottom layer of the stepped structure, and the bottom of the first sidewall is higher than the bottom of the second sidewall.
4. The device according to claim 2, characterized in that, A second well region is formed in the active region of the low-voltage device, a second gate dielectric layer is formed on the active region of the low-voltage device, and a second gate is formed on the second gate dielectric layer. A third LDD region and a fourth LDD region are formed in the substrate on both sides of the second gate. A third heavily doped region is formed in the third LDD region, and a fourth heavily doped region is formed in the fourth LDD region. The impurity concentrations in the third and fourth doped regions are greater than those in the second well region, the third LDD region, and the fourth LDD region.
5. The device according to claim 4, characterized in that, The second gate has a third sidewall and a fourth sidewall formed sequentially from the inside to the outside.
6. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, wherein the regions on the substrate for forming devices include a first region and a second region, the first region is used to form a high-voltage device, the second region is used to form a low-voltage device, the operating voltage of the high-voltage device is greater than the operating voltage of the low-voltage device, a first well region is formed in the substrate of the first region, and a second well region is formed in the substrate of the second region. A first LDD region and a second LDD region are formed in the first well region; An insulating layer and a polycrystalline silicon layer are sequentially formed on the substrate; The insulating layer and polysilicon are etched by photolithography. The remaining insulating layer in the first region forms the first gate dielectric layer, the remaining polysilicon layer in the first region forms the first gate, the remaining insulating layer in the second region forms the second gate dielectric layer, and the remaining polysilicon layer in the second region forms the second gate. The first LDD region and the second LDD are located on both sides of the first gate. A groove is formed in the substrate on the periphery of the first gate by photolithography, so that the upper surface of the active region of the high voltage device in the first region presents a stepped structure. A third LDD region and a fourth LDD region are formed, wherein the third LDD region and the fourth LDD region are located in the substrate on both sides of the second gate; A first heavily doped region and a second heavily doped region are formed, the top of the first heavily doped region and the second heavily doped region are lower than the bottom of the first gate dielectric layer, the first heavily doped region is located in the first LDD region, the second heavily doped region is located in the second LDD region, and the impurity concentration in the first heavily doped region and the second heavily doped region is greater than the impurity concentration in the first well region, the first LDD region and the second LDD region. A third doped region and a fourth doped region are formed, wherein the third doped region is located in the third LDD region and the fourth doped region is located in the fourth LDD region. The impurity concentrations in the third doped region and the fourth doped region are greater than the impurity concentrations in the second well region, the third LDD region and the fourth LDD region.
7. The method according to claim 6, characterized in that, The length of the first gate in the lateral direction is less than the length of the top layer of the stepped structure.
8. The method according to claim 6 or 7, characterized in that, After forming a groove in the substrate surrounding the first gate using photolithography, and before forming the third and fourth LDD regions, the process further includes: A first sidewall and a third sidewall are formed, wherein the first sidewall is located on the periphery of the first gate and the third sidewall is located on the periphery of the second gate.
9. The method according to claim 8, characterized in that, After the formation of the third and fourth LDD regions, and before the formation of the first and second heavily doped regions, the process also includes: A second side wall and a fourth side wall are formed, with the second side wall located around the periphery of the first side wall and the fourth side wall located around the periphery of the third side wall.