Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate comprising a first device region and a second device region; forming a gate stacking material layer and a protective material layer which are stacked in sequence on the upper surface of the substrate, wherein the thickness of the protective material layer above the first device region is smaller than that of the protective material layer above the second device region; based on etching of the gate stack material layer and the protective material layer, a plurality of first gate units and second gate units which are arranged at intervals are formed above the first device region and the second device region respectively, and the etched protective material layer forms a protective layer; forming a groove in the substrate between two adjacent second gate units, and synchronously etching and thinning the protective layer at the top of the second gate units while forming the groove; and forming an epitaxial layer in the groove to form an epitaxial structure. According to the semiconductor structure and the preparation method thereof, the exposure of the gate layer above the second device region is avoided, the gate height difference is improved, and the device yield is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] In the development of 28nm process devices, the performance optimization of PMOS (P-channel Metal-Oxide-Semiconductor) devices is one of the key directions. According to the physical characteristics of PMOS devices, the greater the compressive stress that the PMOS device is subjected to, the more significant the improvement in its drive current. The enhancement of drive current is directly related to the optimization of device electrical performance.

[0003] To achieve this goal, the industry commonly employs germanium-silicon epitaxy (EPI) technology to effectively increase the compressive stress on PMOS devices, thereby improving their electrical performance. However, to ensure that germanium-silicon epitaxy precisely targets only the PMOS region, a clear distinction must be made between PMOS and NMOS (N-channel Metal-Oxide-Semiconductor). Therefore, the PMOS region is additionally etched.

[0004] However, additional etching will cause the oxide and nitride layers on top of the gate structure in the PMOS device to be etched, which protect the gate. On the one hand, this will cause a height difference between the gate structures of NMOS and PMOS devices, especially the shoulder height problem, which will lead to a mismatch in device characteristics and ultimately affect the switching speed and power consumption of the device. On the other hand, in subsequent processes, the exposed gate structure may also cause metal ions in the metal electrode to enter the gate layer, which will affect the device performance and interfere with the normal process. Summary of the Invention

[0005] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems in existing PMOS technologies, such as the presence of an epitaxial layer leading to exposed gate layers and differences in gate structure height between PMOS and NMOS, which affect device switching speed and process progress.

[0006] To achieve the above objectives, the present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0007] A substrate is provided, the substrate including a first device region and a second device region;

[0008] A gate stack material layer and a protective material layer are formed sequentially on the upper surface of the substrate, wherein the thickness of the protective material layer above the first device region is less than the thickness of the protective material layer above the second device region;

[0009] Based on the etching of the gate stack material layer and the protective material layer, a plurality of spaced first gate cells are formed above the first device region and a plurality of spaced second gate cells are formed above the second device region, wherein the etched protective material layer forms a protective layer;

[0010] A trench is formed in the substrate between two adjacent second gate cells, and at the same time the trench is formed, the protective layer on top of the second gate cell is simultaneously etched and thinned.

[0011] An epitaxial layer is formed within the trench to form an epitaxial structure.

[0012] In one embodiment, there is a preset difference between the thickness of the protective material layer above the first device region and the thickness of the protective material layer above the second device region, and during the formation of the trench, the etching thickness at the top of the second gate cell is equal to the preset difference.

[0013] In one embodiment, forming the protective material layer includes the following steps:

[0014] A protective material layer of a predetermined thickness is formed on the upper surface of the gate stack material layer;

[0015] The protective material layer located above the second device region is thinned.

[0016] In one embodiment, forming the first gate unit and the second gate unit includes the following steps:

[0017] The gate stack material layer and the protective material layer above the first device region and the second device region are etched respectively to obtain the gate stack and the protective layer;

[0018] Sidewall structures are formed on the exposed surfaces of the gate stack and the protective layer above the etched first device region and second device region, respectively. The gate stack, the protective layer and the sidewall structure above the first device region constitute the first gate cell, and the gate stack, the protective layer and the sidewall structure above the second device region constitute the second gate cell.

[0019] In one embodiment, etching the protective layer on top of the second gate unit also includes etching a portion of the sidewall structure on top of the second gate unit.

[0020] In one embodiment, forming the trench includes the following steps:

[0021] Dry etching is performed on the substrate between adjacent second gate cells through an opening on the substrate surface to form a pre-trench;

[0022] The pre-groove is wet-etched to obtain the groove.

[0023] In one embodiment, when the pre-trench is formed, the protective layer on top of the second gate cell is simultaneously etched and thinned.

[0024] The present invention also provides a semiconductor structure, comprising:

[0025] The substrate includes a first device region and a second device region;

[0026] The first gate cell and the second gate cell are located above the first device region and the second device region, respectively. Both the first gate cell and the second gate cell include a gate stack and a protective layer. The top of the first gate cell and the top of the second gate cell are flush.

[0027] The epitaxial structure includes a trench located in the substrate between two adjacent second gate cells and an epitaxial layer filling the trench.

[0028] In one embodiment, both the first gate unit and the second gate unit further include a sidewall structure, the sidewall structure comprising a barrier layer, an insulating layer and an isolation layer stacked sequentially.

[0029] In one embodiment, the isolation layer in the first gate unit covers the sidewall of the insulating layer and the upper surface of the protective layer, the isolation layer in the second gate unit covers the sidewall of the insulating layer, and the top of the isolation layer in the first gate unit is flush with the top of the protective layer in the second gate unit.

[0030] The semiconductor structure and its fabrication method described above have the following advantages: When forming the first gate cell and the second gate cell above the first device region and the second device region respectively based on the etching of the gate stack material layer and the protective material layer, by setting the thickness of the protective material layer above the first device region to be smaller than the thickness of the protective material layer above the second device region, during the subsequent etching of trenches in the substrate of the second device region to form an epitaxial structure and the simultaneous etching and thinning of the top of the second gate cell, the protective layer at the top of the second gate cell is prevented from being etched and exposing the gate layer, thereby affecting device performance and operation. The process issues have been effectively addressed, improving product yield and ensuring the smooth progress of subsequent processes. Furthermore, in some embodiments, by setting a preset difference between the thickness of the protective material layer above the first device region and the thickness of the protective material layer above the second device region, and during the formation of the trench, the etching thickness of the top of the second gate cell is equal to the preset difference, so that after the top of the second gate cell is simultaneously etched and thinned, the top of the first gate cell and the top of the second gate cell can remain flush, avoiding the transistor characteristic mismatch caused by the inconsistency in the height of the first and second gate cells, which in turn affects the overall performance of the device. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure provided in one embodiment;

[0033] Figure 2 This is a schematic cross-sectional view of the semiconductor structure after a protective material layer is formed on the upper surface of the gate stacked material layer in a method for fabricating a semiconductor structure provided in one embodiment.

[0034] Figure 3 This is a schematic cross-sectional view of the semiconductor structure after the first shielding layer is formed in a method for fabricating a semiconductor structure provided in one embodiment.

[0035] Figure 4 This is a schematic cross-sectional view of the protective material layer above the first device region after thinning in a semiconductor structure fabrication method provided in one embodiment;

[0036] Figure 5 This is a schematic diagram of the cross-sectional structure after removing the first shielding layer in a method for fabricating a semiconductor structure provided in one embodiment.

[0037] Figure 6This is a schematic cross-sectional view of the semiconductor structure after the barrier layer and insulating layer are formed in a method for fabricating a semiconductor structure provided in one embodiment.

[0038] Figure 7 This is a schematic cross-sectional view of the semiconductor structure after the formation of the first gate unit and the second gate unit in a method for fabricating a semiconductor structure provided in one embodiment.

[0039] Figure 8 This is a schematic cross-sectional view of the semiconductor structure after the second shielding layer is formed in a method for fabricating a semiconductor structure provided in one embodiment.

[0040] Figure 9 This is a schematic diagram of the cross-sectional structure after the pre-trench is formed in a semiconductor structure fabrication method provided in one embodiment;

[0041] Figure 10 This is a schematic diagram of the cross-sectional structure after the epitaxial layer is formed in a semiconductor structure fabrication method provided in one embodiment.

[0042] Explanation of reference numerals in the attached figures:

[0043] 1-Substrate, 11-First device region, 12-Second device region, 2-Gate stack material layer, 21-Gate dielectric material layer, 22-Gate material layer, 23-Buffer material layer, 3-Protective material layer, 31-First shielding layer, 4-First gate cell, 41-Second shielding layer, 5-Second gate cell, 6-Epiaxial structure, 61-Trench, 611-Pre-trench, 62-Epiaxial layer, 7-Gate stack, 71-Gate dielectric layer, 72-Gate layer, 73-Buffer layer, 8-Protective layer, 9-Sidewall structure, 91-Blocking layer, 92-Insulating layer, 93-Isolation layer. Detailed Implementation

[0044] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0047] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0049] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0050] Please see Figures 1 to 10 This invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0051] S1: A substrate 1 is provided, the substrate including a first device region 11 and a second device region 12;

[0052] S2: A gate stack material layer 2 and a protective material layer 3 are formed sequentially on the upper surface of the substrate 1, wherein the thickness of the protective material layer 3 above the first device region 11 is less than the thickness of the protective material layer 3 above the second device region 12.

[0053] S3: Based on the gate stack material layer 2 and the protective material layer 3, a plurality of spaced first gate units 4 are formed above the first device region 11 and a plurality of spaced second gate units 5 are formed above the second device region 12, wherein the etched protective material layer 3 forms a protective layer 8.

[0054] S4: A trench 61 is formed in the substrate 1 between two adjacent second gate units 5, and at the same time as the trench 61 is formed, the top of the second gate unit is simultaneously etched and thinned.

[0055] S5: An epitaxial layer 62 is formed in the trench 61 to form an epitaxial structure 6.

[0056] The above-mentioned semiconductor structure fabrication method, based on the etching of the protective material layer 3 and the gate stacking material layer 2, forms the first gate cell 4 and the second gate cell 5 above the first device region 11 and the second device region 12, respectively. By setting the thickness of the protective material layer 3 above the first device region 11 to be smaller than that above the second device region 12, when the trench 61 is etched in the substrate 1 of the second device region 12 to form the epitaxial structure 6 and the top of the second gate cell 5 is simultaneously etched, the problem of the gate material layer 22 in the second gate cell 5 being exposed after the protective material layer 3 at the top of the second gate cell 5 is etched is avoided, which would affect the device performance and process progress. This effectively improves the product yield and provides a guarantee for the smooth progress of subsequent processes.

[0057] Step S1 is performed, providing a substrate 1, which includes a first device region 11 and a second device region 12.

[0058] The substrate 1 is made of silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., gallium nitride, gallium arsenide, etc.) or alloys thereof, oxide semiconductors (e.g., zinc oxide, gallium oxide, etc.) or combinations thereof. In this embodiment, the substrate 1 includes multiple device regions for forming NMOS devices or PMOS devices. In this embodiment, the first device region 11 is an NMOS device region for forming NMOS devices, and the second device region 12 is a PMOS device region for forming PMOS devices.

[0059] Please see Figures 2 to 5 In step S2, a gate stack material layer 2 and a protective material layer 3 are formed on the upper surface of the substrate 1 in sequence. The thickness of the protective material layer 3 above the first device region 11 is less than the thickness of the protective material layer 3 above the second device region 12.

[0060] The gate stack material layer 2 is used as the base material layer for forming the gate structure above the first device region 11 and the second device region 12. The gate stack material layer 2 includes a gate dielectric material layer 21, a gate material layer 22, and a buffer material layer 23 stacked sequentially. The gate dielectric material layer 21 is made of silicon dioxide or other suitable materials; the gate material layer 22 is made of polysilicon or other suitable materials; and the buffer material layer 23 is made of silicon nitride or other suitable materials. The method for forming the gate dielectric material layer 21 includes chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the gate material layer 22 includes chemical vapor deposition, physical vapor deposition, or other suitable methods; and the method for forming the buffer material layer 23 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. The thicknesses of the gate dielectric material layer 21, the gate material layer 22, and the buffer material layer 23 can be selected according to actual conditions, provided that the performance of the semiconductor structure is satisfied, and are not limited herein.

[0061] In some embodiments, step S2 further includes steps S21-S22, forming the protective material layer 3 includes the following steps:

[0062] S21: A protective material layer 3 of a predetermined thickness is formed on the upper surface of the gate stack material layer 2. The material of the protective material layer 3 includes silicon oxynitride, silicon oxide, or other suitable materials. The method for forming the protective material layer 3 includes chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods. The predetermined thickness can be selected according to actual conditions while meeting the performance requirements of the semiconductor structure, and is not limited here. The protective material layer 3 is used to prevent the gate stack material layer from being chemically corroded or physically damaged.

[0063] S22: Thinning the protective material layer 3 located above the second device region 12. This thinning includes forming a first masking layer 31 on the upper surface of the protective material layer 3 located above the first device region 11, thinning the protective material layer 3 above the second device region 12 based on the first masking layer 31, and then removing the first masking layer 31. The first masking layer 31 protects the protective material layer 3 above the first device region 11 and includes photoresist or other suitable masking materials. The thickness of the first masking layer 31 can be selected according to actual conditions, provided that the performance of the semiconductor structure is satisfied, and is not limited here. Methods for thinning the protective material layer 3 above the second device region 12 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods.

[0064] Furthermore, there is a preset difference between the thickness of the protective material layer 3 above the first device region 11 and the thickness of the protective material layer 3 above the second device region 12. In some embodiments, to ensure that the tops of the subsequently formed first gate cell 4 and second gate cell 5 remain flush, the thickness of the protective material layer 3 in the thinned portion above the second device region 12 is the same as the preset difference during the formation of the protective material layer 3. The preset difference ranges from 8nm to 15nm; exemplarily, the preset difference is 10nm. This preset difference can be calculated by examining the height difference between the gate structures of the second device region 12 and the first device region 11 after the epitaxial structure 6 is formed in the second device region 12 in the prior art.

[0065] Please see Figures 6 to 7 In step S3, based on the gate stack material layer 2 and the protective material layer 3, a plurality of spaced first gate units 4 are formed above the first device region 11 and a plurality of spaced second gate units 5 are formed above the second device region 12, wherein the etched protective material layer 3 forms a protective layer 8.

[0066] In some embodiments, step S3 further includes steps S31-S32, forming the first gate unit 4 and the second gate unit 5 by the following steps:

[0067] S31: The gate stack material layer 2 and the protective material layer 3 above the first device region 11 and the second device region 12 are etched respectively to obtain the gate stack 7 and the protective layer 8. The etching method for the gate stack material layer 2 and the protective material layer 3 includes dry etching, wet etching or other suitable methods. The etched gate stack 7 includes a gate dielectric layer 71, a gate layer 72 and a buffer layer 73 stacked sequentially. The gate dielectric layer 71 serves as an insulating material between the gate layer 72 and the substrate 1, preventing current from flowing directly from the gate layer 72 to the substrate and ensuring that the gate voltage can effectively control the formation of the channel. The gate layer 72 is a key part for controlling the formation of the channel and the flow of current. The gate voltage is changed to control the turn-on and turn-off of the transistor. The buffer layer 73 can serve as a stress buffer layer to reduce device performance degradation caused by stress in the gate structure. In the process, the buffer layer 73 can also serve as an etching stop layer to prevent over-etching during the etching of the second gate cell 5 when forming the epitaxial structure 6, which would affect the device yield. In some embodiments, the height difference between the top of the protective layer 8 above the first device region 11 and the top of the protective layer 8 above the second device region 12 is equal to a preset difference value.

[0068] S32: A sidewall structure 9 is formed on the exposed surfaces of the etched gate stack 7 and the protective layer 8. The gate stack 7, the protective layer 8 and the sidewall structure 9 located above the first device region 11 constitute the first gate unit 4. The gate stack 7, the protective layer 8 and the sidewall structure 9 located above the second device region 12 constitute the second gate unit 5.

[0069] The sidewall structure 9 provides physical support for the gate structure, preventing current from flowing from the gate to the source / drain regions and reducing parasitic capacitance. The sidewall structure 9 includes a barrier layer 91, an insulating layer 92, and an isolation layer 93 stacked sequentially. The barrier layer 91 covers the sidewalls of the gate stack 7 and the protective layer 8, the insulating layer 92 covers the sidewalls of the barrier layer 91, and the isolation layer 93 covers the sidewalls of the insulating layer 92 and the upper surface of the protective layer 8. The barrier layer 91 helps protect the gate from chemical corrosion in subsequent process steps, the insulating layer 92 provides additional insulation as an intermediate layer and helps reduce parasitic capacitance between the gate and the source / drain regions, and the isolation layer 93 is designed to provide mechanical protection and further chemical stability, ensuring the sidewall structure 9 remains intact in subsequent process steps. The barrier layer 91 is made of silicon nitride or other suitable materials; the insulating layer 92 is made of silicon dioxide or other suitable materials; and the isolation layer 93 is made of silicon nitride or other suitable materials. The methods for forming the barrier layer 91 include chemical vapor deposition, physical vapor deposition, or other suitable methods; the methods for forming the insulating layer 92 include chemical vapor deposition, physical vapor deposition, or other suitable methods; and the methods for forming the isolation layer 93 include chemical vapor deposition, physical vapor deposition, or other suitable methods. The thicknesses of the barrier layer 91, insulating layer 92, and isolation layer 93 can be selected according to actual conditions, provided that the performance of the semiconductor structure is satisfied, and are not limited herein. The sidewall structure 9 may also include other stacked structures, and is not limited to the stacked structure composed of the barrier layer 91, insulating layer 92, and isolation layer 93 in this embodiment.

[0070] Please see Figures 8 to 10 Steps S4-S5 are executed to form a trench 61 in the substrate 1 between two adjacent second gate cells 5, and at the same time as the trench 61 is formed, the top of the second gate cell is simultaneously etched; an epitaxial layer 62 is formed in the trench 61 to form an epitaxial structure 6.

[0071] In some embodiments, step S4 further includes steps S41-S42, forming the trench 61 includes the following steps:

[0072] S41: Dry etching is performed on the substrate 1 between adjacent second gate cells 5 through an opening on the surface of the substrate 1 to form a pre-trench 611; wherein the bottom of the pre-trench 611 is spaced apart from the bottom of the substrate 1; the pre-trench 611 is obtained by dry etching, which can quickly achieve the required depth of the pre-trench 611; the spacing between the bottom of the pre-trench 611 and the bottom of the substrate 1 can be selected according to the actual situation, without limitation, while meeting the performance requirements of the semiconductor structure.

[0073] When forming the pre-trench 611, the process further includes forming a second shielding layer 41 covering the first gate cell 4 above the first device region 11, etching the substrate 1 between the second gate cells 5 based on the second shielding layer 41 to form the trench 61 in the substrate 1, and then removing the second shielding layer 41. The second shielding layer 41 is used to protect the first gate cell 4 from being affected in subsequent processes. The second shielding layer 41 includes photoresist or other suitable shielding materials; the thickness of the second shielding layer 41 can be selected according to actual conditions while meeting the performance requirements of the semiconductor structure, and is not limited here.

[0074] Furthermore, during the formation of the pre-trench 611, the protective layer 8 on top of the second gate cell 5 is simultaneously etched and thinned. The etching and thinning of the protective layer 8 on top of the second gate cell 5 also includes etching a portion of the sidewall structure 9 on top of the second gate cell 5. That is, while the protective layer 8 on top of the second gate cell 5 is being etched and thinned, the isolation layer 93 on top of the second gate cell 5 is also being etched. Therefore, during the etching process of the second gate cell 5 formed based on the relatively thick protective material layer 3, the formation of the pre-trench 611 avoids the problem of the gate layer 72 in the second gate cell 5 being exposed after the top of the second gate cell 5 is etched, thus affecting device performance and process progress. This effectively improves product yield and ensures the smooth progress of subsequent processes.

[0075] In some embodiments, there is a preset difference between the thickness of the protective material layer 3 above the first device region 11 and the thickness of the protective material layer 3 above the second device region 12. During the formation of the trench 61, the etching thickness of the top of the second gate cell 5 is equal to the preset difference, that is, the etching thickness of the isolation layer 93 and the protective layer 8 on the top of the second gate cell 5 is equal to the preset difference. Therefore, after the top of the second gate cell 5 is simultaneously etched and thinned, the tops of the first gate cell 4 and the second gate cell 5 remain flush, avoiding the transistor characteristic mismatch caused by the inconsistent heights of the first gate cell 4 and the second gate cell 5, which in turn affects the overall performance of the device.

[0076] S42: Perform wet etching on the pre-trench 611 to obtain the trench 61. The pre-trench 611 is etched by wet etching, which is isotropic etching, and can more easily achieve the morphology of a regular sigma trench. For example, the shape of the sigma trench is hexagonal.

[0077] Specifically, the method for forming the epitaxial layer 62 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. The material of the epitaxial layer 62 includes germanium silicon or other suitable materials. The epitaxial structure 6 is used to increase the compressive stress of the device located above the second device region 12 to meet the requirements of the semiconductor structure for the drive current of the device located above the second device region 12, thereby improving the overall response speed of the device.

[0078] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0079] Please continue reading. Figure 10 The present invention also provides a semiconductor structure, which is prepared by the above-described semiconductor structure preparation method, comprising: a substrate 1, a first gate unit 4, a second gate unit 5, and an epitaxial structure 6, wherein the substrate 1 includes a first device region 11 and a second device region 12; the first gate unit 4 and the second gate unit 5 are respectively located above the first device region 11 and the second device region 12, and both the first gate unit 4 and the second gate unit 5 include a gate stack 7 and a protective layer 8, and the top of the first gate unit 4 and the top of the second gate unit 5 are flush; the epitaxial structure 6 includes a trench 61 located in the substrate 1 between two adjacent second gate units 5 and an epitaxial layer 62 filling the trench 61.

[0080] In some embodiments, both the first gate unit 4 and the second gate unit 5 further include a sidewall structure 9, which includes a barrier layer 91, an insulating layer 92, and an isolation layer 93 stacked sequentially.

[0081] Specifically, in the sidewall structure of the first gate unit 4 and the second gate unit 5, the barrier layer 91 covers the sidewall of the gate stack 7 and the protective layer 8, and the insulating layer 92 covers the sidewall of the barrier layer 91. However, the isolation layer 93 in the first gate unit 4 covers the sidewall of the insulating layer 92 and the upper surface of the protective layer 8, and the isolation layer 93 in the second gate unit 5 covers the sidewall of the insulating layer 92. The top of the isolation layer 93 in the first gate unit 4 is flush with the top of the protective layer 8 in the second gate unit 5.

[0082] By keeping the top of the first gate cell 4 and the top of the second gate cell 5 in the semiconductor structure formed by the above-described semiconductor structure fabrication method flush, the problem of transistor characteristic mismatch caused by the inconsistency in height between the first gate cell 4 and the second gate cell 5, which in turn affects the overall performance of the device, is avoided.

[0083] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0084] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: A substrate is provided, the substrate including a first device region and a second device region; A gate stack material layer and a protective material layer are formed sequentially on the upper surface of the substrate, wherein the thickness of the protective material layer above the first device region is less than the thickness of the protective material layer above the second device region; Based on the etching of the gate stack material layer and the protective material layer, a plurality of spaced first gate cells are formed above the first device region and a plurality of spaced second gate cells are formed above the second device region, wherein the etched protective material layer forms a protective layer; A trench is formed in the substrate between two adjacent second gate cells, and at the same time the trench is formed, the protective layer on top of the second gate cell is simultaneously etched and thinned. An epitaxial layer is formed within the trench to form an epitaxial structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, There is a preset difference between the thickness of the protective material layer above the first device region and the thickness of the protective material layer above the second device region, and during the formation of the trench, the etching thickness at the top of the second gate cell is equal to the preset difference.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming the protective material layer includes the following steps: A protective material layer of a predetermined thickness is formed on the upper surface of the gate stack material layer; The protective material layer located above the second device region is thinned.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of the first gate cell and the second gate cell includes the following steps: The gate stack material layer and the protective material layer above the first device region and the second device region are etched respectively to obtain the gate stack and the protective layer; Sidewall structures are formed on the exposed surfaces of the gate stack and the protective layer above the etched first device region and second device region, respectively. The gate stack, the protective layer and the sidewall structure above the first device region constitute the first gate cell, and the gate stack, the protective layer and the sidewall structure above the second device region constitute the second gate cell.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The etching process for thinning the protective layer at the top of the second gate cell also includes etching a portion of the sidewall structure at the top of the second gate cell.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, Forming the trench includes the following steps: Dry etching is performed on the substrate between adjacent second gate cells through an opening on the substrate surface to form a pre-trench; The pre-groove is wet-etched to obtain the groove.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, During the formation of the pre-trench, the protective layer on top of the second gate cell is simultaneously etched and thinned.

8. A semiconductor structure, characterized in that, include: The substrate includes a first device region and a second device region; The first gate cell and the second gate cell are located above the first device region and the second device region, respectively. Both the first gate cell and the second gate cell include a gate stack and a protective layer. The top of the first gate cell and the top of the second gate cell are flush. The epitaxial structure includes a trench located in the substrate between two adjacent second gate cells and an epitaxial layer filling the trench.

9. The semiconductor structure according to claim 8, characterized in that, Both the first gate unit and the second gate unit further include a sidewall structure, which includes a barrier layer, an insulating layer and an isolation layer stacked sequentially.

10. The semiconductor structure according to claim 9, characterized in that, The isolation layer in the first gate unit covers the sidewall of the insulating layer and the upper surface of the protective layer, and the isolation layer in the second gate unit covers the sidewall of the insulating layer. The top of the isolation layer in the first gate unit is flush with the top of the protective layer in the second gate unit.

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