Technological method applied to manufacturing process of semiconductor device

Abstract

The invention discloses a process method applied to a manufacturing process of a semiconductor device, which comprises the following steps: providing an SOI (Silicon On Insulator) substrate which comprises a silicon substrate and an insulating layer formed in the silicon substrate, isolating the silicon substrate into a top-layer substrate positioned above and a bottom-layer substrate positioned below by the insulating layer, forming a gate dielectric layer on the upper surface of the top-layer substrate, and forming a gate dielectric layer on the lower surface of the bottom-layer substrate; a polysilicon gate is formed on the gate dielectric layer; carrying out pre-amorphization ion implantation, and forming an amorphous region in the top layer substrate at two sides of the polysilicon gate; ion implantation is carried out, a defect enrichment region is formed in the top layer substrate below the amorphous region, the defect enrichment region is not in contact with the amorphous region and the insulating layer, and the defect enrichment region is used for attracting charges generated by collision ionization of the drain electrode and charges introduced by tunneling of the gate dielectric layer when the semiconductor device works.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a process method applied in the fabrication of semiconductor devices. Background Technology

[0002] Semiconductor devices with a silicon-on-insulator (SOI) structure are increasingly widely used due to their lower parasitic capacitance, absence of latch-up effect, strong resistance to radiation / ionizing radiation, and ability to achieve lower power consumption and higher integration density. In particular, the buried oxide layer in the SOI structure can effectively isolate noise and substrate crosstalk, making it especially suitable for fabricating radio frequency (RF) front-end devices, such as low-noise amplifiers and RF switches.

[0003] SOI devices can be classified into floating-body and body-contact types based on whether the body electrode is brought out. Floating-body devices offer higher gate-source transconductance (G). M ) and cutoff frequency (f T SOI devices are commonly used in high-gain amplifiers. However, when the drain-source voltage exceeds a certain value, the output characteristic curve of the SOI device exhibits a kink effect, causing instability in the amplifier's output voltage and gain fluctuations, thus affecting the circuit's stability. Furthermore, the upward tilt of the output characteristic curve reflects the drain-source conductance (G... ds An increase in eigengatron gain (G) often leads to an increase in the amplifier's intrinsic gain (G). M / G ds A decrease in ) will cause the overall performance of the amplifier circuit to degrade. Summary of the Invention

[0004] This application provides a process method applied in the fabrication of semiconductor devices, which can solve the problem of poor electrical performance of SOI semiconductor devices provided in related technologies. The method includes:

[0005] An SOI substrate is provided, the SOI substrate including a silicon substrate and an insulating layer formed in the silicon substrate, the insulating layer separating the silicon substrate into an upper top substrate and a lower bottom substrate, a gate dielectric layer being formed on the upper surface of the top substrate, and a polysilicon gate being formed on the gate dielectric layer;

[0006] Pre-amorphization ion implantation is performed to form amorphous regions in the top substrate on both sides of the polycrystalline silicon gate;

[0007] Ion implantation is performed to form a defect-rich region in the top substrate below the amorphous region. The defect-rich region does not contact the amorphous region or the insulating layer. The defect-rich region is used to attract the charge generated by drain collision ionization and the charge introduced by tunneling of the gate dielectric layer when the semiconductor device is operating.

[0008] In some embodiments, the implantation source in the pre-amorphized ion implantation includes germanium.

[0009] In some embodiments, the implantation source in the ion implantation includes germanium.

[0010] In some embodiments, the direction of ion implantation is at a predetermined angle to the normal of the upper surface of the substrate.

[0011] In some embodiments, the predetermined angle is 5 to 35 degrees.

[0012] In some embodiments, the thickness of the top substrate is greater than 400 angstroms.

[0013] The technical solution of this application has at least the following advantages:

[0014] By forming a defect-rich region in the top substrate of an SOI semiconductor device, it is possible to effectively attract the charge generated by the collisional ionization of the drain and the charge introduced by the tunneling of the gate dielectric layer. This can reduce the warping effect of the SOI device's output characteristic curve, reduce the drain-source conductance, thereby improving the intrinsic gain of the device and enhancing its electrical performance. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a process method applied in the fabrication of semiconductor devices provided in an exemplary embodiment of this application;

[0017] Figures 2 to 4 This is a schematic diagram of the process of a process method provided in an exemplary embodiment of this application;

[0018] Figure 5 These are comparative test data of drain current-drain voltage curves of semiconductor devices fabricated using related technologies and semiconductor devices fabricated using the embodiments of this application, under the same gate-source voltage.

[0019] Figure 6These are comparative test data of the drain-source conductance of semiconductor devices fabricated using related technologies and semiconductor devices fabricated using the embodiments of this application;

[0020] Figure 7 It is a comparative test data curve of off-state current-saturation leakage current of a floating semiconductor device fabricated using related technologies and a floating semiconductor device fabricated using the embodiments of this application, under the same operating voltage;

[0021] Figure 8 It is a comparative test data curve of off-state current-linear threshold voltage of a floating semiconductor device fabricated using related technologies and a floating semiconductor device fabricated using the embodiments of this application, under the same operating voltage;

[0022] Figure 9 These are comparative test data on the intrinsic gain of semiconductor devices fabricated using related technologies and semiconductor devices fabricated using the embodiments of this application under the same gate-source voltage;

[0023] Figure 10 It is a comparative test data curve of off-state current-saturation leakage current of a bulk contact semiconductor device fabricated using related technologies and a bulk contact semiconductor device fabricated using the embodiments of this application, under the same operating voltage;

[0024] Figure 11 This is a comparative test data curve of off-state current versus linear threshold voltage for a bulk contact semiconductor device fabricated using related technologies and a bulk contact semiconductor device fabricated using the embodiments of this application, under the same operating voltage. Detailed Implementation

[0025] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0027] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0028] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0029] refer to Figure 1 It illustrates a flowchart of a process method applied in the fabrication of semiconductor devices according to an exemplary embodiment of this application, such as... Figure 1 As shown, the method includes:

[0030] Step S1: Provide an SOI substrate, the SOI substrate including a silicon substrate and an insulating layer formed in the silicon substrate, the insulating layer separating the silicon substrate into a top layer substrate located above and a bottom layer substrate located below, a gate dielectric layer formed on the upper surface of the top layer substrate, and a polysilicon gate formed on the gate dielectric layer.

[0031] refer to Figure 2 This illustrates a schematic cross-sectional view prior to pre-amorphization ion implantation. For example, such as... Figure 2 As shown, the SOI substrate includes a silicon substrate and an insulating layer 213 formed in the silicon substrate. The insulating layer 213 isolates the silicon substrate as a top layer substrate 212 located above it (its thickness is greater than...). The substrate consists of a bottom substrate 211 and a top substrate 212. A gate dielectric layer 220 is formed on the upper surface of the top substrate 212, and a polysilicon gate 230 is formed on the gate dielectric layer 220. Optionally, sidewalls 231 are formed around the polysilicon gate 230.

[0032] Step S2 involves pre-amorphization ion implantation to form amorphous regions in the top substrate on both sides of the polycrystalline silicon gate.

[0033] refer to Figure 3 This illustrates a schematic cross-sectional view after pre-amorphization implantation (PAI). For example, as shown... Figure 3 As shown, after pre-amorphization ion implantation, an amorphous region 201 is formed in the top substrate 212 on both sides of the polycrystalline silicon gate 230. The implantation source in the pre-amorphization ion implantation includes germanium (Ge).

[0034] Step S3: Ion implantation is performed to form a defect-rich region in the top substrate below the amorphous region. The defect-rich region does not contact the amorphous region or the insulating layer. The defect-rich region is used to attract the charge generated by the drain collision ionization and the charge introduced by the tunneling of the gate dielectric layer when the semiconductor device is working.

[0035] refer to Figure 4 It shows a schematic cross-sectional view after ion implantation. For example, as shown... Figure 4 As shown, after ion implantation, a defect-rich region 202 is formed in the top substrate 212 below the amorphous region 201. This defect-rich region 202 is used to attract the charge generated by drain collision ionization and the charge introduced by tunneling through the gate dielectric layer when the semiconductor device is operating. During the ion implantation process, the direction of ion implantation is at a predetermined angle to the normal of the upper surface of the substrate, which is between 5 degrees (°) and 35 degrees.

[0036] In summary, in the embodiments of this application, by forming a defect-rich region in the top substrate of the SOI semiconductor device, it is possible to effectively attract the charge generated by the collisional ionization of the device drain and the charge introduced by the tunneling of the gate dielectric layer, thereby reducing the warping effect of the SOI device output characteristic curve, reducing the drain-source conductance, and thus improving the intrinsic gain of the device and improving the electrical performance of the device.

[0037] refer to Figure 5 It illustrates a semiconductor device fabricated using related techniques (fabrication via lightly doped drain (LDD) ion implantation directly after PAI). Figure 5 (marked as "related technologies") and semiconductor devices fabricated using the embodiments of this application ( Figure 5 (as labeled "Embodiments of this Application") at the same gate-source voltage (V) gs Drain current - drain voltage (I) at 0.6 volts (V) d -V d Comparison test data of the curves. For example... Figure 5 As shown, the horizontal axis represents the drain-source voltage (V) of the device. ds (Unit: volts), with the vertical axis representing the drain-source current of the device (Id). ds The unit is ampere (A). Under the same bias conditions, the I embodiment of this application... ds higher.

[0038] refer to Figure 6 It shows comparative test data of drain-source conductance for semiconductor devices fabricated using related technologies and semiconductor devices fabricated using embodiments of this application. Figure 6As shown, the horizontal axis represents the drain-source voltage (in volts), and the vertical axis represents the drain-source conductance. The warp point of the device fabricated in this embodiment is improved by approximately 100 millivolts (mV) compared to devices fabricated using related technologies, effectively mitigating the floating body effect.

[0039] refer to Figure 7 It illustrates the off-state current (Io) of a floating semiconductor device fabricated using related technologies and a floating semiconductor device fabricated using embodiments of this application at the same operating voltage (1.2 volts). off )-Saturation leakage current (I dsat Comparison test data curves; Reference Figure 8 It illustrates the off-state current-linear threshold voltage (V0) of a floating semiconductor device fabricated using related technologies and a floating semiconductor device fabricated using embodiments of this application at the same operating voltage (1.2 volts). tlin The comparison test data curve is shown. Figure 7 In the graph, the horizontal axis represents the saturation leakage current (in microamperes per micrometer (μA / μm)), and the vertical axis represents the off-state current (in amperes per micrometer (A / μm)). Figure 8 In the graph, the horizontal axis represents the linear threshold voltage (in volts), and the vertical axis represents the off-state current (in amperes per micrometer). For example... Figure 7 and Figure 8 As shown, the output curve of this application embodiment has a significant improvement.

[0040] refer to Figure 9 It illustrates a semiconductor device fabricated using related technologies and a semiconductor device fabricated using embodiments of this application at the same gate-source voltage (V). gs Comparative test data of intrinsic gain at 0.6 volts. Figure 9 As shown, the horizontal axis represents the drain current / width (I d / w (unit: microampere / micrometer), the vertical axis represents intrinsic gain. Under the same drain current / width conditions, the intrinsic gain of the embodiments of this application is significantly improved compared with related technologies, thereby improving the gain of the amplifier and improving the stability of the circuit.

[0041] refer to Figure 10 It shows comparative test data curves of off-state current-saturation leakage current of a bulk contact semiconductor device fabricated using related technologies and a bulk contact semiconductor device fabricated using embodiments of this application, under the same operating voltage (1.2 volts); Reference Figure 11It shows a comparative test data curve of off-state current-linear threshold voltage of a bulk contact semiconductor device fabricated using related technologies and a bulk contact semiconductor device fabricated using the embodiments of this application at the same operating voltage (1.2 volts). Figure 10 In the graph, the horizontal axis represents the saturation leakage current (in microamperes per micrometer), and the vertical axis represents the off-state current (in amperes per micrometer). Figure 11 In this graph, the horizontal axis represents the linear threshold voltage (in volts), and the vertical axis represents the off-state current (in amperes per micrometer). For example... Figure 10 and Figure 11 As shown, under the same test conditions, the output curves of the two samples are basically the same, which indicates that the method provided in this application embodiment can improve the key characteristics of floating body semiconductor devices while maintaining the original electrical characteristics of bulk contact semiconductor devices without degradation, thus eliminating the need to add an additional mask to distinguish between floating body devices and bulk contact devices.

[0042] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A process method applied in the fabrication of semiconductor devices, characterized in that, include: An SOI substrate is provided, the SOI substrate including a silicon substrate and an insulating layer formed in the silicon substrate, the insulating layer separating the silicon substrate into an upper top substrate and a lower bottom substrate, a gate dielectric layer being formed on the upper surface of the top substrate, and a polysilicon gate being formed on the gate dielectric layer; Pre-amorphization ion implantation is performed to form amorphous regions in the top substrate on both sides of the polycrystalline silicon gate; Ion implantation is performed to form a defect-rich region in the top substrate below the amorphous region. The defect-rich region does not contact the amorphous region or the insulating layer. The defect-rich region is used to attract the charge generated by drain collision ionization and the charge introduced by tunneling of the gate dielectric layer when the semiconductor device is operating.

2. The method according to claim 1, characterized in that, The implantation source in the pre-amorphized ion implantation includes germanium.

3. The method according to claim 2, characterized in that, The implantation source in the ion implantation includes germanium.

4. The method according to any one of claims 1 to 3, characterized in that, The direction of ion implantation is at a predetermined angle to the normal of the upper surface of the substrate.

5. The method according to claim 4, characterized in that, The predetermined angle is between 5 degrees and 35 degrees.

6. The method according to claim 5, characterized in that, The thickness of the top substrate is greater than 400 angstroms.

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