Class III semiconductor packaging structure

Abstract

The invention discloses a third-class semiconductor packaging structure which comprises a first conductive interface, a second conductive interface, a third-class semiconductor power element and an electrostatic discharge protection element. The third type semiconductor power element is provided with a gate end and a source end, the gate end is electrically connected with the first conductive interface, and the source end is electrically connected with the second conductive interface. The electrostatic discharge protection element is a surface-mounted element and is provided with a first end and a second end, and the first end and the second end are attached to the first conductive interface and the second conductive interface respectively.

Description

Technical Field

[0001] This invention relates to a third type of semiconductor package structure, and more particularly to a third type of semiconductor package structure that integrates electrostatic discharge (ESD) protection elements. Background Technology

[0002] Type III semiconductors (such as silicon carbide (SiC) or gallium nitride (GaN)) are used to fabricate power devices. To prevent damage to these devices due to electrostatic discharge (ESD), an ESD protection element is needed connected to the device's gate. Traditional ESD protection methods involve designing the ESD protection element (usually a transistor) and the power device on the same die. The transistor needs to be large enough to achieve ESD protection, which increases the die area and cost.

[0003] Another traditional ESD protection method is to design the ESD protection element and the power element on different chips and then package them to form a package structure. In this case, the ESD protection element is a bare chip and is electrically connected to the gate of the power element by wire bonding. Summary of the Invention

[0004] One of the objectives of this invention is to propose a third type of semiconductor packaging structure that integrates ESD protection elements.

[0005] To achieve the above objectives, the present invention provides a third type of semiconductor package structure, including a first conductive interface, a second conductive interface, a third type of semiconductor power element, and an electrostatic discharge (ESD) protection element. The third type of semiconductor power element has a gate terminal and a source terminal, wherein the gate terminal is electrically connected to the first conductive interface, and the source terminal is electrically connected to the second conductive interface. The ESD protection element is a surface-mount element having a first end and a second end, wherein the first end and the second end are respectively attached to the first conductive interface and the second conductive interface.

[0006] To achieve the above objectives, the present invention also provides a third type of semiconductor package structure, including a conductive interface, a third type of semiconductor power element, and an electrostatic discharge (ESD) protection element. The third type of semiconductor power element has a gate terminal and a source terminal, wherein the gate terminal is electrically connected to the conductive interface via a first wire bonding. The ESD protection element is a bare die, having a first end and a second end located on opposite sides of the ESD protection element, wherein the first end is attached to the conductive interface, and the second end is electrically connected to the source terminal via a second wire bonding. Attached Figure Description

[0007] Figure 1This invention shows a first embodiment of a third type of semiconductor packaging structure.

[0008] Figure 2 show Figure 1 The equivalent circuit diagram of the third type of semiconductor packaging structure.

[0009] Figure 3 The equivalent circuit diagram is shown when the first end of the ESD protection element is connected to the conductive interface by a wire.

[0010] Figure 4 This invention shows a second embodiment of the third type of semiconductor packaging structure.

[0011] Figure 5 Displayed Figure 1 The equivalent circuit diagram of adding impedance elements in the third type of semiconductor packaging structure.

[0012] Figure 6 This illustrates a third embodiment of the third type of semiconductor packaging structure of the present invention.

[0013] Figure reference numerals: 10 - Type III semiconductor package structure; 11 - Conductive interface; 12 - Conductive interface; 13 - Conductive interface; 14 - Conductive interface; 15 - Type III semiconductor power element; 151 - Gate terminal; 152 - Source terminal; 153 - Drain terminal; 16 - Electrostatic discharge protection element; 161 - First terminal; 162 - Second terminal; 163 - Transient voltage suppressor diode; 17 - Wire bonding; 18 - Wire bonding; 19 - Wire bonding; 20 - Wire bonding; 30 - Type III semiconductor package structure; 31 - Substrate 311-Conductive interface; 312-Conductive interface; 313-Conductive interface; 314-Conductive interface; 315-Conductive interface; 316-Conductive interface; 317-Trace; 318-Trace; 319-Trace; 32-Wire bonding; 33-Wire bonding; 34-Wire bonding; 40-Type III semiconductor package structure; 41-Electrostatic discharge protection element; 42-Wire bonding; D-Drain; G-Gate; L1-Inductor; L2-Inductor; L3-Inductor; R1-Resistor; R2-Resistor; R3-Resistor; S-Source. Detailed Implementation

[0014] Figure 1 This invention shows a first embodiment of a third type of semiconductor packaging structure. Figure 1The third type of semiconductor package structure 10 is a dual flat no lead package (DFN) structure, but the present invention is not limited to DFN. The present invention can also be used in other types of package structures, such as chip scale packages (CSP). The third type of semiconductor package structure 10 includes four conductive interfaces 11, 12, 13 and 14, a third type of semiconductor power element 15 and an electrostatic discharge (ESD) protection element 16. The conductive interfaces 11, 12, 13 and 14 form a lead frame. The third type of semiconductor power element 15 is disposed on the conductive interface 13. The third type of semiconductor power element 15 has a gate terminal 151, a source terminal 152 and a drain terminal 153, wherein the gate terminal 151 is electrically connected to the conductive interface 11 through a bonding wire 17, the source terminal 152 is electrically connected to the conductive interface 12 through a bonding wire 18 and then to the conductive interface 13 through a bonding wire 19, and the drain terminal 153 is electrically connected to the conductive interface 14 through a bonding wire 20. Conductive interface 11 serves as a gate pad, acting as the gate G of the third-generation semiconductor package structure 10. Conductive interfaces 12 and 13 serve as source pads, acting as the source S of the third-generation semiconductor package structure 10, and conductive interface 14 serves as a drain pad, acting as the drain D of the third-generation semiconductor package structure 10. The ESD protection element 16 is a surface mount device (SMD). The bottom of the ESD protection element 16 has a first terminal 161 and a second terminal 162 (e.g., ...). Figure 2 The components (as shown) are directly attached to conductive interfaces 11 and 13 respectively to provide ESD protection for the third type of semiconductor power device 15. The electrostatic discharge protection element 16 can be, but is not limited to, a transient voltage suppressor (TVS) diode 163, such as... Figure 2 As shown.

[0015] In one embodiment, the first end 161 and the second end 162 of the ESD protection element 16 can also be directly attached to the conductive interfaces 11 and 12, respectively. In one embodiment, the conductive interfaces 12 and 13 can be integrated, thus eliminating the need for the bonding wire 19.

[0016] Figure 2 show Figure 1 The equivalent circuit diagram of the third type of semiconductor packaging structure. Figure 2 In the diagram, resistor R2 and inductor L2 are the equivalent resistance and inductance of wire bonding 17, and resistor R3 and inductor L3 are the equivalent resistance and inductance of wire bonding 18. From... Figure 1 and Figure 2As can be seen, the ESD protection element 16 of the present invention is directly connected to the conductive interface 11 (gate G) and the conductive interface 12 (source S). Therefore, there is no equivalent resistance and equivalent inductance formed by wire bonding in the path of the ESD protection element 16. This avoids the ESD protection capability of the ESD protection element 16 being affected by wire bonding, and the voltage difference between the gate G and the source S can also be clamped to a fixed value by the ESD protection element 16. Furthermore, since wire bonding involves wire bonding stress, the wire bonding itself also has a yield. The more wires there are, the lower the yield of the third type semiconductor package structure 10. Since the ESD protection element 16 of the present invention does not require wire bonding, the number of wires can be reduced, thereby improving the yield of the third type semiconductor package structure 10.

[0017] Figure 3 The diagram shows the equivalent circuit of ESD protection element 16 connected to conductive interface 11 via a wire bond, illustrating the adverse effects of such a connection. Figure 3 As shown, when the ESD protection element 16 is connected to the conductive interface 11 via a wire, the path of the ESD protection element 16 contains the equivalent resistance R1 and equivalent inductance L1 of the wire, thus affecting the ESD protection capability of the ESD protection element 16. Specifically, the equivalent resistance R1 and equivalent inductance L1 of the wire will generate a voltage difference ΔV = i × R1 + L1 × di / dt. Therefore, the voltage on the gate G must be greater than or equal to ΔV + Vbv for the ESD protection element 16 to activate and provide ESD protection. In other words, the activation speed of ESD protection is slow, affecting the ESD protection capability of the ESD protection element 16, where i is the current through the resistor R1 and inductor L1, and Vbv is the breakdown voltage of the TVS diode 163. Conversely, as Figure 2 As shown, the ESD protection element 16 of the present invention is directly connected to the conductive interface 11 (gate G) and the conductive interface 12 (source S). Therefore, there is no voltage difference ΔV formed by the equivalent resistance R1 and the equivalent inductance L1 in the path of the ESD protection element 16. This allows the ESD protection element 16 to be activated to provide ESD protection when the voltage on the gate G is greater than or equal to Vbv. Furthermore, in Figure 3 In this process, because the value of di / dt may vary, the voltage difference ΔV will also vary, thus the voltage difference between the gate G and the source S will also vary, causing jitter in the gate signal on the gate G, resulting in deviations in the electrical characteristics of the third type of semiconductor package structure 10. Conversely, if... Figure 2As shown, the ESD protection element 16 of the present invention has no equivalent resistance R1 and equivalent inductance L1 in its path. Therefore, the ESD protection element 16 can clamp the voltage difference between the gate G and the source S to a fixed value (Vbv). Generally speaking, the source S is grounded, so the gate signal on the gate G will be fixed at Vbv, thus avoiding gate signal jitter.

[0018] Figure 4 This invention shows a second embodiment of the third type of semiconductor packaging structure. Figure 4 The third type of semiconductor packaging structure 30 is a ball grid array (BGA) package, but the present invention is not limited to BGA packaging. The present invention can also be used in other types of packaging structures, such as a land grid array (LGA) package. Figure 4 The third-generation semiconductor package structure 30 includes a substrate 31, a third-generation semiconductor power element 15, and an electrostatic discharge (ESD) protection element 16. The substrate 31 is used to support the third-generation semiconductor power element 15 and the ESD protection element 16. The substrate 31 has six conductive interfaces 311, 312, 313, 314, 315, and 316, and three traces 317, 318, and 319. The conductive interfaces 311, 312, 313, 314, 315, and 316 are conductive pads. Traces 317 connect to conductive interfaces 311 and 313, 318 connect to conductive interfaces 312 and 314, and 319 connect to conductive interfaces 315 and 316. The conductive interfaces 311, 312, and 313 can be considered as the gate (G), source (S), and drain (D) of the third-generation semiconductor package structure 30, respectively. The surface of the third-class semiconductor power device 15 has a gate terminal 151, a source terminal 152, and a drain terminal 153. The gate terminal 151 is electrically connected to the conductive interface 313 via a wire 32, the source terminal 152 is electrically connected to the conductive interface 314 via a wire 33, and the drain terminal 153 is electrically connected to the conductive interface 316 via a wire 34. The ESD protection element 16 is a surface mount element with a first end and a second end (not shown) on its bottom, which are directly attached to the conductive interfaces 311 and 312, respectively, to provide ESD protection for the third-class semiconductor power device 15.

[0019] exist Figure 4 In this invention, the ESD protection element 16 is directly connected to the conductive interface 311 (gate G) and the conductive interface 312 (source S). Therefore, there is no equivalent resistance and equivalent inductance formed by wire bonding on the path of the ESD protection element 16. This avoids the ESD protection capability of the ESD protection element 16 being affected by wire bonding. Moreover, the voltage difference between the gate G and the source S can be clamped to a fixed value by the ESD protection element 16, avoiding jitter of the gate signal on the gate G.

[0020] Traditional ESD protection components are bare dies. Generally, bare dies are not sold individually, but rather as whole wafers. Because wafers are not easy to store, if the bare dies on a wafer are not fully used, the remaining bare dies will be subject to inventory scrapping, leading to increased costs. Figure 1 and Figure 4 The ESD protection component 16 is an SMD packaged component, so it can be purchased according to demand, reducing inventory scrap and lowering costs. Furthermore, not all bare dies on a wafer are tested, which may result in defective dies, whereas every SMD packaged component is tested before shipment, eliminating yield issues.

[0021] In one embodiment, to improve ESD protection capabilities, it is possible to... Figure 1 and Figure 4 An impedance element RH is added between the first terminal 161 of the ESD protection element 16 and the gate terminal 151 of the third type semiconductor power element 15, such as... Figure 5 The equivalent circuit is shown. Figure 5 In this embodiment, the impedance element RH can reduce the current flowing to the gate end 151. The ESD protection element 16 and the impedance element RH serve as an ESD protection assembly.

[0022] Figure 6 This illustrates a third embodiment of the third type of semiconductor packaging structure of the present invention. Figure 6 The third type of semiconductor packaging structure 40 and Figure 1 Similar to the third type semiconductor package structure 10, the difference is that the electrostatic discharge (ESD) protection element 41 in the third type semiconductor package structure 40 is a vertical bare die and is only disposed on the conductive interface 11. The ESD protection element 41 has a first end and a second end located on opposite sides of the ESD protection element, wherein the first end is located at the bottom of the ESD protection element 41 and is directly attached to the conductive interface 11, and the second end is located at the top of the ESD protection element 41 and is electrically connected to the source terminal 152 of the third type semiconductor power element 15 through wire bonding 42, conductive interface 13, wire bonding 19, conductive interface 12 and wire bonding 18.

[0023] Figure 6 The embodiments described herein can be applied to situations where the conductive interface 13 generates heat, resulting in high temperatures. Specifically, assuming the conductive interface 13 is an exposed pad (E-pad), heat may be generated on the conductive interface 13 during operation of the third-type semiconductor package structure 40, leading to a very high temperature at the conductive interface 13. In such cases, if... Figure 1In typical embodiments, the second end 162 of the ESD protection element 16 is directly attached to the conductive interface 13. The characteristics of the ESD protection element 16 may be affected by the temperature of the conductive interface 13. Figure 6 The second end of the ESD protection element 41 is connected to the conductive interface 13 via a bonding wire 42, thus preventing the temperature of the conductive interface 13 from affecting the characteristics of the ESD protection element 41.

[0024] In one embodiment, to improve ESD protection capabilities, it is possible to Figure 6 An impedance element RH is added between the first terminal of the ESD protection element 41 and the gate terminal 151 of the third-class semiconductor power element 15. Please refer to [reference needed]. Figure 5 The equivalent circuit.

[0025] The above description is merely an embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been provided above with embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A third type of semiconductor packaging structure, characterized in that, include: First conductive interface; A second conductive interface; A third type of semiconductor power device has a gate terminal and a source terminal, wherein the gate terminal is electrically connected to the first conductive interface and the source terminal is electrically connected to the second conductive interface. as well as An electrostatic discharge protection element is a surface mount element having a first end and a second end, wherein the first end and the second end are respectively attached to the first conductive interface and the second conductive interface.

2. The third type of semiconductor packaging structure as described in claim 1, characterized in that, The third type of semiconductor package structure is a dual-plane leadless package structure. The third type of semiconductor package structure includes a lead frame, which includes a source pad and a gate pad. The third type of semiconductor power element is disposed on the source pad. The first conductive interface is the gate pad, which is electrically connected to the gate terminal through a first wire bonding. The second conductive interface is the source pad, which is electrically connected to the source terminal through a second wire bonding.

3. The third type of semiconductor packaging structure as described in claim 1, characterized in that, The third type of semiconductor packaging structure is a ball grid array package. The third type of semiconductor packaging structure includes a substrate carrying the third type of semiconductor power device. The substrate has a first conductive pad, a second conductive pad, a third conductive pad, a fourth conductive pad, a first trace, and a second trace. The first conductive interface is the first conductive pad, the second conductive interface is the second conductive pad, the three conductive pads are electrically connected to the gate terminal through a first wire bonding, the fourth conductive pad is electrically connected to the source terminal through a second wire bonding, the first trace connects the first conductive pad and the third conductive pad, and the second trace connects the second conductive pad and the fourth conductive pad.

4. The third type of semiconductor packaging structure as described in claim 1, characterized in that, It also includes an impedance element coupled between the first terminal and the gate terminal.

5. The third type of semiconductor packaging structure as described in claim 1, characterized in that, The electrostatic discharge protection element includes a transient voltage suppression diode.

6. A third type of semiconductor packaging structure, characterized in that, include: A conductive interface; A third type of semiconductor power device has a gate terminal and a source terminal, wherein the gate terminal is electrically connected to the conductive interface via a first wire bonding; and An electrostatic discharge protection element is a bare wafer with a first end and a second end located on opposite sides of the electrostatic discharge protection element, wherein the first end is attached to the conductive interface and the second end is electrically connected to the source terminal through a second bonding wire.

7. The third type of semiconductor packaging structure as described in claim 6, characterized in that, The third type of semiconductor package structure is a DFN package. The third type of semiconductor package structure includes a lead frame, which includes a source pad and a gate pad. The third type of semiconductor power element is disposed on the source pad. The conductive interface is the gate pad. The source terminal is electrically connected to the source pad via a third bonding wire. The second bonding wire connects the second terminal to the source terminal or connects the second terminal to the source pad.

8. The third type of semiconductor packaging structure as described in claim 6, characterized in that, It also includes an impedance element coupled between the first terminal and the gate terminal.

9. The third type of semiconductor packaging structure as described in claim 6, characterized in that, The electrostatic discharge protection element includes a transient voltage suppression diode.

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