System and method for mitigating peak current and improving overall performance

Abstract

A system for performing peak current mitigation in an application programming subsystem (APSS) dynamically performs mitigation based at least in part on a power rail voltage and a leakage current obtained at a start-up time. The voltage and the leakage current obtained at the start-up time are used to estimate a peak current. A mapping generated prior to the start-up time maps the estimated peak current to current limiting levels and specifies different current limiting levels to be performed for different ranges of the estimated peak current. At the start-up time, the mapping is used to map the estimated peak current to a current limiting level to be applied. Where a condition at run time indicates that a peak current is occurring or may occur quickly, the mapped current limit level is applied to mitigate the peak current.

Description

[0001] Related technical descriptions

[0002] Computing devices may include multiple processor-based subsystems. Such computing devices may be, for example, portable computing devices (“PCDs”), such as laptops or handheld computers, cellular phones or smartphones, portable digital assistants, portable game consoles, etc. Other types of PCDs may be included in automotive and Internet of Things (“IoT”) applications.

[0003] Multiple subsystems may be included within the same integrated circuit chip or on different chips. A “system-on-a-chip” or “SoC” is an example of a chip that integrates numerous components to provide system-level functionality. For example, an SoC may include one or more types of processors, such as a central processing unit (“CPU”), a graphics processing unit (“GPU”), a digital signal processor (“DSP”), and a neural processing unit (“NPU”). An SoC may include other subsystems, such as a transceiver or “modem” subsystem providing wireless connectivity, a memory subsystem, etc.

[0004] For example, processors in SoCs such as CPUs, GPUs, and DSPs sometimes experience temperature rises due to external environmental factors and / or internal factors. Current SoCs typically employ one or more temperature sensors that sense temperature and output temperature values. Thermal management circuitry within the SoC processes these temperature values ​​and performs thermal mitigation procedures to alleviate these temperature rises.

[0005] A System-on-a-Chip (SoC) typically has an Application Processor Subsystem (APSS) comprising multiple clusters of application processors. For example, an APSS may include a performance cluster and a power cluster. The performance cluster includes two to four application processors configured for high performance, and the power cluster includes two to four application processors configured for power efficiency. Each processor in the cluster has its own clock. The processors in the performance cluster operate at a higher clock frequency than the processors in the power cluster. The processors in the power cluster are more power-efficient than the processors in the performance cluster. The SoC's CPU may be one of these application processors, or it may be a separate processor.

[0006] One technique used to reduce the cost of a System-on-a-Chip (SoC) is to employ aggressive size optimization for the SoC's power network. One way to achieve this is to have the processors in the power cluster and performance cluster share the same power supply voltage rail of the power network. In such designs, meeting the SoC's power budget or power constraints can be challenging, especially when all cores are active and operating at maximum clock frequency.

[0007] Traditional peak current mitigation solutions negatively impact performance and are not always able to guarantee that power budgets will not be exceeded, especially when multiple processor clusters share the same power supply voltage rail. A peak current mitigation solution is needed that ensures power budget compliance while also reducing the negative performance impact of traditional peak current mitigation solutions. Summary of the Invention

[0008] Systems, methods, and other examples for performing peak current mitigation in the Application Subsystem (APSS) are disclosed.

[0009] Exemplary implementations of a method for performing peak current mitigation in an Application Subsystem (APSS) include:

[0010] At the startup time of the APSS, the voltage and leakage current values ​​of the power rail electrically coupled to the APSS are obtained. These values ​​are used to estimate the peak current range of the APSS, and a pre-configured mapping from the estimated peak current range to the current limiting level is used to map the estimated peak current range to the current limiting level to be executed.

[0011] During the operation of the APSS, if conditions indicate that the APSS is operating at or near peak current, the mapped current limiting level is applied to at least one processor of the APSS.

[0012] Exemplary implementations of an application processing subsystem (APSS) configured to perform peak current mitigation include:

[0013] At least one processor; and

[0014] The APSS controller includes:

[0015] A startup-time voltage and leakage current acquisition logic unit is configured to acquire the voltage and leakage current values ​​of the power rail electrically coupled to the APSS at the startup time of the APSS.

[0016] A startup-time peak current estimation logic unit is configured to estimate the peak current range of the APSS using the voltage and leakage current values ​​obtained at the startup time of the APSS, and to map the estimated peak current range to the current limiting level to be performed using a pre-configured estimated peak current range-to-current-limiting-level mapping; and

[0017] A runtime mitigation logic unit is configured to cause a mapped current limiting level to be applied to at least one processor of the APSS when conditions indicate that the APSS is operating at or near peak current.

[0018] Exemplary embodiments of a non-transient computer-readable medium including computer instructions for execution by an APSS to perform peak current mitigation within that APSS include:

[0019] A first computer instruction set, which is executed at the startup time of the APSS to obtain the voltage and leakage current values ​​of the power rails to which the APSS is electrically coupled;

[0020] A second computer instruction set is used to perform, at the startup time of the APSS, using the obtained voltage and leakage current values ​​to estimate the peak current range of the APSS.

[0021] A third computer instruction set, executed at the startup time of the APSS, is used to map the estimated peak current range to the current limiting level to be executed using a pre-configured estimated peak current range-to-current limiting level mapping; and

[0022] A fourth computer instruction set is used to execute during the runtime of the APSS when conditions indicate that the APSS is operating at or near a peak current, wherein execution of the fourth computer instruction set causes a mapped current limiting level to be applied to at least one processor of the APSS.

[0023] Another exemplary implementation of APSS for performing peak current mitigation includes:

[0024] At least one processor; and

[0025] The APSS controller includes:

[0026] A component used to obtain the voltage and leakage current values ​​of the power rails electrically coupled to the APSS during the startup time of the APSS;

[0027] A component used to estimate the range of peak current values ​​of an APSS by using the voltage and leakage current values ​​obtained at the startup time of the APSS.

[0028] A component used at startup to map the estimated peak current range to the current limiting level to be performed using a pre-configured estimated peak current range-to-current limiting level mapping; and

[0029] A component for causing the mapped current limiting level to be applied to at least one processor of the APSS during runtime when conditions indicate that the APSS is operating at or near peak current.

[0030] These and other features and advantages will become apparent from the following description, drawings and claims. Attached Figure Description

[0031] In the accompanying drawings, unless otherwise indicated, similar reference numerals are used throughout the various views to refer to similar parts. For reference numerals with letter character names, such as "101a" or "101b", the letter character names distinguish two similar parts or elements present in the same figure. When the aim is to have the reference numerals cover all parts with the same reference numerals in all figures, the letter character names of the reference numerals may be omitted.

[0032] Figure 1 This is a block diagram of an Application Subsystem (APSS) according to a representative implementation, which may be embedded in a SoC such as a PCD, but the principles and concepts of the present invention are not limited to the types of devices employing the principles and concepts of the present invention.

[0033] Figure 2 It is based on the representative implementation plan Figure 1 The diagram shown is a block diagram of the APSS controller for APSS.

[0034] Figure 3 yes Figure 1 The graph shown illustrates how the peak current of the APSS varies with the supply voltage and the ratio of the actual leakage current of the APSS to the leakage current obtained by modeling the SoC design in which the APSS is implemented.

[0035] Figure 4 It is for reference. Figure 3 The flowchart describes the process of generating a value stored in LuT and used at runtime to perform peak current mitigation to reduce the peak current value.

[0036] Figure 5 It is based on the representative implementation plan. Figure 1 The flowchart shown illustrates the process executed by the APSS controller, which is used to... (The sentence is incomplete and requires more context to translate accurately.) Figure 3 The described equations are used to estimate the peak current at startup time, to select the current limiting level to be executed during operation based on the peak current estimate, and to execute the selected current limiting level during operation if the operation time conditions indicate that the APSS is operating at or near the peak current or may soon (e.g., within the next few clock cycles).

[0037] Figure 6 It is based on the representative implementation plan. Figure 5 Box 504 represents the flowchart of the process.

[0038] Figure 7 Examples are given based on representative implementation schemes. Figure 2 The block diagram shown is of runtime mitigation execution logic unit 204, which illustrates how the execution peak current estimate is mapped to the current throttling level.

[0039] Figure 8 Examples of PCD are illustrated, including exemplary implementations of systems, methods, computer-readable media, and other examples providing mitigation solutions that can be implemented according to the principles and concepts of the present invention. Detailed Implementation

[0040] Existing peak current mitigation solutions implement mitigation algorithms that attempt to reduce peak current by either frequency-limiting to reduce the processor's operating frequency or by microarchitectural-limiting to reduce the number of instructions the processor executes per clock cycle. However, such solutions are not SoC-specific but rather uniformly configured across the entire total number of SoCs in a particular design or model. These current-limiting solutions are static because they do not dynamically adapt to each specific SoC. Therefore, some SoCs in the total are current-limited even when current limiting is not required, or at least not at the level applied. Such current-limiting solutions adversely affect performance. Consequently, the performance of many SoCs in the total is unnecessarily adversely affected because current limiting is being performed when it is not needed, or because the applied current-limiting level is greater than necessary.

[0041] This disclosure discloses systems and methods for dynamically performing mitigation based at least in part on power rail voltage and leakage current obtained at startup time. The supply voltage and leakage current are used at startup time to estimate peak current. Leakage current is a component of the total current: Total current = Dynamic current (voltage / frequency dependent) + Leakage current. Leakage may vary for each component. Leakage current is the quiescent current flowing in the supply voltage rail when the processors in the cluster are powered on but inactive. Dynamic current depends on the operating voltage, frequency, and a certain amount of activity of one or more processors in the cluster. According to an exemplary embodiment, the leakage current is determined for a specific SoC during an offline bench test method, fused or programmed into the SoC's registers, and read from the registers at startup time. The supply voltage can vary with time and temperature, and is therefore measured or sensed at startup time.

[0042] The mapping generated before startup maps the estimated peak current to current-limiting levels and determines the different current-limiting levels to be applied for different ranges of the estimated peak current. At startup, this mapping is used to map the estimated peak current to the current-limiting levels to be applied. During runtime, if conditions indicate that a peak current is occurring or may occur soon, the mapped current-limiting levels are applied to mitigate that peak current.

[0043] Because the systems and methods according to the principles and concepts of the present invention are applied on a per-part (i.e., per SoC) basis, unnecessary current limiting is avoided, which results in a reduction of the adverse performance impact that current limiting can cause. Furthermore, because mitigation is not performed uniformly across all SoCs in the total number of SoCs manufactured, many SoCs in the total will remain unlimited and therefore will never suffer performance degradation due to current limiting.

[0044] In the following detailed description, exemplary or representative embodiments of the disclosed specific details are set forth for purposes of explanation and not limitation, in order to provide a thorough understanding of embodiments according to this teaching. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” The word “representative” is used herein synonymously with “exemplary.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects. However, it will be apparent to those skilled in the art, who benefit from this disclosure, that other embodiments of the teaching that depart from the specific details disclosed herein remain within the scope of the appended claims. Furthermore, descriptions of well-known apparatuses and methods may be omitted so as not to obscure the description of exemplary embodiments. Such methods and apparatus are clearly within the scope of this teaching.

[0045] The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting. The defined terms are supplementary to their technical and scientific meanings as generally understood and accepted in the technical field of this teaching content.

[0046] Unless the context clearly indicates otherwise, the terms “a,” “an,” and “the” as used in the specification and appended claims include both singular and plural references. Thus, for example, “an apparatus” includes one apparatus and multiple apparatuses.

[0047] Relative terms are used to describe the relationships between individual elements, as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, these relative terms are intended to cover different orientations of the equipment and / or elements.

[0048] It should be understood that when an element is described as being "connected to," "coupled to," or "electrically coupled to" another element, the element may be directly connected or coupled, or there may be intermediate elements present.

[0049] As used herein, the terms "memory" or "memory device" are intended to refer to a non-transitory, computer-readable storage medium capable of storing computer instructions or computer code for execution by one or more processors. References to "memory" or "memory device" herein should be interpreted as one or more memories or memory devices. For example, memory may refer to multiple memories within the same computer system. Memory may also refer to multiple memories distributed across multiple computer systems or computing devices.

[0050] As used herein, the term "processor" encompasses any electronic component capable of executing computer programs or computer instructions. References to systems including "processor" herein should be interpreted as referring to one or more processors. A processor may be, for example, a multi-core processor comprising multiple processing cores, each of which may include multiple processing stages in a processing pipeline. A processor may also refer to a collection of processors within a single computer system or distributed across multiple computer systems.

[0051] As used herein, the term "controller" encompasses electronic components capable of executing computer programs or executable computer instructions to perform specific tasks, as well as hardware components including one or more state machines having combinational logic configured to perform certain tasks. For example, a controller may be a processor such as a microprocessor, or some other type of processor such as a DSP. References to "controller" herein should be interpreted as one or more controllers.

[0052] Computing devices may include multiple subsystems, cores, or other components. Such computing devices may be, for example, PCDs, such as laptops or handheld computers, cellular or smartphones, portable digital assistants, portable game consoles, automotive safety systems for autonomous vehicles, server chips, etc.

[0053] Figure 1 This is a block diagram of an Application Subsystem for Security (APSS) 100 according to a representative embodiment. The APSS can be embedded in a SoC such as a PCD, but the principles and concepts of the invention are not limited to the type of device employing them. According to this representative embodiment, system 100 includes N processor clusters 1011-101 N Each of these processor clusters comprises M processors, 1021-102 M And APSS controller 110, where N is a positive integer greater than or equal to 2 and M is a positive integer greater than or equal to 1. APSS controller 110 is configured to send signals to clusters 1011-101. N Processor 1021-102 M Output control signal 1111-111 RThe control signal causes an adaptive peak current mitigation process to be executed. This adaptive peak current mitigation process is customized for the SoC and adapts to conditions that occur during startup and runtime, where R equals M x N.

[0054] Figure 2 It is based on the representative implementation plan Figure 1 The diagram shows the block diagram of the APSS controller 110 of the APSS100. When the SoC including the controller 110 boots up, the startup time voltage and leakage current of the controller 110 are read, measured, calculated, or otherwise obtained by the logic unit 201, which obtains clusters 1011-101. N The values ​​of the supply voltage and leakage current of the electrically coupled shared supply voltage rail (not shown). These values ​​are used by the startup-time peak current estimation logic unit 202 of the APSS controller 110 to estimate the range of peak current values. The term "peak current" as used herein refers to "total current" in the above equation, and is specific to the APSS 100 and clusters 1011-101. N The current flowing in the electrically coupled power rails, where all clusters 1011-101 N All processors 1021-102 M They are active and operate at their maximum clock frequency.

[0055] The startup-time peak current range estimation logic unit 202 derives the estimated peak current range to the runtime mitigation logic unit 205. The runtime mitigation enable logic unit 203 of the runtime mitigation logic unit 205 includes a pre-configured mapping of the estimated peak current range to values ​​of different current limiting levels, preferably implemented as a lookup table (LuT) in the logic unit 203. This mapping is used to map the derived estimated peak current range to the current limiting level to be executed. The runtime mitigation enable logic unit 203 uses this mapping to select the current limiting level to be executed to reduce the peak current, and then notifies the runtime mitigation execution logic unit 204 of the current limiting level to be executed when the peak current is occurring or may occur. This level range may include the lowest level that is kept disabled by both the runtime mitigation enable logic unit 203 and the runtime mitigation execution logic unit 204 because current limiting is not required, and intermediate and / or higher current limiting levels corresponding to at least one current limiting level executed to reduce the peak current, as will now be referenced. Figure 3 As described.

[0056] Figure 3This is graph 300, which shows the peak current of the SoC's APSS100 as a function of supply voltage and the ratio of the actual leakage current of the APSS100 to the leakage current obtained by modeling the SoC design. The data used in graph 300 was obtained through post-production collection and analysis of data from multiple SoCs produced from the same production batch or lot. By process-leveling this data, three mathematical equations were obtained, representing the relationship between supply voltage, leakage current ratio, and peak current. These equations represent the conditions that allow graph 300 to be distinguished from each other in four distinct regions: the region below line 301, the region between lines 301 and 302, the region between lines 302 and 303, and the region above line 303.

[0057]

[0058] Where k1, k2, and k3 are constants, and APSS_Voltage is the cluster size 1011-101. N The supply voltage of the power grid rail electrically coupled to the APSS controller 110, Part leakage is the actual leakage current of the power grid, Design leakage estimate is the leakage current of the power grid estimated using the SoC design model, TH1, TH2 and TH3 are the first threshold (TH) value, the second TH value and the third TH value, respectively, and TH1 <TH2<TH3。

[0059] For the data used to generate graph 300, Equations 1 and 3, corresponding to lines 301 and 303 in graph 300, are given as APSS(Volts) + 0.62x = 1.0147 and APSS(Volts) + 0.60x = 1.086, respectively. Therefore, in this example, k1 = 0.62, k3 = 0.60, TH1 = 1.0147, and TH3 = 1.086. The TH values ​​are chosen based on the power budget or power network constraints to which the APSS100 is electrically coupled and based on current limiting levels considered to be guaranteed for peak current values ​​across different ranges. Therefore, the TH values ​​and constant k used in the equations will depend on the specific SoC design. For this example, it is determined that: (1) if the peak current is less than 9.0A, no current limiting is required; (2) if the peak current is greater than or equal to 9.0A and less than 9.5A, approximately 10% current limiting is required; (3) if the peak current is greater than or equal to 9.5A and less than 10.0A, approximately 15% to 20% current limiting is required; and (4) if the peak current is greater than or equal to 10.0A, approximately 20% to 25% current limiting is required. The corresponding TH values ​​of 1.0147 and 1.086 for TH1 and TH3, as well as the constants k1 and k3, are selected based on the data used to generate graph 300. Although Equation 2 is not shown in graph 300 for ease of illustration and discussion, the values ​​of k2 and TH2 are selected in the same manner.

[0060] For the example total amount of data collected and analyzed by the SoC used to generate graph 300, a 10% current limit results in a reduction of approximately 5% in peak current, a 15% to 20% current limit results in a reduction of approximately 10% in peak current, and a 20% to 25% current limit results in a reduction of approximately 15% in peak current. In this context, the percentage of current limit being performed (e.g., 10%) means that (1) frequency current limiting is being used to reduce the processor's operating frequency by that percentage (e.g., reducing the operating frequency by 10%), or (2) microarchitecture current limiting is being used to reduce the number of instructions being executed by the processor's cores during one clock cycle or a series of clock cycles by that percentage (e.g., by inserting idle instructions into the processing pipeline, 10% fewer instructions are being executed). In most cases, microarchitecture current limiting will be used without frequency current limiting because using microarchitecture current limiting can achieve a faster response time than using frequency current limiting.

[0061] It should be noted that the number of equations used to distinguish different regions of curve 300 can be any number greater than or equal to one. The greater the number of equations used for this purpose, the larger the granularity of the current limiting level adopted, which results in a larger granularity of the peak current reduction level.

[0062] Once based on the above reference Figure 3The described method determines the above equations and the corresponding TH and k values, which are stored in the memory device of the APSS controller 110, or in a memory device external to the APSS controller 110 but accessible by the APSS controller. See again... Figure 2 When APSS100 is started, the startup time voltage and leakage current acquisition logic unit 201 obtains the supply voltage value and leakage current value. Then, the startup time peak current estimation logic unit 202 uses the voltage value and leakage current value in combination with the TH and k values ​​stored in memory from Equations 1-3 or similar sets of equations obtained in the same or similar manner to estimate the range of peak current values.

[0063] For example, for ease of discussion, assume only Equations 1 and 3 are used, and using the values ​​of k1 = 0.62, k3 = 0.60, TH1 = 1.0147, and TH3 = 1.086, logic unit 202 determines whether the sum on the left side of Equation 1 is less than 1.0147. If so, logic unit 202 estimates the peak current to be less than 9.0A, and therefore logic unit 202 does not enable runtime mitigation enabling logic unit 203. Preferably, the default state of runtime mitigation enabling logic unit 203 and runtime mitigation execution logic unit 204 is disabled, wherein current limiting is not performed during runtime.

[0064] If startup-time current estimation logic unit 202 determines that the sum on the left side of Equation 1 is not less than TH1 = 1.0147, then logic unit 202 determines whether the sum on the left side of Equation 3 is less than TH3 = 1.086. If not, logic unit 202 estimates the peak current value to be greater than 10.0A. Then, logic unit 202 activates runtime mitigation activation logic unit 203, which in turn activates runtime mitigation execution logic unit 204 and notifies it that a 20% to 25% current limit is required during runtime to adequately reduce the peak current. During runtime, runtime mitigation execution logic unit 204 determines whether certain conditions indicate that current limiting is guaranteed, and if so, causes the 20% to 25% current limit to be executed. These "certain conditions" are referenced below. Figure 6 To describe in more detail.

[0065] If logic unit 202 determines that the sum on the left side of Equation 1 is not less than TH1 = 1.0147 and the sum on the left side of Equation 3 is less than TH3 = 1.086, then the startup time current estimation logic unit 202 estimates the peak current value to be somewhere between 9A and 10A, and activates runtime mitigation activation logic unit 203, which in turn activates runtime mitigation execution logic unit 204 and instructs it to perform a 10% to 20% current limit. Runtime mitigation execution logic unit 204 determines whether certain conditions indicate that current limiting is guaranteed, and if so, causes the 10% to 20% current limit to be executed.

[0066] According to an exemplary implementation, for example, logic component blocks 201-204 are implemented in hardware, such as as one or more state machines. However, it should be noted that... Figure 2 The logic components shown can be implemented in hardware, software, firmware, or any combination thereof.

[0067] As described above, preferably, the LuT will be used to map the peak current estimation range to the current limiting level to be executed during runtime. For example, the result of Equation 1 is used to generate an address in the LuT where the corresponding current limiting level to be executed is stored. In other words, if the sum of the left side of Equation 1 is less than TH1, the corresponding address in the LuT will contain a value indicating that no current limiting will be executed, while if the sum of the left side of Equation 1 is greater than or equal to TH1, the corresponding address in the LuT will contain a value indicating that a specific current limiting level or range of current limiting levels will be executed.

[0068] Figure 4 The above is a reference. Figure 3 The flowchart describes a process 400 that generates data stored in the LuT and will be used at runtime to perform peak current mitigation to reduce the peak current value. Process 400 is a post-production process that is performed offline and may be, for example, cloud-based analytics. Box 401 represents the process of post-production collection and analysis of aggregate data on the distribution of voltage and leakage current values ​​of multiple SoCs having the same design and preferably produced from the same production batch or lot. Box 402 represents the use of this aggregate data to obtain the above reference. Figure 3The described type describes a hierarchical process using one or more mathematical equations to estimate the range of peak current values ​​at startup. Box 403 represents the process of constructing a LuT with a stored address, based on the result of executing one or more equations (i.e., based on different estimates of the range of peak current values ​​made at startup), at which different current limiting levels to be executed are stored. Essentially, at runtime, the address of the LuT is generated using the result of one or more equations produced at startup, from which different values ​​corresponding to different current limiting levels are retrieved. For example, if the result of equations 1 and 2 is that the peak current is estimated to be between 9.0A and 9.5A, this results in the generation of a specific address used at runtime to address the LuT to retrieve the associated current limiting level. If runtime conditions indicate that the APSS100 is operating at peak current or may soon (e.g., within the next few clock cycles), the current limiting level retrieved from the LuT is executed, as will be referred to below. Figure 6 A more detailed description.

[0069] Figure 5 This is a flowchart of process 500 executed by APSS controller 110 according to a representative implementation scheme, which is used for... (referring to the above) Figure 3 The described equations are used to estimate the peak current at startup, to select the current limiting level to be executed during operation based on the peak current estimate, and to execute the selected current limiting level during operation if the operation time conditions indicate that the APSS100 is operating at or near the peak current or may soon (e.g., within the next few clock cycles) operate at the peak current. Box 501 represents the equations provided by... Figure 2 The startup-time voltage and leakage current acquisition logic unit 201 performs the process of acquiring the supply voltage value and leakage current value at startup time. As indicated above, the leakage current can be obtained at startup time by reading a register value in which the leakage current value has been fused or programmed, while the supply voltage is typically measured or sensed at startup time. It should be noted that the process of acquiring the leakage current does not require the use of a current sensor, and the principles and concepts of the present invention can be implemented in a SoC that does not include current sensors, which increase cost and utilize additional area of ​​the SoC.

[0070] Box 502 indicates that by Figure 2 The startup peak time current estimation logic unit 202 performs a process that uses the values ​​obtained at startup time in the equations (e.g., equations 1-3) discussed above to determine the peak current range at startup time as shown in curve 300 by comparing the sum on the left side of the equation with the corresponding TH value. Figure 3 Which region of ) is used to generate the range of estimated peak current values.

[0071] Box 503 represents the process of deriving the estimated peak current range to runtime mitigation logic unit 205. Box 504 represents the process performed by runtime mitigation execution logic unit 204, which, upon determining whether a runtime condition indicates that a peak current may be occurring or will occur, performs a selected current limiting level to reduce the peak current by mapping the result of the equation to a pre-selected current limiting level contained in the LuT using the aforementioned LuT. The process represented by box 504 can be repeated until APSS100 is shut down or restarted.

[0072] Figure 6 It is based on the representative implementation plan. Figure 5 Box 504 represents the flowchart of the process. When Figure 2 Runtime mitigation enabled by logic unit 203 Figure 2 When the runtime mitigation execution logic unit 204 is executed, logic unit 204 determines whether the runtime conditions indicate that APSS 100 is operating at or near the peak frequency or may soon (e.g., within a few clock cycles) begin operating at the peak frequency, as shown in box 601. If not, the process indicated by box 601 may be repeated until a determination is made at box 601 that the conditions have been met or until APSS 100 is shut down or restarted. The conditions that should be met when moving from box 601 to box 602 are typically: (1) all clusters 1011-101 N All processors 1021-102 M All cores are active; (2) All clusters 1011-101 N All processors 1021-102 M Both are operating at their maximum clock frequency; and (3) junction temperature T J greater than a certain temperature TH value Temp (e.g., 85℃). Junction temperature TJ is typically in the cluster range of 1011-101. N Cluster processor 1021-102 M The information is sensed at or near one or more cluster processors. The principles and concepts of the present invention are not limited to the requirement that all of these conditions (1)-(3) must always be met before mitigation steps are taken, but mitigation is generally not required unless all of these conditions are met.

[0073] When the process moves from box 601 to box 602 Figure 2 The runtime mitigation logic unit 205 maps the peak current value range to the corresponding current limiting level and executes the current limiting level to reduce the peak current.

[0074] As indicated above, existing current limiting methods for reducing peak current include frequency current limiting to reduce the operating frequency of the processor, or microarchitectural current limiting to reduce the number of instructions executed by one or more processors in the processor per clock cycle. Any other current limiting techniques suitable for power management may also be used for this purpose. Any current limiting technique may be used alone or in combination with one or more other current limiting techniques.

[0075] One advantage of the systems and methods disclosed herein is that the current limiting is specific to that part (i.e., specific SoC), because the applied current limiting level is largely based on the voltage and leakage current values ​​obtained when the specific SoC is started up. This contrasts with existing methods that use maximum power mitigation mechanisms (MPMMs) that perform static current limiting (i.e., using the same TH value to apply the same current limiting level to all SoCs of the same design). Such mitigation solutions typically result in a 3% to 5% adverse impact on performance across 100% of the SoCs of a particular design or model.

[0076] Because the method of this disclosure selects the current limiting level based at least in part on the estimated peak current obtained at startup based on the voltage and leakage current values, the applied current limiting level is more appropriate. This leads to performance improvements because the adverse effects of current limiting on performance are smaller. (Referring to the above references) Figure 3 For the example SoCs under discussion, a 0% performance impact was observed for peak current values ​​ranging from less than 9.0A to up to 9.5A; a relatively small performance impact of less than 1% was observed for peak current values ​​ranging from 9.5A to 10.0A; and a relatively small performance impact of 1% to 1.5% was observed for peak current values ​​ranging from 10.0A to 10.5A. Therefore, in all cases, the performance impact is very small and affects only a very small number of SoCs. A large number of SoCs will have unlimited current performance because the runtime mitigation enable logic 203 will remain disabled in those SoCs. Another benefit is the reduced cost per unit of the SoC because a current sensor is not required to measure the peak current.

[0077] A post-production process can be performed to fine-tune the current-limiting level value stored in the LuT. The LuT, typically located within the APSS controller 110, can be updated at any time using firmware running on the APSS controller 110. A peak current measurement of the peak current flowing in the power rails can be performed and compared to an estimated peak current range to correlate the estimate with the measured value. If the estimate does not correlate well with the measurement, the LuT value can be adjusted until the aforementioned equation produces the same result for both the measured and estimated peak current ranges. This post-production process may also include analyzing the relationship between peak current mitigation and performance to determine the impact on overall performance, stability, and start-up time key performance indicators (KPIs). Based on this analysis, the LuT value can also be fine-tuned.

[0078] Figure 7 Examples are given based on representative implementation schemes. Figure 2 The block diagram shown for runtime mitigation execution logic unit 204 illustrates how peak current estimate ranges are mapped to current limiting levels. Peak current estimates, performed using equations similar to Equations 1-3, are received by LuT logic unit 700, where P is a positive integer greater than or equal to one and typically greater than or equal to two. The larger the value of P, the greater the number of current limiting levels available for different peak current estimates. LuT address generation logic unit 701 of LuT logic unit 700 converts each peak current range estimate into a corresponding LuT address, which is then received by LuT 702. LuT 702 outputs the corresponding current limiting level stored at the received LuT address. This current limiting level is received by current limiting control signal generation logic unit 703, which generates... Figure 1 The corresponding control signal shown is 1111-111 R These control signals are delivered to cluster 1011-101 N Cluster processor 1021-102 M This causes them to perform rate limiting at the corresponding rate limiting level.

[0079] For example, suppose Equations 1-3 are used to estimate the peak current range as (1) 0 to 9.0 mA, (2) greater than 9.0 mA but less than 9.5 mA, (3) greater than 9.5 mA but less than 10.0 mA, or (4) greater than 10.0 mA. The LuT address generation logic unit 701 can convert range (1) to address 0,0 in LuT 702, range (2) to address 0,1 in LuT 702, range (3) to address 1,0 in LuT 702, and range (4) to address 1,1 in LuT 702. Each of these addresses will contain a value corresponding to the current limiting level to be used for each corresponding estimated peak current range.

[0080] Figure 8 Examples of the PCD 800 are illustrated, such as mobile phones, smartphones, portable game consoles (such as extended reality (XR) devices, virtual reality (VR) devices, augmented reality (AR) devices, or mixed reality (MR) devices), autonomous driving systems for automobiles, server chips, etc., in which exemplary embodiments of systems, methods, computer-readable media, and other examples of mitigation solutions provided according to the principles and concepts of the invention are shown. For clarity, Figure 8 Some interconnects, signals, etc. are not shown.

[0081] PCD 800 may include SoC 802. SoC 802 may include CPU 804, NPU 805, GPU 806, DSP 807, analog signal processor 808, modem / modem subsystem 854, or other processors. CPU 804 may include one or more CPU cores, such as a first CPU core 8041, a second CPU core 8042, and so on up to the Mth CPU core 804. M . Figure 1 The APSS 110 and processor cluster 101a-101N shown are in Figure 8 It is shown separately from CPU 804, but CPU 804 can be processor cluster 1011-101. N The processor is located in a processor cluster. Furthermore, the APSS controller 110 may include logic components implemented in, for example, a CPU 804, NPU 805, GPU 806, or DSP 807.

[0082] Display controller 809 and touchscreen controller 812 may be coupled to CPU 804. A touchscreen display 814 external to SoC 802 may be coupled to display controller 810 and touchscreen controller 812. PCD 800 may also include a video decoder 816 coupled to CPU 804. A video amplifier 818 may be coupled to video decoder 816 and touchscreen display 814. A video port 820 may be coupled to video amplifier 818. A Universal Serial Bus (“USB”) controller 822 may also be coupled to CPU 804, and a USB port 824 may be coupled to USB controller 822. A Subscriber Identity Module (“SIM”) card 826 may also be coupled to CPU 804.

[0083] One or more memory modules 828 may be coupled to the CPU 804 and the APSS controller 110. The one or more memory modules 804 may include both volatile and non-volatile memory. Examples of volatile memory include static random access memory (“SRAM”) and dynamic random access memory (“DRAM”). Such memory may be external to or internal to the SoC 802. The one or more memory modules 828 may include local cache memory such as Level 1 (L1)–Level 3 (L3) cache memory, and / or system-level cache memory such as Last Level Cache (LLC) memory.

[0084] A stereo audio CODEC 834 may be coupled to an analog signal processor 808. Additionally, an audio amplifier 836 may be coupled to the stereo audio CODEC 834. A first stereo speaker 838 and a second stereo speaker 840 may be coupled to the audio amplifier 836, respectively. Furthermore, a microphone amplifier 842 may be coupled to the stereo audio CODEC 834, and a microphone 844 may be coupled to the microphone amplifier 842. An FM radio tuner 846 may be coupled to the stereo audio CODEC 834. An FM antenna 848 may be coupled to the FM radio tuner 846. Additionally, a stereo headset 850 may be coupled to the stereo audio CODEC 834. Examples of other devices that may be coupled to the CPU 804 include one or more digital (e.g., CCD or CMOS) cameras 852.

[0085] A modem or RF transceiver 854 may be coupled to an analog signal processor 808 and a CPU 804. An RF switch 856 may be coupled to an RF transceiver 854 and an RF antenna 858. Additionally, a keypad 860 and a mono headset with a microphone 862 may be coupled to the analog signal processor 808. The SoC 802 may have one or more internal or on-chip thermal sensors 870. A power source 874 and a PMIC 876 may supply power to the SoC 802.

[0086] Firmware or software for performing the methods described above may be stored in any of the memories described above, or in local memory that can be directly accessed by the APSS controller 110. Execution of such firmware or software can control aspects of any of the methods described above or configure aspects of any of the systems described above. Any such memory or other non-transitory storage medium having firmware or software stored therein in a computer-readable form for execution by processor hardware is an example of a "computer-readable medium," as understood in the patent dictionary.

[0087] Specific implementation examples are described in the following numbered clauses.

[0088] 1. A method for performing peak current mitigation in an application subsystem (APSS), the method comprising:

[0089] At the startup time of the APSS, the voltage and leakage current values ​​of the power rail electrically coupled to the APSS are obtained. The obtained voltage and leakage current values ​​are used to estimate the peak current value of the APSS, and a pre-configured estimated peak current range-to-current-limiting-level mapping is used to map the estimated peak current range to the current-limiting level to be executed; and

[0090] During the operation of the APSS, if conditions indicate that the APSS is operating at or near peak current, the mapped current limiting level is applied to at least one processor of the APSS.

[0091] 2. The method according to Clause 1, wherein the APSS comprises multiple clusters of processors, each cluster comprising multiple processors.

[0092] processor, and the method further includes:

[0093] During the operation of the APSS, if conditions indicate that the APSS is operating at or near peak current, the mapped current limiting level is applied to all processors of the APSS.

[0094] 3. The method according to any one of Clauses 1 and 2, wherein the mapped current limiting level is applied by performing at least one of the following: (1) reducing the operating frequency of the at least one processor; and (2) reducing the number of instructions executed by the at least one processor during a clock cycle of the at least one processor or during a clock cycle sequence of the at least one processor.

[0095] 4. The method according to any one of clauses 1 to 3, wherein the pre-configured estimated peak current range to current limiting level mapping is implemented in a LuT logic unit including a lookup table (LuT) address generation logic unit and a LuT, the LuT address generation logic unit being configured to convert the estimated peak current range into a memory address in the LuT having a plurality of memory addresses, each memory address having a corresponding current limiting level stored therein, each corresponding current limiting level corresponding to a corresponding estimated peak current range or an estimated range of peak current values.

[0096] 5. The method according to any one of Clauses 1 to 4, wherein the conditions include at least one of the following: (1) each processor is operating at a maximum clock frequency; (2) each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

[0097] 6. The method according to clauses 1 to 4, wherein the conditions include: (1) each processor is operating at a maximum clock frequency; (2) each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

[0098] 7. An application processing subsystem (APSS) configured to perform peak current mitigation, the APSS comprising:

[0099] At least one processor; and

[0100] APSS controller, the APSS controller comprising:

[0101] A startup time voltage and leakage current acquisition logic unit is configured to acquire the voltage and leakage current values ​​of the power rail electrically coupled to the APSS at the startup time of the APSS.

[0102] A startup-time peak current estimation logic unit is configured to estimate the peak current range of the APSS using voltage and leakage current values ​​obtained at the startup time of the APSS, and to map the estimated peak current range to a current limiting level to be performed using a pre-configured estimated peak current range-to-current-limiting-level mapping; and

[0103] A runtime mitigation logic unit is configured to cause a mapped current limiting level to be applied to the at least one processor of the APSS when a condition indicates that the APSS is operating at or near a peak current.

[0104] 8. The APSS as described in Clause 7, wherein the at least one processor comprises a plurality of clusters of processors, each cluster comprising a plurality of processors, and wherein the runtime mitigation logic is configured to cause a mapped current limiting level to be applied to all said processors of the APSS when a condition indicates that the APSS is operating at or near a peak current.

[0105] 9. The APSS according to any one of Clauses 7 to 8, wherein the mapped current limiting level is applied by performing at least one of the following: (1) reducing the operating frequency of the at least one processor; and (2) reducing the number of instructions executed by the at least one processor during a clock cycle of the at least one processor or during a clock cycle sequence of the at least one processor.

[0106] 10. The APSS according to any one of clauses 7 to 9, wherein the startup time peak estimation logic unit includes a lookup table (LuT) logic unit pre-configured to implement a mapping of the estimated peak current value range to a current limiting level, the LuT logic unit including a LuT address generation logic unit and a LuT, the LuT address generation logic unit being configured to convert the estimated peak current value range into a memory address in the LuT, the LuT having a plurality of memory addresses, each memory address having a corresponding current limiting level stored therein, each corresponding current limiting level corresponding to a corresponding estimated peak current value range.

[0107] 11. An APSS according to any one of Clauses 7 to 10, wherein the condition includes at least one of the following: (1) each processor is operating at its maximum clock frequency; (2) each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

[0108] 12. An APSS according to any one of Clauses 7 to 10, wherein the conditions include: (1) each processor is operating at a maximum clock frequency; (2) each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

[0109] 13. The APSS according to any one of Clauses 7 to 12, wherein the APSS is implemented in a system-on-chip (SoC) integrated circuit (IC) package.

[0110] 14. The APSS as described in Clause 13, wherein the SoC IC is implemented in a portable computing device (PCD).

[0111] 15. A non-transitory computer-readable medium comprising computer instructions executable by an application subsystem (APSS) to perform peak current mitigation within the APSS, the computer instructions...

[0112] include:

[0113] A first computer instruction set, the first computer instruction set being used to execute at the startup time of the APSS to

[0114] Used to obtain the voltage and leakage current values ​​of the power rail to which the APSS is electrically coupled;

[0115] A second computer instruction set, the second computer instruction set being used at the startup time of the APSS.

[0116] The obtained voltage and leakage current values ​​are used to estimate the peak current range of the APSS;

[0117] A third computer instruction set, executed at the startup time of the APSS, is used to map the estimated peak current range using a pre-configured estimated peak current range-to-current-limiting-level mapping.

[0118] To the required rate limiting level; and

[0119] A fourth computer instruction set is configured to execute during the runtime of the APSS when conditions indicate that the APSS is operating at or near a peak current, wherein execution of the fourth computer instruction set causes a mapped current limiting level to be applied to at least one processor of the APSS.

[0120] 16. The non-transitory computer-readable medium according to Clause 15, wherein the APSS comprises a plurality of clusters of processors, each cluster comprising a plurality of processors, and wherein the fourth computer instruction set comprises computer instructions for execution at runtime when conditions indicate that the APSS is operating at or near a peak current.

[0121] The computer instructions cause the mapped rate limiting level to be applied to all processors of the APSS.

[0122] 17. A nontransitory computer-readable medium according to any one of Clauses 15 to 16, wherein the fourth computer instruction set causes the mapped rate limiting level to be applied by performing at least one of the following: (1) reducing the operating frequency of the at least one processor; and (2) reducing the number of instructions executed by the at least one processor during a clock cycle of the at least one processor or during a clock cycle sequence of the at least one processor.

[0123] 18. The non-transitory computer-readable medium according to claims 15 to 17, wherein the pre-configured estimated peak current range to current limiting level mapping is implemented in a LuT logic unit including a lookup table (LuT) address generation logic unit and a LuT, the LuT address generation logic unit being configured to translate the estimated peak current range into a memory address in the LuT having a plurality of memory addresses, each memory address having a corresponding current limiting level stored therein, each corresponding current limiting level corresponding to a corresponding estimated peak current range.

[0124] 19. A nontransitory computer-readable medium according to any one of clauses 15 to 18, wherein the condition includes at least one of the following: (1) each processor is operating at a maximum clock frequency; (2) each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a preselected junction temperature threshold.

[0125] 20. A nontransitory computer-readable medium according to any one of clauses 15 to 18, wherein the conditions include: (1) each processor is operating at a maximum clock frequency; (2) each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a preselected junction temperature threshold.

[0126] 21. The non-transitory computer-readable medium according to clauses 15 to 20, wherein the non-transitory computer-readable medium includes a memory device in a system-on-chip (SoC) integrated circuit (IC) package, the memory device being either inside the APSS or outside the APSS and accessible by the APSS.

[0127] 22. The non-transitory computer-readable medium as described in Clause 21, wherein the SoC IC package is used in a portable computing device (PCD).

[0128] 23. An application subsystem (APSS) for performing peak current mitigation, the APSS comprising:

[0129] At least one processor; and

[0130] APSS controller, the APSS controller comprising:

[0131] A component used to obtain the voltage and leakage current values ​​of the power rail to which the APSS is electrically coupled at the start-up time of the APSS;

[0132] A component for estimating the range of peak current values ​​of the APSS using the voltage and leakage current values ​​obtained at the startup time of the APSS;

[0133] A component used at startup to map the estimated peak current range to the current limiting level to be performed using a pre-configured estimated peak current range-to-current limiting level mapping; and

[0134] A component for causing the mapped current limiting level to be applied to at least one processor of the APSS during runtime when conditions indicate that the APSS is operating at or near peak current.

[0135] 24. The APSS as described in Clause 23, wherein the at least one processor comprises a plurality of clusters of processors, each cluster comprising a plurality of processors, and wherein the component for causing the APSS to operate under conditions indicating that the APSS is at peak current or peak...

[0136] When operating near the current value, the mapped current limiting level is applied to all processors of the APSS.

[0137] 25. The APSS according to any one of Clauses 23 to 24, wherein the mapped current limiting level is applied by performing at least one of the following: (1) reducing the operating frequency of the at least one processor; and (2) reducing the number of instructions executed by the at least one processor during a clock cycle of the at least one processor or during a clock cycle sequence of the at least one processor.

[0138] 26. The APSS according to any one of clauses 23 to 25, wherein the pre-configured estimated peak current range to current limiting level mapping is implemented using a LuT logic unit including a lookup table (LuT) address generation logic unit and a LuT, the LuT address generation logic unit being configured to convert the estimated peak current range into a memory address in the LuT having a plurality of memory addresses, each memory address having a corresponding current limiting level stored therein, each corresponding current limiting level corresponding to a corresponding estimated peak current range.

[0139] 27. An APSS according to any one of clauses 23 to 26, wherein the condition includes at least one of the following: (1) each processor is operating at a maximum clock frequency; (2) each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

[0140] 28. An APSS according to any one of clauses 23 to 26, wherein the conditions include: (1) each processor is operating at a maximum clock frequency; (2) each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

[0141] 29. The APSS according to any one of Clauses 23 to 28, wherein the APSS is implemented in a system-on-chip (SoC) integrated circuit (IC) package.

[0142] 30. The APSS as described in Clause 29, wherein the SoC IC is implemented in a portable computing device (PCD).

[0143] Alternative embodiments will become apparent to those skilled in the art to which this invention pertains. Therefore, although alternative aspects have been illustrated and described in detail, it should be understood that various substitutions and changes may be made therein.

Claims

1. A method for performing peak current mitigation in an application subsystem (APSS), the method comprising: At the startup time of the APSS, the voltage and leakage current values ​​of the power rail to which the APSS is electrically coupled are obtained. The obtained voltage and leakage current values ​​are used to estimate the peak current range of the APSS, and a pre-configured estimated peak current range to current limiting level mapping is used to map the estimated peak current range to the current limiting level to be performed. as well as During the operation of the APSS, if conditions indicate that the APSS is operating at or near peak current, the mapped current limiting level is applied to at least one processor of the APSS.

2. The method of claim 1, wherein the APSS comprises multiple clusters of processors, each cluster comprising multiple processors, and wherein the method further comprises: During the operation of the APSS, if conditions indicate that the APSS is operating at or near peak current, the mapped current limiting level is applied to all processors of the APSS.

3. The method of claim 1, wherein the mapped current limiting level is applied by performing at least one of the following: (1) reducing the operating frequency of the at least one processor; and (2) reducing the number of instructions executed by the at least one processor during a clock cycle of the at least one processor or during a clock cycle sequence of the at least one processor.

4. The method of claim 1, wherein the pre-configured estimated peak current range to current limiting level mapping is implemented in a LuT logic unit including a lookup table (LuT) address generation logic unit and a LuT, the LuT address generation logic unit being configured to convert the estimated peak current range into a memory address in the LuT having a plurality of memory addresses, each memory address having a corresponding current limiting level stored therein, each corresponding current limiting level corresponding to a corresponding estimated peak current range.

5. The method of claim 2, wherein the condition includes at least one of the following: (1) each processor is operating at a maximum clock frequency; (2) each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

6. The method of claim 2, wherein the conditions include: (1) Each processor is operating at its maximum clock frequency; (2) Each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

7. An application processing subsystem (APSS) configured to perform peak current mitigation, the APSS comprising: At least one processor; and APSS controller, the APSS controller comprising: A startup time voltage and leakage current acquisition logic unit is configured to acquire the voltage and leakage current values ​​of the power rail electrically coupled to the APSS at the startup time of the APSS. A startup-time peak current estimation logic unit is configured to estimate the peak current range of the APSS using voltage and leakage current values ​​obtained at the startup time of the APSS, and to map the estimated peak current range to a current limiting level to be performed using a pre-configured estimated peak current range-to-current-limiting-level mapping; and A runtime mitigation logic unit is configured to cause a mapped current limiting level to be applied to the at least one processor of the APSS when a condition indicates that the APSS is operating at or near a peak current.

8. The APSS of claim 7, wherein the at least one processor comprises a plurality of clusters of processors, each cluster comprising a plurality of processors, and wherein the runtime mitigation logic is configured to cause a mapped current limiting level to be applied to all of the processors of the APSS when a condition indicates that the APSS is operating at or near a peak current.

9. The APSS of claim 7, wherein the mapped rate limiting level is applied by performing at least one of the following: (1) reducing the operating frequency of the at least one processor; and (2) reducing the number of instructions executed by the at least one processor during a clock cycle of the at least one processor or during a clock cycle sequence of the at least one processor.

10. The APSS of claim 7, wherein the startup time peak estimation logic unit includes a lookup table (LuT) logic unit pre-configured to implement a mapping of the estimated peak current range to current limiting levels, the LuT logic unit including a LuT address generation logic unit and a LuT, the LuT address generation logic unit being configured to convert the estimated peak current range into memory addresses in the LuT, the LuT having a plurality of memory addresses, each memory address having a corresponding current limiting level stored therein, each corresponding current limiting level corresponding to a corresponding estimated peak current range.

11. The APSS of claim 8, wherein the condition includes at least one of the following: (1) each processor is operating at a maximum clock frequency; (2) each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

12. The APSS of claim 8, wherein the conditions include: (1) Each processor is operating at its maximum clock frequency; (2) Each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

13. The APSS of claim 7, wherein the APSS is implemented in a system-on-chip (SoC) integrated circuit (IC) package.

14. The APSS of claim 13, wherein the SoCIC is implemented in a portable computing device (PCD).

15. A non-transitory computer-readable medium comprising computer instructions executable by an application subsystem (APSS) to perform peak current mitigation within the APSS, the computer instructions comprising: A first computer instruction set, which is executed at the startup time of the APSS to obtain the voltage and leakage current values ​​of the power rails to which the APSS is electrically coupled; A second computer instruction set is used at the startup time of the APSS to perform an estimation of the peak current range of the APSS using the obtained voltage and leakage current values. A third computer instruction set, which is executed at the startup time of the APSS, is used to map the estimated peak current range to the current limiting level to be executed using a pre-configured estimated peak current range to current limiting level mapping. and A fourth computer instruction set is configured to execute during the runtime of the APSS when conditions indicate that the APSS is operating at or near a peak current, wherein execution of the fourth computer instruction set causes a mapped current limiting level to be applied to at least one processor of the APSS.

16. The non-transitory computer-readable medium of claim 15, wherein the APSS comprises a plurality of clusters of processors, each cluster comprising a plurality of processors, and wherein the fourth set of computer instructions comprises computer instructions for execution at runtime when a condition indicating that the APSS is operating at or near a peak current is present, the computer instructions causing a mapped current limiting level to be applied to all said processors of the APSS.

17. The non-transitory computer-readable medium of claim 15, wherein the fourth computer instruction set causes the mapped rate limiting level to be applied by performing at least one of the following: (1) reducing the operating frequency of the at least one processor; and (2) reducing the number of instructions executed by the at least one processor during a clock cycle of the at least one processor or during a clock cycle sequence of the at least one processor.

18. The non-transitory computer-readable medium of claim 15, wherein the pre-configured estimated peak current range to current limiting level mapping is implemented in a LuT logic unit including a lookup table (LuT) address generation logic unit and a LuT, the LuT address generation logic unit being configured to convert the estimated peak current range into a memory address in the LuT having a plurality of memory addresses, each memory address having a corresponding current limiting level stored therein, each corresponding current limiting level corresponding to a corresponding estimated peak current range.

19. The non-transitory computer-readable medium of claim 16, wherein the condition includes at least one of the following: (1) Each processor is operating at the maximum clock frequency; (2) Each processing core of each processor is active; and (3) The junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

20. The non-transitory computer-readable medium of claim 16, wherein the conditions include: (1) Each processor is operating at its maximum clock frequency; (2) Each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

21. The non-transitory computer-readable medium of claim 15, wherein the non-transitory computer-readable medium comprises a memory device in a system-on-chip (SoC) integrated circuit (IC) package, the memory device being either inside the APSS or outside the APSS and accessible by the APSS.

22. The non-transitory computer-readable medium of claim 21, wherein the SoC IC package is used in a portable computing device (PCD).

23. An application subsystem (APSS) for performing peak current mitigation, the APSS comprising: At least one processor; and APSS controller, the APSS controller comprising: A component used to obtain the voltage and leakage current values ​​of the power rail to which the APSS is electrically coupled at the start-up time of the APSS; A component for estimating the range of peak current values ​​of the APSS using the voltage and leakage current values ​​obtained at the startup time of the APSS; A component used at startup to map the estimated peak current range to the current limiting level to be performed using a pre-configured estimated peak current range-to-current limiting level mapping; and A component for causing the mapped current limiting level to be applied to at least one processor of the APSS during runtime when conditions indicate that the APSS is operating at or near peak current.

24. The APSS of claim 23, wherein the at least one processor comprises a plurality of clusters of processors, each cluster comprising a plurality of processors, and wherein the component for causing causes the mapped current limiting level to be applied to all of the processors of the APSS when conditions indicate that the APSS is operating at or near a peak current.

25. The APSS of claim 23, wherein the mapped rate limiting level is applied by performing at least one of the following: (1) reducing the operating frequency of the at least one processor; and (2) reducing the number of instructions executed by the at least one processor during a clock cycle of the at least one processor or during a clock cycle sequence of the at least one processor.

26. The APSS of claim 23, wherein the pre-configured estimated peak current range to current limiting level mapping is implemented using a LuT logic unit including a lookup table (LuT) address generation logic unit and a LuT, the LuT address generation logic unit being configured to convert the estimated peak current range into a memory address in the LuT having a plurality of memory addresses, each memory address having a corresponding current limiting level stored therein, each corresponding current limiting level corresponding to a corresponding estimated peak current range.

27. The APSS of claim 24, wherein the condition includes at least one of the following: (1) each processor is operating at its maximum clock frequency; (2) each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

28. The APSS of claim 24, wherein the conditions include: (1) Each processor is operating at its maximum clock frequency; (2) Each processing core of each processor is active; and (3) the junction temperature of the APSS exceeds a pre-selected junction temperature threshold.

29. The APSS of claim 23, wherein the APSS is implemented in a system-on-chip (SoC) integrated circuit (IC) package.

30. The APSS of claim 29, wherein the SoCIC is implemented in a portable computing device (PCD).

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