Automobile NAND FLASH chip test method, device and equipment and storage medium

Abstract

The embodiment of the invention provides an automobile NAND FLASH chip test method and device, equipment and a storage medium, and belongs to the technical field of chip test and evaluation. The method comprises the steps that a target chip and a target part are determined, the target chip is an NAND FLASH chip, and the target part is an automobile part where the target chip is put into application; determining a test item according to the target part, wherein the test item comprises at least one of a function test item, a performance test item and a reliability test item; testing the target chip according to the test item to obtain a test data set corresponding to the test item; and inputting the test data set into a preset evaluation model, and determining a test result of the target chip according to an output result of the preset evaluation model. The invention aims to improve the accuracy of the test result of the NAND FLASH chip, thereby improving the overall performance and reliability of an automobile system.

Description

Technical Field

[0001] This invention relates to the field of chip testing and evaluation technology, and in particular to a method, apparatus, equipment and storage medium for testing automotive NAND FLASH chips. Background Technology

[0002] In the existing technology, with the development of intelligent driving vehicles, the requirements of automotive systems for memory are becoming increasingly higher. Not only do they need large capacity and high speed, but they also need to have high reliability, low power consumption and strong anti-interference capabilities. NAND FLASH memory, due to its high performance, high storage capacity and small size packaging, meets the current needs of intelligent driving vehicle development and is widely used in vehicle systems.

[0003] Existing testing methods for memory often focus on a single dimension, such as testing only read / write speed or storage capacity, while ignoring the chip's overall performance in actual automotive applications. This makes it difficult to fully reflect the actual performance of NAND FLASH chips, which may lead to improper selection and affect the overall performance and reliability of automotive systems.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0005] The main objective of this application is to provide a method, apparatus, device, and storage medium for testing automotive NAND FLASH chips, aiming to improve the accuracy of NAND FLASH chip test results, thereby improving the overall performance and reliability of automotive systems.

[0006] To achieve the above objectives, one aspect of this application proposes a method for testing automotive NAND FLASH chips, comprising: The target chip and target component are identified, wherein the target chip is a NAND FLASH chip and the target component is an automotive part in which the target chip is applied; Test items are determined based on the target part, and the test items include at least one of functional test items, performance test items, and reliability test items; The target chip is tested according to the test items to obtain the test dataset corresponding to the test items; The test dataset is input into a preset evaluation model, and the test results of the target chip are determined based on the output of the preset evaluation model.

[0007] In some embodiments, the step of testing the target chip according to the test items to obtain the test dataset corresponding to the test items includes: The target chip is tested according to the functional test items, which include one or more of the following: power-on initialization function, data read / write function, mode register read / write function, automatic refresh function, data bus toggle function, data mask function, and ECC error correction function. Obtain the first dataset corresponding to the functional test item, wherein the test dataset includes the first dataset.

[0008] In some embodiments, the step of testing the target chip according to the test items to obtain the test dataset corresponding to the test items includes: The target chip is tested according to the performance test items, which include one or more of array timing requirements, storage capacity, transmission rate and power consumption. Obtain the second dataset corresponding to the performance test item, wherein the test dataset includes the second dataset.

[0009] In some embodiments, the step of testing the target chip according to the test items to obtain the test dataset corresponding to the test items includes: The target chip is tested according to the reliability test items, which include one or more of the following: environmental temperature adaptability, service life, package integrity, and electrical characteristic reliability. Obtain the third dataset corresponding to the reliability test item, wherein the test dataset includes the third dataset.

[0010] In some embodiments, the preset evaluation model includes a primary evaluation model and a secondary evaluation model. The step of inputting the test dataset into the preset evaluation model and determining the test result of the target chip based on the output of the preset evaluation model includes: Based on the target part, the first-level evaluation model is determined, and the test dataset is input into the first-level evaluation model to obtain the first prediction result output by the first-level evaluation model. The secondary evaluation model is determined based on the test item, and the test dataset corresponding to the test item is input into the secondary evaluation model to obtain the second prediction result output by the secondary evaluation model. The test result is determined based on the first prediction result and the second prediction result.

[0011] In some embodiments, the test dataset includes a first dataset, a second dataset, and a third dataset, and the step of inputting the corresponding test dataset into the corresponding secondary evaluation model according to the test item includes: Input the first dataset into the secondary evaluation model corresponding to the functional test item; Input the second dataset into the secondary evaluation model corresponding to the performance test project; Input the third dataset into the secondary evaluation model corresponding to the reliability test project.

[0012] In some embodiments, the step of determining the test result based on the first prediction result and the second prediction result includes: Determine whether the first prediction result and the second prediction result match; When the first prediction result matches the second prediction result, the test result is determined to include both the first prediction result and the second prediction result. When the first prediction result does not match the second prediction result, the test result is determined to include the first prediction result and the warning message.

[0013] To achieve the above objectives, another aspect of this application proposes an automotive NAND FLASH chip testing system, the system comprising: The test preparation module is used to identify the target chip and the target part, wherein the target chip is a NAND FLASH chip and the target part is an automotive part in which the target chip is applied; The test execution module is used to determine test items based on the target component, wherein the test items include at least one of functional test items, performance test items, and reliability test items; and to test the target chip according to the test items to obtain the test dataset corresponding to the test items. The predictive analysis module is used to input the test dataset into a preset evaluation model and determine the test results of the target chip based on the output of the preset evaluation model.

[0014] To achieve the above objectives, another aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the method described above.

[0015] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the methods described above.

[0016] The embodiments of this application include at least the following beneficial effects: This application provides a method, apparatus, device, and storage medium for testing automotive NAND FLASH chips. This solution first selects the target chip to be tested and the target component where the target chip will be used. Test items are then determined based on the target component, allowing the test items to be adapted to the usage scenario of the target chip. The target chip is then tested according to the determined test items. These test items can include functional test items, performance test items, and reliability test items across three dimensions. A test dataset corresponding to each test item is obtained, and the test dataset is input into a preset evaluation model. The test results of the target chip are determined through analysis using the preset evaluation model. Compared to current methods that focus on testing chips from a single dimension, this application can combine functional, performance, and reliability test items for testing, and can adapt the test items to the usage scenario. Combined with model analysis, this further improves the accuracy of NAND FLASH chip test results, thereby improving the overall performance and reliability of the automotive system. Attached Figure Description

[0017] Figure 1 This is a flowchart of a testing method for automotive NAND FLASH chips provided in an embodiment of this application; Figure 2 This is a flowchart of step S400 provided in the embodiments of this application; Figure 3 This is another flowchart of a testing method for automotive NAND FLASH chips provided in an embodiment of this application; Figure 4 This is a schematic diagram of the sensor arrangement system based on indoor area size provided in an embodiment of this application; Figure 5 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0020] In related technologies, with the development of intelligent driving vehicles, the requirements of automotive systems for memory are becoming increasingly demanding. Not only do they need large capacity and high speed, but they also need to have high reliability, low power consumption and strong anti-interference capabilities. NAND FLASH memory, due to its high performance, high storage capacity and small size packaging, meets the current needs of intelligent driving vehicle development and is widely used in vehicle systems.

[0021] Existing testing methods for memory often focus on a single dimension, such as testing only read / write speed or storage capacity, while ignoring the chip's overall performance in actual automotive applications. This makes it difficult to fully reflect the actual performance of NAND FLASH chips, which may lead to improper selection and affect the overall performance and reliability of automotive systems.

[0022] In view of this, this application provides a method, apparatus, device, and storage medium for testing automotive NAND FLASH chips. Figure 1 This is an optional flowchart of a testing method for automotive NAND FLASH chips provided in an embodiment of this application. Figure 1 The method may include, but is not limited to, steps S100 to S400.

[0023] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0024] Step S100: Determine the target chip and the target part. The target chip is a NAND FLASH chip, and the target part is an automotive part in which the target chip is applied. The chip tested in this application embodiment is a NAND FLASH chip, also known as a memory in the prior art. It is a type of FLASH memory, which adopts a non-linear macrocell mode internally, providing a cheap and effective solution for the realization of large-capacity solid-state memory. NAND FLASH chips have advantages such as large capacity and fast rewrite speed, and are suitable for storing large amounts of data. Therefore, they are currently widely used in automotive in-vehicle systems, and this application involves components of various modules in the in-vehicle system.

[0025] In the automotive manufacturing process, for chips to be installed in the vehicle system, passing relevant tests before installation is a necessary condition. This includes NAND flash chips. Therefore, the target chip is the alternative NAND flash chip to be installed in the vehicle system. If it passes the test, the target chip can be installed in the vehicle system; if it fails the test, the target chip is considered defective and cannot be installed in the vehicle system. Secondly, the target component is a part within the vehicle system, which is the component that the target chip will be used after passing the test. This target component may belong to various modules in the vehicle system, such as the energy management module or the central control module, etc., and is not limited in this embodiment.

[0026] Step S200: Determine the test items based on the target part. The test items include at least one of the following: functional test items, performance test items, and reliability test items. In this embodiment, the test items are defined as tests in three dimensions: functionality, performance, and reliability. Specifically, the test items include functional test items for testing functionality, performance test items for testing performance, and reliability test items for testing reliability. Each of the three dimensions of test items also includes multiple test contents.

[0027] It's understandable that due to the functional differences between the target component and various modules in the vehicle system, the chips installed within them will have different priorities, leading to different test items. For example, for a chip in component A, meeting functional and performance requirements is the focus, while for a chip in component B, functionality and reliability are the priorities. Based on this difference, the test items required for the target chip can be determined according to the target component, identifying the necessary test dimensions, and then conducting functional testing, performance testing, or reliability testing.

[0028] Step S300: Test the target chip according to the test items to obtain the test dataset corresponding to the test items; Based on the test items determined in step S200, further testing operations are performed on the target chip according to the determined test items. It should be noted that the test items determined for the target component include not only the three test dimensions, but also the test content under each test dimension. For example, in the functional test items, it is determined to perform automatic refresh function testing, but not data bus flip-flop function testing. For the three test dimensions and the test content under each test dimension, this embodiment does not limit the test order. The staff can flexibly arrange multiple chips to be tested in the three dimensions simultaneously according to the on-site needs or design requirements to improve test efficiency.

[0029] After completing the testing operation, the test dataset of the target chip is collected and summarized. In order to ensure that the subsequent data analysis steps can be carried out in sequence, the data specifications of the test dataset are ensured to be consistent even if different test items are performed on different target chips. For test items that are not performed, they can be set to preset values ​​or processed in other ways.

[0030] Step S400: Input the test dataset into the preset evaluation model, and determine the test results of the target chip based on the output of the preset evaluation model.

[0031] In this embodiment, a preset evaluation model is also applied. This preset evaluation model is a machine learning model. This embodiment does not limit the specific model type used. For example, it can be a random forest or XGBoost model. This preset evaluation model is obtained by training using the sample dataset collected from previous tests. It can make predictions and evaluations based on the test dataset of the target chip and output a quantitative value that represents the quality of the target chip. Based on the output result, the output result is compared with the pass threshold. When the output result is greater than or equal to the pass threshold, the test result is determined to be that the target chip has passed the test. When the current output result is less than the pass threshold, the test result is determined to be that the target chip has failed the test.

[0032] Steps S100 to S400, as illustrated in this embodiment, involve first selecting the target chip for testing and the target component where the target chip will be used. Test items are then determined based on the target component, allowing the test items to be adapted to the usage scenario of the target chip. The target chip is then tested according to the determined test items. These test items can include functional tests, performance tests, and reliability tests, resulting in a test dataset. This dataset is then input into a preset evaluation model, which analyzes and determines the test results for the target chip. Compared to current chip testing methods that focus on a single dimension, this application combines functional, performance, and reliability test items, and allows for adaptation to usage scenarios. Combined with model analysis, this further improves the accuracy of NAND FLASH chip test results, thereby enhancing the overall performance and reliability of the automotive system.

[0033] In some embodiments, step S300 includes: The target chip is tested according to the functional test items, which include one or more of the following: power-on initialization function, data read and write function, mode register read and write function, automatic refresh function, data bus toggle function, data mask function, and ECC error correction function. Obtain the first dataset corresponding to the functional test project. The test dataset includes the first dataset.

[0034] Specifically, the power-on initialization function is the function of automatically executing the hardware and software initialization process after the chip is powered on. This includes configuring the clock frequency of the registers, the default values ​​of pin functions, self-testing, and establishing the initial communication link to ensure that each module enters the preset safe working state. For vehicle systems, the test parameters include fast startup time, and whether or not it can start quickly affects the function of the vehicle computer.

[0035] Data read / write functionality refers to the data access function of on-chip memory units or external interfaces, ensuring that the chip supports synchronous or asynchronous data read / write operations. Among these, test parameters include read / write time and read / write latency. For example, for the power control module of an automobile, it is crucial to meet the nanosecond-level read / write latency.

[0036] The mode register read / write function is a function that sets the chip's operating mode by configuring registers. It can set the chip to work in normal mode, sleep mode, etc. The test parameters include whether it can distinguish between register group types used for status monitoring and those used for function configuration, whether it can implement hardware locks or software permission hierarchical write protection mechanisms, and whether it can achieve dynamic mode switching during runtime. The mode register read / write function is crucial for supporting the rapid switching of automobiles between, for example, high-performance computing mode and low-power standby mode.

[0037] The automatic refresh function is a feature that periodically refreshes data to avoid data loss due to problems such as charge leakage. The test parameters include refresh cycle, refresh granularity, and whether refresh can be interrupted. Testing the automatic refresh function can ensure that the vehicle maintains data stability under abnormal environmental conditions and avoids control logic errors caused by refresh failure.

[0038] The data bus flip function dynamically flips the data bus signal, thereby reducing switching activities during bus transmission, lowering power consumption and electromagnetic radiation. Test parameters include whether adjacent cycles can be compared and flipped, and whether the receiving end can be instructed to restore the data according to the flip state. For high-speed automotive data buses, the ability of the data bus flip function to be implemented affects the vehicle's dynamic power consumption and the electromagnetic interference resistance of devices such as car radios.

[0039] The data masking function is a feature that masks or encrypts specific fields during data reading and writing to protect sensitive information. Test parameters include whether hardware masking and / or software masking can be implemented. In vehicle systems, the data masking function is used to protect the calibration parameters of the vehicle's computer and ensure system security.

[0040] ECC error correction is a function that adds redundant parity bits to data to detect and correct single-bit and / or double-bit errors. The test parameters include whether it supports encoding methods such as Hamming code or BCH, and the error correction range. In high-speed caches of autonomous driving chips, ECC error correction can reduce the bit error rate and make it meet the safety level requirements.

[0041] It is understandable that the content of each of the above functional test items is crucial to the final user experience of the in-vehicle system. Performing functional tests also helps to improve the reliability of the vehicle system and ensure that the final produced vehicle matches the design performance.

[0042] Depending on the target component, the functional test items can include one or more of the above-mentioned functional test items according to actual needs, thereby improving the flexibility of testing. The test parameters of each test item constitute the first dataset, which represents the test data of the target chip in the functional dimension. In other embodiments, other functional test items can be designed according to the needs of the staff, such as interface diagnostic functions and communication protocol enhancement functions, etc., to further improve the flexibility and test coverage of chip testing, so as to comprehensively analyze the quality of the target chip.

[0043] In some embodiments, step S300 includes: The target chip is tested according to the performance test items, which include one or more of the following: array timing requirements, storage capacity, transmission rate and power consumption. Obtain the second dataset corresponding to the performance test project. The test dataset includes the second dataset.

[0044] Specifically, array timing requirements include testing the timing characteristics of the internal logic array of the chip, as well as the input and output signal timing of the external interface of the chip. Array timing requirements are used to ensure that the signals of various functional modules inside or outside the chip work synchronously and in a coordinated manner, so as to avoid data misalignment or delay.

[0045] Storage capacity can be determined by writing data to the address pin of the target chip, comparing the written data with the read data, and further determining the storage capacity of the target chip. Storage capacity is used to ensure that the target chip can store information such as navigation maps, user preference data, and adaptive learning data.

[0046] The transmission rate can be determined by setting a first cycle and a second cycle. In the first cycle, data is continuously written to the preset address space of the target chip, and the content of the written data is recorded. In the second cycle, the data is read and compared to see if the written data and the read data are consistent. The required transmission time is recorded and the transmission rate is determined. The transmission rate affects the data interaction speed between the chip and external devices or internal modules, and affects the decision response time of various intelligent modules in the vehicle system.

[0047] Power consumption can be measured by selecting the pin corresponding to the target chip, setting the input voltage and measurement range, applying the voltage, measuring the current, and calculating the power consumption. Power consumption represents the chip's heat generation and battery life, and is a key indicator for judging system reliability.

[0048] Depending on the target component, the performance test items can include one or more of the above-mentioned performance test items according to actual needs, thereby improving the flexibility of testing. The test parameters of each test item constitute a second dataset, which represents the test data of the target chip in the performance dimension. In other embodiments, other performance test items, such as electromagnetic interference resistance performance, can be designed according to the needs of the staff, to further improve the flexibility and test coverage of chip testing, so as to comprehensively analyze the quality of the target chip.

[0049] In some embodiments, step S300 includes: The target chip is tested according to the reliability test items, which include one or more of the following: environmental temperature adaptability, service life, package integrity, and electrical characteristic reliability. Obtain the third dataset corresponding to the reliability test project. The test dataset includes the third dataset.

[0050] Specifically, multiple temperature adaptability levels and corresponding operating temperature ranges are set for environmental temperature adaptability. For example, temperature adaptability level 0 corresponds to an operating temperature range of... to Temperature adaptability level 1 corresponds to an operating temperature range of: to Temperature adaptability level 2 corresponds to an operating temperature range of: to Temperature adaptability level 3 corresponds to an operating temperature range of: to The temperature adaptability level of the target chip is determined by testing its operating temperature range. This temperature adaptability level allows us to understand the extreme temperature environments that the target chip can support, and determine whether it can be used in high-temperature areas such as engine control units.

[0051] Based on the determined temperature adaptability level, further evaluate its service life. The test specifications for service life can be found in the table below:

[0052] Packaging integrity reflects whether the target chip is protected from mechanical stress, moisture, or corrosive gases, ensuring the reliability of physical and electrical connections. The packaging integrity of the target chip can be tested through tests such as shear strength test, destructive bond pull test, and solderability test, thereby understanding the packaging integrity of the target chip under the influence of various external factors.

[0053] The requirements for electrical reliability are used to prevent the target chip from being affected by factors such as voltage fluctuations, electromagnetic interference and electrostatic discharge, and to ensure the stability of signal transmission and logic control of the vehicle system. The electrical reliability of the target chip can be tested by conducting tests such as human body electrostatic discharge test, electrostatic discharge test of charged device model, and latch-up effect test.

[0054] Depending on the target component, the reliability test items can include one or more of the above-mentioned reliability test items according to actual needs, thereby improving the flexibility of the test. The test parameters of each test item constitute a third dataset, which represents the test data of the target chip in the reliability dimension. In other embodiments, other reliability test items can be designed according to the needs of the staff, such as those targeting electromagnetic radiation effects and storage life, to further improve the flexibility and test coverage of chip testing, so as to comprehensively analyze the quality of the target chip.

[0055] In some embodiments, reference Figure 2 Step S400 includes: Step S410: Determine the first-level evaluation model based on the target part, input the test dataset into the first-level evaluation model, and obtain the first prediction result output by the first-level evaluation model. Step S420: Determine the secondary evaluation model based on the test items, input the test dataset corresponding to the test items into the secondary evaluation model, and obtain the second prediction result output by the secondary evaluation model; Step S430: Determine the test result based on the first prediction result and the second prediction result.

[0056] In this embodiment, the preset evaluation model includes a primary evaluation model and a secondary evaluation model. Both the primary and secondary evaluation models are machine learning models, and their model types can be the same or different; this embodiment does not impose any limitations. The primary evaluation model differs from the secondary evaluation model in that it corresponds to the type of the target component. That is, different primary evaluation models are applied to different NAND FLASH chips on different target components. Therefore, the primary evaluation model used needs to be determined based on the type of the target component. The secondary evaluation model, on the other hand, corresponds to the test dimensions. That is, for the three test dimensions of function, performance, and reliability, each test dimension has at least one secondary evaluation model. Therefore, the secondary evaluation model used needs to be determined based on the actual test dimensions included in the test items. For example, if the target chip only underwent functional and performance testing, the secondary evaluation model would include at least one secondary evaluation model for functional testing and at least one secondary evaluation model for performance testing.

[0057] Furthermore, after determining the model used for predictive analysis, the test dataset—i.e., all test parameters in the test operation—is input into the primary evaluation model for holistic analysis, obtaining the first predictive result output by the primary evaluation model. Simultaneously, the test dataset corresponding to each test item is input into the secondary evaluation model for the corresponding test dimension for targeted analysis, obtaining the second predictive result output by the secondary evaluation model. By combining the first and second predictive results, the results of the holistic and targeted analyses are summarized to determine the test results. This adds an evaluation dimension to the model's prediction direction, improving the accuracy of NAND FLASH chip test results, thereby enhancing the overall performance and reliability of the automotive system.

[0058] In other embodiments, the secondary evaluation model may also be multiple models corresponding to specific test content.

[0059] In other embodiments, since the test dataset input to the primary evaluation model includes data from multiple test dimensions, the data volume is relatively large. Furthermore, although some test parameters are obtained through different test dimensions, they may actually have correlations. Therefore, before inputting the test dataset into the primary evaluation model, principal component analysis or other analytical methods can be used to remove redundant data or merge correlated data, thereby reducing the dimensionality of the test dataset and improving the accuracy of chip test results.

[0060] In some embodiments, reference Figure 3 The step of inputting the corresponding test dataset into the corresponding secondary evaluation model according to the test item includes: Input the first dataset into the secondary evaluation model corresponding to the functional test project; Input the second dataset into the secondary evaluation model corresponding to the performance test project; Input the third dataset into the secondary evaluation model corresponding to the reliability test project.

[0061] Specifically, for the first, second, and third datasets obtained through testing operations in the above embodiments, in order to enable targeted analysis of each dataset, they are input into the corresponding secondary evaluation models for the testing dimensions. The first dataset is input into the secondary evaluation model related to the functional test items, i.e., the functional test dimension; the second dataset is input into the secondary evaluation model related to the performance test items, i.e., the performance test dimension; and the third dataset is input into the secondary evaluation model related to the reliability test items, i.e., the reliability test dimension. At the same time, the output results of each secondary evaluation model are merged into the second prediction result, thereby realizing fine-grained analysis of the test data, expanding the dimensions of chip test analysis, improving the accuracy of NAND FLASH chip test results, and thus improving the overall performance and reliability of the automotive system.

[0062] In addition, the test dataset used as input to the first-level evaluation model, as well as the first, second, and third datasets used as input to the second-level evaluation model, were all cleaned and processed before being input into the model. Normalization and other processing can also be performed according to the specific needs of the machine learning model.

[0063] In some embodiments, the step of determining the test result based on the first prediction result and the second prediction result includes: Determine whether the first and second prediction results match; When the first prediction result matches the second prediction result, the test result is determined to include both the first and second prediction results. When the first prediction result does not match the second prediction result, the test result is determined to include the first prediction result and the warning message.

[0064] Optionally, the first prediction result obtained by the first-level evaluation model and the second prediction result obtained by the second-level evaluation model in the above embodiments represent coarse-grained and fine-grained prediction results, respectively. They respectively judge whether the target chip test is passed. Therefore, it is necessary to further consider merging the two prediction results to determine whether the first prediction result matches the second prediction result.

[0065] When the first and second prediction results match (e.g., both are judged as test pass, or both are judged as test fail), it is determined that there is no discrepancy between the two prediction results, and the test result includes both predictions, and is output. However, when the first and second prediction results do not match, it indicates a conflict between the predictions of the primary and secondary evaluation models—one model judges the test pass, while the other judges it fail. In this case, the primary prediction result should be prioritized because it is determined based on the target component type. Compared to the secondary evaluation model, it has a higher degree of adaptability to the actual needs of the target chip, thus having higher reliability when prediction results conflict. Therefore, the test result should include the primary prediction result. However, conflicting prediction results cannot be ignored. Therefore, a warning message should also be output to notify staff, ensuring the test result also includes this warning message. Staff should be notified to review and verify the information, and it can be further determined whether the conflict-related secondary evaluation model needs to be iteratively updated to resolve the conflict.

[0066] By merging the first and second prediction results, and prioritizing the first prediction result when the two prediction results do not match, coarse-grained and fine-grained analysis can be performed while avoiding the impact of prediction conflicts on the chip testing process. This improves the accuracy of NAND FLASH chip test results and enhances the reliability of chip testing.

[0067] The following is a detailed description and explanation of the solutions in the embodiments of the present invention, using specific application examples: This application provides a method for testing automotive NAND FLASH chips. The method involves identifying the target NAND FLASH chip to be tested and the target component into which the target chip will be used. Based on the target component, the method determines the test items to be performed on the target chip, including functional test items, performance test items, and reliability test items.

[0068] The target chip is tested according to the functional test items, including its power-on initialization function, data read / write function, mode register read / write function, automatic refresh function, data bus toggle function, data mask function, and ECC error correction function. The parameters obtained from the tests are used to obtain the first dataset. The target chip is tested according to the performance test items, including its array timing requirements, storage capacity, transmission rate, and power consumption. The parameters obtained from the tests are used to obtain the second dataset. The target chip is tested according to the reliability test items, including its environmental temperature adaptability, operating life, package integrity, and electrical characteristic reliability. The parameters obtained from the tests are used to obtain the third dataset. The combination of the first, second, and third datasets is defined as the test dataset.

[0069] Based on the target part, a primary evaluation model is determined. The test dataset is input into the primary evaluation model to obtain the first prediction result corresponding to the primary evaluation model. Multiple corresponding secondary evaluation models are determined based on functional test items, performance test items, and reliability test items. The first dataset is input into the secondary evaluation model corresponding to the functional test item, the second dataset into the secondary evaluation model corresponding to the performance test item, and the third dataset into the secondary evaluation model corresponding to the reliability test item. The corresponding outputs of each secondary evaluation model are obtained and merged into a second prediction result. The first and second prediction results are then compared. If they match, the test result includes both the first and second prediction results; otherwise, the test result includes both the first prediction result and a warning message.

[0070] Please see Figure 4 This application also provides an automotive NAND FLASH chip testing system, which can implement the above-described automotive NAND FLASH chip testing method. The system includes: The test preparation module is used to identify the target chip and the target part. The target chip is a NAND FLASH chip, and the target part is the automotive part in which the target chip will be used. The test execution module is used to determine the test items based on the target part. The test items include at least one of the functional test items, performance test items, and reliability test items; and to test the target chip according to the test items to obtain the test dataset corresponding to the test items. The predictive analysis module is used to input the test dataset into a preset evaluation model and determine the test results of the target chip based on the output of the preset evaluation model.

[0071] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0072] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described automotive NAND FLASH chip testing method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0073] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0074] Please see Figure 5 , Figure 5 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 901 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 902 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 902 can store the operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 902 and is called and executed by the processor 901 to execute the automotive NAND FLASH chip testing method of the embodiments of this application. The input / output interface 903 is used to implement information input and output; The communication interface 904 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 905 transmits information between various components of the device (e.g., processor 901, memory 902, input / output interface 903, and communication interface 904); The processor 901, memory 902, input / output interface 903, and communication interface 904 are connected to each other within the device via bus 905.

[0075] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described automotive NAND FLASH chip testing method.

[0076] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0077] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0078] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0079] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0080] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0081] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0082] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0083] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0085] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0086] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method for testing automotive NAND FLASH chips, characterized in that, The method includes: The target chip and target component are identified, wherein the target chip is a NAND FLASH chip and the target component is an automotive part in which the target chip is applied; Test items are determined based on the target part, and the test items include at least one of functional test items, performance test items, and reliability test items; The target chip is tested according to the test items to obtain the test dataset corresponding to the test items; The test dataset is input into a preset evaluation model, and the test results of the target chip are determined based on the output of the preset evaluation model.

2. The method according to claim 1, characterized in that, The step of testing the target chip according to the test items and obtaining the test dataset corresponding to the test items includes: The target chip is tested according to the functional test items, which include one or more of the following: power-on initialization function, data read / write function, mode register read / write function, automatic refresh function, data bus toggle function, data mask function, and ECC error correction function. Obtain the first dataset corresponding to the functional test item, wherein the test dataset includes the first dataset.

3. The method according to claim 1, characterized in that, The step of testing the target chip according to the test items and obtaining the test dataset corresponding to the test items includes: The target chip is tested according to the performance test items, which include one or more of array timing requirements, storage capacity, transmission rate and power consumption. Obtain the second dataset corresponding to the performance test item, wherein the test dataset includes the second dataset.

4. The method according to claim 1, characterized in that, The step of testing the target chip according to the test items and obtaining the test dataset corresponding to the test items includes: The target chip is tested according to the reliability test items, which include one or more of the following: environmental temperature adaptability, service life, package integrity, and electrical characteristic reliability. Obtain the third dataset corresponding to the reliability test item, wherein the test dataset includes the third dataset.

5. The method according to claim 1, characterized in that, The preset evaluation model includes a primary evaluation model and a secondary evaluation model. The step of inputting the test dataset into the preset evaluation model and determining the test result of the target chip based on the output of the preset evaluation model includes: Based on the target part, the first-level evaluation model is determined, and the test dataset is input into the first-level evaluation model to obtain the first prediction result output by the first-level evaluation model. The secondary evaluation model is determined based on the test item, and the test dataset corresponding to the test item is input into the secondary evaluation model to obtain the second prediction result output by the secondary evaluation model. The test result is determined based on the first prediction result and the second prediction result.

6. The method according to claim 5, characterized in that, The test dataset includes a first dataset, a second dataset, and a third dataset. The step of inputting the corresponding test dataset into the corresponding secondary evaluation model according to the test item includes: Input the first dataset into the secondary evaluation model corresponding to the functional test item; Input the second dataset into the secondary evaluation model corresponding to the performance test project; Input the third dataset into the secondary evaluation model corresponding to the reliability test project.

7. The method according to claim 5, characterized in that, The step of determining the test result based on the first prediction result and the second prediction result includes: Determine whether the first prediction result and the second prediction result match; When the first prediction result matches the second prediction result, the test result is determined to include both the first prediction result and the second prediction result. When the first prediction result does not match the second prediction result, the test result is determined to include the first prediction result and the warning message.

8. A testing system for automotive NAND FLASH chips, characterized in that, The system includes: The test preparation module is used to identify the target chip and the target part, wherein the target chip is a NAND FLASH chip and the target part is an automotive part in which the target chip is applied; The test execution module is used to determine test items based on the target component, wherein the test items include at least one of functional test items, performance test items, and reliability test items; and to test the target chip according to the test items to obtain the test dataset corresponding to the test items. The predictive analysis module is used to input the test dataset into a preset evaluation model and determine the test results of the target chip based on the output of the preset evaluation model.

9. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method of any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 7.

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