Chip replaceability test method and device, electronic equipment and storage medium

Abstract

The invention provides a chip replaceability test method and device, electronic equipment and a storage medium, and belongs to the technical field of semiconductors, a replaceability test index system of a chip is constructed, and a target chip is tested according to the replaceability test index system to obtain test result data, determining the replaceability requirement satisfaction degree of each evaluation secondary index, and searching a score range corresponding to the replaceability requirement satisfaction degree according to a preset score comparison table; and determining a total replaceability score of the target chip according to a weight set for each evaluation domain and the score range, and determining a replaceability level of the target chip according to the total replaceability score. Therefore, by constructing a comprehensive chip replaceability test index system, an automatic test process is realized, user-defined weights are supported, the test efficiency and accuracy are improved, the system replacement risk is reduced, and different scene requirements are met.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and more specifically, relates to a chip replaceability testing method, apparatus, electronic device, and storage medium. Background Technology

[0002] With the rapid development of semiconductor technology, chips, as core components of electronic devices, have seen an explosive growth in variety and models, covering multiple fields from low-power embedded chips to high-performance computing chips, and from general-purpose processors to application-specific integrated circuits (ASICs). Chips from different manufacturers, using different processes and architectures, exhibit significant differences in functionality, performance, interface specifications, and reliability. In practical applications such as industrial control, smart terminals, and IoT devices, chip replacement has become a common phenomenon due to demands for supply chain adjustments, cost optimization, and technological upgrades. However, chip replacement is not a simple physical replacement; its core challenge lies in ensuring the stability, functional continuity, and performance compliance of the replaced system. For example, in industrial automation control scenarios, insufficient real-time response capabilities of the replacement chip may lead to production process interruptions; in IoT scenarios, a significant difference in power consumption characteristics between the new and original chips may cause a sharp drop in device battery life; and in financial security equipment, insufficient compatibility of the encryption algorithms in the replacement chip may pose data security risks. Therefore, comprehensive and rigorous testing of the replaceability of new chips is a crucial step in ensuring the normal operation of the system after replacement.

[0003] Currently, chip replaceability testing in the industry largely relies on customized solutions developed in-house. This results in fragmented and inconsistent test metrics, leading to a lack of comparability between test results from different companies and making it difficult to comprehensively assess the potential risks of chip replacement. Furthermore, traditional testing often depends on manual configuration of the test environment, data recording, and result analysis, which is not only inefficient but also prone to human error, affecting the final replaceability determination. In addition, different application scenarios have significantly different core chip requirements, and existing testing methods do not provide differentiated evaluation strategies for these scenarios, often employing a one-size-fits-all scoring standard, resulting in test results that are out of touch with actual application needs. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a chip replaceability testing method, apparatus, electronic device and storage medium, which can significantly improve the comprehensiveness, efficiency and accuracy of chip replaceability testing and meet the needs of different scenarios.

[0005] This application provides a chip replaceability testing method, which includes the following steps: A replaceability test index system for a chip is constructed, and the target chip is tested according to the replaceability test index system to obtain test result data; wherein, the replaceability test index system includes multiple evaluation domains, and each evaluation domain contains primary evaluation indexes and secondary evaluation indexes. Based on the test results data, determine the degree to which the substitutability requirements of each of the secondary evaluation indicators are met, and find the score range corresponding to the degree to which the substitutability requirements are met according to the preset scoring comparison table; The overall replaceability score of the target chip is determined based on the weights set for each of the evaluation domains and the score range, and the replaceability level of the target chip is determined based on the overall replaceability score.

[0006] In some embodiments, six evaluation domains are determined based on the chip replacement scenario requirements: hardware compatibility, functional adaptability, performance adaptability, reliability, security, and software compatibility. Each evaluation domain is further refined into at least one primary evaluation indicator, and each primary evaluation indicator is further refined into at least one secondary evaluation indicator.

[0007] In some embodiments, determining the degree to which the substitutability requirements of each of the evaluation secondary indicators are met based on the test result data includes the following steps: Determine the substitutability benchmark requirements for each of the aforementioned secondary evaluation indicators; The test results data are compared one by one with the substitutability benchmark requirements, and the degree to which the substitutability requirements of each of the secondary evaluation indicators are met is determined based on the comparison results; the degree to which the substitutability requirements are met includes four categories: fully met, partially met, basically met, and not met.

[0008] In some embodiments, determining the total substitutability score of the target chip based on the weights assigned to each of the evaluation domains and the score range includes the following steps: Set the weights for each of the evaluation domains; The second score of the primary evaluation indicator is obtained by calculating the arithmetic mean of the first score values ​​of the secondary evaluation indicator; and the third score of the evaluation domain is obtained by calculating the arithmetic mean of the second score values ​​of the primary evaluation indicator; wherein the median value of the score range of the secondary evaluation indicator is used as its first score value. The overall replaceability score of the target chip is calculated based on the third score of the evaluation domain and the set weights.

[0009] In some embodiments, determining the total substitutability score of the target chip based on the weights assigned to each of the evaluation domains and the score range includes the following steps: Set weights for each of the evaluation domains; wherein, a uniform weight is set for each of the evaluation domains, or a weight is set for each of the primary evaluation indicators under each evaluation domain; The second score of the primary evaluation indicator is obtained by calculating the arithmetic mean of the first score values ​​of the secondary evaluation indicator; and the third score of the evaluation domain for which no weight is assigned is obtained by calculating the arithmetic mean of the second score values ​​of the primary evaluation indicator; wherein the first score value of the secondary evaluation indicator is determined based on the median of its score range or its actual degree of satisfaction. The total substitutability score of the target chip is calculated based on the second score of the first-level evaluation indicator and the set weight, or the third score of the evaluation domain and the set weight.

[0010] In some embodiments, determining the substitutability level of the target chip based on the overall substitutability score includes the following steps: Establish a mapping table between the substitutability level and the total substitutability score range; The substitutability score range of the target chip is determined based on its total substitutability score, and the substitutability level of the target chip is obtained by comparing it with the mapping table; the substitutability level includes four categories: complete replacement, functional replacement, no substitutability, and non-substitutable.

[0011] In some embodiments, the method further includes the following steps: Different configuration templates are preset for different business scenarios; the configuration template includes a mapping table between the weights of each evaluation domain, the replaceability level and the total replaceability score range; Based on the target configuration template invoked, determine or modify the mapping table between the weights of the evaluation domain, the substitutability level, and the total substitutability score range.

[0012] In some embodiments, a chip replaceability testing apparatus is also provided, the apparatus being: The testing module is used to construct a chip replaceability test index system and test the target chip according to the replaceability test index system to obtain test result data; wherein, the replaceability test index system includes multiple set evaluation domains, and each evaluation domain includes primary evaluation indexes and secondary evaluation indexes. The scoring module is used to determine the degree to which the substitutability requirements of each of the secondary evaluation indicators are met based on the test result data, and to find the score range corresponding to the degree to which the substitutability requirements are met according to a preset scoring reference table. The rating module is used to determine the total replaceability score of the target chip based on the weights set for each of the evaluation domains and the score range, and to determine the replaceability level of the target chip based on the total replaceability score.

[0013] In some embodiments, an electronic device is also provided, including: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the memory via the bus, and when the machine-readable instructions are executed by the processor, the steps of the chip substitutability testing method described in any of the preceding embodiments are performed.

[0014] In some embodiments, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, performs the steps of the chip replaceability testing method described in any of the preceding embodiments.

[0015] This application discloses a chip replaceability testing method, apparatus, electronic device, and storage medium. It constructs a chip replaceability testing index system and tests a target chip according to this system to obtain test result data. The replaceability testing index system includes multiple defined evaluation domains, and each evaluation domain contains primary and secondary evaluation indicators. Based on the test result data, the degree of replaceability requirement fulfillment for each secondary evaluation indicator is determined, and a score range corresponding to the degree of replaceability requirement fulfillment is found using a preset scoring reference table. The total replaceability score of the target chip is determined based on the weights set for each evaluation domain and the score range, and the replaceability level of the target chip is determined based on the total replaceability score. Therefore, by constructing a comprehensive chip replaceability testing index system, an automated testing process is achieved, custom weights are supported, testing efficiency and accuracy are improved, system replacement risks are reduced, and different scenario requirements are met. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A flowchart of the chip replaceability testing method described in an embodiment of this application is shown; Figure 2The flowchart illustrates the process of determining the degree to which the substitutability requirements of each of the secondary evaluation indicators are met based on the test result data, as described in an embodiment of this application. Figure 3 A flowchart illustrating the determination of the total substitutability score of the target chip by setting weights for each of the evaluation domains and the score ranges according to an embodiment of this application is shown. Figure 4 A schematic diagram of the chip replaceability testing apparatus according to an embodiment of this application is shown; Figure 5 A schematic diagram of the structure of the electronic device described in an embodiment of this application is shown. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0019] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0021] In view of the technical problems raised in the background art, this application provides a chip replaceability testing method, apparatus, electronic device and storage medium, which can significantly improve the comprehensiveness, efficiency and accuracy of chip replaceability testing and meet the needs of different scenarios.

[0022] See the instruction manual appendix Figure 1This application provides a chip replaceability testing method, the method comprising the following steps: S1. Construct a chip replaceability test index system, and test the target chip according to the replaceability test index system to obtain test result data; wherein, the replaceability test index system includes multiple evaluation domains, and each evaluation domain includes primary evaluation indexes and secondary evaluation indexes. S2. Determine the degree of substitutability requirement satisfaction for each of the secondary evaluation indicators based on the test result data, and find the score range corresponding to the degree of substitutability requirement satisfaction according to the preset scoring comparison table. S3. Determine the total replaceability score of the target chip based on the weights set for each of the evaluation domains and the score range, and determine the replaceability level of the target chip based on the total replaceability score.

[0023] Specifically, in step S1, when constructing the chip replaceability test index system, firstly, based on the key requirements of the chip replacement scenario or the different types of chips, six core evaluation domains are defined: hardware compatibility, functional adaptability, performance adaptability, reliability, security, and software compatibility. Among them, hardware compatibility can be further refined into three evaluation domains: instruction set compatibility, physical interface compatibility, and electrical characteristic compatibility. In addition, for each evaluation domain, specific primary evaluation indicators are refined. For example, under the physical interface compatibility evaluation domain, three primary evaluation indicators are set: general peripheral interface, application-specific peripheral, and external memory interface. Furthermore, for each primary evaluation indicator, quantifiable or verifiable secondary evaluation indicators are further broken down. For example, under the general peripheral interface evaluation primary indicator, five secondary evaluation indicators are set: number of general purpose input / output interfaces (GPIO), multiplexing function, number of serial communication interfaces, serial communication interface supported protocols, and parallel interface specifications.

[0024] The primary and secondary evaluation indicators set for each evaluation domain can be found in the final chip replaceability testing indicator system, as shown in Table 1 below. This unifies the testing dimensions, forms a comprehensive evaluation framework, covers multiple aspects of chip replaceability, and eliminates inconsistencies in evaluation standards among different companies or testing organizations.

[0025]

[0026] Table 1 Then, the target chip (chip under test) is tested according to the constructed replaceability test index system. In one embodiment, test equipment (probe station, signal analyzer, etc.) is first used to test various indicators of the target chip to generate raw test data (voltage, current, interface protocol matching results, etc.); then, the raw test data output by the test equipment (such as binary, specific instrument format) is converted into a general format (CSV, JSON, etc.) and its integrity and validity are verified to obtain the final test result data for subsequent processing.

[0027] See attached instructions Figure 2 In step S2, determining the degree to which the substitutability requirements of each of the secondary evaluation indicators are met based on the test result data includes the following steps: S201. Determine the substitutability benchmark requirements for each of the aforementioned secondary evaluation indicators; S202. The test result data is compared with the substitutability benchmark requirements one by one, and the degree of substitutability requirement satisfaction of each of the secondary evaluation indicators is determined according to the comparison results; the degree of substitutability requirement satisfaction includes four categories: fully satisfied, partially satisfied, basically satisfied, and not satisfied.

[0028] In step S201, the replaceability benchmark requirements for each of the secondary evaluation indicators are configured through a preset rule base based on chip industry general standards, typical application scenario requirements, and historical test data. For example, according to the requirements of international / domestic standards (such as IEEE and JEDEC standards), the number of general-purpose input / output interfaces (GPIO) must be ≥90% of the original chip's number; in industrial scenarios, the electrostatic discharge (ESD) level benchmark requirement is ≥±8kV (contact discharge), and in consumer electronics scenarios, the electrostatic discharge (ESD) level benchmark requirement is ≥±4kV (contact discharge).

[0029] In step S202, the test result data obtained in step S1 is compared one by one with the substitutability benchmark requirements of each secondary evaluation index. Based on the comparison results, the degree of satisfaction of each evaluation item is divided into four categories: "fully satisfied", "partially satisfied (can be adjusted and adapted)", "basically satisfied (requires functional combination)", and "not satisfied (fundamental differences exist)". For evaluation items judged as "partially satisfied", "basically satisfied", or "not satisfied", the differences from their substitutability benchmark requirements are recorded in detail (e.g., two fewer interfaces, 8% voltage error, etc.) to facilitate periodic traceability and query.

[0030] Then, a preset scoring reference table is invoked, such as a scoring reference table for instruction set compatibility, which includes the correspondence between the degree of substitutability requirement satisfaction and the score range; then, based on the degree of substitutability requirement satisfaction of each of the aforementioned secondary evaluation indicators, the corresponding score range is found in the preset scoring reference table, such as "fully satisfied" corresponding to 90-100 points, "partially satisfied" corresponding to 70-89 points, etc.; finally, the score range of each of the aforementioned secondary evaluation indicators is obtained and stored.

[0031] The degree to which the substitutability requirements of each secondary evaluation indicator are met is quantified into a score range, which serves as the basis for subsequent score calculations. In one embodiment, the instruction set compatibility scoring comparison table is shown in Table 2 below.

[0032]

[0033] Table 2 See the instruction manual appendix Figure 3 In step S3, determining the total substitutability score of the target chip based on the weights set for each of the evaluation domains and the score range includes the following steps: S301. Set the weights for each of the evaluation domains; S302. The second score of the primary evaluation indicator is obtained by calculating the arithmetic mean of the first score values ​​of the secondary evaluation indicator; and the third score of the evaluation domain is obtained by calculating the arithmetic mean of the second score values ​​of the primary evaluation indicator; wherein the median value of the score range of the secondary evaluation indicator is used as its first score value. S303. Calculate the total substitutability score of the target chip based on the third score value of the evaluation domain and the set weight.

[0034] In step S301, the weight values ​​of each evaluation domain are set according to the business scenario requirements, and the weight values ​​of each evaluation domain are ensured to be between 0 and 1, with a total of 100%. For example, industrial control scenarios emphasize reliability, so their weights can be increased.

[0035] In step S302, the evaluation of secondary indicators is the most basic unit of the test. Here, the median value of its score range is taken as its first score value. For example, if the score range for instruction set compatibility determined in step S2 is 90-100 points, then 95 is taken as its first score value. In other implementations, the method of determining the first score value based on the score range of the evaluation secondary indicator can be set according to the specific application. For example, the specific score can be determined based on the actual degree of satisfaction of the evaluation secondary indicator. This application does not impose any restrictions or fixations on this.

[0036] The second score for each primary evaluation indicator is obtained by summing the first scores of all its secondary evaluation indicators. In one embodiment, it is assumed that all secondary evaluation indicators under the primary evaluation indicator have the same importance, and the arithmetic mean of the first scores of all secondary evaluation indicators is directly taken as its second score. For example, if the first scores of the two secondary evaluation indicators under the primary evaluation indicator of instruction set compatibility are 90 and 95 respectively, then the second score of the primary evaluation indicator of instruction set compatibility is (90+95) / 2=92.5. In other embodiments, if the importance of the secondary evaluation indicators under the primary evaluation indicator is not the same, the weight of each secondary evaluation indicator is set by customization, and the weighted average is calculated according to the weight to obtain the second score. For example, if the weight of the serial communication interface supported protocol is set to 40% and the weight of the number of general input / output interfaces is set to 60% in the primary evaluation indicator of physical interface compatibility, and the first scores are 80 and 90 respectively, then the second score of the primary evaluation indicator of physical interface compatibility is 80×40% + 90×60% = 86.

[0037] The score of an evaluation domain is obtained by summing the second scores of all its primary evaluation indicators. In one embodiment, if the importance of each primary evaluation indicator under the evaluation domain is different, the weight of each primary evaluation indicator is set by customization, and a weighted average is calculated according to the weight to obtain the second score. For example, in the performance adaptability evaluation domain, if the performance weight is 40%, the memory access performance weight is 30%, and the data throughput weight is 30%, the second scores are 92.5, 86, and 90 respectively. Then, the weighted average of the second scores of the primary evaluation indicators is calculated according to the weight, and the third score of the performance adaptability evaluation domain is 92.5 × 40% + 86 × 30% + 90 × 30% = 89.8. In other embodiments, if the importance of each primary evaluation indicator under the performance adaptability evaluation domain is the same, that is, if no weight is set for each primary evaluation indicator (default equal weight), then the simple average of all primary evaluation indicators (92.5 + 86 + 90) / 3 ≈ 89.5 is taken as the third score of the performance adaptability evaluation domain.

[0038] Then, based on the third score values ​​of all evaluation domains obtained in step S302 and the weights of each evaluation domain set in step S301, the total substitutability score of the target chip is calculated. In one embodiment, the weights of each evaluation domain and the corresponding third score values ​​are shown in Table 3 below.

[0039]

[0040] Table 3 Overall score for the substitutability of the target chip The calculation formula is as follows: =1

[0041] in, The weights for each evaluation domain are given, and the weighted sum of all weights is 1. The third score for each evaluation domain is calculated to be Z = 87.5.

[0042] After obtaining the overall substitutability score of the target chip, the mapping table between its substitutability level and the range of the overall substitutability score is invoked, as shown in Table 4 below. Then, based on this mapping table and the obtained overall substitutability score of the target chip, the range of the overall substitutability score to which it belongs is located, and the corresponding substitutability level is matched according to the located range of the overall substitutability score.

[0043]

[0044] Table 4 It should be noted that this application also pre-sets different configuration templates for different business scenarios (such as industrial automation control scenarios, high-performance computing scenarios, and IoT scenarios). When a user selects a specific scenario, the configuration template adapted to that scenario will be automatically invoked. The configuration template includes a mapping table between the weights of each evaluation domain, the substitutability level, and the total substitutability score range, and can be adjusted appropriately. This aims to simplify user operations, make test configurations more closely match the actual needs of specific application scenarios, and improve testing efficiency and relevance.

[0045] As can be seen, the proposed chip replaceability testing method, by constructing a system covering six evaluation domains and multi-level indicators including hardware compatibility and functional adaptability, unifies testing dimensions and judgment standards. This solves the problems of fragmentation and incomparable results in traditional testing, making chip replaceability assessment systematic and reducing manual intervention. Furthermore, it enhances scenario adaptability by providing customized weight suggestions and scoring ranges through configuration templates, allowing users to customize adjustments. This ensures that the evaluation results align with actual needs, providing a basis for direct replacement and a quantitative reference for replacement schemes requiring modification and adaptation. This effectively reduces system replacement risks and improves the scientific and economical nature of chip selection and replacement.

[0046] Based on the same inventive concept, this application also provides a chip replaceability testing device. Since the principle of the device in this application is similar to the chip replaceability testing method described above in this application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0047] As per the instruction manual Figure 4 As shown in the illustration, this application also provides a chip replaceability testing apparatus, the apparatus comprising: Test module 401 is used to construct a chip replaceability test index system and test the target chip according to the replaceability test index system to obtain test result data. The replaceability test index system includes multiple evaluation domains, and each evaluation domain includes primary evaluation indexes and secondary evaluation indexes. Specifically, based on the chip replacement scenario requirements, six evaluation domains are determined: hardware compatibility, functional adaptability, performance adaptability, reliability, security, and software compatibility. Each evaluation domain is further refined into at least one primary evaluation index, and each primary evaluation index is further refined into at least one secondary evaluation index.

[0048] The scoring module 402 is used to determine the degree of substitutability requirement satisfaction for each of the secondary evaluation indicators based on the test result data, and to find the score range corresponding to the degree of substitutability requirement satisfaction according to a preset scoring comparison table. The rating module 403 is used to determine the total replaceability score of the target chip based on the weights set for each of the evaluation domains and the score range, and to determine the replaceability level of the target chip based on the total replaceability score.

[0049] In some embodiments, the scoring module 402 determines the degree to which the substitutability requirements of each of the evaluation secondary indicators are met based on the test result data, including: determining the substitutability benchmark requirements for each of the evaluation secondary indicators; comparing the test result data with the substitutability benchmark requirements one by one, and determining the degree to which the substitutability requirements of each of the evaluation secondary indicators are met based on the comparison results; the degree to which the substitutability requirements are met includes four categories: fully met, partially met, basically met, and not met.

[0050] In some embodiments, the rating module 403 determines the total substitutability score of the target chip based on the weights set for each of the evaluation domains and the score range, including: setting the weights for each of the evaluation domains; obtaining a second score value for the primary evaluation index by calculating the arithmetic mean of the first score values ​​of the secondary evaluation index; and obtaining a third score value for the evaluation domain by calculating the arithmetic mean of the second score values ​​of the primary evaluation index; wherein the median value of the score range of the secondary evaluation index is used as its first score value; and the total substitutability score of the target chip is calculated based on the third score value of the evaluation domain and the set weights.

[0051] In some embodiments, the rating module 403 determines the substitutability level of the target chip based on the total substitutability score, including: determining a mapping table between the substitutability level and the range of the total substitutability score; determining the range of the total substitutability score to which the target chip belongs based on the total substitutability score of the target chip, and obtaining the substitutability level of the target chip by comparing with the mapping table; the substitutability level includes four categories: complete replacement, functional replacement, no substitutability, and non-replaceable.

[0052] In some embodiments, the apparatus further includes: A preset module is used to pre-set different configuration templates for different business scenarios; the configuration template includes a mapping table between the weights, substitutability levels and total substitutability score ranges of each evaluation domain; based on the target configuration template being called, the mapping table between the weights, substitutability levels and total substitutability score ranges of the evaluation domain is determined or modified.

[0053] The chip replaceability testing apparatus described in this application constructs a chip replaceability testing index system through a testing module, and tests the target chip according to the replaceability testing index system to obtain test result data. The replaceability testing index system includes multiple defined evaluation domains, and each evaluation domain contains primary and secondary evaluation indicators. A scoring module determines the degree to which the replaceability requirements of each secondary evaluation indicator are met based on the test result data, and finds the score range corresponding to the degree of meetability requirements according to a preset scoring reference table. A rating module determines the total replaceability score of the target chip based on the weights set for each evaluation domain and the score range, and determines the replaceability level of the target chip based on the total replaceability score. Thus, by constructing a comprehensive chip replaceability testing index system, an automated testing process is achieved, custom weights are supported, testing efficiency and accuracy are improved, system replacement risks are reduced, and the needs of different scenarios are met.

[0054] Based on the same concept of the present invention, as shown in the appendix to the specification. Figure 5 As shown in the embodiment of this application, an electronic device 500 is provided. The electronic device 500 includes: at least one processor 501, at least one network interface 504 or other user interface 503, a memory 505, and at least one communication bus 502. The communication bus 502 is used to enable communication between these components. The electronic device 500 may optionally include a user interface 503, including a display (e.g., touchscreen, LCD, CRT, holographic imaging, or projector), a keyboard, or a clicking device (e.g., mouse, trackball, touchpad, or touchscreen).

[0055] Memory 505 may include read-only memory and random access memory, and provides instructions and data to processor 501. A portion of memory 505 may also include non-volatile random access memory (NVRAM).

[0056] In some implementations, memory 505 stores executable modules or data structures, or subsets thereof, or extended sets thereof: The 5051 operating system contains various system programs used to implement various basic business functions and handle hardware-based tasks. Application module 5052 contains various applications, such as launchers, media players, and browsers, to implement various application functions.

[0057] In this embodiment of the application, the processor 501 executes steps such as a chip replaceability test method by calling a program or instruction stored in the memory 505.

[0058] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs steps such as those in a chip replaceability testing method.

[0059] Specifically, the storage medium can be a general-purpose storage medium, such as a portable disk or hard drive. When the computer program on the storage medium is run, it can significantly improve the comprehensiveness, efficiency, and accuracy of chip replaceability testing, meeting the needs of different scenarios.

[0060] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and there may be other division methods in actual implementation. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the mutual coupling or direct coupling or communication connection shown or discussed may be through some communication interface, and the indirect coupling or communication connection of the apparatus or units may be electrical, mechanical, or other forms.

[0061] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0062] In addition, the functional units in the embodiments provided in this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0063] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0064] Finally, it should be noted that the above embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A method for testing chip replaceability, characterized in that, The method includes the following steps: A replaceability test index system for a chip is constructed, and the target chip is tested according to the replaceability test index system to obtain test result data; wherein, the replaceability test index system includes multiple evaluation domains, and each evaluation domain contains primary evaluation indexes and secondary evaluation indexes. Based on the test results data, determine the degree to which the substitutability requirements of each of the secondary evaluation indicators are met, and find the score range corresponding to the degree to which the substitutability requirements are met according to the preset scoring comparison table; The overall replaceability score of the target chip is determined based on the weights set for each of the evaluation domains and the score range, and the replaceability level of the target chip is determined based on the overall replaceability score.

2. The chip replaceability testing method according to claim 1, characterized in that, in, Based on the needs of chip replacement scenarios, six evaluation domains are determined: hardware compatibility, functional adaptability, performance adaptability, reliability, security, and software compatibility. Each evaluation domain is further refined into at least one primary evaluation indicator, and each primary evaluation indicator is further refined into at least one secondary evaluation indicator.

3. The chip replaceability testing method according to claim 1, characterized in that, Determining the degree to which the substitutability requirements of each of the secondary evaluation indicators are met based on the test result data includes the following steps: Determine the substitutability benchmark requirements for each of the aforementioned secondary evaluation indicators; The test results data are compared one by one with the substitutability benchmark requirements, and the degree to which the substitutability requirements of each of the secondary evaluation indicators are met is determined based on the comparison results; the degree to which the substitutability requirements are met includes four categories: fully met, partially met, basically met, and not met.

4. The chip replaceability testing method according to claim 1, characterized in that, Determining the total substitutability score of the target chip based on the weights assigned to each of the evaluation domains and the score range includes the following steps: Set the weights for each of the evaluation domains; The second score of the primary evaluation indicator is obtained by calculating the arithmetic mean of the first score values ​​of the secondary evaluation indicator; and the third score of the evaluation domain is obtained by calculating the arithmetic mean of the second score values ​​of the primary evaluation indicator; wherein the median value of the score range of the secondary evaluation indicator is used as its first score value. The overall replaceability score of the target chip is calculated based on the third score of the evaluation domain and the set weights.

5. The chip replaceability testing method according to claim 1, characterized in that, Determining the total substitutability score of the target chip based on the weights assigned to each of the evaluation domains and the score range includes the following steps: Set weights for each of the evaluation domains; wherein, a uniform weight is set for each of the evaluation domains, or a weight is set for each of the primary evaluation indicators under each evaluation domain; The second score of the primary evaluation indicator is obtained by calculating the arithmetic mean of the first score values ​​of the secondary evaluation indicator; and the third score of the evaluation domain, for which no weight is assigned, is obtained by calculating the arithmetic mean of the second score values ​​of the primary evaluation indicator; wherein the first score value of the secondary evaluation indicator is determined based on the median of its score range or its actual degree of satisfaction. The total substitutability score of the target chip is calculated based on the second score of the first-level evaluation indicator and the set weight, or the third score of the evaluation domain and the set weight.

6. The chip replaceability testing method according to claim 5, characterized in that, Determining the substitutability level of the target chip based on the overall substitutability score includes the following steps: Establish a mapping table between the substitutability level and the total substitutability score range; The substitutability score range of the target chip is determined based on its total substitutability score, and the substitutability level of the target chip is obtained by comparing it with the mapping table; the substitutability level includes four categories: complete replacement, functional replacement, no substitutability, and non-substitutable.

7. The chip replaceability testing method according to claim 6, characterized in that, The method further includes the following steps: Different configuration templates are preset for different business scenarios; the configuration template includes a mapping table between the weights of each evaluation domain, the replaceability level and the total replaceability score range; Based on the target configuration template invoked, determine or modify the mapping table between the weights of the evaluation domain, the substitutability level, and the total substitutability score range.

8. A chip replaceability testing device, characterized in that, The device: The testing module is used to construct a chip replaceability test index system and test the target chip according to the replaceability test index system to obtain test result data; wherein, the replaceability test index system includes multiple set evaluation domains, and each evaluation domain includes primary evaluation indexes and secondary evaluation indexes. The scoring module is used to determine the degree to which the substitutability requirements of each of the secondary evaluation indicators are met based on the test result data, and to find the score range corresponding to the degree to which the substitutability requirements are met according to a preset scoring reference table. The rating module is used to determine the total replaceability score of the target chip based on the weights set for each of the evaluation domains and the score range, and to determine the replaceability level of the target chip based on the total replaceability score.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of a chip replaceability testing method as described in any one of claims 1 to 7 are performed.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of a chip replaceability testing method as described in any one of claims 1 to 7.

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