Direct-current superconducting quantum interferometer simulator with reconfigurable all electrical parameters

Abstract

The invention discloses a direct current superconducting quantum interferometer simulator with reconfigurable all electrical parameters, which belongs to the field of superconducting electronics and weak magnetic signal detection, and comprises a circuit comprising a programmable logic device and capable of receiving a DC SQUID input signal and a model parameter and outputting a DC SQUID output voltage signal; the DC SQUID characteristic solver can be processed by a circuit comprising a programmable logic device, numerical parallel solving is carried out on the electrical differential equation set under given DC SQUID model parameters, a solving result is post-processed to obtain an actual DC SQUID output voltage signal, and the actual DC SQUID output voltage signal is stored in a memory of the circuit comprising the programmable logic device; and the DC SQUID output calculator can obtain a DC SQUID output voltage signal according to the DC SQUID input signal and a user setting parameter and output the DC SQUID output voltage signal to output equipment. The simulator can improve the DC SQUID reading and control electronics research and development and test efficiency.

Description

Technical Field

[0001] This invention belongs to the fields of superconducting electronics and weak magnetic signal detection, and specifically relates to a DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters for readout and control verification of DC superconducting quantum interference devices. Background Technology

[0002] A superconducting quantum interference device (SQUID) is a type of magnetic sensor with extremely high sensitivity that operates at low temperatures, constructed using the Josephson structure. By converting the signal to be measured into a magnetic signal, the SQUID can achieve highly sensitive measurements of the physical signal being measured and has been widely used in many fields such as high-energy physics, quantum computing, geophysics, and medicine.

[0003] A superconducting quantum interference device (SQUID) consisting of two Josephson junctions connected in parallel operates under DC bias and is also known as a DC superconducting quantum interference device (DC SQUID). Compared to other types of SQUIDs, it achieves higher sensitivity. A DC SQUID is a nonlinear device; the relationship between the magnetic flux detected by the DC SQUID and its output voltage (hereinafter referred to as the transfer characteristic curve) differs under different DC bias currents. Under an appropriate DC bias current, the transfer characteristic curve of a DC SQUID exhibits periodicity, with a period equal to one magnetic flux quantum. By selecting a suitable quiescent operating point, the DC SQUID can detect the magnetic flux signal and amplify it to output a voltage signal.

[0004] Based on the physical characteristics of DC SQUID, such as Figure 1 As shown, the readout and control electronics of a DC SQUID can typically be divided into the following parts according to their functions: DC SQUID bias section, DC SQUID output voltage signal readout section, and DC SQUID feedback section; among which, the DC SQUID bias section includes the DC SQUID's... , , The bias, where The bias current of a DC squuid determines its transfer characteristic curve. Furthermore, and These are the bias voltage and bias flux of the DC SQUID, respectively. The biasing of these two physical quantities is used to adjust the quiescent operating point of the DC SQUID on this transfer curve. The DC SQUID biasing section in readout and control electronics, through the biasing of these three electrical quantities, enables the DC SQUID to operate at a quiescent operating point with a high flux-to-voltage conversion factor (hereinafter referred to as...). , , The definitions are the same as above); the DCSQUID output voltage signal readout section mainly consists of a low-noise amplifier (LNA), which is used to amplify and read out the DC SQUID output voltage signal. The output voltage signal is... The DC SQUID feedback section consists of a feedback circuit, often referred to as a flux lock loop (FLL). The signal generated by the feedback circuit will pass through a resistor. and inductor A feedback magnetic flux signal is generated and coupled into the DC SQUID. This part is used to perform negative feedback on the DC SQUID to increase its dynamic range. It should be noted that, considering the actual readout circuit structure, the bias of the DC SQUID typically... and The bias is not applied directly to the DC SQUID, but rather indirectly to the DC SQUID's static operating point by applying the DC SQUID output voltage signal readout and DC SQUID feedback functional modules.

[0005] In the verification and testing of DC SQUID readout and control electronics, the verification of electronic feedback functionality is particularly important. It is necessary to verify the level of control the electronics have over this nonlinear controlled object. Directly co-tuning readout and control electronics with DC SQUIDs typically encounters the following difficulties: Low-critical-temperature DC SQUIDs with better signal-to-noise ratios usually require testing in a cryogenic environment at the liquid helium level. Liquid helium is a non-renewable resource and expensive, resulting in high testing costs. Even with high-critical-temperature DC SQUIDs, it is difficult to obtain a cryogenic environment suitable for their normal operation under typical electronic testing conditions. In a single test, the DC SQUID needs to be slowly transferred from room temperature to the cryogenic end, resulting in a long testing time. DC SQUIDs are highly susceptible to electromagnetic interference in the environment, requiring extremely stringent testing conditions. These testing difficulties significantly impact and limit the development and testing of readout and control electronics.

[0006] Due to the aforementioned testing limitations, using a DC SQUID simulator to simulate the actual behavior of a DC SQUID is a common method in the research and development, feedback algorithm optimization, and verification of DC SQUID readout and control electronics. Using a DC SQUID simulator for integrated testing of readout and control electronics allows for rapid functional testing of the system under typical electronics testing conditions, enabling the evaluation of the readout and control electronics feedback functionality.

[0007] Currently, DC SQUID simulators can be implemented using either analog circuits or digital circuits.

[0008] In analog circuit schemes, adders, with operational amplifiers at their core, are often used as analog substitutes for DC SQUIDs. One input signal of the adder is equivalent to the magnetic flux signal or current signal input to the DC SQUID (if understood as a current signal, this current signal is coupled to the DC SQUID through an inductor), and the other input signal is equivalent to the feedback current signal input to the DC SQUID (again, the feedback current signal is coupled to the DC SQUID through an inductor), and the output signal of the adder serves as the output voltage signal of the DC SQUID. However, the method of using adders to simulate DC SQUIDs in analog circuit-based DC SQUID simulators cannot reflect the nonlinear characteristics of DC SQUIDs, resulting in unclear physical meaning and representing a relatively crude simulation method. To introduce the nonlinear characteristics of DC SQUIDs, a signal generator can be introduced into the above foundation, but this still suffers from low integration, poor flexibility, and poor model accuracy.

[0009] In digital circuit solutions, microprocessors and field-programmable gate arrays (FPGAs) typically serve as the core of a DC SQUID simulator, equipped with necessary analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). The input signal of the ADC is equivalent to the magnetic flux or current signal detected by the DC SQUID, while the output signal of the DAC is equivalent to the voltage signal output by the DC SQUID. The system pre-stores the transfer characteristic curve of the DC SQUID in the memory of the microprocessor or FPGA. After the input signal is acquired and quantized by the ADC, a lookup table operation is performed in the memory to obtain the corresponding output voltage signal, which is then sent to the DAC output. The transfer characteristic curve and related parameters stored in the system can be configured via serial port download. In current technical solutions, the transfer characteristic curve configuration in memory typically falls into two categories: a standard sine curve and a measured DC SQUID transfer characteristic curve.

[0010] Current digital DC-SQUID simulators can describe the nonlinear characteristics of DC-SQUIDs, but they still have the following drawbacks: The model is coarse; the transfer characteristic curve of an actual DC-SQUID differs significantly from the sine function curve, making the use of a sine function for a crude description of a DC-SQUID; the model is incomplete; the transfer characteristic curve of an actual DC-SQUID is affected by... The static operating point is controlled by the static operating point. and The control is not considered; simply storing the transfer characteristic curve and using a lookup table method does not take into account... The current modeling approach for DC SQUIDs lacks a degree of freedom and flexibility. To test multiple DC SQUIDs with different parameters, multiple sets of transfer characteristic curves for each DC SQUID are required, necessitating extensive preliminary work and time-consuming adjustments. Besides the problems with the modeling method, current digital DC SQUID simulators require communication with a host computer to fully describe the characteristics of the DC SQUID, resulting in low integration and inconvenience.

[0011] Therefore, most of the DC SQUID simulators implemented at this stage suffer from problems such as poor model accuracy, poor completeness, poor flexibility, and poor integration. The problem that needs to be solved is how to achieve a DC SQUID simulator with high accuracy, high completeness, high flexibility, and high integration, so as to facilitate the design and testing of DC SQUID readout and control electronics.

[0012] In view of this, the present invention is hereby proposed. Summary of the Invention

[0013] The purpose of this invention is to provide a DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters, which can flexibly and accurately provide DC SQUID models. It has short computation time, high system integration, and high model completeness, which can improve the efficiency of DC SQUID readout and control electronics research and development and testing, thereby solving the above-mentioned technical problems existing in the prior art.

[0014] The objective of this invention is achieved through the following technical solution: A fully electrically reconfigurable DC superconducting quantum interference device simulator, comprising: A circuit containing programmable logic devices, including input devices, output devices and interactive devices, is capable of receiving external magnetic flux signals input through the input devices and parameters of a DC SQUID model set through the interactive devices, and outputting actual DC SQUID output voltage signals through the output devices. The DC SQUID characteristic solver can use circuits containing programmable logic devices to process the numerical parallel solution of the electrical differential equations satisfied by the DC SQUID under the given parameters of the DC SQUID model. The solution results are then post-processed to obtain the DC SQUID output voltage signal and stored in the memory of the circuit containing programmable logic devices. The DC SQUID output calculator can obtain the net input magnetic flux signal corresponding to the external magnetic flux signal based on the external magnetic flux signal received by the circuit containing programmable logic devices and the user-defined parameters. It then searches for the corresponding DC SQUID output voltage signal in the memory of the circuit containing programmable logic devices according to the net input magnetic flux signal. The difference between the DC SQUID output voltage signal and the DC SQUID voltage bias signal is used to obtain the actual DC SQUID output voltage signal. Finally, the actual DC SQUID output voltage signal is output to the output device of the circuit containing programmable logic devices.

[0015] Compared with existing technologies, the fully electrically reconfigurable DC superconducting quantum interference device simulator and method provided by this invention have the following advantages: By employing a circuit containing programmable logic devices and combining it with a DC SQUID characteristic solver, the equations satisfied by the adopted DC SQUID can be solved numerically and in parallel. The solution results are post-processed to obtain the actual DC SQUID output voltage signal and stored in the memory of the circuit containing programmable logic devices. The actual DC SQUID output voltage signal can then be obtained in conjunction with a DC SQUID output calculator. This DC SQUID simulator offers a variety of DC SQUID models, with significantly improved accuracy, completeness, and flexibility compared to previous DC SQUID models. By segmenting the solution time, it transforms equations with strong dependencies into a parallel computing format suitable for segmented pipelined computation of circuits containing programmable logic devices (PLDs). This leverages the computational advantages of PLDs, enabling rapid modification and updates of DC SQUID features with high throughput, further reducing the time overhead in DC SQUID readout and control electronics testing. Since the DC SQUID simulator's computation process is entirely implemented within the PLD circuits and is equipped with interactive devices, it eliminates the need for a host computer. Users can control the simulator and acquire its status through the onboard interactive devices, achieving an integrated simulator that improves system integration and ease of use. This DCSQUID simulator can perform tests on DC SQUID readout and control electronics, especially feedback control functions, under general electronic testing conditions. It can reduce costs and improve testing efficiency in the R&D, feedback algorithm optimization, and device verification stages of DC SQUID readout and control electronics. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the readout and control electronics structure of a DC SQUID for magnetic measurement in the prior art.

[0018] Figure 2 This is the electrical structure diagram of a DC SQUID based on the RCSJ model.

[0019] Figure 3This is a schematic diagram of the segmented excitation signal of a DC superconducting quantum interference device simulator with reconfigurable electrical parameters, using a ramp signal as an example, provided in an embodiment of the present invention. The even-numbered dashed lines (2nd, 3rd, 6th, 8th, and 10th) from left to right represent the five equal-division lines of the excitation signal start point and the set excitation signal end point. The intersection time of each signal segment (including the extended portion of the last signal segment) is the same, i.e., the distances between segments 2, 3, 4, 5, 6, 7, 8, 9, 10, and 11 are the same. A represents the excitation signal start point; B represents the set excitation signal end point; and C represents the actual excitation signal end point.

[0020] Figure 4 A schematic diagram of the circuit structure of a DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters provided in an embodiment of the present invention.

[0021] Figure 5 A flowchart illustrating the implementation method of a DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters provided in this embodiment of the invention.

[0022] Figure 6 The parallel variables of the fully electrically reconfigurable DC superconducting quantum interference device simulator provided in this embodiment of the invention. Schematic diagram of parallelization of numerical solution.

[0023] Figure 7 A schematic diagram of segmented pipeline calculation for a DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters provided in an embodiment of the present invention.

[0024] Figure 8 This is a flowchart illustrating the operation of a DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters, as described in an embodiment of the present invention. Detailed Implementation

[0025] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the specific content of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments, which do not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present invention.

[0026] First, the following explanations are provided for the terms that may be used in this article: The term "and / or" means that either or both can be achieved simultaneously. For example, X and / or Y means that it includes both "X" or "Y" as well as the three cases of "X and Y".

[0027] The terms "comprising," "including," "containing," "having," or other similar semantic descriptions should be interpreted as non-exclusive inclusion. For example, including a technical feature element (such as raw material, component, ingredient, carrier, dosage form, material, size, part, component, mechanism, device, step, process, method, reaction conditions, processing conditions, parameter, algorithm, signal, data, product or article of manufacture, etc.) should be interpreted as including not only the expressly listed technical feature element, but also other technical feature elements that are not expressly listed and are well-known in the art.

[0028] The term "composed of" excludes any technical features not expressly listed. When used in a claim, it closes the claim to exclude all technical features other than those expressly listed, except for associated conventional impurities. If the term appears only in a clause of a claim, it limits the claim to the elements expressly listed in that clause; elements recited in other clauses are not excluded from the overall claim.

[0029] Unless otherwise explicitly specified or limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this document according to the specific circumstances.

[0030] When concentration, temperature, pressure, size, or other parameters are expressed as numerical ranges, such ranges should be understood to specifically disclose all ranges formed by any pairing of upper limits, lower limits, or preferred values ​​within that range, regardless of whether the range is explicitly stated; for example, if the numerical range "2 to 8" is stated, then that range should be interpreted to include ranges such as "2 to 7", "2 to 6", "5 to 7", "3 to 4 and 6 to 7", "3 to 5 and 7", "2 and 5 to 7", etc. Unless otherwise stated, the numerical ranges described herein include both their endpoints and all integers and fractions within that range.

[0031] The terms “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “back,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” “outer,” “clockwise,” and “counterclockwise” indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience and simplification of description and do not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this document.

[0032] The solution provided by this invention will be described in detail below. Contents not described in detail in the embodiments of this invention are prior art known to those skilled in the art. Where specific conditions are not specified in the embodiments of this invention, they shall be performed according to conventional conditions in the art or conditions recommended by the manufacturer. Reagents or instruments used in the embodiments of this invention whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0033] See Figure 4 This invention provides a fully reconfigurable DC superconducting quantum interference device (CQUID) simulator. This DC SQUID simulator can flexibly and accurately provide DC SQUID models, can be used independently of a host computer, and features short computation time, high system integration, and high model completeness. It can improve the efficiency of DC SQUID readout and control electronics research and development and testing, including: A circuit containing programmable logic devices, including input devices, output devices and interactive devices, is capable of receiving external magnetic flux signals input through the input devices and parameters of a DC SQUID model set through the interactive devices, and outputting corresponding DC SQUID output voltage signals through the output devices. The DC SQUID characteristic solver can use circuits containing programmable logic devices to process and numerically solve the electrical differential equations satisfied by the corresponding DC SQUID under the given parameters of the DC SQUID model. The solution results are post-processed to obtain the corresponding DC SQUID output voltage value and stored in the memory of the circuit containing programmable logic devices. The DC SQUID output calculator can obtain the net input magnetic flux signal corresponding to the external magnetic flux signal based on the external magnetic flux signal received by the circuit containing programmable logic devices and the user-defined parameters. Based on the net input magnetic flux signal, it searches for the corresponding DC SQUID output voltage signal in the memory of the circuit containing programmable logic devices, calculates the difference between the output voltage signal and the voltage bias signal of the SQUID to obtain the actual DC SQUID output voltage signal, and outputs the actual DC SQUID output voltage signal to the output device of the circuit containing programmable logic devices.

[0034] Preferably, in the above simulator, the circuit containing the programmable logic device includes: a programmable logic device, a multi-channel ADC as an input device, a single-channel DAC as an output device, a memory, and an interactive device; wherein, The multi-channel ADC, as an input device, is electrically connected to the input terminal of the programmable logic device to input external magnetic flux signals; One of the DACs, serving as an output device, is electrically connected to the output terminal of a programmable logic device to output a DCSQUID output voltage signal. The memory is electrically connected to the storage terminal of the programmable logic device and can store the corresponding DC SQUID output voltage value obtained by the DC SQUID characteristic solver. The interactive device is electrically connected to a programmable logic device and can be used to set the parameters of the DC SQUID model.

[0035] Preferably, in the above simulator, the programmable logic device is an FPGA chip or a system-on-a-chip that includes programmable logic. The memory is an external memory or a memory in a programmable logic device.

[0036] As can be seen, the aforementioned hardware circuitry requires external components to enable these components to function properly.

[0037] Preferably, in the above simulator, the DC SQUID characteristic solver utilizes a circuit containing programmable logic devices to process data in a numerical parallel manner under given DC SQUID model parameters, and obtains the DC SQUID output voltage signal after data processing of the solution results, including: Step 1: Determine the solution time step, discretize the electrical differential equations satisfied by DC SQUID, transform the continuous time model into a discrete numerical solution, simplify the iterative operations involved in the difference equations, and obtain the simplified difference equations; this can reduce computational dependence and facilitate parallel operation. Step 2: Solve the constant operation terms in the simplified difference equation in advance, including the magnetic flux quantum and the division between the solution time steps; avoid repeatedly calculating the constants in subsequent calculations. Step 3: Based on the magnitude of each parameter of the solution time step, select the units to use for all physical quantities in the equations obtained from the above processing; avoid situations where the numerical values ​​of physical quantities in the difference equations have large differences in magnitude. Step 4: Select the data format for the physical quantities involved in the difference equation, and implement data fixed-pointing according to the selected data format; the selected data format needs to have sufficient accuracy to ensure solution convergence, and also needs to have a sufficient range of representation to complete the above physical quantities; Step 5: Calculate the sine function in the equation using a lookup table. Set up a read-only memory in the circuit containing programmable logic devices, use the input of the sine function as the address, and use the stored value as the calculated value of the sine function. Step 6: Convert the division operation in the simplified difference equation into a multiplication operation, and parallelize all multiplication, addition and sine taking operations that have no data dependency in the single calculation of the difference equation, so as to realize the parallelization of numerical solution and form a calculation process of one iteration of the difference equation. Step 7: Implement the above calculation process using time-segment decomposition and segment parallel calculation according to the calculation flow obtained in Step 6, and calculate the corresponding DC SQUID output voltage signal.

[0038] Preferably, in the simulator described above, in step 1, the given DC SQUID model solved by the DC SQUID characteristic solver is a DC SQUID based on the RCSJ model (Resistively and Capacitively Shunted Junction model), consisting of a feedback-free circuit formed by a left Josephson junction and a right Josephson junction connected in parallel, and its circuit structure is as follows: Figure 2 As shown, the DC SQUID satisfies the following set of electrical differential equations: ; In the above formula, and These represent the current flowing through the left Josephson junction and the right Josephson junction of the DC SQUID, respectively. This is the bias current of the DC SQUID; and These represent the contributions of the left and right Josephson junctions of the DC SQUID to the loop inductance of the DC SQUID, respectively. and The sum of these constitutes the loop inductance of the DC SQUID; The input is the external magnetic flux signal; It is the quantum of magnetic flux; The phase difference of the wave functions of the two superconductors that form the left Josephson junction. The phase difference of the wave functions of the two superconductors that form the right Josephson junction; It can be any integer; and These are the capacitances of the left and right Josephson junctions, respectively. and These are the resistances of the left Josephson junction and the right Josephson junction, respectively. and These are the critical currents of the left and right Josephson junctions, respectively. For time;

[0039] Preferably, to facilitate the processing of the equations, the parameters in the above model can be further constrained. ,make ; Furthermore, when using the above model to describe a DC SQUID, the input external magnetic flux signal and the bias current of the DC SQUID are considered to be slowly varying physical quantities. The direct impact of changes in these two physical quantities on the output voltage can be ignored. The output voltage of the DC SQUID... Written as: ; The electrical differential equations satisfied by the DC SQUID based on the RCSJ model are discretized, transforming the continuous-time model into a discrete numerical solution. The iterative operations involved in the difference equations are simplified to obtain the simplified difference equations.

[0040] Preferably, the above electrical differential equations are discretized using the explicit Euler scheme, which has lower computational complexity. The discretization results are as follows: ; In the above formula, The time step chosen when discretizing the differential equation; the variables in the above equation Written as: ; The above variables The subscript or These are all discrete independent variables introduced during the transformation from differential equations to difference equations, and they are all integers, i.e.: ; The remaining variables in the simplified difference equation above are defined in the same way as the corresponding variables used in the electrical differential equations satisfied by DC SQUID based on the RCSJ model.

[0041] Preferably, the RCSJ model used above can be simplified to an RSJ model. Under this condition, the capacitance effect in the RCSJ model used to describe DCSQUID can be ignored, thus transforming it into an RSJ model. Eliminating the capacitance terms in the above equation, the electrical differential equations satisfied by the DC SQUID based on the RSJ model are as follows: ; The variables in the above equation have the same definition as the corresponding variables used in the set of electrical differential equations satisfied by DC SQUID based on the RCSJ model.

[0042] Preferably, to facilitate the processing of the equations, the parameters in the above model can be further constrained. ,make ; Furthermore, when using the RSJ model described above to describe the DC SQUID, the input external magnetic flux signal and bias current are considered to be slowly varying physical quantities, and the direct impact of the changes in these two variables on the output voltage can be ignored. The output voltage of the DC SQUID can be written as: ; The electrical differential equations satisfied by the DC SQUID based on the RSJ model are discretized, transforming the continuous-time model into a discrete numerical solution. The iterative operations involved in the difference equations are simplified to obtain the simplified difference equations.

[0043] Preferably, the above system of differential equations is discretized using the explicit Euler scheme, which has lower computational complexity. The discretization results are as follows: ; In the above formula, The time step chosen when discretizing the differential equation; The above variables The subscript or These are all discrete independent variables introduced during the transformation from differential equations to difference equations, and they are all integers, i.e.: ; The remaining variables in the simplified difference equation above are defined in the same way as the corresponding variables used in the electrical differential equations satisfied by DC SQUID based on the RCSJ model.

[0044] Preferably, in the above set of equations, the model can be simplified in a targeted manner according to the actual application requirements to reduce computational complexity.

[0045] Preferably, for convenience in the above solution process, the gain of the low-noise amplifier in electronics is multiplied into the output voltage of the above difference equation in advance.

[0046] Preferably, in the simulator described above, in step 8, the DC SQUID characteristic solver implements the above calculation process according to the calculation flow obtained in step 7, using a time-time decomposition and segmented parallel computing method, including: Time-segment decomposition computation and segmented parallel pipeline computation; among which... The time period decomposition calculation method is as follows: The DC SQUID characteristic solver analyzes the number of clock cycles required for a single calculation of the difference equation based on the parallel processing analysis of the difference equation. If the analysis shows that the number of clock cycles required for a single recursion is... The solution time will then be... Divided into A time period , The first time period The start time of each time period is written as... (For ease of explanation, the solution time step is not considered here.) It should be noted that, in principle, the following is true. It can be any positive integer, but it must satisfy the following conditions: Only under certain conditions can the computational advantages of programmable logic devices be fully utilized in this problem.

[0047] The method for calculating the segmented parallel pipeline is as follows: The DC SQUID characteristic solver is divided into segments. and number of segments Parallel pipelined computation is performed on each of the decomposed time periods in both cases; the number of segments... In the first case, data for the first time period and the corresponding excitation signal are sent in during the first clock cycle, data for the second time period and the corresponding excitation signal are sent in during the second clock cycle, and so on, until the... After one clock cycle, the result of the second time point in the first time period is calculated, and this data, along with the excitation signal at that moment, is sent into the calculation process to continue calculating the result of the third time point in the first time period. After one clock cycle, the second time point of the second time period is calculated and combined with the excitation signal at the current moment for subsequent iterations, so as to realize the parallel calculation of the output voltage of each time period under the same set of hardware solution resources; In the number of segments In the second case, based on the calculation process of the first case, maintain a length of The first-in-first-out (FIFO) register caches the iterative solution quantities of the equation, where... This solution method can extend the number of clock cycles required for the entire solution process to... This allows it to form the same computational structure as the first case for performing calculations.

[0048] The DC SQUID characteristic solver also includes a segmented excitation signal generator to provide excitation signals for parallel pipeline calculations in each time period. It can receive external magnetic flux signals input to the model described above. The number of segments in the excitation signal is consistent with the number of segments in the segmented solution of the DC SQUID characteristic solver. Each output interface of the segmented excitation signal generator outputs the waveform of the corresponding segment. The segmented excitation signal generator outputs the above segments in turn for calculation in each time period. Furthermore, the excitation signals in the segmented excitation signal generator have a certain intersection to facilitate subsequent splicing of the segmented calculation results. The form of this intersection is: the last segment of the current signal segment is the same as the first segment of the next signal segment; the last segment of the last signal segment is the same as the first segment of the first signal segment; and the intersection time of all intersecting signal segments (i.e., the duration of the same portion of the current and next signal segments) is the same. The specific intersection time of the segmented excitation signal generator is determined by the group delay of the digital low-pass filter that subsequently filters the results. The intersection time should be greater than the group delay of the digital low-pass filter to ensure that there is no abrupt change at the splicing point when concatenating the results. To implement the above-mentioned segmented excitation signal generator, the last segment of the segmented excitation signal generator needs to be extended accordingly. The extension length is equal to the intersection time of the segmented excitation signal generator, and the extended signal is the same as the starting segment signal of the first segment. The specific waveform of the excitation signal is not limited, but a ramp signal is a better choice. Taking a five-segment ramp excitation signal as an example, its waveform segmentation diagram is shown below. Figure 3 The excitation signals for each time period have the same meaning. Taking the excitation signal for time period 1 as an example, it means that the excitation signal for time period 1 is used for calculation within the time period that is divided into time periods in the solution of time periods.

[0049] Preferably, in the simulator described above, the duration of the excitation signal is not limited in principle, but for convenience, the duration of the excitation signal (including the extension time of the last segment of the signal) is set to the total solution time T of the electrical differential equations satisfied by DC SQUID.

[0050] Preferably, in the simulator described above, when scanning the transfer characteristic curve of the external magnetic flux signal input to the excitation signal, the conditions that the intersection of two adjacent segments of the segmented excitation signal generator (including the signals at the beginning and end) must meet can be either completely identical or relaxed to be related to the magnetic flux quantum. The remainders are the same. To facilitate the calculation of the DCSQUID output voltage signal, the scanning range of the input magnetic flux can be set to... .

[0051] Preferably, each segment of the above differential equation system is solved using zero initial conditions. For the RCSJ model, the zero initial conditions are: ; All variables in the above equation have the same definitions as the corresponding variables used in the set of electrical differential equations satisfied by DC SQUID based on the RCSJ model.

[0052] For the RSJ model, the following zero initial conditions are used for solving each segment: ; All variables in the above formula have the same definitions as the corresponding variables used in the RSJ model description of DC SQUID.

[0053] Preferably, during the solution process of each segment of the above differential equation system, all physical quantities except those connected to the segmented excitation signal generator are maintained at the set values ​​during the solution process.

[0054] Preferably, in the simulator described above, after step 8, the DC SQUID characteristic solver sends the calculated output voltage signal to a digital low-pass filter designed in the programmable logic device to filter out high-frequency oscillation signals, thereby obtaining the required corresponding DC SQUID output voltage signal. The output voltage signal of the digital low-pass filter, which serves as the corresponding DC SQUID output voltage signal, is then segmented and stored in the memory of the programmable logic device (e.g., Block Random Access Memory, BRAM).

[0055] Preferably, in the simulator described above, the digital low-pass filter is a multi-channel parallel low-pass filter capable of achieving data refresh in a single clock cycle. The multi-channel parallel low-pass filter can simultaneously perform low-pass filtering on the results of the segmented solution, obtaining the characteristics of DC SQUID while avoiding data compression.

[0056] Preferably, in the above simulator, the DC SQUID characteristic solver performs post-processing on the output voltage signal of the digital low-pass filter, which is segmented and stored in the on-chip memory of the programmable logic device, in the following manner: The segmented output voltage signals are spliced ​​and aligned, and the splicing positions of each segment of the output voltage signal are marked. The output voltage signal alerts to any overflow in the calculation results and marks the location of the data overflow. (With proper data format selection, the DC SQUID parameter used in practice usually does not cause data overflow.) When scanning the transfer characteristic curve, the DC SQUID characteristic solver performs period conversion on the period of the transfer characteristic curve to obtain the representation of the period of the transfer characteristic curve (i.e., one magnetic flux quantum) under the selected data format.

[0057] Preferably, in the simulator described above, the DC SQUID output calculator obtains the output voltage signal based on the transfer characteristic curve obtained by the DC SQUID characteristic solver, user-defined parameters, and ADC sampling values. This part calculates the net input flux signal based on the input signals of the multiple ADCs and the various user-defined parameters. Then, based on this net input flux signal, it searches the memory for the DC SQUID output voltage signal (if the net input flux signal exceeds the scanning range of the DC SQUID characteristic solver, auxiliary calculation is performed using the periodic characteristics of the DC SQUID). The output voltage signal is then compared with the bias voltage of the DC SQUID. The actual output voltage signal of the DC SQUID is obtained by subtracting the voltages, and finally the signal is output to the DAC.

[0058] In summary, the DC SQUID simulator provided by this invention can perform tests on DC SQUID readout and control electronics, especially feedback control functions, under general electronic testing conditions. This reduces costs and improves testing efficiency during the R&D, feedback algorithm optimization, and device verification stages of DC SQUID readout and control electronics. Furthermore, the underlying principle of this DC SQUID simulator is the RCSJ model, which has clear physical meaning, is easy to configure and use, and can provide multiple DC SQUID models. The accuracy, completeness, and flexibility of these models are significantly improved compared to previous DC SQUID models. On the other hand, this invention provides a method for solving the RCSJ model on a programmable logic device. By segmenting the solution time, the equation with strong dependencies is transformed into a parallel computing format suitable for segmented pipelined computation on a programmable logic device. This leverages the computational advantages of the programmable logic device, enabling rapid modification and updating of DC SQUID characteristics with high throughput, further reducing the time overhead in DC SQUID readout and control electronics testing. In addition, the DC SQUID simulator computation process described in this invention is entirely implemented within the programmable logic device of the electronics and is also equipped with an interactive device. It does not require a host computer, and users can control the simulator and obtain its status through the onboard interactive device, realizing an integrated simulator, improving system integration and making it more convenient to use.

[0059] Based on the RCSJ model or its simplified RSJ model, a DCSQUID simulator with fully reconfigurable electrical parameters is proposed. This simulator can accurately simulate the operating characteristics of DCSQUID and be used for electronic testing by flexibly specifying the DC SQUID construction parameters and bias parameters.

[0060] To more clearly demonstrate the technical solution and its effects provided by the present invention, the following detailed description of the solution provided by the embodiments of the present invention is provided with reference to specific examples.

[0061] Example 1 For ease of technical description, the DC SQUID in the following embodiments refers to a DC SQUID described by the RSJ model, which is simplified from the RCSJ model, and consists of two Josephson structures with identical parameters. It should be noted that the method, apparatus, and claims proposed in this invention are compatible with the situation described by the RCSJ model, and a DC SQUID simulator based on the RCSJ model can be realized after modifying the equations. Using the method described in this invention to model DC SQUID using the RCSJ model should also be included within the scope of this invention.

[0062] For ease of technical description, the following embodiments use FPGA as an example. It should be emphasized again that, as described in the technical content, the choice of specific programmable logic device does not affect the core of this invention. Using other types of programmable logic devices or System-on-Chip (SoC) chips containing programmable logic to construct the simulator should also be considered part of this invention.

[0063] An example of constructing a DC SQUID transfer characteristic curve for a symmetric DC SQUID simulator is shown below, and its configuration is as follows: Figure 4As shown, the circuit includes a programmable logic device, a DC SQUID characteristic solver, and a DC SQUID output calculator. A circuit containing programmable logic devices provides the actual electronic entities for the DC SQUID simulator. It receives external magnetic flux signals from the input device and DC SQUID model parameters set via an interactive device, and outputs the corresponding DC SQUID output voltage signal via the output device. A DC SQUID characteristic solver, based on the DC SQUID to be constructed, performs numerical parallel solution of the DC SQUID equations under given DC SQUID model parameters through analysis, numerical discretization, numerical simplification, parallelization, pipelined processing, excitation signal generation, and data post-processing. The solution results are then post-processed to obtain and store the actual DC SQUID output voltage signal. A DC SQUID output calculator calculates the output voltage signal of the constructed DC SQUID. This part calculates the DC SQUID output voltage signal based on the input external magnetic flux signal and the generated DC SQUID model, and outputs it to the output device of the circuit containing programmable logic devices.

[0064] The overall implementation process of the simulator is as follows: Figure 5 As shown, it includes the following steps.

[0065] S1: In terms of hardware circuitry, the circuit containing programmable logic devices in this embodiment includes an FPGA chip, two ADCs, and one DAC. This example uses two ADCs and one DAC. Specifically, one ADC is configured to sample and quantize the signal detected by the DC SQUID; the other ADC is used to acquire the feedback signal for readout and control electronics. Optionally, more ADCs can be deployed to bias the DC SQUID signal. , , The acquisition process involves a DAC to output the response of a DC SQUID signal. Optionally, if there is no need to output a DC SQUID signal, a DAC may be omitted. Both the multiplexed ADC and DAC are connected to the FPGA. In addition, the circuitry of this embodiment is equipped with an interactive device for user interaction. This embodiment also includes other components necessary for the proper functioning of the above devices.

[0066] The aforementioned FPGA chip is used to process complex computation and control logic and connects to the ADC, DAC, and interactive devices mentioned above, using the BRAM inside the FPGA chip as memory.

[0067] S2: In solving the DC SQUID characteristic solver, this embodiment incorporates the readout and control electronics gains into the electrical differential equations satisfied by the DC SQUID. After appropriate transformation, while maintaining computational convergence, a suitablely large time step is used as the solution time step (generally on the picosecond scale; for ease of explanation, a specific time step of 1 picosecond is selected below). Specifically, the electrical differential equations satisfied by the DC SQUID based on the RSJ model are discretized using the explicit Euler scheme, resulting in the following equation: ; In the above formula, The phase difference of the wave functions of the two superconductors that form the left Josephson junction. The phase difference of the wave functions of the two superconductors that form the right Josephson junction; The resistance of a single Josephson junction in a DC SQUID; For discrete time intervals; This is the bias current of the DC SQUID; The contribution of a single Josephson junction to the DC SQUID loop inductance; The magnetic flux signal is an external input. The critical current for a single Josephson junction; It is the quantum of magnetic flux; For low-noise amplifier gain; To reduce computational dependency, the discretized difference equations are modified to address the following: and The iterative formula is further simplified, and the simplified result is shown in the following formula: .

[0068] S3: Regarding the solution of the DC SQUID characteristic solver, this embodiment further completes the solution involving magnetic flux quantum in advance. Solution time step as well as For multiplication and division operations, the relevant calculation results are treated as a whole constant in the calculation; taking a solution time step of 1 picosecond as an example, the specific steps are as follows: ; The calculation uses the International System of Units (SI), but other unit systems can also be used for calculation in advance. In addition, different calculation precisions will affect the calculation results, but even if the results are different, this does not affect the core of the invention.

[0069] S4: Regarding the solution of the DC SQUID characteristic solver, this embodiment further selects picoseconds, ohms, microamps, millivolts, picohens, and one magnetic flux quantum as the units for time, resistance, current, voltage, inductance, and magnetic flux, respectively, and designs the model parameters based on these units. It should be noted that the above unit selection is only an example; other unit selection methods can also be used to represent the equation with higher precision without affecting the core of the invention. In addition, all physical quantities in the hardware calculation logic use a 32-bit data width, and the data interpretation uses the Q15.16 fixed-point data format. It should be noted that there are multiple choices for the specific fixed-point format; other fixed-point formats can also be used as suitable data formats. Furthermore, for FPGAs with sufficient resources, floating-point data formats can also be selected. The specific data format does not affect the core of the invention.

[0070] S5: In terms of solving the DC SQUID characteristic solver, this embodiment further constructs a ROM in the FPGA for the lookup table calculation of the sine function.

[0071] S6: Regarding the solution of the DC SQUID feature solver, this embodiment further treats division as multiplication and decomposes the iterative operation process of the above equation system to parallelize the operation and form a single calculation flowchart. Specifically, regarding... See the parallelized iterative process. Figure 6 , The parallelized iterative process is similar to this.

[0072] S7: Regarding the solution of the DC SQUID feature solver, this embodiment further decomposes the solution time period according to the calculation flowchart obtained in step S6, dividing the time period to be solved into 5 segments (the number of segments here corresponds exactly to the number of clock cycles required for a single iteration), and performs segment-parallel pipelined calculation on each time period, simultaneously calculating the solutions for multiple time periods. The pipeline operation is illustrated as follows: Figure 7 As shown. It should be noted that the specific number of segments can be any integer, but the advantages of the FPGA can be maximized when the number of segments is greater than or equal to the number of clock cycles required for a single iteration. For ease of explanation, the number of segments is chosen to be equal to the number of clock cycles required for a single iteration. The technical content section of this invention describes the handling of different segment number selections; the specific segment number selection does not affect the core of this invention.

[0073] S8: Regarding the solution of the DC SQUID characteristic solver, further, in this embodiment, a segmented excitation signal generator is designed and implemented in the FPGA to provide excitation signals for the segmented parallel pipeline calculation, with 5 segments (consistent with the number of segments in step S7). An optional approach is to design a segmented ramp signal generator. The segmented excitation signal generated by this generator is connected to the input external magnetic flux signal, and the start signal of its numerical solution is used as the enable signal for the segmented excitation signal.

[0074] S9: Regarding the piecewise solution of the DC SQUID characteristic solver, further, the above difference equations are solved using zero initial conditions, and physical quantities other than the input external magnetic flux signal are kept at a set constant. The zero initial conditions involved in this step are as follows: .

[0075] S10: Regarding the solving of the DC SQUID characteristic equation, this embodiment further incorporates a low-pass filter designed in the FPGA to filter the voltage signal obtained from solving the DC SQUID equation. The filtered signal is written into the FPGA's BRAM. Optionally, to improve readability and adapt to the solution process, the low-pass filter can be designed as a five-channel low-pass filter (the number of channels corresponds to the number of segments), and the memory can be divided into multiple memory blocks. Specific filter types and storage structures do not affect the core of this invention.

[0076] S11: In terms of solving the DC SQUID characteristic solver, further, the data calculated in step S10 is analyzed and spliced ​​in the FPGA, the splicing address of the BRAM is marked, and the data overflow position is marked; in addition, the period conversion logic is designed to calculate the period of the output transfer characteristic curve. Optionally, in S4, a reasonable selection of the unit of magnetic flux can simplify the period conversion logic.

[0077] S12: Regarding the output of the DC SQUID output calculator, the FPGA calculates the net input flux signal based on the ADC input signal and user-defined parameters. It then looks up the net input flux signal in a table in the BRAM. If, during the lookup process, the total flux exceeds one period of the DC SQUID transfer characteristic curve, the curve period calculated in S11 is used in conjunction with the lookup. The value obtained from the lookup is subtracted... The actual output voltage signal of the DC SQUID is then obtained, which can be output through a DAC.

[0078] Furthermore, it also includes the following steps: S13: Finally, in terms of system application, this embodiment uses FPGA to implement the interface logic of the interactive device to provide data interaction for users.

[0079] To further clarify the solution of this embodiment, the workflow of the simulator in this embodiment is given below, such as... Figure 8 As shown, it includes: Step P1: The user sets parameters through the interactive device. The device sends parameters such as the resistance of a single Josephson junction, the critical current of a single Josephson junction, the contribution of a single Josephson junction to the loop inductance, the bias current, the readout and control electronics gain, etc., to the FPGA of the circuit containing programmable logic devices in DC SQUID, and starts a DC SQUID numerical solution.

[0080] Step P2: The data obtained from the first solution is written into the BRAM of the FPGA after passing through a low-pass filter. The FPGA performs post-processing operations such as splicing and periodic calculation on the calculated curves.

[0081] Step P3: The FPGA calculates and outputs the post-processing results to the interactive device.

[0082] Step P4: The user sets the bias voltage via the interactive device. and bias flux .

[0083] Step P5: The FPGA starts processing the signal input from the ADC according to the set parameters, looks up the output voltage signal in the BRAM table and subtracts it. Then it is output to the DAC.

[0084] It is important to note that the parameter configuration in the above process does not have a specific order requirement. The only requirement is that the resistor, critical current, bias current, input inductor, readout, and control electronics gains are completed before performing DC SQUID simulation; and all parameters are configured before the output signal. Furthermore, the above process can be interrupted at any time and returned to P1 for re-execution.

[0085] This embodiment demonstrates a DC SQUID characteristic solver with configurable parameters and implements the scanning acquisition of transfer characteristic curves. It should be noted that the piecewise excitation signal generator of the DC SQUID characteristic solver can be connected to any physical quantity. After adjusting the calculation structure of S2, scanning analysis can be performed on any physical quantity (e.g., fixing the magnitude of the input magnetic flux signal and scanning the relationship between the DC SQUID output voltage and the DC SQUID bias current). Any scanning analysis of other physical quantities related to DC SQUID, including implementing multiple physical quantity scans in one instance, should be considered part of this invention.

[0086] In addition, this DC SQUID simulator includes an FPGA-based hardware parallel pipeline algorithm for solving the DC SQUID electrical model. This embodiment only includes the parallel hardware solution method for symmetric DC SQUIDs. It is evident that when simulating asymmetric DC SQUIDs, after slight modifications to the model equations, the parallel processing method described herein can still adapt to these conditions and operate normally, and should be considered part of this invention.

[0087] It needs to be emphasized again that, as stated at the beginning of this embodiment section, this embodiment only demonstrates the solution of the equations for DC SQUID under the RSJ model. Obviously, when using the RCSJ model to solve DC SQUID, only slight modifications to the model equations in S2 are needed, and capacitance-related equations can be added to perform the solution according to the method described in the patent (when using the RCSJ model, the time step that can be selected in S2 is usually on the order of hundreds of femtoseconds). Therefore, using the method described in the patent to model DC SQUID using the RCSJ model should also be considered as part of this invention.

[0088] It should be noted that this invention provides an FPGA solution method for a segmented parallel pipelined DC SQUID model, and describes its method for solving single parameters by scanning in the technical content section. This method is further illustrated in the subsequent embodiments and accompanying drawings. Obviously, if the time axis is not segmented and pipelined, but instead parallelized pipelined processing of multiple tasks is performed, this method can also achieve: parallel simulation modeling of a five-channel DC SQUID (based on...). Figure 6 The invention demonstrates its high throughput computational characteristics in single-step iterations (the more computational steps, the higher the number of parallel operations it can support) and multivariable scan simulation modeling with a single DC SQUID. In these scenarios, the invention's parallel pipelined application based on the iterative equations (or their modifications) mentioned in this invention should be considered part of this invention.

[0089] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0090] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters, characterized in that, include: A circuit containing programmable logic devices, including input devices, output devices and interactive devices, is capable of receiving external magnetic flux signals input through the input devices and parameters of a DC SQUID model set through the interactive devices, and outputting actual DC SQUID output voltage signals through the output devices. The DC SQUID characteristic solver can use circuits containing programmable logic devices to process the numerical parallel solution of the electrical differential equations satisfied by the DC SQUID under the given parameters of the DC SQUID model. The solution results are then post-processed to obtain the DC SQUID output voltage signal and stored in the memory of the circuit containing programmable logic devices. The DC SQUID output calculator can obtain the net input magnetic flux signal corresponding to the external magnetic flux signal based on the external magnetic flux signal received by the circuit containing programmable logic devices and the user-defined parameters. It then searches for the corresponding DC SQUID output voltage signal in the memory of the circuit containing programmable logic devices according to the net input magnetic flux signal. The difference between the DC SQUID output voltage signal and the DC SQUID voltage bias signal is used to obtain the actual DC SQUID output voltage signal. Finally, the actual DC SQUID output voltage signal is output to the output device of the circuit containing programmable logic devices.

2. The DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters according to claim 1, characterized in that, The circuit containing the programmable logic device includes: a programmable logic device, a multi-channel ADC as an input device, a single-channel DAC as an output device, a memory, and an interaction device; wherein, The multi-channel ADC, as an input device, is electrically connected to the input terminal of the programmable logic device; One of the DACs, acting as an output device, is electrically connected to the output terminal of a programmable logic device; The memory is electrically connected to the storage terminal of the programmable logic device; Interactive devices are electrically connected to programmable logic devices.

3. The DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters according to claim 2, characterized in that, The programmable logic device is an FPGA chip or a system-on-a-chip that includes programmable logic. The memory is an external memory or a memory in a programmable logic device.

4. The DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters according to any one of claims 1-3, characterized in that, The DC SQUID characteristic solver utilizes a circuit containing programmable logic devices to perform numerical parallel solutions to the electrical differential equations satisfied by the DC SQUID under given DC SQUID model parameters. The solution results are then processed to obtain the DC SQUID output voltage signal, including: Step 1: Determine the solution time step, discretize the electrical differential equations satisfied by DC SQUID, transform the continuous time model into a discrete numerical solution, simplify the iterative operations involved in the difference equations, and obtain the simplified difference equations. Step 2: Solve in advance the constant multiplication terms in the simplified difference equation, including the division between the magnetic flux quantum and the solution time step; Step 3: Based on the magnitude of each parameter of the solution time step, select the units to be used for all physical quantities in the difference equation obtained from the above processing. Step 4: Select the data format for the physical quantities involved in the difference equation, and perform data localization according to the selected data format; Step 5: Calculate the sine function in the difference equation using a lookup table. Set up a read-only memory in the circuit containing the programmable logic device, use the input of the sine function as the address, and use the stored value as the calculated value of the sine function. Step 6: Convert the division operation in the simplified difference equation into a multiplication operation, and parallelize all multiplication, addition and sine taking operations that have no data dependency in the single calculation of the difference equation, so as to realize the parallelization of numerical solution and form a calculation process of one iteration of the difference equation. Step 7: Implement the above calculation process using time-segment decomposition and segment parallel calculation according to the calculation flow obtained in Step 6, and calculate the corresponding DC SQUID output voltage signal.

5. The DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters according to claim 4, characterized in that, In step 1, the DC SQUID model solved by the DC SQUID characteristic solver is a DC SQUID with no feedback circuit, based on the RCSJ model, consisting of a left Josephson junction and a right Josephson junction connected in parallel. The set of electrical differential equations satisfied by this DC SQUID is as follows: ； In the above formula, and These represent the current flowing through the left Josephson junction and the right Josephson junction of the DC SQUID, respectively. This is the bias current of the DC SQUID; and These represent the contributions of the left and right Josephson junctions of the DC SQUID to the loop inductance of the DC SQUID, respectively. and The sum of these constitutes the loop inductance of the DC SQUID; The input is the external magnetic flux signal; It is the quantum of magnetic flux; The phase difference of the wave functions of the two superconductors that form the left Josephson junction. The phase difference of the wave functions of the two superconductors that form the right Josephson junction; It can be any integer; and These are the capacitances of the left and right Josephson junctions, respectively. and These are the resistances of the left Josephson junction and the right Josephson junction, respectively. and These are the critical currents of the left and right Josephson junctions, respectively. For time; Let the parameters in the above formula And ignoring the direct impact of the slowly varying physical quantities of the input external magnetic flux signal and the bias current of the DC SQUID on the output voltage, the output voltage of the DC SQUID is... Written as: ； The electrical differential equations satisfied by the DC SQUID above are discretized in the following way, transforming the continuous-time model into a discrete numerical solution. The iterative operations involved in the difference equations are simplified, resulting in the simplified difference equations: ； In the above formula, The time step chosen when discretizing the differential equation; the variables in the above equation Written as: ； The above variables The subscript and These are all discrete independent variables introduced during the transformation from differential equations to difference equations, and they are all integers, i.e.: ； The remaining variables of the simplified difference equation above are defined in the same way as the corresponding variables used in the electrical differential equations satisfied by DC SQUID based on the RCSJ model. Alternatively, in step 1, the DC SQUID model solved by the DC SQUID characteristic solver is a DC SQUID based on the RSJ model simplified from the above RCSJ model, and the DC SQUID satisfies the following set of electrical differential equations: ； The variables in the above equation have the same definition as the corresponding variables used in the set of electrical differential equations satisfied by DC SQUID based on the RCSJ model; Let the parameters in the set of electrical differential equations satisfied by the DC SQUID based on the RSJ model described above be... And ignoring the direct impact of the slowly varying physical quantities of the input external magnetic flux signal and the bias current of the DC SQUID on the output voltage, the output voltage of the DC SQUID is... Written as: ； The electrical differential equations satisfied by the DC SQUID based on the RSJ model are discretized in the following way, transforming the continuous-time model into a discrete numerical solution. The iterative operations involved in the difference equations are simplified, resulting in the simplified difference equations: ； In the above formula, The time step chosen when discretizing the differential equation; The above variables The subscript or These are all discrete independent variables introduced during the transformation from differential equations to difference equations, and they are all integers, i.e.: ； The remaining variables in the simplified difference equation above are defined in the same way as the corresponding variables used in the electrical differential equations satisfied by DC SQUID based on the RCSJ model.

6. The DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters according to claim 5, characterized in that, In step 7, during the process of solving the electrical differential equations satisfied by DC SQUID, the gain of the low-noise amplifier in the electronics is multiplied into the output voltage of the above difference equations in advance. In step 7, the DC SQUID characteristic solver implements the above calculation process according to the calculation flow obtained in step 7, using a time-time decomposition and segment-parallel computation method. This includes time-time decomposition calculation and segment-parallel pipelined calculation. The time period decomposition calculation method is as follows, including: The DC SQUID characteristic solver analyzes the number of clock cycles required for a single calculation of the difference equation based on the parallel processing analysis of the difference equation. If the analysis shows that the number of clock cycles required for a single recursion is... The solution time will then be... Divided into A time period , The first time period The start time of each time period is written as... , ; The parallel pipeline calculation method for the aforementioned segment is as follows: The DC SQUID characteristic solver is divided into segments. and number of segments Parallel pipelined computation is performed on each of the decomposed time periods in two scenarios, where the number of segments... In the first case, data for the first time period and the corresponding excitation signal are sent in during the first clock cycle, data for the second time period and the corresponding excitation signal are sent in during the second clock cycle, and so on, until the... After one clock cycle, the result of the second time point in the first time period is calculated, and this data, along with the excitation signal at that moment, is sent into the calculation process to continue calculating the result of the third time point in the first time period. After one clock cycle, the second time point of the second time period is calculated and combined with the excitation signal at the current moment for subsequent iterations, so as to realize the parallel calculation of the output voltage of each time period under the same set of hardware solution resources; In the number of segments In the second case, based on the calculation process of the first case, maintain a length of The first-in-first-out (FIFO) register caches the iterative solution quantities of the equation, where... It can extend the number of clock cycles required for the entire solution process to This allows it to form the same computational structure as the first case for performing calculations.

7. The DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters according to claim 6, characterized in that, The DC SQUID characteristic solver also includes a segmented excitation signal generator to provide excitation signals for parallel pipeline calculations in each time period. It can accept external magnetic flux signals as input. The number of segments in the excitation signal is consistent with the number of segments in the segmented solution of the DC SQUID characteristic solver. Each output interface of the segmented excitation signal generator outputs the waveform of the corresponding segment. The segmented excitation signal generator outputs the above segments in turn for calculation in each time period. The excitation signals in this segmented excitation signal generator have a certain intersection. The form of this intersection is: the end signal of the current signal segment is the same as the beginning signal of the next signal segment, the end signal of the last signal segment is the same as the beginning signal of the first signal segment, and the intersection time of all intersecting signal segments is the same, that is, the duration of the same part of the current signal segment and the next signal segment is the same. The intersection time of the segmented excitation signal generator is greater than the group delay of the digital low-pass filter that subsequently filters the results; The last segment of the segmented excitation signal generator is extended accordingly, and the extension length is the intersection time of the segmented excitation signal generator. The extended signal is the same as the starting segment signal of the first segment. The duration of the excitation signal is set to the total solution time of the electrical differential equations satisfied by DC SQUID; When scanning the transfer characteristic curve of an external magnetic flux signal input to the excitation signal, the intersection of two adjacent segments of the segmented excitation signal generator must satisfy the condition that they are completely identical or that the magnetic flux quantum... The remainders are the same; to facilitate the calculation of the DC SQUID output voltage signal, the scanning range of the input magnetic flux is set to... .

8. The DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters according to claim 6, characterized in that, In step 7, the following zero initial conditions are used to solve each segment of the electrical differential equations satisfied by the DC SQUID based on the RCSJ model: ； All variables in the above equation have the same definitions as the corresponding variables used in the set of electrical differential equations satisfied by DC SQUID based on the RCSJ model; In step 7, the following zero initial conditions are used to solve each segment of the electrical differential equation system satisfied by the DC SQUID based on the RSJ model: ； All variables in the above equation have the same definitions as the corresponding variables used in the set of electrical differential equations satisfied by DC SQUID based on the RSJ model; In the process of solving each segment of the above differential equation system, all physical quantities except those connected to the segmented excitation signal generator are maintained at the set values ​​during the solution process.

9. The DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters according to claim 4, characterized in that, After step 7, the DC SQUID characteristic solver sends the calculated output voltage signal to a digital low-pass filter designed in the programmable logic device to filter out the high-frequency oscillation signal, thereby obtaining the required DC SQUID output voltage signal. The output voltage signal of the digital low-pass filter, which serves as the DC SQUID output voltage signal, is then segmented and stored in the memory of the circuit containing the programmable logic device.

10. The DC superconducting quantum interference device simulator with fully reconfigurable electrical parameters according to claim 9, characterized in that, The digital low-pass filter employs a multi-channel parallel low-pass filter capable of single-cycle data refresh. The DC SQUID characteristic solver performs post-processing on the output signal of the digital low-pass filter, which is segmented and stored in the memory of a circuit containing programmable logic devices, in the following manner: The segmented output voltage signals are spliced ​​and aligned, and the splicing positions of each segment of the output voltage signal are marked. The output voltage signal is used to alert the user when the calculation result overflows, and the location of the data overflow is marked. When scanning the transfer characteristic curve, the DC SQUID characteristic solver performs period conversion on the period of the transfer characteristic curve to obtain the representation of the period of the transfer characteristic curve under the selected data format.

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