Wafer testing method
By setting programmable logic devices between the port groups of the wafer to form a test template and perform tests, the delay problem of wafer testing needing to be performed after 3D packaging is solved, realizing single-wafer testing before packaging and reducing production costs.
Patent Information
- Application Number
- CN202211658295.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-22
- Publication Date
- 2026-01-16
- Estimated Expiration
- 2042-12-22
AI Technical Summary
Current 3DIC wafer testing requires 3D packaging and cannot be performed on a single wafer, resulting in delayed test results and increased production costs due to rework and disassembly.
Programmable logic devices, such as programmable fuses or programmable chips, are placed between designated port groups on the wafer. Test templates are formed by assigning values, and tests are performed using a wafer tester to achieve single-wafer testing.
Testing is performed before wafer packaging to avoid rework and reduce production costs.
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Figure CN115840134B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of wafer testing, and in particular to a wafer testing method. BACKGROUND
[0002] Wafer testing is an important step in the chip production process, which can prevent defective products from entering the market and improve product yield.
[0003] Existing 3DIC wafer (Three-Dimensional Integrated Circuits Wafer, 3-dimensional packaging wafer) testing cannot be performed on a single wafer. A storage wafer needs to be connected to the wafer to be tested, and the wafer to be tested can only be tested by providing data from the storage wafer. Therefore, wafer testing needs to be performed after 3D packaging, and the testing time is relatively late. The test result has a long time delay. If the wafer testing fails, it needs to be reworked and disassembled, which increases the production cost.
[0004] How to achieve single wafer testing without relying on a storage wafer has become a problem to be solved. SUMMARY
[0005] The technical problem solved by the present application is to provide a wafer testing method to achieve single wafer testing before wafer packaging.
[0006] To solve the above technical problem, one technical solution adopted by the present application is to provide a wafer testing method, which comprises the following steps: obtaining a wafer to be tested and determining testing requirements; setting a programmable logic device between each specified port group of the wafer to be tested; based on the testing requirements, assigning a value to each programmable logic device to provide a value for each port group to form a test template; and testing the test template by using a wafer testing machine.
[0007] In one possible implementation, the step of obtaining a wafer to be tested and determining testing requirements comprises: obtaining multiple wafers of the same batch as the wafer to be tested according to the electrical function of the wafer, wherein each electrical function to be tested is tested by a wafer to be tested.
[0008] In one possible implementation, the step of setting a programmable logic device between each specified port group of the wafer to be tested comprises: obtaining a multi-channel conversion chip, the multi-channel conversion chip comprising a first channel and a second channel, setting the programmable logic device on the first channel, and connecting the specified port group through the multi-channel conversion chip.
[0009] In one possible implementation, the programmable logic device is a programmable fuse or a programmable chip.
[0010] In a possible implementation, before the step of assigning values to each programmable logic device, the method further includes: obtaining parameters of the programmable logic device and assignment conditions.
[0011] In a possible implementation, the number of ports required by each port group is determined according to an electrical function to be tested by the wafer to be tested; the number of ports is a port on or a port off; the step of assigning values to each programmable logic device and providing values for each port group to form a test template includes: in response to the programmable logic device being a programmable fuse, causing the programmable fuse to store values by default to control the corresponding port group to be on, or performing programming on the programmable fuse to control the corresponding port group to be off; in response to the programmable logic device being a programmable chip, causing the programmable chip to store values by default to control the corresponding port group to be off, or performing programming on the programmable chip to control the corresponding port group to be on.
[0012] In a possible implementation, the step of performing programming on the programmable fuse includes: applying an off voltage to the programmable fuse to cause the programmable fuse to be programmed; the step of performing programming on the programmable chip includes: using an ultraviolet (UV) box to irradiate the programmable chip to cause the programmable chip to be programmed.
[0013] In a possible implementation, before the step of assigning values to each programmable logic device, the method further includes: adjusting the multi-channel conversion chip to control the port groups to be connected through the first channel.
[0014] In a possible implementation, the step of testing the test template by using the wafer testing machine includes: obtaining a distribution of test pads of the wafer to be tested, and causing the test pins of the wafer testing machine to abut against each test pad to perform electrical testing.
[0015] In a possible implementation, in response to all electrical function tests of the wafer passing, the multi-channel conversion chip is adjusted to control the port groups to be connected through the second channel, so that the wafer to be tested remains to have the electrical function after being tested.
[0016] The wafer testing method provided in the present application has the following beneficial effects: Different from the prior art, the wafer testing method provided in the present application includes: obtaining a wafer to be tested and determining test requirements; setting programmable logic devices between each specified port group of the wafer to be tested; assigning values to each programmable logic device based on the test requirements, and providing values for each port group to form a test template; and testing the test template by using a wafer testing machine. The wafer testing method provided in the present application sets programmable logic devices between ports of a wafer, and provides port data for the wafer to be tested by using the programmable logic devices before wafer testing, so that the ports of the wafer to be tested are in a specific connection template for realizing an electrical function to be tested. The wafer testing method does not rely on a storage wafer to provide port data, and wafer testing can be performed before 3D packaging. When the testing does not pass, the wafer does not need to be returned to work and disassembled, and the production cost is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description only represent some of the embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on these drawings.
[0018] Figure 1 is a flowchart of a first embodiment of a wafer testing method of the present application;
[0019] Figure 2 is a flowchart of a second embodiment of a wafer testing method of the present application. DETAILED DESCRIPTION
[0020] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings of the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort fall within the scope of the present application.
[0021] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present application. However, it is obvious for those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid obscuring the present application, some technical features well known in the art are not described; that is, all the features of the actual embodiments are not described here, and the well-known functions and structures are not described in detail.
[0022] In addition, the drawings are only schematic illustrations of the present application, and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus repeated description thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0023] The existing wafer testing needs to rely on the storage wafer to provide port data, and the testing needs to be performed after 3D packaging, so that the single wafer cannot be directly tested, the testing result delay time is longer, and if the testing fails, a batch of wafers needs to be disassembled for rework, which delays production.
[0024] Based on the above problems, the wafer test method can effectively solve the above problems, and the wafer test method provided by the present application will be described in detail below in combination with the drawings and embodiments.
[0025] Please refer to Figure 1 , Figure 1 is the flowchart of the first embodiment of the wafer test method of the present application. In a specific embodiment, the wafer test method of the present application comprises:
[0026] S11: Obtain the wafer to be tested and determine the test requirement.
[0027] The wafer is a microelectronic device with specific electrical function. In order to achieve the specific electrical function, the wafer determines the circuit distribution and electronic parameters on it at the beginning of the design before production. Wafer testing is to test the electrical function of the sampled wafer to see if it has the required electrical function, so as to avoid the flow of defective wafer products into the market. Randomly select a wafer to be tested from a batch of wafer products, check the model of the batch of wafers, determine the electrical function that the batch of wafers needs to achieve, and the electrical function is the test requirement of the wafer to be tested.
[0028] S12: Set programmable logic devices between each specified port group of the wafer to be tested.
[0029] The wafer product has several connection ports on its surface. When packaging, the wafer is fixedly connected to other devices or wafers through the connection ports, and serves as a device with specific electrical function. When the wafer is connected to other devices or wafers, the other devices or wafers provide port data to the ports of the wafer to be tested, so that the specified ports on the wafer are connected or disconnected, and a specific circuit pattern is formed inside the wafer, so that the wafer has a specific electrical function. Different connection states between the wafer ports make the wafer have different electrical functions.
[0030] The programmable logic device can be reprogrammed according to the use requirement when in use, and its state can be changed by modifying the internal circuit of the programmable logic device. The programmable logic device is set between each port group of the wafer. By modifying the programmable logic device, the connection between the ports of the wafer when the wafer is connected to other devices or wafers can be simulated, so that the ports of the wafer are in a specific connection template for achieving the electrical function to be tested.
[0031] S13: Based on the test requirement, each programmable logic device is assigned a value, and a value is provided for each port group to form a test template.
[0032] Among them, the port value required by the port group is determined according to the electrical function to be tested of the wafer to be tested, and the port value is the port on or off. Specifically, determining the port value determines the connection template that the port of the wafer to be tested needs to achieve the electrical function to be tested.
[0033] After the programmable logic is set between each designated port group of the wafer under test, each programmable logic device is modified according to the determined connection template that the ports of the wafer under test need to achieve, so that the corresponding port group of each programmable logic device is disconnected or connected, and the ports of the wafer under test are in a specific connection template that realizes the electrical function to be tested. Then, the wafer under test forms a test template corresponding to the electrical function to be tested.
[0034] In some embodiments, the programmable logic device is a programmable fuse or a programmable chip.
[0035] For example, the programmable logic device can be an EFUSE or an OTP, etc.
[0036] The EFUSE is a one-time programmable fuse memory, which has a programmable fuse on the device. Through a continuous current pulse, the fuse can be programmed to make the fuse melt and set the EFUSE between the port groups. When the fuse is not melted, the EFUSE provides the port data of the connected port group. When the fuse is melted, the EFUSE provides the port data of the disconnected port group. The OTP is a programmable chip, specifically a one-time programmable register. The register data can be programmed and modified once. When the OTP is not modified, the OTP provides the port data of the disconnected port group. When the OTP is modified, the OTP provides the port data of the connected port group. The specific type of programmable logic device is not limited, and in other embodiments, the programmable logic device can also be an anti-fuse programming device, a programmable diode, an erasable memory, etc.
[0037] S14: testing the test template by using a wafer tester.
[0038] After the ports of the wafer under test are in a specific connection template that realizes the electrical function to be tested, the electrical function to be tested is tested by using a wafer tester.
[0039] In some embodiments, S14 includes obtaining the distribution of the test pads of the wafer under test, and making the test pins of the wafer tester abut each test pad to perform electrical testing. The wafer tester includes a plurality of test pins. The wafer is placed on the wafer tester, and the test pins contact each test pad of the wafer. During testing, the wafer tester applies an input signal to the wafer through the test pins, and collects the output signal of the wafer. The output signal is identified, and whether the electrical function to be tested passes the test is determined by whether the wafer under test has a specified effect on the input signal.
[0040] The above scheme sets a programmable logic device between the ports of the wafer, and provides the wafer to be tested with port data through the programmable logic device before wafer testing, so that the ports of the wafer to be tested are in a specific connection template for realizing the electrical function to be tested, and the wafer to be tested does not rely on the storage wafer to provide the port data.
[0041] The wafer testing can be performed before 3D packaging, and if the testing fails, the production cost is reduced without rework and disassembly.
[0042] In some embodiments, a batch of wafers can have multiple electrical functions to be tested. To improve the testing efficiency, the S11 includes: obtaining multiple wafers of the same batch as the wafers to be tested according to the electrical functions of the wafers, wherein each electrical function to be tested is tested by a wafer to be tested.
[0043] Specifically, after the wafer is produced, the wafer has not only one electrical function, and the wafer is connected to different storage wafers or devices, different 3D packages, storage wafers or devices
[0044] provide different port connection data for the wafer, and the change of the wafer port connection template enables the wafer to have different electrical functions. To test multiple electrical functions of the wafer at the same time and improve the testing efficiency, multiple wafers of the same batch are obtained as wafers to be tested, and each wafer to be tested is used to test
[0045] one electrical function, a programmable logic device is set at a specified port group of each wafer to be tested, and the programmable logic device on each wafer to be tested is respectively valued, so that the ports of each wafer to be tested are in a specific different connection template for realizing different electrical functions. Then, the wafer tester tests each test template, so that multiple electrical functions of a batch of wafer products can be tested at the same time, and the testing efficiency is improved.
[0046] Please refer to Figure 2 , Figure 2 is a flowchart of a second embodiment of the wafer testing method of the present application. In this embodiment, the wafer testing method includes:
[0047] S21: Obtain a wafer to be tested and determine the testing requirement.
[0048] For details, please refer to S11, which will not be repeated here.
[0049] S22: Obtain a multi-channel conversion chip, the multi-channel conversion chip includes a first channel and a second channel, and a programmable logic device is set on the first channel and connected to a specified port group through the multi-channel conversion chip.
[0050]
[0051] The multi-channel conversion chip has multiple circuits, and any circuit can be selected to be turned on as needed. The multi-channel conversion chip includes, for example, a four-channel conversion chip, an eight-channel conversion chip, a sixteen-channel conversion chip, and the like. In the present embodiment, the multi-channel conversion chip is preferably a two-channel conversion chip. The two-channel conversion chip includes a first channel and a second channel.
[0052] Unlike the first embodiment, in the present embodiment, the programmable logic device is arranged on the first channel of the multi-channel conversion chip, and then the multi-channel conversion chip is arranged between the port groups. The multi-channel conversion chip is adjusted so that each port group can provide port data through the programmable logic device to control the turn-on or turn-off of the port, or can not accept the port data provided by the programmable logic device, so that the port group of the wafer remains in a state without connection of the programmable logic device.
[0053] S23: Adjust the multi-channel conversion chip to control the connection of the port group through the first channel.
[0054] Before the wafer under test is subjected to electrical function testing by the wafer tester, the first channel of all multi-channel conversion chips is turned on, and the second channel is turned off, so that each port group accepts the port data provided by the programmable logic device.
[0055] S24: Based on the testing requirements, each programmable logic device is assigned a value to provide a value to each port group to form a test template.
[0056] The port value is determined according to the electrical function to be tested of the wafer under test, and the port value is the turn-on or turn-off of the port. Specifically, the port value is determined, i.e., the connection template of the port of the wafer under test to achieve the electrical function to be tested.
[0057] After the programmable logic is arranged between each designated port group of the wafer under test, the connection required by each port group of the wafer under test to achieve the electrical function to be tested is determined, and each programmable logic device is modified so that the corresponding port group of each programmable logic device is turned off or turned on, so that the wafer under test reaches the connection state of the port corresponding to the electrical function to be tested, and the wafer under test becomes a test template corresponding to the electrical function to be tested.
[0058] The programmable logic device is a programmable fuse or a programmable chip, such as EFUSE or OTP, etc.
[0059] Before each programmable logic device is assigned a value, the parameters and assignment conditions of the programmable logic device are obtained.
[0060] Response to programmable logic device is programmable fuse, make its default storage assignment control corresponding port group is on, or programmable fuse is burned control corresponding port group is off; response to programmable logic device is programmable chip, make its default storage assignment control corresponding port group is off, or programmable chip is burned control corresponding port group is on. When programmable logic device is EFUSE, when its fuse is not burned, not to EFUSE programming assignment, EFUSE provides the port data of the port group with on connection, when the EFUFE is assigned, the fuse is burned, and the EFUSE provides the port data of the port with off connection. When OTP is not burned, not to OTP assignment, OTP provides the port data of the port with off connection, when OTP is burned, OTP is modified, and OTP provides the port data of the port with on connection.
[0061] Further, the programmable fuse is burned by applying an off voltage, and different programmable fuses require different off voltages for burning. The specific off voltage assignment condition can be consulted from the model and factory parameters of the programmable fuse. For example, the off voltage of EFUSE is generally 2.5V, and a 10mA direct current pulse of 200 microseconds can burn EFUSE. The OTP is burned by using ultraviolet UV box to irradiate it. The data stored on the OTP can be erased by ultraviolet rays, so as to achieve the purpose of burning and changing programming.
[0062] S25: test the test template by using a wafer test machine.
[0063] For details, please refer to S14, which will not be repeated here.
[0064] S26: in response to the fact that all electrical function tests of the wafer pass, adjust the multi-channel conversion chip to control the port group to pass through the second channel connection, so that the waired wafer can keep the electrical function after being tested.
[0065] Specifically, when the electrical function to be tested of each of the plurality of wafers in the same batch of wafers passes the test, the batch of wafers passes the test requirement, so that the wafer to be tested can keep its electrical function for subsequent packaging or use. Adjust the multi-channel conversion chip to make the port group of the wafer to be tested pass through the second channel connection, and each programmable logic device is not connected between the port groups.
[0066] When the electrical function test of the wafer to be tested fails, since the wafer is a single wafer test and has not been packaged or connected to other devices, it is not necessary to disassemble it, and it can be directly modified, avoiding disassembly and rework of unqualified test, and reducing production cost.
[0067] The above embodiment, on the one hand, before wafer testing, the programmable logic device provides the port data for the wafer to be tested, so that the port of the wafer to be tested is in a specific connection template for realizing the electrical function to be tested, and the wafer testing can be performed before 3D packaging, and if the testing fails, the wafer does not need to be disassembled, thereby reducing the production cost. On the other hand, the programmable logic device is arranged between the port groups of the wafer to be tested through the multi-channel conversion chip, if the wafer testing is passed, the programmable logic device is not connected between the port groups by adjusting the multi-channel conversion chip, so that the wafer can maintain the electrical function after testing, and is used for subsequent 3D packaging or is connected to other devices, thereby further reducing the production cost.
[0068] It should be understood that every feature, structure, or characteristic described above in relation to one embodiment can be included in at least one embodiment of the present application. Therefore, the appearance of the phrase "in one embodiment" or "in an embodiment" in various places throughout the specification is not necessarily referring to the same embodiment. In addition, these features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the size of the serial number of the above processes does not mean the execution order in various embodiments of the present application, and the execution order of the processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The serial number of the above embodiments of the present application is only for description, not representing the advantages and disadvantages of the embodiments.
[0069] The devices disclosed in the several device embodiments of the present application can be combined in any suitable manner, without conflict, to obtain new device embodiments.
[0070] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims
1. A wafer testing method, characterized by, The wafer testing method comprises: acquiring a wafer to be tested and determining testing requirements; setting programmable logic devices between each specified port group of the wafer to be tested; the step of setting programmable logic devices between each specified port group of the wafer to be tested comprises: acquiring a multi-channel conversion chip, the multi-channel conversion chip comprising a first channel and a second channel, setting the programmable logic devices on the first channel, and connecting the specified port groups through the multi-channel conversion chip; based on the testing requirements, assigning values to each programmable logic device, providing values for each port group, and forming a testing template; testing the testing template by using a wafer testing machine; and in response to passing of all electrical function tests of the wafer, adjusting the multi-channel conversion chip to control the port groups to be connected through the second channel, so that the wafer to be tested remains electrical function after being tested.
2. The wafer testing method of claim 1, wherein The step of acquiring a wafer to be tested and determining testing requirements comprises: According to the electrical function of the wafer, a plurality of wafers of the same batch are acquired as wafers to be tested, wherein each electrical function to be tested is tested by a wafer to be tested.
3. The wafer testing method according to claim 1, wherein the programmable logic device is a programmable fuse or a programmable chip. Before the step of assigning values to each programmable logic device, the method further comprises:
4. The wafer testing method of claim 3, wherein acquiring parameters and assignment conditions of the programmable logic device.
5. The wafer testing method according to claim 4, wherein the number of ports required by the port group is determined according to the electrical function to be tested of the wafer to be tested; and the number of ports is a port on or a port off. The step of assigning values to each programmable logic device and providing values for each port group to form a testing template comprises: in response to the programmable logic device being a programmable fuse, the programmable fuse is set to store assignment values by default to control the corresponding port group to be on, or the programmable fuse is programmed to control the corresponding port group to be off; in response to the programmable logic device being a programmable chip, the programmable chip is set to store assignment values by default to control the corresponding port group to be off, or the programmable chip is programmed to control the corresponding port group to be on.
6. The wafer testing method according to claim 5, wherein the step of programming the programmable fuse comprises: applying an off voltage to the programmable fuse to program it; the step of programming the programmable chip comprises: using an ultraviolet (UV) box to irradiate the programmable chip to program it. Before the step of assigning values to each programmable logic device, the method further comprises: adjusting the multi-channel conversion chip to control the port groups to be connected through the first channel. The step of testing the testing template by using a wafer testing machine comprises:
7. The wafer testing method of claim 1, wherein acquiring the distribution of test pads of the wafer to be tested, so that the test pins of the wafer testing machine abut against each test pad for electrical testing. 8. The wafer testing method of claim 1, wherein,
Citation Information
Patent Citations
Automatic testing method, device and equipment for chip pins and storage medium
CN114910774A