Chip temperature control method and system based on chip particle integration technology
By identifying chip temperature distribution and operating data, and generating suitable new chip operation control information, the problems of excessively large heat dissipation devices and high costs are solved, achieving efficient temperature control without external devices and reducing chip temperature rise limits and costs.
Patent Information
- Application Number
- CN202510834876.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-20
- Publication Date
- 2025-11-14
AI Technical Summary
In existing technologies, the large size and high cost of heat dissipation devices result in poor chip temperature control, making them unsuitable for general environments.
By acquiring temperature detection information and operating data from the chip, identifying temperature distribution and chip operation information, generating new chip operation control information that is adapted to the chip, reducing the load on individual chips, lowering the overall chip temperature rise limit, and adjusting the temperature control strategy through collaborative interaction between chips.
It can effectively reduce chip temperature control costs and improve temperature control efficiency without the need for external equipment, ensuring normal chip operation and enhancing temperature control performance.
Smart Images
Figure CN120949906A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip integration and collaborative interaction technology, and in particular to a chip temperature control method and system based on chip integration technology. Background Technology
[0002] Multi-chip integration technology refers to the technology of integrating modular chiplets into a multi-chip integrated system using advanced packaging technology. When multiple chips are working simultaneously, the chip temperature rises rapidly, resulting in faster chip wear and aging, which affects the chip's lifespan. Therefore, how to regulate the chip temperature based on multi-chip integration to effectively reduce the chip temperature is a current research focus.
[0003] Traditional temperature control methods involve real-time monitoring of the chip's temperature and adding additional heat dissipation devices to the chip, thereby enabling effective temperature control. However, while this method can effectively reduce temperature, the heat dissipation devices are too large and costly, requiring specific devices to accommodate both the chip and the heat dissipation device. This makes it unsuitable for general environmental conditions, resulting in poor temperature control performance for the chip. Summary of the Invention
[0004] The main objective of this invention is to provide a chip temperature control method and system based on chip-to-chip integration technology, which aims to solve the problem that the existing technology has poor chip temperature control performance because the heat dissipation device is too large and expensive, and requires a specific device to accommodate the chip and heat dissipation device together, making it unsuitable for general environmental conditions.
[0005] To achieve the above objectives, the present invention provides a chip temperature control method based on chip-to-chip integration technology, the method comprising:
[0006] The system acquires the chip's temperature detection information and the chip's current operating data, and based on the chip's temperature detection information, identifies the chip's temperature distribution information through a temperature adaptation distribution identification strategy.
[0007] Based on the current operating data of the chip, identify the chip operating information of each target chip adapted to each operating task of the chip, and based on the chip operating information of each operating task and the temperature distribution information, identify the chip operating temperature change information of the chip.
[0008] Based on the core functions of each chip in the chip and the chip operating temperature change information, a temperature control adjustment strategy is used to generate new core operation control information for each new target core adapted to each running task of the chip.
[0009] Optionally, the step of identifying the temperature distribution information of the chip based on the temperature detection information of the chip through a temperature adaptation distribution identification strategy includes:
[0010] Based on the temperature range corresponding to the temperature detection information, the applicable temperature adjustment strategy for the chip is identified, and based on the temperature adjustment strategy, the chip temperature detection map corresponding to the temperature detection information is subjected to image optimization processing to obtain the target temperature detection map corresponding to the chip.
[0011] Based on the target temperature detection map, the temperature data corresponding to each location point of the chip is identified through a temperature grid splitting and identification strategy. The temperature data corresponding to each location point is then distributed and sorted according to the position information of each location point in the target temperature detection map to obtain the temperature distribution information of the chip.
[0012] Optionally, identifying the chip operation information of each target chip adapted to each running task of the chip based on the chip's current operating data includes:
[0013] The current running data is divided into current sub-running data corresponding to each running task, and the current running process of each target core corresponding to each current sub-running data and the current execution function of each target core are identified.
[0014] Based on the current running process and current execution function of each target core, the current function application degree of each target core is identified, and the current running process, current execution function, and current function application degree of each target core are used as the core running information of each target core adapted for each running task.
[0015] Optionally, identifying the chip's chip operating temperature change information based on the chip's chip operating information for each running task and the temperature distribution information includes:
[0016] For each running task, based on the position information of each target core corresponding to the running task, the temperature data corresponding to the core is identified in the temperature distribution information;
[0017] Based on the current function of each target core, the application level of the current function of each target core, and the temperature data corresponding to each target core, identify the temperature association information corresponding to each current function.
[0018] The temperature-related information corresponding to all currently executed functions is used as the chip's core operating temperature change information.
[0019] Optionally, based on the chip functions of each non-target chip and the chip's chip operating temperature change information, a temperature control adjustment strategy is used to generate new chip operation control information for each new target chip adapted to each running task of the chip, including:
[0020] Based on the chip operating temperature change information, among the target chips, chips with abnormal temperatures are screened, and based on the temperature association information of the current function being executed corresponding to the chip with abnormal temperatures, and the target chip temperature of the chip, among the non-target chips, each new target chip corresponding to the current function is screened.
[0021] Based on the current running process of the target core, new running tasks of each new target core are identified, and new core running control information of each new target core is generated based on the new running tasks of each new target core.
[0022] Optionally, the step of identifying new running tasks for each new target core based on the current running process of the target core, and generating new core running control information for each new target core based on the new running tasks of each new target core, includes:
[0023] Based on the current running process of the target core, the remaining core task flow of the target core is identified, and based on the remaining core task flow, the core cooperation task nodes between each new target core and the core interaction task nodes between each new target core are identified through a task allocation strategy.
[0024] The core cooperation task nodes and core interaction task nodes between the new target cores are sorted according to the remaining core task flow to obtain the new running task of each new target core.
[0025] Based on the new operating tasks of each new target core, a core control instruction sequence for each new target core is generated through an instruction generation strategy, and the core control instruction sequence for each new target core is used as the new core operating control information for each new target core.
[0026] Furthermore, to achieve the above objectives, the present invention also provides a chip temperature control system based on chip-integration technology, the chip temperature control system based on chip-integration technology comprising:
[0027] The acquisition module is used to acquire the chip's temperature detection information and the chip's current operating data, and based on the chip's temperature detection information, to identify the chip's temperature distribution information through a temperature adaptation distribution identification strategy;
[0028] The identification module is used to identify the chip operation information of each target chip adapted to each running task of the chip based on the current running data of the chip, and to identify the chip operation temperature change information of the chip based on the chip operation information of each running task and the temperature distribution information.
[0029] The generation module is used to generate new core operation control information for each new target core adapted to each running task of the chip, based on the core function of each core of the chip and the core operating temperature change information of the chip, and through a temperature control adjustment strategy.
[0030] Optionally, the acquisition module is specifically used for:
[0031] Based on the temperature range corresponding to the temperature detection information, the applicable temperature adjustment strategy for the chip is identified, and based on the temperature adjustment strategy, the chip temperature detection map corresponding to the temperature detection information is subjected to image optimization processing to obtain the target temperature detection map corresponding to the chip.
[0032] Based on the target temperature detection map, the temperature data corresponding to each location point of the chip is identified through a temperature grid splitting and identification strategy. The temperature data corresponding to each location point is then distributed and sorted according to the position information of each location point in the target temperature detection map to obtain the temperature distribution information of the chip.
[0033] Optionally, the identification module is specifically used for:
[0034] The current running data is divided into current sub-running data corresponding to each running task, and the current running process of each target core corresponding to each current sub-running data and the current execution function of each target core are identified.
[0035] Based on the current running process and current execution function of each target core, the current function application degree of each target core is identified, and the current running process, current execution function, and current function application degree of each target core are used as the core running information of each target core adapted for each running task.
[0036] Optionally, the identification module is specifically used for:
[0037] For each running task, based on the position information of each target core corresponding to the running task, the temperature data corresponding to the core is identified in the temperature distribution information;
[0038] Based on the current function of each target core, the application level of the current function of each target core, and the temperature data corresponding to each target core, identify the temperature association information corresponding to each current function.
[0039] The temperature-related information corresponding to all currently executed functions is used as the chip's core operating temperature change information.
[0040] Optionally, the generation module is specifically used for:
[0041] Based on the chip operating temperature change information, among the target chips, chips with abnormal temperatures are screened, and based on the temperature association information of the current function being executed corresponding to the chip with abnormal temperatures, and the target chip temperature of the chip, among the non-target chips, each new target chip corresponding to the current function is screened.
[0042] Based on the current running process of the target core, new running tasks of each new target core are identified, and new core running control information of each new target core is generated based on the new running tasks of each new target core.
[0043] Optionally, the generation module is specifically used for:
[0044] Based on the current running process of the target core, the remaining core task flow of the target core is identified, and based on the remaining core task flow, the core cooperation task nodes between each new target core and the core interaction task nodes between each new target core are identified through a task allocation strategy.
[0045] The core cooperation task nodes and core interaction task nodes between the new target cores are sorted according to the remaining core task flow to obtain the new running task of each new target core.
[0046] Based on the new operating tasks of each new target core, a core control instruction sequence for each new target core is generated through an instruction generation strategy, and the core control instruction sequence for each new target core is used as the new core operating control information for each new target core.
[0047] Thirdly, this application provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method described in any one of the first aspects.
[0048] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the steps of the method described in any one of the first aspects.
[0049] Fifthly, this application provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the steps of the method described in any one of the first aspects.
[0050] This invention provides a chip temperature control method and system based on chip-integrated technology. The method includes: acquiring temperature detection information and current operating data of the chip; identifying temperature distribution information of the chip based on the temperature detection information using a temperature adaptation distribution identification strategy; identifying chip-integrated operating information of each target chip adapted to each operating task of the chip based on the current operating data of the chip; identifying chip-integrated operating temperature change information of the chip based on the chip-integrated operating information of each operating task and the temperature distribution information; and generating new chip-integrated operating control information of each new target chip adapted to each operating task of the chip based on the chip-integrated function and the chip-integrated operating temperature change information using a temperature control adjustment strategy. This solution, after temperature detection of the chip, combines the current operating data of each chip to comprehensively analyze the chip's chip operating temperature change information. It then analyzes the correlation between chip operating temperature changes and chip functions, thereby adapting multiple auxiliary chips to each chip to reduce the load on individual chips and effectively lower the temperature rise limit of each individual chip. Furthermore, this solution combines the chip and each auxiliary chip to re-adapt the new chip operating control information to each new target chip. This ensures that each chip's operational tasks can be executed normally and reduces the overall temperature rise limit of each chip, eliminating the need for external equipment. This effectively reduces the chip's temperature control cost and efficiency, thus comprehensively improving the chip's temperature control performance. Attached Figure Description
[0051] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0052] Figure 1 This is a flowchart of a chip temperature control method based on chip-to-chip integration technology provided in an embodiment of the present invention;
[0053] Figure 2 This is a schematic diagram of the chip temperature control system based on chip-particle integration technology provided in an embodiment of the present invention;
[0054] Figure 3 An internal structural diagram of a computer device provided in an embodiment of the present invention. Detailed Implementation
[0055] The chip temperature control method based on chip-integrated technology provided in this invention is applied to a chip temperature control system based on chip-integrated technology. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this application. The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or accompanying drawings of this application are used to distinguish different objects, not to describe a particular order.
[0056] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0057] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.
[0058] The chip temperature control method based on chip-integration technology provided in this application embodiment can be applied to chip temperature control application environments based on chip-integration technology. This method can be applied to terminals, servers, or systems including terminals and servers, and is implemented through interaction between the terminal and server. The terminal can be, but is not limited to, various personal computers, laptops, etc. After detecting the chip temperature, the terminal combines the current operating data of each chip to comprehensively analyze the chip chip operating temperature change information, thereby analyzing the correlation between the chip operating temperature change and the chip chip function. This allows for the adaptation of multiple auxiliary chips to each chip, reducing the load on individual chips and effectively lowering the temperature rise limit of individual chips. Then, this solution combines the chip and each auxiliary chip to re-adapt the new chip chip operating control information to each new target chip. This ensures that each chip's operating task can be executed normally and reduces the overall temperature rise limit of each chip, eliminating the need for external devices. This effectively reduces the chip temperature control cost and efficiency, thus comprehensively improving the chip temperature control effect.
[0059] In one embodiment, such as Figure 1As shown, a chip temperature control method based on chip-to-chip integration technology is provided. Taking the application of this method in a terminal as an example, the method includes the following steps:
[0060] Step S101: Obtain the chip's temperature detection information and the chip's current operating data, and based on the chip's temperature detection information, identify the chip's temperature distribution information through a temperature adaptation distribution identification strategy.
[0061] In this embodiment, the terminal receives temperature data from a microscopic infrared thermal imaging detection device, obtaining the chip's temperature detection information. Then, the terminal uses a detection program installed on the chip to acquire the chip's current operating data in real time. This current operating data includes the current operating data of each individual chip. The chip's temperature detection information is its temperature detection imaging data. Finally, based on the chip's temperature detection information, the terminal identifies the chip's temperature distribution information using a temperature adaptation distribution recognition strategy. This strategy identifies the distribution of temperature data among the chip's individual chips. The specific recognition strategy will be explained in detail later.
[0062] Step S102: Based on the current operating data of the chip, identify the chip operating information of each target chip adapted to each operating task of the chip, and based on the chip operating information of each operating task and the temperature distribution information, identify the chip operating temperature change information of the chip.
[0063] In this embodiment, the terminal identifies the chip operation information of each target chip adapted to each running task based on the chip's current operating data. Based on the chip operation information of each running task and the temperature distribution information, the terminal identifies the chip's chip operating temperature change information. Each target chip is the chip executing each running task, and the chip operation information of each target chip includes, but is not limited to, the chip's execution progress for that running task and the chip's operating status. The chip operating temperature change information is the temperature correlation information corresponding to each chip when executing the current function corresponding to the current task. This temperature correlation information includes the correlation between the running degree of the current function and the temperature rise relationship; the specific identification process will be explained in detail later.
[0064] Step S103: Based on the chip functions of each chip and the chip operating temperature change information, new chip operation control information for each new target chip adapted to each running task of the chip is generated through temperature control adjustment strategy.
[0065] In this embodiment, the terminal, based on the chip's individual chip functions and chip operating temperature variation information, generates new chip operation control information for each new target chip adapted to each running task through a temperature control adjustment strategy. This temperature control adjustment strategy is used to adapt each running task to a new target chip and control the execution degree of each new target chip for each function. The specific generation process will be described in detail later.
[0066] Based on the above scheme, after temperature detection of the chip, the current operating data of each chip is combined to comprehensively analyze the chip chip operating temperature change information. This analysis reveals the correlation between chip operating temperature changes and chip chip functions, allowing for the adaptation of multiple auxiliary chips to each chip, reducing the load on individual chips and effectively lowering the temperature limit of individual chips. Furthermore, this scheme combines the chip and auxiliary chips to re-adapt the new chip chip operating control information to each new target chip. This ensures that each chip's operating task can be executed normally and reduces the overall temperature limit of each chip, eliminating the need for external equipment. This effectively reduces the chip's temperature control cost and efficiency, thus comprehensively improving the chip's temperature control performance.
[0067] Optionally, based on the chip's temperature detection information, a temperature adaptation distribution recognition strategy is used to identify the chip's temperature distribution information. This includes: identifying the applicable temperature adjustment strategy for the chip based on the temperature range corresponding to the temperature detection information; and performing image optimization processing on the chip temperature detection map corresponding to the temperature detection information based on the temperature adjustment strategy to obtain the target temperature detection map corresponding to the chip; and based on the target temperature detection map, identifying the temperature data corresponding to each location point of the chip through a temperature grid splitting recognition strategy, and sorting the temperature data corresponding to each location point according to the position information of each location point in the target temperature detection map to obtain the chip's temperature distribution information.
[0068] In this embodiment, the terminal identifies the applicable temperature adjustment strategy for the chip based on the temperature range corresponding to the temperature detection information. Based on the temperature adjustment strategy, it performs image optimization processing on the chip temperature detection map corresponding to the temperature detection information to obtain the target temperature detection map for the chip. The temperature adjustment strategy refers to the temperature identification map corresponding to different temperature ranges, such as 0-100 degrees Celsius, 100-500 degrees Celsius, and 500-1000 degrees Celsius. The microscopic level of temperature detection varies across different temperature ranges. Since this step uses microscopic infrared thermometry, the microscopic infrared thermometry parameters adapted to different temperature ranges are different. The correlation information between different temperature ranges and different microscopic infrared thermometry parameters corresponds to different temperature adjustment strategies, thereby ensuring that a temperature adjustment strategy that can clearly distinguish the temperature data differences between different chips is obtained. This correlation information is preset in the terminal and is obtained by staff through creative research on the application of microscopic infrared thermometry technology to chip chip temperature measurement.
[0069] Based on the target temperature detection map, the terminal uses a temperature grid segmentation and identification strategy to identify the temperature data corresponding to each location point on the chip. The temperature data at each location point is then distributed and sorted according to its position on the target temperature detection map to obtain the chip's temperature distribution information. The size of this grid is the size of a single chip; that is, the grid is preset in the terminal and used to divide the grid range of each chip within the chip.
[0070] Based on the above scheme, by identifying the temperature range, the temperature detection map is optimized so that after dividing the chip into individual chips, the temperature data of each chip can be obtained, thereby improving the accuracy of identifying chip temperature data.
[0071] Optionally, based on the chip's current operating data, identify the chip operation information of each target chip adapted to each operating task, including: splitting the current operating data into current sub-operating data corresponding to each operating task, and identifying the current operating process and current execution function of each target chip corresponding to each current sub-operating data; based on the current operating process and current execution function of each target chip, identify the current function application degree of each target chip, and use the current operating process, current execution function, and current function application degree of each target chip as the chip operation information of each target chip adapted to each operating task.
[0072] In this embodiment, the terminal breaks down the current running data into current sub-running data corresponding to each running task, and identifies the current running process of each target core corresponding to each current sub-running data, as well as the current execution function of each target core. Each core can run numerous functions, and when executing different tasks, the current execution function of a core is one or more of these functions. Therefore, identifying the current execution function of a target core refers to the function applied by the core when processing the running task, and the degree of operation (or percentage of function operation) of that function.
[0073] The terminal identifies the current functional application level of each target chip based on the current running process and the current execution function of each target chip, and uses the current running process, the current execution function, and the current functional application level of each target chip as the chip running information of each target chip adapted for each running task.
[0074] Based on the above scheme, by detecting and identifying the current running process, current function, and application level of each target core, the comprehensiveness of the analysis of the operating status of each core is improved. This facilitates the accuracy of analyzing the correlation information between different temperature data and various execution functions.
[0075] Optionally, based on the chip operation information and temperature distribution information of each running task, the chip operation temperature change information is identified, including: for each running task, based on the position information of each target chip corresponding to the running task, identifying the temperature data corresponding to the chip in the temperature distribution information; based on the current execution function of each target chip, the current function application degree of each target chip, and the temperature data corresponding to each target chip, identifying the temperature association information corresponding to each currently executed function; and using the temperature association information corresponding to all currently executed functions as the chip operation temperature change information.
[0076] In this embodiment, for each running task, the terminal identifies the temperature data corresponding to the core particle in the temperature distribution information based on the location information of each target core particle corresponding to the running task.
[0077] The terminal identifies temperature correlation information corresponding to each currently executed function based on the current function application level of each target core and the corresponding temperature data. Specifically, the terminal sorts the temperature data of each core corresponding to different application levels of the same currently executed function in ascending order of application level, obtaining temperature correlation information between the temperature data corresponding to the current function and the application level. This temperature correlation information represents the correspondence between changes in the application level of the current function and changes in the temperature data.
[0078] Finally, the terminal uses the temperature-related information corresponding to all currently executed functions as the chip's core operating temperature change information.
[0079] Based on the above scheme, by identifying the temperature data of each core, the relationship between the changes in temperature data and different currently executed functions can be analyzed, thereby improving the accuracy of identifying the temperature-related information corresponding to each currently executed function.
[0080] Optionally, based on the chip functions of each non-target chip and the chip operating temperature change information, a temperature control adjustment strategy is used to generate new chip operation control information for each new target chip adapted to each running task of the chip. This includes: based on the chip operating temperature change information, screening out temperature-abnormal chips among each target chip, and based on the temperature association information of the currently executed function corresponding to the temperature-abnormal chip and the chip's target chip temperature, screening out each new target chip corresponding to the currently executed function among each non-target chip; identifying new running tasks of each new target chip based on the current running process of the target chip, and generating new chip operation control information for each new target chip based on the new running tasks of each new target chip.
[0081] In this embodiment, the terminal filters out temperature-abnormal chips from among the target chips based on chip operating temperature change information. Then, based on the temperature association information of the currently executed function corresponding to the temperature-abnormal chip and the target chip temperature, it filters out new target chips corresponding to the currently executed function from among the non-target chips. The temperature-abnormal chip is the chip corresponding to a temperature data value greater than a preset temperature threshold of the terminal. Each new target chip belongs to the same working area as the temperature-abnormal chip, and among the executed functions of the new target chip, the chip whose currently executed function is in an idle state is the one corresponding to the temperature-abnormal chip.
[0082] Finally, based on the current running process of the target core, the terminal identifies the new running tasks of each new target core and generates new core running control information for each new target core based on these new running tasks. This new core running control information consists of the execution flow of each new target core, obtained by sorting the new running tasks according to their task flow. Then, the terminal filters the current execution function's degree range corresponding to temperature data below a preset temperature threshold for each new target core based on the temperature association information of its current execution function. Finally, the terminal uses the execution degree range and execution flow of each new target core as its new core running control information.
[0083] Based on the above scheme, the new target chips are screened and their operation control information is controlled, which improves the temperature control effect of the entire chip and ensures the execution progress of each task.
[0084] Optionally, based on the current running process of the target core, new running tasks for each new target core are identified, and new core running control information for each new target core is generated based on the new running tasks of each new target core. This includes: identifying the remaining core task flow of the target core based on the current running process of the target core, and identifying core cooperative task nodes and core interactive task nodes between each new target core based on the remaining core task flow through a task allocation strategy; sorting the core cooperative task nodes and core interactive task nodes between each new target core according to the remaining core task flow to obtain new running tasks for each new target core; and generating core control instruction sequences for each new target core through an instruction generation strategy based on the new running tasks of each new target core, and using the core control instruction sequences of each new target core as the new core running control information for each new target core.
[0085] In this embodiment, the terminal identifies the remaining task flow of the target core based on its current running process, and then, based on the remaining task flow, identifies the core cooperation task nodes and core interaction task nodes between new target cores through a task allocation strategy. Core cooperation task nodes are nodes corresponding to processes executed simultaneously by multiple cores, while core interaction task nodes are nodes where multiple cores interactively execute the same task in a fixed order.
[0086] Then, the terminal sorts the chip cooperation task nodes and chip interaction task nodes between the new target chips according to the remaining chip task flow to obtain new running tasks for each new target chip. These new running tasks include task information on whether each chip executes simultaneously or interactively at different process nodes.
[0087] Finally, based on the new operational tasks of each new target chip, the terminal generates a chip control instruction sequence for each new target chip using an instruction generation strategy. This sequence is then used as the new chip operation control information for each new target chip. The instruction generation strategy is preset within the terminal and is a conversion program that transforms task information into chip execution instructions.
[0088] Based on the above scheme, by processing the nodes of different core particles for different tasks, the temperature control effect of different core particles when performing tasks is improved.
[0089] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0090] Based on the same inventive concept, this application also provides a chip temperature control system based on chip-integrated technology for implementing the chip temperature control method based on chip-integrated technology described above. The solution provided by this system is similar to the solution described in the above method. Therefore, the specific limitations of one or more chip temperature control system embodiments based on chip-integrated technology provided below can be found in the limitations of the chip temperature control method based on chip-integrated technology described above, and will not be repeated here.
[0091] Further reference Figure 2 As a response to the above Figure 1 The present application provides an embodiment of a chip temperature control system 200 based on chip-integrated technology, which includes an acquisition module 210, an identification module 220, and a generation module 230, wherein:
[0092] The acquisition module 210 is used to acquire the temperature detection information of the chip and the current operating data of the chip, and based on the temperature detection information of the chip, identify the temperature distribution information of the chip through a temperature adaptation distribution identification strategy;
[0093] The identification module 220 is used to identify the chip operation information of each target chip adapted to each running task of the chip based on the current running data of the chip, and to identify the chip operation temperature change information of the chip based on the chip operation information of each running task and the temperature distribution information.
[0094] The generation module 230 is used to generate new core operation control information for each new target core adapted to each running task of the chip, based on the core function of each core of the chip and the core operating temperature change information of the chip, and through a temperature control adjustment strategy.
[0095] Optionally, the acquisition module 210 is specifically used for:
[0096] Based on the temperature range corresponding to the temperature detection information, the applicable temperature adjustment strategy for the chip is identified, and based on the temperature adjustment strategy, the chip temperature detection map corresponding to the temperature detection information is subjected to image optimization processing to obtain the target temperature detection map corresponding to the chip.
[0097] Based on the target temperature detection map, the temperature data corresponding to each location point of the chip is identified through a temperature grid splitting and identification strategy. The temperature data corresponding to each location point is then distributed and sorted according to the position information of each location point in the target temperature detection map to obtain the temperature distribution information of the chip.
[0098] Optionally, the identification module 220 is specifically used for:
[0099] The current running data is divided into current sub-running data corresponding to each running task, and the current running process of each target core corresponding to each current sub-running data and the current execution function of each target core are identified.
[0100] Based on the current running process and current execution function of each target core, the current function application degree of each target core is identified, and the current running process, current execution function, and current function application degree of each target core are used as the core running information of each target core adapted for each running task.
[0101] Optionally, the identification module 220 is specifically used for:
[0102] For each running task, based on the position information of each target core corresponding to the running task, the temperature data corresponding to the core is identified in the temperature distribution information;
[0103] Based on the current function of each target core, the application level of the current function of each target core, and the temperature data corresponding to each target core, identify the temperature association information corresponding to each current function.
[0104] The temperature-related information corresponding to all currently executed functions is used as the chip's core operating temperature change information.
[0105] Optionally, the generation module 230 is specifically used for:
[0106] Based on the chip operating temperature change information, among the target chips, chips with abnormal temperatures are screened, and based on the temperature association information of the current function being executed corresponding to the chip with abnormal temperatures, and the target chip temperature of the chip, among the non-target chips, each new target chip corresponding to the current function is screened.
[0107] Based on the current running process of the target core, new running tasks of each new target core are identified, and new core running control information of each new target core is generated based on the new running tasks of each new target core.
[0108] Optionally, the generation module 230 is specifically used for:
[0109] Based on the current running process of the target core, the remaining core task flow of the target core is identified, and based on the remaining core task flow, the core cooperation task nodes between each new target core and the core interaction task nodes between each new target core are identified through a task allocation strategy.
[0110] The core cooperation task nodes and core interaction task nodes between the new target cores are sorted according to the remaining core task flow to obtain the new running task of each new target core.
[0111] Based on the new operating tasks of each new target core, a core control instruction sequence for each new target core is generated through an instruction generation strategy, and the core control instruction sequence for each new target core is used as the new core operating control information for each new target core.
[0112] The modules in the chip temperature control system based on chip-embedded technology described above can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each module.
[0113] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 3As shown, the computer device includes a processor, memory, communication interface, display screen, and input system connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a chip temperature control method based on chip-integrated technology. The display screen can be an LCD screen or an e-ink display screen. The input system can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.
[0114] Those skilled in the art will understand that Figure 3 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0115] In one embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in any one of the first aspects.
[0116] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any one of the first aspects.
[0117] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of the method described in any one of the first aspects.
[0118] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.
[0119] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0120] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0121] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A chip temperature control method based on chip-to-chip integration technology, characterized in that, The method includes: The system acquires the chip's temperature detection information and the chip's current operating data, and based on the chip's temperature detection information, identifies the chip's temperature distribution information through a temperature adaptation distribution identification strategy. Based on the current operating data of the chip, identify the chip operating information of each target chip adapted to each operating task of the chip, and based on the chip operating information of each operating task and the temperature distribution information, identify the chip operating temperature change information of the chip. Based on the core functions of each chip in the chip and the chip operating temperature change information, a temperature control adjustment strategy is used to generate new core operation control information for each new target core adapted to each running task of the chip.
2. The method according to claim 1, characterized in that, The step of identifying the temperature distribution information of the chip based on the temperature detection information of the chip, through a temperature adaptation distribution identification strategy, includes: Based on the temperature range corresponding to the temperature detection information, the applicable temperature adjustment strategy for the chip is identified, and based on the temperature adjustment strategy, the chip temperature detection map corresponding to the temperature detection information is subjected to image optimization processing to obtain the target temperature detection map corresponding to the chip. Based on the target temperature detection map, the temperature data corresponding to each location point of the chip is identified through a temperature grid splitting and identification strategy. The temperature data corresponding to each location point is then distributed and sorted according to the position information of each location point in the target temperature detection map to obtain the temperature distribution information of the chip.
3. The method according to claim 1, characterized in that, The process of identifying the chip operation information of each target chip adapted to each running task of the chip based on the chip's current operating data includes: The current running data is divided into current sub-running data corresponding to each running task, and the current running process of each target core corresponding to each current sub-running data and the current execution function of each target core are identified. Based on the current running process and current execution function of each target core, the current function application degree of each target core is identified, and the current running process, current execution function, and current function application degree of each target core are used as the core running information of each target core adapted for each running task.
4. The method according to claim 3, characterized in that, The method of identifying the chip's chip operating temperature change information based on the chip's chip operating information for each running task and the temperature distribution information includes: For each running task, based on the position information of each target core corresponding to the running task, the temperature data corresponding to the core is identified in the temperature distribution information; Based on the current function of each target core, the application level of the current function of each target core, and the temperature data corresponding to each target core, identify the temperature association information corresponding to each current function. The temperature-related information corresponding to all currently executed functions is used as the chip's core operating temperature change information.
5. The method according to claim 3, characterized in that, Based on the chip functions of each non-target chip and the chip's chip operating temperature change information, a temperature control adjustment strategy is used to generate new chip operation control information for each new target chip adapted to each running task of the chip, including: Based on the chip operating temperature change information, among the target chips, chips with abnormal temperatures are screened, and based on the temperature association information of the current function being executed corresponding to the chip with abnormal temperatures, and the target chip temperature of the chip, among the non-target chips, each new target chip corresponding to the current function is screened. Based on the current running process of the target core, new running tasks of each new target core are identified, and new core running control information of each new target core is generated based on the new running tasks of each new target core.
6. The method according to claim 5, characterized in that, The process of identifying new running tasks for each new target core based on its current running process, and generating new core running control information for each new target core based on its new running tasks, includes: Based on the current running process of the target core, the remaining core task flow of the target core is identified, and based on the remaining core task flow, the core cooperation task nodes between each new target core and the core interaction task nodes between each new target core are identified through a task allocation strategy. The core cooperation task nodes and core interaction task nodes between the new target cores are sorted according to the remaining core task flow to obtain the new running task of each new target core. Based on the new operating tasks of each new target core, a core control instruction sequence for each new target core is generated through an instruction generation strategy, and the core control instruction sequence for each new target core is used as the new core operating control information for each new target core.
7. A chip temperature control system based on chip-to-chip integration technology, characterized in that, The system includes: The acquisition module is used to acquire the chip's temperature detection information and the chip's current operating data, and based on the chip's temperature detection information, to identify the chip's temperature distribution information through a temperature adaptation distribution identification strategy; The identification module is used to identify the chip operation information of each target chip adapted to each running task of the chip based on the current running data of the chip, and to identify the chip operation temperature change information of the chip based on the chip operation information of each running task and the temperature distribution information. The generation module is used to generate new core operation control information for each new target core adapted to each running task of the chip, based on the core function of each core of the chip and the core operating temperature change information of the chip, and through a temperature control adjustment strategy.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.