Multi-stage cascade semantic analysis framework for kernel security level control code generation tool
By using a multi-stage cascaded semantic analysis framework, the performance bottlenecks and error handling limitations in the digital instrumentation and control system of nuclear power plants are solved, and an efficient and reliable code generation tool is realized, which supports the analysis of large projects and real-time requirements and meets the nuclear power industry standards.
Patent Information
- Application Number
- CN202511125200.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-12
- Publication Date
- 2025-11-14
Smart Images

Figure CN120950080A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of nuclear instrumentation and control system software technology, specifically to a multi-stage cascaded semantic analysis framework, system, device, and medium for a nuclear safety-level control code generation tool. Background Technology
[0002] The digital instrumentation and control system of a nuclear power plant is a critical support system for ensuring the safe operation of the plant. In the software development of this system, semantic analysis using code generation tools is a crucial step in ensuring system safety and reliability. According to the requirements of nuclear power industry standards IEC 61513 and IEC 60880, nuclear safety-grade software must undergo rigorous verification and validation processes. However, existing technologies have the following limitations: Current status of mainstream international technologies: ① SCADE Suite: Advantages: Mature formal verification methods, complete toolchain support, and extensive industrial application experience; Disadvantages: Significant performance bottlenecks, simplistic error handling mechanisms, and insufficient real-time performance. ② Simulink: Advantages: Provides a rich model library and a graphical development environment; Disadvantages: Insufficient security verification capabilities and poor code traceability.
[0003] Domestic research progress: ① Tsinghua University: Conducting research on code generation technology based on formal methods; ② Chinese Academy of Sciences: Establishing a real-time system modeling and verification platform; ③ Industry applications: There is an urgent need for localization, but the accumulation of technology is limited.
[0004] Key technical issues: ① Performance bottlenecks: Insufficient processing capacity for large-scale models (>50,000 lines of code), excessive memory consumption (>4GB), and low CPU utilization (<40%). ② Limitations in error handling: Single errors cause analysis interruptions, error location accuracy is low, and there is a lack of systematic error classification and handling mechanisms. ③ Real-time performance issues: Low accuracy of clock analysis, insufficient efficiency of synchronization mechanisms, and limited processing capacity of multi-clock domain systems.
[0005] Based on the analysis of the current state of the technology, there is an urgent need to develop a new semantic analysis framework to address key issues such as performance, reliability, and real-time performance of existing technologies. Summary of the Invention
[0006] The purpose of this invention is to provide a multi-stage cascaded semantic analysis framework, system, device, and medium for nuclear safety-level control code generation tools, so as to solve the technical problems existing in the prior art.
[0007] This invention is achieved through the following technical solution: In a first aspect, the first embodiment of the present invention provides a multi-stage cascaded semantic analysis framework for a nuclear safety-level control code generation tool, comprising: an input layer, an analysis module layer, an error handling layer, and an output layer. The input layer is used to receive and preprocess the control model XML file, verify the file format, and perform preliminary syntax checks. The analysis module layer is used to analyze the file's post-syntax, namespace, type, clock, causal relationship, and initialization semantic analysis tasks respectively after receiving the analysis request, and obtain the analysis results; The error handling layer is used to collect, classify, locate, and generate reports of various error information that occurs in the analysis module layer; The output layer is used to generate and output standardized analysis reports and optimization suggestions.
[0008] Furthermore, the framework also includes a cache management layer. After receiving an analysis request, the cache management layer performs a cache query through a hash index mechanism. When a cache hit occurs, the cache result is returned and the access record is updated. If a cache miss occurs, the analysis request is forwarded to the analysis module layer for analysis, and the analysis result is cached. The framework uses copy-on-write technology to handle concurrent updates and uses a version control mechanism to track data changes.
[0009] Furthermore, the analysis module layer includes: a post-syntax analysis module, a namespace analysis module, a type analysis module, a clock analysis module, a causal relationship analysis module, and an initialization analysis module. The post-parse module performs syntax rule verification and type declaration checks based on an improved recursive descent parsing algorithm; The namespace analysis module is used to manage identifier scope, optimize the symbol table, and detect conflicts. The type analysis module is used to perform type matching on the input data, process basic types, structure types and generic types respectively, merge type information and perform final verification to obtain type analysis results; The clock analysis module is used to construct clock dependencies using directed graph theory to perform clock dependency analysis, identify clock domains, construct clock domain dependency graphs, and verify clock hierarchy structures, and uses an improved synchronization verification algorithm to verify timing synchronization. The causal relationship analysis module uses an optimized graph structure to represent the dependencies between system components, performs circular dependency detection and temporal dependency analysis, and finally verifies the analysis results. The initialization analysis module is used for variable initialization verification, state initialization check, and startup sequence analysis to evaluate the security of the system startup process.
[0010] Furthermore, the error handling layer includes an error collector, an error classifier, an error locator, and a report generator. The error collector is used to collect errors generated by each module in parallel and prioritize the errors according to their severity. The error classifier is used to classify errors according to their severity and process them in different ways; The error locator is used to locate errors based on the abstract syntax tree, analyze the context in which the error occurs, and locate the error at the line level of the source code. The report generator is used to generate standardized error reports and display errors graphically.
[0011] Furthermore, the error collector includes: an error collection agent unit, an asynchronous transmission unit, and an error buffering and batch processing unit. The error collection agent unit is used to capture and record various error information that occurs during the analysis process in real time in each analysis module; The asynchronous transmission unit uses an asynchronous transmission mechanism to transmit error information; The error caching and batch processing unit is used to cache and batch process the collected error information.
[0012] Furthermore, the error collector also includes: a multi-level classification unit, a dynamic adjustment unit, and an error association analysis unit. The multi-level classification unit establishes a multi-level classification system based on the severity of the error; The dynamic adjustment unit adaptively adjusts the processing priority based on the severity of the error and the system resource status. The error association analysis unit is used to identify and process multiple errors that have a causal relationship.
[0013] Secondly, another embodiment of the present invention provides a multi-stage cascaded semantic analysis method for a nuclear safety-level control code generation tool, comprising: Receive the control model XML file and preprocess it, verifying the file format and performing a preliminary syntax check; Upon receiving the analysis request, the file's post-syntax, namespace, type, clock, causal relationship, and initialization semantic analysis tasks are analyzed to obtain the analysis results. Collect various error messages, classify, locate, and generate reports of these errors; Generate and output standardized analysis reports and optimization recommendations.
[0014] Furthermore, the method also includes: after receiving the analysis request, performing a cache query through a hash index mechanism; when a cache hit occurs, returning the cache result and updating the access record; if a cache miss occurs, re-analyzing the analysis request and caching the analysis result. Concurrent updates are handled using copy-on-write technology, and data changes are tracked through a version control mechanism.
[0015] Furthermore, the specific methods for analyzing the post-syntax, namespace, type, clock, causal relationship, and initialization semantic analysis tasks of the file respectively include: Syntax rule verification and type declaration checking are performed based on an improved recursive descent analysis algorithm; The symbol table management mechanism is based on red-black trees. It adopts a hierarchical scope management strategy to locate and control identifiers, uses a scope snapshot mechanism based on copy-on-write technology and an incremental update strategy based on change logs for scope management, uses string interning technology to manage symbols in a unified manner, optimizes the symbol table with a segmented loading mechanism and multi-level indexes, and performs duplicate declaration detection, scope conflict analysis and intelligent naming suggestions. Type analysis and classification are performed on the input data. Type inference and checking are performed based on the improved Hindley-Milner algorithm. Basic types, structural types and generic types are processed separately. The type information is merged and finally verified to obtain the type analysis results. Clock dependency analysis is performed by constructing clock dependencies using directed graph theory, which includes identifying clock domains, constructing clock domain dependency graphs, and verifying clock hierarchy. An improved synchronization verification algorithm is then used to verify timing synchronization. An optimized graph structure is used to represent the dependencies between system components, and circular dependency detection and temporal dependency analysis are performed. The analysis results are then verified. Variable initialization verification, state initialization check, and startup sequence analysis are used to assess the security of the system startup process.
[0016] Furthermore, the specific methods for collecting various error messages, classifying, locating, and generating reports of these error messages include: Errors generated by each module are collected in parallel and prioritized according to their severity. The errors are categorized according to their severity and handled in different ways. Error localization is based on abstract syntax trees, which analyze the context in which the error occurs and pinpoint the error to the line level of the source code. Generate standardized error reports and display errors graphically.
[0017] Furthermore, the specific method for collecting errors generated by each module in parallel includes: Capture and record various error messages that occur during the analysis process in real time; Error information is transmitted using an asynchronous transmission mechanism; The collected error information is cached and processed in batches.
[0018] Furthermore, the specific method for prioritizing errors according to their severity includes: A multi-level classification system was established based on the severity of the errors; Adaptively adjust processing priorities based on the severity of the error and the status of system resources; Identify and handle multiple errors that have a causal relationship.
[0019] Thirdly, another embodiment of the present invention provides a computer device including a processor, an input device, an output device, and a memory, wherein the processor, the input device, the output device, and the memory are interconnected, the memory is used to store a computer program, the computer program includes program instructions, and the processor is configured to invoke the program instructions to execute the method described in the above embodiments.
[0020] Fourthly, another embodiment of the present invention provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the methods described in the above embodiments.
[0021] Compared with the prior art, the present invention has the following advantages and beneficial effects: The multi-stage cascaded semantic analysis framework, method, device, and medium for nuclear safety level control code generation tools provided in this invention have the following advantages: First, the performance of the digital instrumentation and control system for nuclear power plants has been significantly improved, breaking through the performance bottlenecks of existing technologies. Through innovative multi-threaded parallel processing mechanisms and optimized memory management strategies, overall analysis efficiency has been increased by 150%, memory usage has been reduced by 40%, and CPU utilization has been increased to 85%. In particular, in the analysis of large-scale projects, it has successfully overcome the scale limitations of existing technologies, supporting project analysis of more than 100,000 lines of code, meeting the actual development needs of digital instrumentation and control systems for nuclear power plants.
[0022] Second, error handling capabilities are significantly enhanced, ensuring the reliability of code generation. The adoption of a distributed error collection architecture and an intelligent error classification system achieves 95% error location accuracy and reduces error repair time by 60%. An innovative intelligent error repair suggestion mechanism is introduced, supporting the automatic repair of 30% of common errors, greatly improving development efficiency.
[0023] Third, the timing analysis performance has been significantly optimized, improving the system's real-time performance. Through improved clock dependency analysis algorithms and multi-clock domain concurrent analysis techniques, the clock analysis accuracy has reached 98%, achieving concurrent analysis capability across 32 clock domains. Simultaneously, reanalysis time has been reduced by 85%, and the timing problem prevention rate has increased to 90%, providing strong assurance for the real-time performance of nuclear safety-grade software.
[0024] Fourth, the reliability of the digital instrumentation and control system of nuclear power plants has been comprehensively improved, fully meeting the requirements of nuclear power industry standards. The multi-stage cascaded semantic analysis framework of a nuclear safety-grade control code generation tool in this invention significantly improves the correctness of code generation, strictly complying with the requirements of IEC 61513 and IEC 60880 standards. In actual verification in multiple nuclear power projects, it has demonstrated excellent stability and reliability, providing reliable technical support for nuclear safety-grade software development. Attached Figure Description
[0025] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be considered as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of a multi-stage cascaded semantic analysis framework for a nuclear safety-level control code generation tool provided in the first embodiment of the present invention; Figure 2 for Figure 1 A schematic diagram of the command space analysis module in the document; Figure 3 for Figure 1 Workflow diagrams for the type analysis module, clock analysis module, and causal analysis module; Figure 4 This is a schematic diagram of the workflow of the error handling layer in the embodiment; Figure 5 This is a schematic diagram of the error collector in the embodiment; Figure 6 This is a flowchart illustrating the workflow of the cache management layer. Figure 7 A flowchart illustrating a multi-stage cascaded semantic analysis method for a nuclear safety-level control code generation tool, as provided in another embodiment of the present invention; Figure 8 for Figure 7 A flowchart of the specific method for step S2. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.
[0027] like Figure 1 As shown in the first embodiment of the present invention, a multi-stage cascaded semantic analysis framework for a nuclear safety-level control code generation tool is provided. This framework adopts a multi-level cascaded architecture and mainly includes four functional layers: the input layer is responsible for receiving and preprocessing control model XML files, implementing file format verification and preliminary syntax checking. The analysis module layer is the core of the framework, containing six serially connected analysis modules, each focusing on a specific type of semantic analysis task. The error handling layer uniformly manages the error information generated by each analysis module, providing error classification, location, and report generation functions. The output layer is responsible for generating the final analysis report and optimization suggestions.
[0028] This framework adopts a modular design, with each module communicating through standardized interfaces. The system can be developed using C++, and the runtime environment supports Linux and Windows platforms.
[0029] In this embodiment, the analysis module layer includes: a post-syntax analysis module, a namespace analysis module, a type analysis module, a clock analysis module, a causal relationship analysis module, and an initialization analysis module.
[0030] The post-parse module utilizes an improved recursive descent parsing algorithm to perform grammar rule verification and type declaration checks. It supports dynamic expansion and real-time verification of grammar rules. An adaptive lexical analyzer is employed to handle complex grammatical structures. Multi-threaded parallel processing improves analysis efficiency, and an incremental analysis strategy re-analyzes only changed parts. A type inference system based on attribute grammars supports generic and polymorphic type checks. The system employs a real-time verification mechanism to detect type errors during the coding phase. Integrated intelligent type inference reduces the need for explicit type declarations. Optimized lookup tables improve lexical analysis speed by 30%. Node pooling technology reduces memory usage by 50%. A cache reuse strategy improves repeated analysis efficiency by 80%.
[0031] like Figure 2As shown, the namespace analysis module manages identifier scope, optimizes the symbol table, and detects conflicts. A symbol table management mechanism based on red-black trees, through a hierarchical scope management strategy, achieves precise identifier location and access control. The system supports dynamic scope chain management, employs a scope snapshot mechanism using copy-on-write technology, and an incremental update strategy based on change logs. String interning technology enables unified symbol management, significantly reducing memory usage. A segmented loading mechanism combined with the LRU algorithm enables efficient processing of large projects. A multi-dimensional index structure is established, optimizing the search complexity to O(log n).
[0032] like Figure 3 As shown, the type analysis module performs type matching on the input data, processing basic types, structure types, and generic types respectively, merging type information, and performing final verification to obtain the type analysis result. Based on the Hindley-Milner algorithm, the type analysis module implements accurate type inference and checking functions, including: local type inference strategy, recursive type processing mechanism, and type constraint solving system. The Hindley-Milner algorithm is a method for automatically inferring the type of expressions in a programming language, ensuring that all expressions are well-typed without requiring explicit type annotations everywhere. The type analysis module provides rich type feature support, including: a basic type system supporting type conversion and operator overloading; composite type support supporting complex types such as arrays and structures; and subtype relationships establishing a type inheritance hierarchy through type lattices.
[0033] The clock analysis module uses directed graph theory to construct clock dependencies for analysis, identifying clock domains, constructing clock domain dependency graphs, and verifying clock hierarchy. An improved synchronization verification algorithm is used to verify timing synchronization. This improved algorithm ensures system timing correctness, including: cross-domain data transmission verification, sampling point timing analysis, and timing margin assessment.
[0034] The causal relationship analysis module implements system-level dependency analysis based on graph theory, including dependency graph construction, circular dependency detection, and temporal dependency analysis. Dependency graph construction uses an optimized graph structure to represent dependencies between system components, including: ① Node representation: abstracting system components as graph nodes; ② Edge representation: using weighted directed edges to represent dependencies; ③ Attribute annotation: adding temporal, type, and other attributes to nodes and edges. Circular dependency detection implements efficient loop detection algorithms, including: ① Tarjan's algorithm: identifying strongly connected components; ② Priority analysis: assessing the severity of circular dependencies; ③ Feedback processing: generating solutions to circular dependencies. Temporal dependency analysis comprehensively considers data flow and control flow dependencies, including: ① Control dependency: analyzing dependencies in program execution flow; ② Data dependency: tracing data transmission paths; ③ Resource dependency: identifying access conflicts to shared resources.
[0035] The initialization analysis module verifies the correctness of the startup process of the nuclear power plant's digital instrumentation and control system, performing variable initialization verification, state initialization checks, and startup sequence analysis. Variable initialization verification ensures all variables are correctly initialized before use, including: ① Static analysis: checking the initialization status at the time of variable declaration; ② Dynamic tracing: analyzing the initialization sequence during runtime; ③ Condition verification: handling the initialization logic in conditional branches. State initialization checks verify the initialization process of the state machine of the nuclear power plant's digital instrumentation and control system, including: ① State integrity: ensuring all states have explicit initial values; ② Transition validity: verifying the correctness of initial state transitions; ③ Deadlock prevention: detecting deadlock risks during the initialization process. Startup sequence analysis assesses the safety of the nuclear power plant's digital instrumentation and control system startup process, including: ① Dependency ordering: generating the optimal order of component initialization; ② Timing verification: ensuring the correctness of timing during startup; ③ Resource allocation: verifying resource usage during startup.
[0036] like Figure 4 As shown, the error handling layer employs a multi-layered error management architecture, including an error collector, error classifier, error locator, and report generator, to achieve efficient collection, precise location, and intelligent processing of error information. The error collector is distributed, enabling lightweight error collection that collects errors generated by various modules in parallel and prioritizes them according to severity. The error classifier categorizes errors based on their severity and processes them using different methods. The error locator includes: an AST analyzer for error location based on an abstract syntax tree; a context tracker for analyzing the context in which the error occurred; and a source code locator for precise location down to the line-level of source code. The report generator produces standardized error reports and provides graphical error visualizations, and also includes an export module supporting multiple export formats.
[0037] like Figure 5 As shown, the error collector includes an error collection agent unit, an asynchronous transmission unit, and an error caching and batch processing unit. The error collection agent unit can capture and record various error messages that occur during the analysis process in real time. The asynchronous transmission unit adopts an asynchronous error message transmission mechanism, effectively reducing the impact of error collection on the main analysis process. The error caching and batch processing unit establishes an error caching and batch processing mechanism, significantly improving error handling efficiency through reasonable caching strategies and batch processing methods.
[0038] The error collector also includes a multi-level classification unit, a dynamic adjustment unit, and an error correlation analysis unit. The multi-level classification unit establishes a multi-level classification system based on the severity of errors, enabling accurate identification and classification of different types of errors. The dynamic adjustment unit implements a dynamic error processing order adjustment mechanism, adaptively adjusting processing priorities according to error severity and system resource status. The error correlation analysis unit has error correlation analysis capabilities, effectively identifying and processing multiple errors with causal relationships.
[0039] The error handling layer achieves the following technical effects: (1) High efficiency: Through distributed architecture and asynchronous processing mechanism, error handling efficiency is significantly improved.
[0040] (2) Accuracy: With the help of a multi-level classification system and association analysis function, the error is accurately located and classified.
[0041] (3) Reliability: The use of caching and batch processing mechanisms ensures the reliable transmission and processing of error information.
[0042] (4) Intelligence: Intelligent error handling is achieved through adaptive priority management.
[0043] This invention organically combines various input layers, analysis module layers, error handling layers, and output layers. The modules communicate using standardized interfaces, supporting flexible expansion and customization. Simultaneously, a robust error handling mechanism provides developers with clear problem diagnosis and repair suggestions. This not only solves key problems in existing technologies but also achieves an overall improvement in the quality and efficiency of nuclear safety-grade control code generation. The application of this invention is of great significance for enhancing the independent controllability of digital instrumentation and control systems in my country's nuclear power plants.
[0044] In another embodiment of the present invention, based on the first embodiment, the framework further includes a cache management layer to implement intelligent caching and incremental updates of analysis results. For example... Figure 6As shown, after receiving an analysis request, the cache management layer performs a cache lookup using a hash index mechanism. This design ensures rapid data location capabilities and significantly improves system response speed. When a cache hit occurs, the cached result is returned and the access record is updated. If a cache miss occurs, the analysis request is forwarded to the analysis module layer for analysis, and the analysis result is cached. Copy-on-write technology is used to handle concurrent updates, and a version control mechanism tracks data changes to ensure the reliability and consistency of cached data. In abnormal situations, the system can recover to a previous stable state through a rollback mechanism. Through this optimized cache management mechanism, the cache management layer effectively improves analysis efficiency while ensuring data reliability, providing performance assurance for the entire semantic analysis framework. Practical applications show that this mechanism improves the analysis performance of the nuclear power plant's digital instrumentation and control system by approximately 35%, significantly reducing redundant computation overhead.
[0045] The multi-stage cascaded semantic analysis framework for a nuclear safety-level control code generation tool provided in this invention represents a significant technological advancement compared to existing technologies, specifically in the following four aspects: First, the performance of the digital instrumentation and control system for nuclear power plants has been significantly improved, breaking through the performance bottlenecks of existing technologies. Through innovative multi-threaded parallel processing mechanisms and optimized memory management strategies, overall analysis efficiency has been increased by 150%, memory usage has been reduced by 40%, and CPU utilization has been increased to 85%. In particular, in the analysis of large-scale projects, it has successfully overcome the scale limitations of existing technologies, supporting project analysis of more than 100,000 lines of code, meeting the actual development needs of digital instrumentation and control systems for nuclear power plants.
[0046] Second, error handling capabilities are significantly enhanced, ensuring the reliability of code generation. The adoption of a distributed error collection architecture and an intelligent error classification system achieves 95% error location accuracy and reduces error repair time by 60%. An innovative intelligent error repair suggestion mechanism is introduced, supporting the automatic repair of 30% of common errors, greatly improving development efficiency.
[0047] Third, the timing analysis performance has been significantly optimized, improving the system's real-time performance. Through improved clock dependency analysis algorithms and multi-clock domain concurrent analysis techniques, the clock analysis accuracy has reached 98%, achieving concurrent analysis capability across 32 clock domains. Simultaneously, reanalysis time has been reduced by 85%, and the timing problem prevention rate has increased to 90%, providing strong assurance for the real-time performance of nuclear safety-grade software.
[0048] Fourth, the reliability of the digital instrumentation and control system of nuclear power plants has been comprehensively improved, fully meeting the requirements of nuclear power industry standards. The multi-stage cascaded semantic analysis framework of a nuclear safety-grade control code generation tool in this invention significantly improves the correctness of code generation, strictly complying with the requirements of IEC 61513 and IEC 60880 standards. In actual verification in multiple nuclear power projects, it has demonstrated excellent stability and reliability, providing reliable technical support for nuclear safety-grade software development.
[0049] like Figure 7 As shown, another embodiment of the present invention provides a multi-stage cascaded semantic analysis method for a nuclear safety-level control code generation tool, comprising the following steps: S1: Receive the control model XML file and preprocess it, verify the file format and perform a preliminary syntax check; S2: After receiving the analysis request, analyze the file's post-syntax, namespace, type, clock, causal relationship and initialization semantic analysis tasks respectively, and obtain the analysis results; S3: The collection method also includes: after receiving the analysis request, performing a cache query through the hash index mechanism. When a cache hit occurs, the cache result is returned and the access record is updated. If a cache miss occurs, the analysis request is re-analyzed and the analysis result is cached. S4: Uses copy-on-write technology to handle concurrent updates and tracks data changes through a version control mechanism.
[0050] The specific methods for analyzing the file's post-syntax, namespace, type, clock, causal relationships, and initial semantic analysis tasks in step S2 are as follows: Figure 8 As shown, it includes: Syntax rule verification and type declaration checking are performed based on an improved recursive descent analysis algorithm; The symbol table management mechanism is based on red-black trees. It adopts a hierarchical scope management strategy to locate and control identifiers, uses a scope snapshot mechanism based on copy-on-write technology and an incremental update strategy based on change logs for scope management, uses string interning technology to manage symbols in a unified manner, optimizes the symbol table with a segmented loading mechanism and multi-level indexes, and performs duplicate declaration detection, scope conflict analysis and intelligent naming suggestions. Type analysis and classification are performed on the input data. Type inference and checking are performed based on the improved Hindley-Milner algorithm. Basic types, structural types and generic types are processed separately. The type information is merged and finally verified to obtain the type analysis results. Clock dependency analysis is performed by constructing clock dependencies using directed graph theory, which includes identifying clock domains, constructing clock domain dependency graphs, and verifying clock hierarchy. An improved synchronization verification algorithm is then used to verify timing synchronization. An optimized graph structure is used to represent the dependencies between system components, and circular dependency detection and temporal dependency analysis are performed. The analysis results are then verified. Variable initialization verification, state initialization check, and startup sequence analysis are used to assess the security of the system startup process.
[0051] The specific methods for collecting, classifying, locating, and generating reports of various error messages include: Errors generated by each module are collected in parallel and prioritized according to their severity. The errors are categorized according to their severity and handled in different ways. Error localization is based on abstract syntax trees, which analyze the context in which the error occurs and pinpoint the error to the line level of the source code. Generate standardized error reports and display errors graphically.
[0052] The specific method for collecting errors generated by each module in parallel includes: Capture and record various error messages that occur during the analysis process in real time; Error information is transmitted using an asynchronous transmission mechanism; The collected error information is cached and processed in batches.
[0053] Specific methods for prioritizing errors according to their severity include: A multi-level classification system was established based on the severity of the errors; Adaptively adjust processing priorities based on the severity of the error and the status of system resources; Identify and handle multiple errors that have a causal relationship.
[0054] Various error messages are categorized, located, and reported. Generate and output standardized analysis reports and optimization recommendations.
[0055] The multi-stage cascaded semantic analysis method for a nuclear safety-level control code generation tool provided in this embodiment of the invention is based on the same inventive concept and has the same beneficial effects as the multi-stage cascaded semantic analysis framework for the aforementioned nuclear safety-level control code generation tool, and will not be repeated here.
[0056] Another embodiment of the present invention provides a computer device, which includes a processor, an input device, an output device, and a memory. The processor, the input device, the output device, and the memory are interconnected. The memory is used to store a computer program, which includes program instructions. The processor is configured to call the program instructions to execute the method described in the first embodiment above.
[0057] It should be understood that, in the embodiments of the present invention, the processor may be a Central Processing Unit (CPU), but it may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.
[0058] Input devices may include touchpads, fingerprint sensors (used to collect the user's fingerprint information and fingerprint orientation information), microphones, etc., while output devices may include displays (LCDs, etc.), speakers, etc.
[0059] The memory may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of the memory may also include non-volatile random access memory. For example, the memory may also store information about the device type.
[0060] In specific implementations, the processor, input device, and output device described in the embodiments of the present invention can execute the implementation methods described in the framework provided in the embodiments of the present invention, or they can execute the implementation methods described in the methods provided in the embodiments of the present invention, which will not be elaborated here.
[0061] The present invention also provides an embodiment of a computer-readable storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, cause the processor to perform the methods described in the above embodiments.
[0062] The computer-readable storage medium can be an internal storage unit of the terminal described in the foregoing embodiments, such as the terminal's hard drive or memory. The computer-readable storage medium can also be an external storage device of the terminal, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the terminal. Furthermore, the computer-readable storage medium can include both internal storage units and external storage devices. The computer-readable storage medium is used to store the computer program and other programs and data required by the device. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.
[0063] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0064] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the terminals and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0065] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices or units, or may be electrical, mechanical or other forms of connection.
[0066] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and specification of the present invention.
Claims
1. A multi-stage cascaded semantic analysis framework for a nuclear safety-level control code generation tool, characterized in that, include: Input layer, analysis module layer, error handling layer, and output layer. The input layer is used to receive and preprocess the control model XML file, verify the file format, and perform preliminary syntax checks. The analysis module layer is used to analyze the file's post-syntax, namespace, type, clock, causal relationship, and initialization semantic analysis tasks respectively after receiving the analysis request, and obtain the analysis results; The error handling layer is used to collect, classify, locate, and generate reports of various error information that occurs in the analysis module layer; The output layer is used to generate and output standardized analysis reports and optimization suggestions.
2. The framework as described in claim 1, characterized in that, The framework also includes a cache management layer. After receiving an analysis request, the cache management layer performs a cache query through a hash index mechanism. When a cache hit occurs, the cache result is returned and the access record is updated. If a cache miss occurs, the analysis request is forwarded to the analysis module layer for analysis, and the analysis result is cached. Concurrent updates are handled using copy-on-write technology, and data changes are tracked through a version control mechanism.
3. The framework as described in claim 1 or 2, characterized in that, The analysis module layer includes: a post-syntax analysis module, a namespace analysis module, a type analysis module, a clock analysis module, a causal relationship analysis module, and an initialization analysis module. The post-parse module performs syntax rule verification and type declaration checks based on an improved recursive descent parsing algorithm; The namespace analysis module is used to manage identifier scope, optimize the symbol table, and detect conflicts. The type analysis module is used to perform type matching on the input data, process basic types, structure types and generic types respectively, merge type information and perform final verification to obtain type analysis results; The clock analysis module is used to construct clock dependencies using directed graph theory to perform clock dependency analysis, identify clock domains, construct clock domain dependency graphs, and verify clock hierarchy structures, and uses an improved synchronization verification algorithm to verify timing synchronization. The causal relationship analysis module uses an optimized graph structure to represent the dependencies between system components, performs circular dependency detection and temporal dependency analysis, and finally verifies the analysis results. The initialization analysis module is used for variable initialization verification, state initialization check, and startup sequence analysis to evaluate the security of the system startup process.
4. The framework as described in claim 3, characterized in that, The error handling layer includes an error collector, an error classifier, an error locator, and a report generator. The error collector is used to collect errors generated by each module in parallel and prioritize the errors according to their severity. The error classifier is used to classify errors according to their severity and process them in different ways; The error locator is used to locate errors based on the abstract syntax tree, analyze the context in which the error occurs, and locate the error at the line level of the source code. The report generator is used to generate standardized error reports and display errors graphically.
5. The framework as described in claim 4, characterized in that, The error collector includes: an error collection agent unit, an asynchronous transmission unit, and an error buffering and batch processing unit. The error collection agent unit is used to capture and record various error information that occurs during the analysis process in real time in each analysis module; The asynchronous transmission unit uses an asynchronous transmission mechanism to transmit error information; The error caching and batch processing unit is used to cache and batch process the collected error information.
6. The framework as described in claim 5, characterized in that, The error collector further includes: a multi-level classification unit, a dynamic adjustment unit, and an error association analysis unit. The multi-level classification unit establishes a multi-level classification system based on the severity of the error; The dynamic adjustment unit adaptively adjusts the processing priority based on the severity of the error and the system resource status. The error association analysis unit is used to identify and process multiple errors that have a causal relationship.
7. A multi-stage cascaded semantic analysis method for a nuclear safety-level control code generation tool, characterized in that, include: Receive the control model XML file and preprocess it, verifying the file format and performing a preliminary syntax check; Upon receiving the analysis request, the file's post-syntax, namespace, type, clock, causal relationship, and initialization semantic analysis tasks are analyzed to obtain the analysis results. Collect various error messages, classify, locate, and generate reports of these errors; Generate and output standardized analysis reports and optimization recommendations.
8. The method as described in claim 7, characterized in that, The method further includes: after receiving the analysis request, performing a cache query through a hash index mechanism; when a cache hit occurs, returning the cache result and updating the access record; if a cache miss occurs, re-analyzing the analysis request, caching the analysis result, using copy-on-write technology to handle concurrent updates, and tracking data changes through a version control mechanism.
9. The method as described in claim 8, characterized in that, The specific methods for analyzing the post-syntax, namespace, type, clock, causal relationship, and initialization semantic analysis tasks of the file include: Syntax rule verification and type declaration checking are performed based on an improved recursive descent analysis algorithm; The symbol table management mechanism is based on red-black trees. It adopts a hierarchical scope management strategy to locate and control identifiers, uses a scope snapshot mechanism based on copy-on-write technology and an incremental update strategy based on change logs for scope management, uses string interning technology to manage symbols in a unified manner, optimizes the symbol table with a segmented loading mechanism and multi-level indexes, and performs duplicate declaration detection, scope conflict analysis and intelligent naming suggestions. Type analysis and classification are performed on the input data. Type inference and checking are performed based on the improved Hindley-Milner algorithm. Basic types, structural types and generic types are processed separately. The type information is merged and finally verified to obtain the type analysis results. Clock dependency analysis is performed by constructing clock dependencies using directed graph theory, which includes identifying clock domains, constructing clock domain dependency graphs, and verifying clock hierarchy. An improved synchronization verification algorithm is then used to verify timing synchronization. An optimized graph structure is used to represent the dependencies between system components, and circular dependency detection and temporal dependency analysis are performed. The analysis results are then verified. Variable initialization verification, state initialization check, and startup sequence analysis are used to assess the security of the system startup process.
10. The method as described in claim 9, characterized in that, The specific methods for collecting various types of error information, classifying, locating, and generating reports of the error information include: Errors generated by each module are collected in parallel and prioritized according to their severity. The errors are categorized according to their severity and handled in different ways. Error localization is based on abstract syntax trees, which analyze the context in which the error occurs and pinpoint the error to the line level of the source code. Generate standardized error reports and display errors graphically.
11. The method as described in claim 10, characterized in that, The specific method for collecting errors generated by each module in parallel includes: Capture and record various error messages that occur during the analysis process in real time; Error information is transmitted using an asynchronous transmission mechanism; The collected error information is cached and processed in batches.
12. The method as described in claim 11, characterized in that, The specific method for prioritizing errors according to their severity includes: A multi-level classification system was established based on the severity of the errors; Adaptively adjust processing priorities based on the severity of the error and the status of system resources; Identify and handle multiple errors that have a causal relationship.
13. A computer device comprising a processor, an input device, an output device, and a memory, wherein the processor, input device, output device, and memory are interconnected, and the memory is used to store a computer program, the computer program comprising program instructions, characterized in that... The processor is configured to invoke the program instructions to perform the method as described in any one of claims 7-12.
14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, cause the processor to perform the method as described in any one of claims 7-12.
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