Single bus equipment IO data acquisition and control method
By constructing a single-bus system, using master and slave I/O interfaces, and setting bus levels and timing, the complex wiring and debugging difficulties of multi-module low I/O signal systems were solved, achieving the effects of simplified wiring and improved acquisition capabilities.
Patent Information
- Application Number
- CN202511083812.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-04
- Publication Date
- 2025-11-14
AI Technical Summary
Existing technologies in multi-module low-IO signal acquisition systems are characterized by complex wiring, difficult installation, complex system debugging, and a high probability of failure. Especially when there are many modules, existing solutions cannot effectively simplify wiring and improve acquisition capabilities.
By constructing a single-bus system, using one master station and multiple slave stations' IO interfaces, and setting bus level states and timing requirements, the system enables data uploading and downloading of module IO signals, simplifying field wiring and improving data acquisition capabilities.
It simplifies wiring and enables efficient data acquisition for multi-module low-IO signal systems, reduces installation and debugging difficulty, and improves the equipment's IO signal acquisition capabilities.
Smart Images
Figure CN120950425A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of data acquisition technology, specifically a method for acquiring and controlling I / O data of a single-bus device. Background Technology
[0002] For acquisition systems with multiple modules and each module having a small number of I / O signals (e.g., one input and one output), wiring installation and system debugging are complex tasks. The current main implementation schemes include the following three methods.
[0003] 1) Direct signal input to the main control acquisition board: Each module requires three wires, including a positive and negative DC power supply wire (usually 5V, 12V, or 24V) and a signal wire. The signal wire must be connected to the acquisition board of the acquisition system. This method is theoretically the simplest and easiest to troubleshoot. However, in this system, each module has an independent signal line. When the number of modules is large, the number of wires increases significantly, making installation and wiring more difficult. Furthermore, each module's signal requires an interface on the acquisition board, increasing the performance and number of acquisition modules, resulting in a poor overall cost-effectiveness.
[0004] 2) Asynchronous serial communication: Asynchronous serial communication is a basic inter-device communication method with high speed, bidirectional transmission and reception, and data verification functions. However, in the multi-node, low-IO signal system mentioned above, the data load is extremely low, and each module node is required to have asynchronous serial communication capability, placing relatively high demands on the module nodes. Furthermore, asynchronous serial communication requires four wires: two for power and two for transmit and receive signals. When there are many nodes, the installation, wiring, and debugging work are not significantly improved.
[0005] 3) Gateway and hierarchical acquisition method: Combining the advantages and disadvantages of 1) and 2), the gateway and hierarchical acquisition management method is a better design method for acquisition systems with multiple modules and low IO signals. However, with the introduction of the intermediate layer gateway, the amount of system debugging functions increases and the probability of system failure increases. Summary of the Invention
[0006] The purpose of this invention is to address the problems existing in the prior art and provide a method for acquiring and controlling I / O data of a single-bus device. This method constructs a single-wire bus by connecting one I / O interface of the acquisition module with the I / O interfaces of multiple modules. The functions and timing requirements of the master and slave control nodes on the single-wire bus are defined, enabling the uploading and downloading of I / O signal data from each module. Simultaneously, the acquisition module has a large number of I / O interface resources, effectively providing multiple single-wire buses, significantly improving the device's I / O signal acquisition capability and greatly simplifying field wiring, thus bringing numerous conveniences to on-site installation and commissioning.
[0007] To achieve the above objectives, the present invention employs the following technical solution: A method for acquiring and controlling I / O data of a single-bus device is disclosed. First, a single-bus system is constructed, comprising a master station and several slave stations, each with its own I / O interface. Each I / O interface on the bus is an open-drain source output and is connected to the positive terminal of the power supply via pull-up resistors. Then, addresses are assigned to the slave stations, ranging from 1 to N, where N is a natural number greater than 1. Finally, the bus level states are set, with the master station controlling the bus timing and the slave stations responding according to the timing requirements. The bus level states include high and low levels.
[0008] Preferably, the bus time base unit is set to 3ms, with data 1 representing a high level and data 0 representing a low level.
[0009] Preferably, a data frame is composed of several time base units arranged sequentially from left to right, wherein 1 to M are fixed to 0, and M is a natural number greater than 1; M+1 is fixed to 1; M+2 is for identifying read and write control, wherein 1 indicates that the data frame is a read operation, and 0 indicates that the data frame is a write operation; the odd-numbered bits in M+3 to M+2N+2 are the response bits of slave station 1 to N in sequence, and this bit is controlled by the respective slave station module to be 0, indicating that the module is online; the even-numbered bits in M+3 to M+2N+2 are data bits, wherein when the data frame is a read operation, it represents the data measured by each module, and when the data frame is a write operation, it represents the output status of the module to be controlled.
[0010] Preferably, the interval between data frames is greater than 120ms, and the bus is in an idle state of 1.
[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention establishes a single-wire bus by connecting one I / O interface of the acquisition module with the I / O interfaces of multiple modules. The functions and timing requirements of the master and slave nodes on this single-wire bus are defined, enabling the uploading and downloading of I / O signal data for each module. Simultaneously, the acquisition module has a large number of I / O interface resources, effectively providing multiple single-wire buses. This significantly improves the device's I / O signal acquisition capability and greatly simplifies field wiring, bringing numerous conveniences to on-site installation and commissioning. Attached Figure Description
[0012] Figure 1 It is a single-bus topology diagram.
[0013] Figure 2 This is a schematic diagram illustrating the time base unit.
[0014] Figure 3 This is a schematic diagram of the data frame structure.
[0015] Figure 4 This is a schematic diagram illustrating the bus. Detailed Implementation
[0016] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined in this application.
[0017] Example: The present invention describes a single-bus device IO data acquisition and control method. This method can be used in the fields of electromechanical measurement and control, data acquisition and management, especially for acquisition systems with a large number of measurement and control modules but a small number of IO signals per module.
[0018] This embodiment uses 8 slave stations and 38 time base units as an example for illustration.
[0019] As attached Figure 1 As shown, the single bus includes a master station and eight slave stations, each with its own I / O interface. Each I / O interface is an open-drain source output, connected to the positive power supply via pull-up resistors. Slave stations are assigned addresses, numbered 1 to 8. The bus voltage levels include both high and low, and the bus timing is controlled by the master station, with the slave stations responding according to the timing requirements.
[0020] Further details are attached. Figure 2 As shown, the bus time base is 3ms, including two levels: data 1 (high level) and data 0 (low level). In the attached diagram, 'x' represents either 1 or 0.
[0021] Furthermore, the data frame consists of 38 time base units, with the format shown in the attached figure. Figure 3 As shown, bits 1-20 are fixed at 0; bit 21 is fixed at 1; bit 22 is for read / write control, where 1 indicates a read operation and 0 indicates a write operation. Bits 23, 25, 27, 29, 31, 33, 35, and 37 are response bits for slave stations 1-8, controlled by their respective slave modules, indicating that the module is online (bit 0). Bits 24, 26, 28, 30, 32, 34, 36, and 38 are data bits. For read operations, these bits represent the data measured by each module; for write operations, they represent the output status of the module to be controlled.
[0022] Further details are attached. Figure 4 As shown, the interval between data frames should be greater than 120ms, and the bus should be in an idle state of 1.
[0023] This embodiment achieves module I / O signal acquisition and control through coordinated control of the master station and eight slave station I / O ports. The bus has read / write capabilities and online monitoring capabilities for slave devices. This bus implementation allows for the connection of eight modules via three wires (two for power and one for signal) in series, greatly simplifying wiring. Furthermore, when the master control module has multiple I / O pins, it can simultaneously provide multiple single-bus, significantly simplifying the acquisition system for low I / O signals from multiple modules.
Claims
1. A method for acquiring and controlling I / O data of a single-bus device, characterized in that: First, a single-bus system is constructed, consisting of one master station and several slave stations, each with its own I / O interface. Each I / O interface on the bus is an open-drain source output and is connected to the positive power supply via pull-up resistors. Then, addresses are assigned to the slave stations, ranging from 1 to N, where N is a natural number greater than 1. Finally, the bus level states are set, with the master station controlling the bus timing and the slave stations responding according to the timing requirements. The bus level states include high and low levels.
2. The method for acquiring and controlling I / O data of a single-bus device according to claim 1, characterized in that: Set the bus time base unit to 3ms, where data 1 represents a high level and data 0 represents a low level.
3. The method for acquiring and controlling I / O data of a single-bus device according to claim 2, characterized in that: A data frame is composed of several time base units arranged from left to right. Units 1 through M are fixed at 0, where M is a natural number greater than 1; M+1 is fixed at 1; M+2 is for read / write control, where 1 indicates a read operation and 0 indicates a write operation; the odd-numbered bits from M+3 to M+2N+2 are the response bits for slave stations 1 through N, controlled by their respective slave modules, with bit 0 indicating the module is online; the even-numbered bits from M+3 to M+2N+2 are data bits, representing the data measured by each module during a read operation and the output status of the module to be controlled during a write operation.
4. The method for acquiring and controlling I / O data of a single-bus device according to claim 3, characterized in that: The interval between data frames is greater than 120ms, and the bus is in an idle state of 1.