A general interface algorithm acceleration device and acceleration method

Abstract

The application provides a general interface algorithm acceleration device and an acceleration method, which comprises the following steps: a configuration unit is configured to configure information of a software task to be executed; an algorithm scheduling acceleration unit is configured to read the software task, analyze data from the software task, obtain configuration information and data required by an algorithm, and write the configuration information and data into an algorithm module; an SPI_RNG unit is configured to obtain random numbers from an external random source according to task requirements and write the random numbers into the algorithm module; after the algorithm calculation is completed, the algorithm scheduling acceleration unit obtains an algorithm end flag, reads an algorithm result, places the algorithm result at a result output address specified by the configuration unit, updates an algorithm state, and transmits the updated algorithm state to the configuration unit; and the configuration unit executes a task according to the updated task state and a related address of the algorithm scheduling acceleration unit. The application can reduce additional time other than algorithm calculation, and improves the actual application efficiency of the algorithm.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of embedded chips, and particularly relates to a general interface algorithm acceleration device and an acceleration method. BACKGROUND

[0002] In the calling process of the general interface algorithm, the general interface algorithm module needs to be configured multiple times, and CPU operation and DMA operation for data transmission need to be performed multiple times in the configuration process. The CPU configuration and the DMA operation occupy a large amount of additional time, thereby reducing the actual performance of the algorithm. SUMMARY

[0003] Therefore, the application aims to provide a general interface algorithm acceleration device and an acceleration method to reduce the number of CPU interventions and the number of DMA initiations.

[0004] To achieve the above-mentioned purpose, the technical scheme of the application is as follows:

[0005] In a first aspect, the application provides a general interface algorithm acceleration device, comprising a configuration unit, an SPI_RNG unit and an algorithm scheduling acceleration unit connected with each other.

[0006] The configuration unit is configured to perform information configuration on a software task to be executed.

[0007] The algorithm scheduling acceleration unit is configured to read the software task and perform data analysis on the software task to obtain configuration information and data required by the algorithm, and write the configuration information and the data into a backend algorithm module for algorithm calculation.

[0008] The SPI_RNG unit is configured to obtain random numbers from an external random source according to task requirements and write the random numbers into the algorithm module.

[0009] In response to the end of the algorithm calculation, the algorithm scheduling acceleration unit obtains an algorithm end flag and reads an algorithm result, places the algorithm result at a result output address specified by the configuration unit, updates an algorithm state and transmits the updated algorithm state to the configuration unit, and the configuration unit executes a corresponding task according to the updated task state of the algorithm scheduling acceleration unit and a related address. The updated task state corresponds to the algorithm state.

[0010] In a second aspect, based on the same inventive concept, the application further provides a general interface algorithm acceleration method, comprising:

[0011] performing information configuration on a software task to be executed;

[0012] read the software task and parse data from the software task to parse configuration information and data required by the algorithm, obtain a random number from an external random source, and write the random number, the configuration information and the data into the algorithm;

[0013] In response to the end of the algorithm calculation, an algorithm end flag is obtained and an algorithm result is read, the algorithm state is updated according to the algorithm result, and the task state and related addresses are updated based on the updated algorithm state to execute corresponding tasks.

[0014] In a third aspect, based on the same inventive concept, the present application also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method of the second aspect when executing the program.

[0015] In a fourth aspect, based on the same inventive concept, the present application also provides a non-transitory computer readable storage medium, wherein the non-transitory computer readable storage medium stores computer instructions for causing the computer to execute the method of the second aspect.

[0016] Compared with the prior art, the general interface algorithm acceleration device and the acceleration method have the following beneficial effects:

[0017] The general interface algorithm acceleration device parses the configuration operation and data required by the algorithm from the software task, and then completes the configuration of the algorithm flow and the delivery of data through the self-owned general bus interface, thereby greatly reducing the number of CPU intervention and the number of CPU configuration DMA start, and further greatly reducing the additional time outside the algorithm calculation, and effectively improving the actual application efficiency of the algorithm. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which form a part of this application, are intended to provide further understanding of the application and are incorporated herein for a purpose of explanations. The illustrative embodiments of the present application, together with its description, are used to explain the present application and are not intended to limit the present application unduly.

[0019] Figure 1 A general interface algorithm acceleration device structure diagram according to an embodiment of the present application;

[0020] Figure 2 A general interface algorithm acceleration method flowchart according to an embodiment of the present application;

[0021] Figure 3 An electronic device hardware structure diagram according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] For purposes of the present application, the following terms have the following meanings:

[0023] It should be noted that, unless otherwise defined, technical terms or scientific terms used in the embodiments of the present application shall have the common meaning understood by one of ordinary skill in the art to which the present application pertains. The terms "first", "second", and similar terms used in the embodiments of the present application do not denote any order, quantity, or importance, but are merely used to distinguish different components. The terms "include", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms do not mean only physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are merely used to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0024] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0025] Referring to FIG. 1, Figure 1 The embodiment provides a general interface algorithm acceleration device, which comprises a configuration unit, an SPI_RNG unit, and an algorithm scheduling acceleration unit connected together.

[0026] The configuration unit is configured to perform information configuration on a software task to be executed.

[0027] The algorithm scheduling acceleration unit is configured to read the software task and perform data analysis from the software task to obtain configuration information and data required by the algorithm, and write the configuration information and data into an algorithm module at the back end for algorithm calculation.

[0028] The SPI_RNG unit is configured to obtain random numbers from an external random source according to the task requirement and write the random numbers into the algorithm module.

[0029] In response to the end of the algorithm calculation, the algorithm scheduling acceleration unit obtains an algorithm end flag and reads the algorithm result, places the algorithm result at a result output address specified by the configuration unit, updates the algorithm state and transmits the updated algorithm state to the configuration unit, and the configuration unit executes the corresponding task according to the updated task state and the related address of the algorithm scheduling acceleration unit. The updated task state corresponds to the algorithm state.

[0030] Specifically, in the present embodiment, the configuration unit has a general bus interface BUS_S for receiving CPU configuration. In order to minimize the number of CPU participation, the unit only needs to perform three CPU configurations, i.e. configuring the algorithm scheduling acceleration unit to read the address of the software task, outputting the address of the algorithm result and the number of software tasks after the completion of the algorithm, and a total of three parameters. The unit is also responsible for obtaining the state of the algorithm scheduling from the algorithm scheduling acceleration unit, updating the state of the above three parameters according to the state, and at the same time, the unit can also control the SPI_RNG unit to write a specific number of random numbers to a specific address (only used during initial debugging).

[0031] The SPI_RNG unit includes a general bus master interface BUS_M3 for directly writing the required random numbers to the algorithm or the designated address. In the general interface algorithm, the externally generated random numbers are required. If the random numbers are obtained from the outside through the general CPU channel and then written to the algorithm, a large amount of operation time will be wasted. In order to reduce these times, the SPI_RNG unit in the present device can directly obtain random numbers from the external random source and then directly send the random numbers to the algorithm module through the general bus master interface (the algorithm module and the algorithm scheduling acceleration unit are used in cooperation, the algorithm module refers to a module with a general configuration interface (such as AHB, OPB, etc.), and the algorithm runs in the module. The algorithm applied in the present embodiment refers to the quantum-resistant algorithm, and in addition, other algorithms can also be run, which will not be described here), thereby greatly reducing the acquisition time of the random numbers and improving the algorithm efficiency.

[0032] The prior art generally configures the algorithm scheduling acceleration unit through software. The advantage of this is flexibility, but the obvious disadvantage is slow speed. The CPU executes software instructions and then configures the algorithm through the bus, which makes the intermediate process of scheduling extremely long and affects the execution efficiency of the algorithm. In order to solve these problems, the present embodiment implements the configuration and data required by the algorithm through a task, and then analyzes the task through the algorithm scheduling acceleration unit to directly schedule the algorithm, thereby saving the wasted time of the CPU and the bus.

[0033] The algorithm scheduling acceleration unit is a core unit of the acceleration device, which obtains the number of tasks to be executed from the configuration unit, obtains the tasks from the specified address according to the number of tasks, analyzes the tasks after obtaining the tasks, parses the data required by the algorithm from the tasks (the tasks will include the type and attribute of the algorithm and the data required by the algorithm, and one task of the algorithm scheduling acceleration unit is to analyze the type and attribute of the algorithm, and allocate subsequent data according to the analyzed information), then sends to the algorithm module through the general interface, and obtains random numbers from the SPI_RNG unit according to the task demand, and sends the random numbers into the algorithm module, when the algorithm calculation is completed, the algorithm scheduling acceleration unit obtains the algorithm end flag from the algorithm module, then updates the algorithm state to the configuration unit, the configuration unit updates the task state and related address according to the state of the algorithm scheduling acceleration unit, and completes the corresponding task.

[0034] Further, the algorithm scheduling acceleration unit receives the task request and task address from the configuration unit, uses the general bus master interface BUS_M1 to obtain the read task from the specified address (i.e. reads the task from the storage unit set in the back end, writes the task into the algorithm module through the general bus master interface BUS_M2, after the algorithm is completed, the BUS_M1 interface reads the result from the algorithm result of the algorithm module, and writes the result into the result address by the BUS_M2 interface), analyzes the task through the internal analysis logic (the analysis process is that the algorithm scheduling acceleration unit obtains the task from the specified address, analyzes the type and attribute of the algorithm by analyzing the special field in the task, and parses the configuration information and data required by the algorithm from the task), then writes the configuration information and data into the algorithm through the BUS_M2 interface, because the algorithm does not need random numbers at any time, but needs external random number input at some time, the algorithm scheduling acceleration unit will control the acquisition of random numbers according to the state of the algorithm, when the random number is needed, the algorithm scheduling acceleration unit will send the request of the random number, the address of the requested random number and the data to the SPI_RNG unit, the SPI_RNG unit will write the random number required by the algorithm into the algorithm module through the BUS_M3 interface according to the request address and the number of random numbers, and send the rng_done flag to the algorithm scheduling acceleration unit after writing is completed, to tell the scheduling unit that the next operation can be performed.

[0035] When the algorithm calculation is completed, the algorithm scheduling acceleration unit obtains the algorithm end flag from the algorithm, reads the algorithm result from the algorithm, places the algorithm result into the result output address specified by the configuration unit, then updates the algorithm state to the configuration unit, the configuration unit updates the task state and related address according to the state of the algorithm scheduling acceleration unit, and completes the corresponding task.

[0036] It should be noted that when the random number is not needed, 128 four-byte random numbers are pre-fetched in advance as the random numbers needed next time, and when the algorithm needs the random number, the random numbers are directly sent to the algorithm module. If the number of pre-fetched random numbers is not enough, more random numbers are taken from the external random source.

[0037] The device of the embodiment schedules the algorithm scheduling acceleration unit to read the software task, parses the configuration operation and data required by the algorithm from the software task, and then completes the configuration of the algorithm flow and the delivery of the data through the self-owned general bus interface, thereby greatly reducing the number of CPU intervention and the number of CPU configuration DMA start, and further greatly reducing the additional time outside the algorithm calculation, effectively improving the actual application efficiency of the algorithm. The following table is the performance comparison of two algorithms before and after the application of the acceleration device of the embodiment, as follows:

[0038] Algorithm name Performance before acceleration (times / second) Performance after acceleration (times / second) Remark Kyber 3244 5300 The algorithm itself has a small calculation proportion, and the software scheduling is more, so the improvement is large Dilithium 1034 1290 The algorithm itself has a large calculation proportion, and the software scheduling is relatively small, so the improvement effect is not as good as Kyber

[0039] It should be noted that some embodiments of the present application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the acts or steps recited in the claims can be performed in an order other than that described above and still achieve desirable results. Additionally, the process depicted in the figures does not necessarily require the particular order shown, or sequential order, to achieve the desired results. In some implementations, multitasking and parallel processing can be advantageous.

[0040] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the embodiments of the present application also provide a general interface algorithm acceleration method.

[0041] As shown in Figure 2 The general interface algorithm acceleration method comprises the following steps:

[0042] Step S101, information configuration is performed on the software task to be executed;

[0043] Step S102, reading the software task and performing data parsing from the software task to parse the configuration information and data required by the algorithm, obtaining random numbers from an external random source, and writing the random numbers, configuration information and data into the algorithm;

[0044] Step S103, in response to the end of the algorithm calculation, obtaining an algorithm end flag and reading the algorithm result, updating the algorithm state according to the algorithm result, updating the task state and related address based on the updated algorithm state, and executing the corresponding task.

[0045] Through the cooperation of the steps S101, S102 and S103, the original complicated algorithm configuration process and the configuration process of the DMA can be simplified to only a few simple configurations, and after the first algorithm configuration is completed, the configuration of the next algorithm can be completed in the calculation process of the algorithm, so that the entire algorithm process is streamlined, and the entire algorithm process is almost only the calculation process of the algorithm, thereby greatly improving the calculation efficiency of the algorithm and completing the acceleration process of the algorithm.

[0046] The method of the above embodiment is used to implement the corresponding device in any of the above embodiments, and has the beneficial effects of the corresponding device embodiment, which will not be repeated here.

[0047] Based on the same inventive concept, corresponding to any of the above method embodiments, the embodiments of the present application also provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of the above embodiments when executing the program.

[0048] Figure 3 A more specific hardware structure of an electronic device is shown, which can include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040 and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030 and the communication interface 1040 are connected to each other through the bus 1050 for communication within the device.

[0049] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application specific integrated circuit (ASIC), or one or more integrated circuits, etc., for executing related programs to implement the technical solutions provided by the embodiments of the present application.

[0050] The memory 1020 can be implemented by a ROM (Read Only Memory), a RAM (Random Access Memory), a static storage device, a dynamic storage device, etc. The memory 1020 can store an operating system and other application programs, and when the technical solutions provided by the embodiments of the present application are implemented by software or firmware, the related program codes are stored in the memory 1020 and executed by the processor 1010.

[0051] The input / output interface 1030 is configured to connect an input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure) or externally connected to the device to provide corresponding functions. The input device can include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device can include a display, a speaker, a vibrator, an indicator light, etc.

[0052] The communication interface 1040 is configured to connect a communication module (not shown in the figure) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired manner (such as a USB, a network cable, etc.) or through a wireless manner (such as a mobile network, WIFI, Bluetooth, etc.).

[0053] The bus 1050 includes a channel to transmit information between various components (such as the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040) of the device.

[0054] It should be noted that although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040, and the bus 1050, in the specific implementation process, the device can also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above device can also only contain components necessary for implementing the embodiments of the present specification, and does not have to contain all the components shown in the figure.

[0055] The electronic device of the above embodiments is used to realize the corresponding method in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which are not described here.

[0056] Based on the same inventive concept, corresponding to the method of any of the above embodiments, the present application also provides a non-transitory computer readable storage medium storing computer instructions for causing the computer to execute the method of any of the above embodiments.

[0057] The computer readable media of the present embodiments includes permanent and non-permanent, removable and non-removable media, which can be implemented by any method or technology to store information. The information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape disk storage or other magnetic storage device, or any other non-transmission medium that can be used to store information accessible by a computing device.

[0058] The storage medium of the above embodiments stores computer instructions for causing the computer to perform the method as described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which are not described here again.

[0059] Those skilled in the art should understand that the discussion of any of the above embodiments is only exemplary, and is not intended to imply that the scope (including claims) of the present application is limited to these examples; the above embodiments or technical features between different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of brevity..

[0060] In addition, in order to simplify the description and discussion, and so as not to make the embodiments of the present application difficult to understand, the well-known power / ground connections of integrated circuit (IC) chips and other components can or can not be shown in the provided drawings. In addition, the devices can be shown in the form of block diagrams in order to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented the embodiments of the present application (i.e. these details should be fully within the understanding of those skilled in the art). Where specific details (e.g. circuits) are set forth in order to describe the exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application can be implemented without these specific details or with variations of these specific details. Therefore, these descriptions should be considered illustrative rather than limiting.

[0061] While the present application has been described in connection with certain embodiments thereof, many modifications, substitutions, changes, and of forms will be apparent to those of ordinary skill in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) can use the embodiments discussed.

[0062] Embodiments of the present application are intended to cover all such alterations, modifications, and variations as they can come within the scope of the appended claims. Accordingly, although specific embodiments have been furthered in connection with the present application, any omission, substitution, or change, in principle and in form, made to the present application should be included in the scope of the present application.

Claims

1. A universal interface algorithm acceleration device, characterized in that: comprising a configuration unit, a SPI_RNG unit and an algorithm scheduling acceleration unit connected together; wherein the configuration unit is configured to configure information for a software task to be executed; the algorithm scheduling acceleration unit is configured to read the software task and parse data from the software task to obtain configuration information and data required by the algorithm, and write the configuration information and data into an algorithm module in a backend for algorithm calculation; the SPI_RNG unit is configured to obtain random numbers from an external random source according to task requirements and write them into the algorithm module; in response to the end of the algorithm calculation, the algorithm scheduling acceleration unit obtains an algorithm end flag and reads algorithm results, places the algorithm results at a result output address specified by the configuration unit, updates the algorithm state and transmits the updated algorithm state to the configuration unit, and the configuration unit executes corresponding tasks according to the updated task state and related address of the algorithm scheduling acceleration unit, wherein the updated task state corresponds to the algorithm state; a universal bus slave interface is provided on the configuration unit for receiving CPU configuration, and the configured information includes a software task address, an algorithm result output address and a software task number; a first universal bus master interface and a second universal bus master interface are provided on the algorithm scheduling acceleration unit, wherein the first universal bus master interface is used to read the software task from a specified target address, and the second universal bus master interface is used to write the configuration information and data into the algorithm module; the algorithm scheduling acceleration unit reads the software task from the specified target address, parses a special field in the task to obtain the type, attribute and data required by the algorithm, and writes the parsed information into the algorithm module; a third universal bus interface is provided on the SPI_RNG unit for writing random numbers into the algorithm module; the algorithm scheduling acceleration unit controls the acquisition of the random numbers according to the state of the algorithm, and in response to the need for the random numbers, sends an address and data requesting the random numbers to the SPI_RNG unit, the SPI_RNG unit writes the random numbers into the algorithm module through the third universal bus interface, and after the writing is completed, sends a stop flag to the algorithm scheduling acceleration unit. 2.The device of claim 1, characterized in that: the configuration unit is further configured to control the SPI_RNG unit to write a predetermined number of random numbers into a target address. 3.The device of claim 1, characterized in that: in response to the random numbers not being needed, 128 four-byte random numbers are pre-fetched and directly sent to the algorithm module, and in response to the number of pre-fetched random numbers being insufficient, random numbers are obtained from an external random source.

4. A method for accelerating a general-purpose interface algorithm, applied to the general-purpose interface algorithm acceleration device according to any one of claims 1-3, characterized in that, comprising: configuring information for a software task to be executed; reading a software task and performing data parsing from the software task to parse configuration information and data required by an algorithm, obtaining a random number from an external random source, and writing the random number, the configuration information and the data into the algorithm; in response to the end of the algorithm calculation, obtaining an algorithm end flag and reading an algorithm result, updating an algorithm state according to the algorithm result, and updating a task state and a related address based on the updated algorithm state to execute a corresponding task. 5.An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method of claim 4 when executing the program.

6. A non-transitory computer-readable storage medium, comprising: In the method, the non-transitory computer readable storage medium stores computer instructions for causing a computer to execute the method of claim 4.

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