Data bit width conversion device, data bit width conversion method and chip

Abstract

The invention discloses a data bit width conversion device, a data bit width conversion method and a chip, and the data bit width conversion device comprises a bit splicing module which is used for receiving the data information of i pieces of x-bit-width to-be-converted data; the splicing module is also used for splicing the i pieces of data to be converted according to the input data packet header signal, the input data packet tail signal and the input effective data segment information corresponding to each piece of data to be converted to form spliced data; and the output control module is used for generating output effective data segment information according to the input effective data segment information, and outputting j converted data according to the output effective data segment information and the spliced data. According to the data conversion method and device, the i pieces of data to be converted are spliced through the splicing module according to the input data packet header signal, the input data packet tail signal and the input valid data segment information corresponding to each piece of data to be converted, the spliced data are formed, invalid data cannot be output during data bit width conversion, and therefore the bandwidth utilization rate is increased.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and specifically to a data bit width conversion device, a data bit width conversion method, and a chip. Background Technology

[0002] In modern computer systems, different functional modules or devices often need to exchange data. Due to differences in design architecture, processing precision, or interface standards between functional modules or devices, data bit width conversion is often required during data transmission to meet the data bit width requirements of different functional modules or devices.

[0003] Existing data bit width conversion devices require users to predetermine the maximum input data bit width and the maximum output data bit width, and control the data bit width conversion based on a fixed maximum bit width preset value and a counter.

[0004] However, in real-world applications, each input data entry may contain invalid bits that do not carry valid information. Existing data bit-width conversion devices can only transmit invalid bits along with valid data. This results in invalid data occupying valuable transmission bandwidth, reducing bandwidth utilization. This problem is particularly pronounced in high-speed data processing scenarios where high data transmission efficiency is required. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this application provides a data bit width conversion device, a data bit width conversion method, and a chip. The data bit width conversion module concatenates i data bits to be converted according to the input data packet header signal, input data packet tail signal, and input valid data segment information corresponding to each data bit to be converted, forming concatenated data. During data bit width conversion, invalid data will not be output, thereby improving bandwidth utilization.

[0006] To address the above problems, the present invention provides the following technical solution: In a first aspect, embodiments of this application provide a data bit-width conversion device, comprising: a bit-splitting module, used to receive data information of i data points with a bit width of x to be converted, wherein the data information includes valid data, an input data packet header signal, an input data packet tail signal, and input valid data segment information, wherein each bit in the input valid data segment information is used to indicate whether the corresponding data segment in the valid data is valid, and i and x are both positive integers; The splicing module is also used to splice i pieces of data to be converted according to the input data packet header signal, input data packet tail signal and input valid data segment information corresponding to each piece of data to be converted, so as to form spliced ​​data; The output control module is used to generate output valid data segment information based on the input valid data segment information, and output j converted data based on the output valid data segment information and the concatenated data, wherein each bit in the output valid data segment information is used to indicate whether the corresponding data segment in the concatenated data is valid, and j is a positive integer.

[0007] In some implementations, the merging module is specifically used for: Sequentially determine whether the value of each bit in the input valid data segment information is a first preset value. If it is the first preset value, write the data segment corresponding to the current bit in the input valid data segment information into the concatenated data; otherwise, discard the data segment corresponding to the current bit in the input valid data segment information.

[0008] In some implementations, the merging module is specifically used for: When the input data packet header signal of the current pen to be converted indicates that the current pen to be converted is packet header data, the data segments corresponding to the bits in the input valid data segment information are sequentially written into the low bits of the spliced ​​data; When the input data packet tail signal of the current pen to be converted indicates that the current pen to be converted is packet tail data, the data segments corresponding to the bits in the input valid data segment information are sequentially written into the spliced ​​data to form the spliced ​​data.

[0009] In some embodiments, the merging module is further used for: If there is a bit in the input valid data segment information that indicates that the corresponding data segment is invalid, then the bit in the input valid data segment information is deleted to obtain the processed input valid data segment information; If all bits of the input valid data segment information are bits indicating that the corresponding data segment is valid, then the input valid data segment information is determined as the processed input valid data segment information; The processed valid input data segments are sequentially concatenated to obtain the concatenated valid input data segments.

[0010] In some implementations, the output control module is specifically used for: The valid information of each output data segment is determined based on the concatenated input valid data segment information and the number of bits of valid information in each output data segment.

[0011] In some implementations, the output control module is specifically used for: The converted data of the current pen is determined based on the valid information of the output data segment of the current pen and the spliced ​​data; Determine the output data packet header signal of the current pen-converted data; The output data packet tail signal of the converted data of the current pen is determined based on the valid information of the next output data segment after the valid information of the current pen output data segment. Output the converted data of the current pen, the corresponding output data packet header signal, and the output data packet tail signal.

[0012] In some implementations, if the next valid output data segment of the valid information of the current pen output data segment is all 0, then the output data packet tail signal corresponding to the data converted by the current pen is determined to be 1; otherwise, the output data packet tail signal corresponding to the data converted by the current pen is determined to be 0.

[0013] In some implementations, the output control module is specifically used for: Obtain the first valid information of the output data segment, determine and output the data segment corresponding to the first valid information of the output data segment in the spliced ​​data, the output data packet header signal corresponding to the data segment, and the output data packet tail signal, wherein the output data packet header signal is 1, and the data segment corresponding to the first valid information of the output data segment in the spliced ​​data is the converted data segment; For the valid information of the last output data segment, determine and output the data segment corresponding to the valid information of the last output data segment in the spliced ​​data, the output data packet header signal corresponding to the data segment, and the output data packet tail signal, wherein the output data packet tail signal is 1; For valid information of the intermediate pen output data segment, determine and output the data segment corresponding to the valid information of the intermediate pen output data segment, the output data packet header signal corresponding to the data segment, and the output data packet tail signal, wherein the output data packet header signal is 0 and the output data packet tail signal is 0.

[0014] Secondly, embodiments of this application provide a data bit width conversion method, using the data bit width conversion apparatus as described in the first aspect, the data bit width conversion method comprising: The concatenation module receives data information of i data points with a width of x bits to be converted. The data information includes valid data, input data packet header signal, input data packet tail signal, and input valid data segment information. Each bit in the input valid data segment information is used to indicate whether the corresponding data segment in the valid data is valid. i and x are both positive integers. The splicing module splices i pieces of data to be converted according to the input data packet header signal, input data packet tail signal and input valid data segment information corresponding to each piece of data to be converted, to form spliced ​​data; The output control module generates output valid data segment information based on the input valid data segment information, and outputs j converted data based on the output valid data segment information and the concatenated data. Each bit in the output valid data segment information is used to indicate whether the corresponding data segment in the concatenated data is valid, and j is a positive integer.

[0015] Thirdly, embodiments of this application provide a chip including the data bit-width conversion device as described in the first aspect.

[0016] This application provides a data bit width conversion device, a data bit width conversion method, and a chip. This application uses a bit-splitting module to splice i pieces of data to be converted according to the input data packet header signal, input data packet tail signal, and input valid data segment information corresponding to each piece of data to be converted, forming spliced ​​data. During data bit width conversion, invalid data will not be output, thereby improving bandwidth utilization. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the first embodiment of the data bit width conversion device provided in this application.

[0018] Figure 2 This is a schematic diagram of the second embodiment of the data bit width conversion device provided in this application.

[0019] Figure 3 This is a schematic diagram of the third embodiment of the data bit width conversion device provided in this application.

[0020] Figure 4 This is a schematic flowchart of the data bit width conversion device provided in the embodiments of this application. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "multiple" means two or more, unless otherwise explicitly specified.

[0023] This application provides a data bit width conversion device, a data bit width conversion method, and a chip. The data bit width conversion module concatenates i data bits to be converted according to the input data packet header signal, input data packet tail signal, and input valid data segment information corresponding to each data bit to be converted, forming concatenated data. During data bit width conversion, invalid data will not be output, thereby improving bandwidth utilization.

[0024] In some embodiments, the data bit-width conversion device is used to convert i data entries with a width of x bits into j data entries, wherein the effective bit width of the first to j-1 data entries is y, and the effective bit width of the j-th data entry is less than or equal to y. Let Y be the effective bit width of the j-th data entry, where i, x, j, y, and Y are all positive integers, and Y is less than or equal to y. The unit of bit width is bits. A data bit width conversion device can be used to convert large-bit-width data to small-bit-width data, or vice versa. That is, the value of x can be greater than or less than the value of y. For example, a data bit width conversion device can be used to convert 4 256-bit data entries to 8 128-bit data entries. Another example is using a data bit width conversion device to convert 8 128-bit data entries to 4 256-bit data entries.

[0025] The data bit width conversion device provided in this application will now be described in detail with reference to the accompanying drawings.

[0026] Please see Figure 1 , Figure 1 This is a schematic diagram of the first embodiment of the data bit-width conversion device provided in this application. (See attached diagram.) Figure 1 As shown, in some embodiments, the data bit-width conversion device 1 includes a bit-splitting module 10 and an output control module 20. The bit-splitting module 10 receives data information from i pieces of data with a bit width of x to be converted. The data information includes valid data, an input data packet header signal, an input data packet tail signal, and input valid data segment information. Each bit in the input valid data segment information indicates whether the corresponding data segment in the valid data is valid. The bit-splitting module 10 also splices the i pieces of data to be converted according to the input data packet header signal, the input data packet tail signal, and the input valid data segment information corresponding to each piece of data to be converted, forming spliced ​​data. The output control module 20 generates output valid data segment information based on the input valid data segment information, and outputs j pieces of converted data based on the output valid data segment information and the spliced ​​data. Each bit in the output valid data segment information indicates whether the corresponding data segment in the spliced ​​data is valid. The effective bit width of the first to j-1 pieces of converted data is y, and the effective bit width of the j-th piece of converted data is less than or equal to y. Y is the effective bit width of the j-th converted data, where i, x, j, y, and Y are all positive integers, and Y is less than or equal to y.

[0027] By using the above method, invalid data will not be output during data bit width conversion, thereby improving bandwidth utilization.

[0028] Specifically, each bit in the input valid data segment information is used to indicate whether a corresponding data segment with a first preset bit width in the data to be converted is valid.

[0029] Optionally, the first preset bit width is 1 bit, 2 bits, 4 bits, 8 bits, or 16 bits, etc.

[0030] Optionally, one piece of data to be converted corresponds to one or more valid input data segments.

[0031] In some implementations, the concatenation module is specifically used to: sequentially determine whether each bit in the input valid data segment information is a first preset value; if it is the first preset value, then write the data segment corresponding to the current bit in the input valid data segment information into the concatenated data; otherwise, discard the data segment corresponding to the current bit in the input valid data segment information.

[0032] Optionally, the first setting value is 1 or 0.

[0033] In some implementations, the concatenation module is specifically used for: when the input data packet header signal of the current data to be converted indicates that the current data to be converted is packet header data, sequentially writing the data segments corresponding to the bits in the input valid data segment information into the lower bits of the concatenated data; when the input data packet tail signal of the current data to be converted indicates that the current data to be converted is packet tail data, sequentially writing the data segments corresponding to the bits in the input valid data segment information into the concatenated data, thereby forming the concatenated data. For example, when the input data packet header signal is 1, it indicates that the current data to be converted is packet header data. When the input data packet header signal is 0, it indicates that the current data to be converted is not packet header data.

[0034] For example, when the input data packet header signal of the current pen to be converted is 1 and the input data packet tail signal is 0, the current pen to be converted data is packet header data. When the input data packet header signal of the current pen to be converted is 0 and the input data packet tail signal is 1, the current pen to be converted data is packet tail data.

[0035] For example, when the header signal of the input data packet to be converted is 1 and the tail signal of the input data packet is 1, the data packet to be converted is both header data and tail data, and the number of data packets to be converted is 1.

[0036] For example, when the header signal of the input data packet to be converted is 0 and the tail signal of the input data packet is 0, it means that the current data to be converted is neither header data nor tail data, but intermediate data to be converted.

[0037] In some implementations, the concatenation module is further used to: when the input data packet header signal of the current pen to be converted indicates that the current pen to be converted is not packet header data, and the input data packet tail signal of the current pen to be converted indicates that the current pen to be converted is not packet tail data, write the data segments corresponding to the bits in the input valid data segment information into the concatenated data in sequence, wherein the order of writing the data segments is from the least significant bit to the most significant bit.

[0038] In some implementations, the concatenation module is further configured to: if the input valid data segment information contains bits indicating that the corresponding data segment is invalid, then delete those bits from the input valid data segment information to obtain processed input valid data segment information; if all bits in the input valid data segment information are bits indicating that the corresponding data segment is valid, then determine that input valid data segment information as processed input valid data segment information; and sequentially concatenate each processed input valid data segment information to obtain concatenated input valid data segment information. In this way, the concatenated input valid data segment information does not include bits indicating that the corresponding data segment is invalid, and therefore the subsequent output valid data segment information determined based on the input valid data segment information will also not include bits indicating that the corresponding data segment is invalid, thereby improving bandwidth utilization.

[0039] For example, the first preset value is 1, the first preset bit width is 8 bits, the bit width of a piece of data to be converted is 24 bits, and its corresponding input valid data segment information is 101. The concatenation module is used to sequentially write the data segment of the [7:0] interval in the current piece of data to be converted corresponding to the first bit in the input valid data segment information into the concatenated data, discard the data segment of the [15:8] interval in the current piece of data to be converted corresponding to the second bit in the input valid data segment information, and sequentially write the data segment of the [23:16] interval in the current piece of data to be converted corresponding to the third bit in the input valid data segment information into the concatenated data. When the current piece of data to be converted is packet header data, the concatenation module is used to write the data segment of the [7:0] interval in the current piece of data to be converted into the [7:0] interval of the concatenated data, and write the data segment of the [23:16] interval in the current piece of data to be converted into the [15:8] interval of the concatenated data. The concatenation module is also used to delete the second bit in the current input valid data segment information to obtain the processed input valid data segment information. The processed input valid data segment information is 11, which means that the data segments in the [15:0] interval of the concatenated data are all valid data.

[0040] In some implementations, the data information for each piece of data to be converted also includes an input data validity signal, which indicates whether the current piece of data to be converted requires conversion processing. The concatenation module is further configured to receive the valid data, input data packet header signal, input data packet tail signal, and input valid data segment information of the current piece of data to be converted, and process the current piece of data to be converted, when the input data validity signal of the current piece of data to be converted indicates that the current piece of data to be converted requires conversion processing; otherwise, it will not receive the valid data, input data packet header signal, input data packet tail signal, and input valid data segment information of the current piece of data to be converted, and will not process the current piece of data to be converted.

[0041] In some implementations, the output control module is specifically used to: determine the valid information of each output data segment based on the concatenated input valid data segment information and the number of bits in the valid information of each output data segment. Specifically, the value of each bit in the valid output data segment information is used to indicate whether the corresponding data segment with the second preset bit width in the converted data is valid. The output control module is used to divide the bit width of each converted data segment by the second preset bit width to obtain the number of bits in the valid information of each output data segment, and to divide the concatenated input valid data segment information into multiple valid output data segments with the same number of bits based on the number of bits in the valid information of each output data segment. For example, if the second preset bit width is 8 bits and the bit width of each converted data segment is 256 bits, then the number of bits in the valid information of each output data segment is 256 ÷ 8 = 32 bits.

[0042] In some implementations, the output control module is specifically used to: determine the converted data of the current pen based on the valid information of the current pen output data segment and the spliced ​​data; determine the output packet header signal of the converted data of the current pen; determine the output packet tail signal of the converted data of the current pen based on the valid information of the next pen output data segment; and output the converted data of the current pen, the corresponding output packet header signal, and the output packet tail signal.

[0043] Furthermore, the output control module is specifically used to: if the valid information of the next valid output data segment of the current pen output data segment is all 0, then the output data packet tail signal corresponding to the converted data of the current pen is determined to be 1; otherwise, the output data packet tail signal corresponding to the converted data of the current pen is determined to be 0.

[0044] When the next valid output data segment of the current pen output data segment is all 0, it means that the next valid output data segment is empty. Therefore, the data after the current pen is converted is the data after the last pen conversion.

[0045] In some implementations, the output control module is specifically used to: acquire valid information of the first output data segment, determine and output the data segment corresponding to the valid information of the first output data segment in the concatenated data, the corresponding output data packet header signal, and the corresponding output data packet tail signal, wherein the output data packet header signal is 1. The data segment corresponding to valid information of one output data segment in the concatenated data is one converted data segment. For valid information of the last output data segment, determine and output the data segment corresponding to the valid information of the last output data segment in the concatenated data, the corresponding output data packet header signal, and the corresponding output data packet tail signal, wherein the output data packet tail signal is 1. For valid information of intermediate output data segments, determine and output the data segment corresponding to the valid information of the intermediate output data segment, the corresponding output data packet header signal, and the corresponding output data packet tail signal, wherein the output data packet header signal is 0, and the output data packet tail signal is 0. In this case, when the output data packet header signal is 1, it indicates that the converted data of the corresponding segment is the packet header data in the output data; when the output data packet tail signal is 1, it indicates that the converted data of the corresponding segment is the packet tail data in the output data.

[0046] In some implementations, when there are multiple valid output data segments, the output data packet header signal corresponding to the first valid output data segment is 1, and the output data packet tail signal is 0. The output data packet header signal corresponding to the last valid output data segment is 0, and the output data packet tail signal is 1.

[0047] In some implementations, when there is only one valid output data segment, the first valid output data segment is also the last valid output data segment. In this case, the output data packet header signal corresponding to the valid output data segment is 1, and the output data packet tail signal is 1.

[0048] Please see Figure 2 , Figure 2 This is a schematic diagram of the second embodiment of the data bit-width conversion device provided in this application. (See attached diagram.) Figure 2As shown, in some embodiments, the output control module 20 includes an output counter 21, a signal output module 22, and a data output module 23. The output counter 21 receives the input data packet tail signal and, when the input data packet tail signal indicates that the current data to be converted is packet tail data, starts counting the number of converted data packets to obtain an output count value. Based on the output count value and a second preset bit width, it determines the first data start and end interval of the valid information for each output data segment. Based on the output count value and the bit width of each data packet to be converted, it determines the second data start and end interval of each converted data packet. It then sends a signal to the merging module 10 to select the valid information for each output data segment and the corresponding converted data packet in the merging module 10. This causes the merging module 10 to send the valid information for each output data segment to the signal output module 22 and the data output module 23, and also causes the merging module 10 to send the converted data packet of the current packet to the data output module 23. The signal output module 22 determines and outputs an output data control signal, which includes an output data valid signal, an output data packet header signal, and an output data packet tail signal corresponding to each converted data packet. The output data valid signal indicates whether the data after the corresponding pen conversion is valid, the output data packet header signal indicates that the data after the corresponding pen conversion is the header data in the output data, and the output data packet tail signal indicates that the data after the corresponding pen conversion is the tail data in the output data.

[0049] The data output module 23 is used to output the converted data for each pen and the valid information of the corresponding output data segment.

[0050] Optionally, the signal output module 22 is also used to acquire the output count value of the output counter 21; when the output data packet header signal corresponding to the current converted data is 1, the output count value is determined to be 0. When the output data packet tail signal corresponding to the current converted data is 1, the output count value is determined to be the number of converted data entries minus 1. The number of converted data entries is j, where j is the number of converted data entries that the data bit width conversion device currently needs to output.

[0051] In some implementations, the output counter 21 is also used to acquire the next valid output data segment information of each valid output data segment in the concatenation module. If the next valid output data segment information of the current valid output data segment is all 0, a signal is sent to the signal output module 22 to make the signal output module 22 determine the output data packet header signal corresponding to the converted data of the current segment as 0 and the output data packet tail signal as 1. The output counter 21 is also used to clear the output count value to zero when the next valid output data segment information of the current valid output data segment is all 0.

[0052] In some implementations, the signal output module 22 is also used to determine the output data valid signal as 1 when the value of each bit in the valid information of the current pen output data segment is the first set value of the converted data.

[0053] The following example illustrates the working steps of the output control module by converting i pieces of data with a width of x bits into j pieces of data. The working steps include steps S11 to S15. The second preset width is a bits.

[0054] Step S11: The output counter receives the input data packet tail signal. When the input data packet tail signal indicates that the current pen data to be converted is packet tail data, it starts counting the number of converted data to obtain an output count value, b, with an initial value of 1. The output counter sends a signal to the splicing module to select the data segment in the interval [cb-1:c(b-1)] of the spliced ​​input valid data segment information in the splicing module as the valid information of the current pen output data segment, and to select the data segment in the interval [yb-1:y(b-1)] of the spliced ​​data as the converted data of the current pen. This causes the splicing module to send the valid information of each output data segment to the signal output module and the data output module, and to send the converted data of the current pen to the data output module.

[0055] Where c = y ÷ a.

[0056] Step S12: The signal output module outputs the data after the current pen is converted, the valid information of the current pen's output data segment, the output data packet header signal, and the output data packet tail signal.

[0057] Specifically, the output counter acquires the next valid output data segment information for each valid output data segment in the concatenation module. If the next valid output data segment information for the current valid output data segment is all 0, and b is not equal to 0, a signal is sent to the signal output module to make the signal output module set the output data packet header signal corresponding to the current converted data segment to 0 and the output data packet tail signal to 0. If b is equal to 0, a signal is sent to the signal output module to make the signal output module set the output data packet header signal corresponding to the current converted data segment to 1 and the output data packet tail signal to 0.

[0058] Step S13: Let b = b + 1; when b < j, return to step S11, and when b = j, execute step S14.

[0059] Step S14: Select the data segment in the range [cb-1:c(b-1)] of the concatenated input valid data segment information in the concatenation module as the valid information of the current pen output data segment, so that the concatenation module sends the valid information of the current pen output data segment to the signal output module, and determines that the output data packet tail signal is 1; and, sequentially determine whether each bit of the valid information of the current pen output data segment is the first set value. If it is the first set value, select the data segment in the range [N:y(b-1)] of the concatenated data that corresponds to the current bit of the valid information of the current pen output data segment, so as to obtain the data after the current pen conversion, and make the concatenation module send the data after the current pen conversion to the data output module. N is greater than or equal to y(b-1) and less than or equal to yb-1, where N is the valid bit width of the concatenated data -1.

[0060] Step S15: The signal output module outputs the output data control signal. Simultaneously, the data output module outputs the converted data of the current pen and the valid information of the current pen's output data segment, and the output counter resets its count value to zero.

[0061] Please see Figure 3 , Figure 3 This is a schematic diagram of the third embodiment of the data bit-width conversion device provided in this application. (See attached diagram.) Figure 3 As shown, in some embodiments, the data bit-width conversion device 1 further includes an input control module 30. The input control module 30 includes an input counter 31, a first register 32, and a second register 33. The input counter 31 receives input data control signals, forwards these signals to the splicing module 10, and, when the input data valid signal indicates that the current data to be converted is valid, determines the bit width of the currently stored spliced ​​valid input data segment information in the splicing module 10 as the current input count value. The input data control signals include an input data valid signal, an input data packet header signal, and an input data packet tail signal. The initial value of the input count is 0.

[0062] The first register 32 is used to receive and store the valid input data segment information according to the input count value of the input counter 31, and the second register 33 is used to receive and store the data to be converted according to the input count value of the input counter 31.

[0063] Specifically, the first register 32 is used to obtain the current input count value, determine the first storage area of ​​the input valid data segment information based on the input count value and the number of bits representing the valid data segment in the current pen input valid data segment information, and store the current pen input valid data segment information into the corresponding first storage area.

[0064] Specifically, the input count value of input counter 31 is d, and the number of bits representing the valid data segment in the current pen input valid data segment information is e, then the first storage interval is [e-1, d].

[0065] Specifically, the second register 33 is used to obtain the input count value, multiply the input count value by the first preset bit width as the low bit of the second storage area corresponding to the current pen data to be converted, and store the data segments corresponding to each bit of the current pen input valid data segment information that indicates the validity of the corresponding data segment in the second storage area in order from low bit to high bit.

[0066] In some implementations, the merging module 10 can obtain the valid information of the output data segment in the first register 32 and obtain the data to be converted in the second register 33.

[0067] In some embodiments, the input counter 31 is also used to forward the input data control signal to the output counter 21. The output counter 21 is also used to receive the input data control signal, and when the input data valid signal in the input data control signal indicates that the data to be converted is valid, to determine the output data valid signal as a value indicating that the converted data is valid.

[0068] Please see Figure 4 , Figure 4 This is a schematic flowchart of the data bit-width conversion device provided in an embodiment of this application. Figure 4 As shown, this application also provides a data bit width conversion method, which uses the data bit width conversion device described above. The data bit width conversion method includes steps S100 to S300.

[0069] Step S100: The data concatenation module receives data information of i data points with a width of x bits to be converted.

[0070] Each piece of data to be converted includes valid data, input data packet header signal, input data packet tail signal, and input valid data segment information. Each bit in the input valid data segment information is used to indicate whether the corresponding data segment in the valid data is valid.

[0071] Step S200: The concatenation module concatenates the i data to be converted according to the input data packet header signal, input data packet tail signal and input valid data segment information corresponding to each data to be converted, to form concatenated data.

[0072] Step S300: The output control module generates output valid data segment information based on the input valid data segment information, and outputs j converted data based on the output valid data segment information and the spliced ​​data.

[0073] Each bit in the output valid data segment information is used to indicate whether the corresponding data segment in the concatenated data is valid.

[0074] This application also provides a chip, including the data bit-width conversion device described above.

[0075] In summary, this application provides a data bit-width conversion device, a data bit-width conversion method, and a chip. The data bit-width conversion device is used to convert i data entries with a width of x bits into j data entries. It includes: a bit-splitting module for receiving data information from i data entries with a width of x bits to be converted, wherein each data entry includes valid data, an input data packet header signal, an input data packet tail signal, and input valid data segment information. Each bit in the input valid data segment information indicates whether the corresponding data segment in the valid data is valid, and i and x are both positive integers; the bit-splitting module is also used to splice the i data entries to be converted according to the input data packet header signal, the input data packet tail signal, and the input valid data segment information corresponding to each data entry to be converted, forming spliced ​​data; and an output control module for generating output valid data segment information based on the input valid data segment information, and outputting j converted data entries based on the output valid data segment information and the spliced ​​data. Each bit in the output valid data segment information indicates whether the corresponding data segment in the spliced ​​data is valid, the effective bit width of the first to j-1 converted data entries is y, and the effective bit width of the j-th converted data entry is less than or equal to y. Y represents the effective bit width of the j-th converted data, where i, x, j, y, and Y are all positive integers, and Y is less than or equal to y. This application uses a concatenation module to concatenate the i-th data to be converted based on the input data packet header signal, input data packet tail signal, and input valid data segment information corresponding to each data to be converted, forming concatenated data. During data bit width conversion, invalid data is not output, thereby improving bandwidth utilization.

[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A data bit-width conversion device for converting i data entries with a width of x bits into j data entries, characterized in that, include: The concatenation module is used to receive data information of i data segments with a width of x bits to be converted. The data information includes valid data, input data packet header signal, input data packet tail signal, and input valid data segment information. Each bit in the input valid data segment information is used to indicate whether the corresponding data segment in the valid data is valid. i and x are both positive integers. The splicing module is also used to splice i pieces of data to be converted according to the input data packet header signal, input data packet tail signal and input valid data segment information corresponding to each piece of data to be converted, so as to form spliced ​​data; The output control module is used to generate output valid data segment information based on the input valid data segment information, and output j converted data based on the output valid data segment information and the concatenated data, wherein each bit in the output valid data segment information is used to indicate whether the corresponding data segment in the concatenated data is valid, and j is a positive integer.

2. The data bit width conversion device according to claim 1, characterized in that, The assembly module is specifically used for: Sequentially determine whether each bit in the input valid data segment information is a first preset value. If it is the first preset value, write the data segment corresponding to the current bit in the input valid data segment information into the concatenated data; otherwise, discard the data segment corresponding to the current bit in the input valid data segment information.

3. The data bit width conversion device according to claim 2, characterized in that, The assembly module is specifically used for: When the input data packet header signal of the current pen to be converted indicates that the current pen to be converted is packet header data, the data segments corresponding to the bits in the input valid data segment information are sequentially written into the low bits of the spliced ​​data; When the input data packet tail signal of the current pen to be converted indicates that the current pen to be converted is packet tail data, the data segments corresponding to the bits in the input valid data segment information are sequentially written into the spliced ​​data to form the spliced ​​data.

4. The data bit width conversion device according to claim 1, characterized in that, The assembly module is also used for: If there is a bit in the input valid data segment information that indicates that the corresponding data segment is invalid, then the bit in the input valid data segment information is deleted to obtain the processed input valid data segment information; If all bits of the input valid data segment information are bits indicating that the corresponding data segment is valid, then the input valid data segment information is determined as the processed input valid data segment information; The processed valid input data segments are sequentially concatenated to obtain the concatenated valid input data segments.

5. The data bit width conversion device according to claim 4, characterized in that, The output control module is specifically used for: The valid information of each output data segment is determined based on the concatenated input valid data segment information and the number of bits of valid information in each output data segment.

6. The data bit width conversion device according to claim 5, characterized in that, The output control module is specifically used for: The converted data of the current pen is determined based on the valid information of the output data segment of the current pen and the spliced ​​data; Determine the output data packet header signal of the current pen-converted data; The output data packet tail signal of the converted data of the current pen is determined based on the valid information of the next output data segment after the valid information of the current pen output data segment. Output the converted data of the current pen, the corresponding output data packet header signal, and the output data packet tail signal.

7. The data bit width conversion device according to claim 6, characterized in that: If the next valid output data segment of the current pen output data segment is all 0, then the output data packet tail signal corresponding to the converted data of the current pen is determined to be 1; otherwise, the output data packet tail signal corresponding to the converted data of the current pen is determined to be 0.

8. The data bit width conversion device according to claim 7, characterized in that, The output control module is specifically used for: Obtain the first valid information of the output data segment, determine and output the data segment corresponding to the first valid information of the output data segment in the spliced ​​data, the output data packet header signal corresponding to the data segment, and the output data packet tail signal, wherein the output data packet header signal is 1, and the data segment corresponding to the first valid information of the output data segment in the spliced ​​data is the converted data segment; For the valid information of the last output data segment, determine and output the data segment corresponding to the valid information of the last output data segment in the spliced ​​data, the output data packet header signal corresponding to the data segment, and the output data packet tail signal, wherein the output data packet tail signal is 1; For valid information of the intermediate pen output data segment, determine and output the data segment corresponding to the valid information of the intermediate pen output data segment, the output data packet header signal corresponding to the data segment, and the output data packet tail signal, wherein the output data packet header signal is 0 and the output data packet tail signal is 0.

9. A data bit width conversion method, characterized in that, The data bit width conversion apparatus as described in any one of claims 1-8, wherein the data bit width conversion method comprises: The concatenation module receives data information of i data entries with a width of x bits to be converted. The data information includes valid data, input data packet header signal, input data packet tail signal, and input valid data segment information. Each bit in the input valid data segment information is used to indicate whether the corresponding data segment in the valid data is valid. i and x are both positive integers. The splicing module splices i pieces of data to be converted according to the input data packet header signal, input data packet tail signal and input valid data segment information corresponding to each piece of data to be converted, to form spliced ​​data; The output control module generates output valid data segment information based on the input valid data segment information, and outputs j converted data based on the output valid data segment information and the concatenated data. Each bit in the output valid data segment information is used to indicate whether the corresponding data segment in the concatenated data is valid, and j is a positive integer.

10. A chip, characterized in that, Includes the data bit width conversion device as described in any one of claims 1-8.

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