Inter-core interconnection system and display card device comprising same

Abstract

The invention relates to an inter-core interconnection system and a display card device comprising the same. The inter-core interconnection system comprises: at least two cores; the at least two cores are connected through the cross-bar switch matrix bus, each core of the at least two cores comprises an on-chip inter-core interconnection interface used for inter-core interconnection, the on-chip inter-core interconnection interface is provided with an interface conversion module, and the interface conversion module is used for converting the on-chip inter-core interconnection interface into the on-chip inter-core interconnection interface into the on-chip inter-core interconnection interface. The on-chip inter-core interconnection interface converts first data and a first address into a first data packet with a first custom data packet format by using the interface conversion module, and sends the first data and the first address to the crossbar switch matrix bus in the form of the first data packet, and / or sends the first data and the first address to the crossbar switch matrix bus in the form of a second custom data packet format; and the on-chip inter-core interconnection interface receives a second data packet with a second custom data packet format from the crossbar switch matrix bus, and converts the second data packet into second data and a second address by utilizing the interface conversion module.

Description

Technical Field

[0001] This disclosure relates to an inter-core interconnect system and a graphics card device including the inter-core interconnect system. Accordingly, this disclosure also relates to a write operation method and a read operation method for inter-core interconnect. Background Technology

[0002] In chip design, inter-core interconnects, especially multi-core interconnects, generally employ the standard AXI (Advanced eXtensible Interface) bus protocol. The AXI bus protocol, a crucial component of the AMBA 3.0 protocol proposed by ARM (Advanced RISC Machines Ltd.), is an on-chip bus designed for high performance, high bandwidth, and low latency. It features separate address / control and data phases, supports unaligned data transfer, and in burst transfers, only the starting address is needed. It also features separate read / write data channels, supports significant transfer access and out-of-order access, and facilitates timing closure. AXI is a new high-performance protocol within the AMBA (Advanced Microcontroller Bus Architecture) framework. AXI technology enriches the existing AMBA standard, meeting the needs of ultra-high performance and complex System-on-a-chip (SoC) designs. AXI characteristics include: unidirectional channel architecture; information flow is unidirectional; and independent data and address channels. The data and address channels are separated, allowing for individual optimization of each channel. Timing channels can be controlled as needed, maximizing clock frequency and minimizing latency.

[0003] In chip design, especially in multi-core interconnect designs, crossbar interconnects are typically used for routing. Multiple cores are connected to each other in a star topology via crossbar interconnects using relevant technologies.

[0004] The drawbacks of this technology are as follows: When using the standard AXI3 (AMBA 3.0) bus protocol, the cores use the crossbar switch matrix bus of this technology to send data and addresses via direct routing. Although this is highly efficient, the bus width is large, requiring more than 220 lines for a single core. In multi-core scenarios, the number of lines required increases exponentially. Furthermore, during the chip physical implementation phase, the wiring between cores connects to the crossbar switch matrix of this technology, consuming significant wiring resources. This places a heavy burden on the back-end layout and routing of the chip, and also makes timing difficult to achieve and wastes space. Summary of the Invention

[0005] The objective of this disclosure is to address the efficiency and area issues of inter-core interconnection, especially multi-core interconnection, by using packet switching, and to minimize the number of buses required while maintaining bus efficiency, thus facilitating implementation by backend chips.

[0006] According to a first aspect of this disclosure, in order to solve the above-mentioned problems, an inter-core interconnection system employing a packet switching method is proposed. The inter-core interconnection system may have: at least two cores; and a crossbar switch matrix bus for connecting the at least two cores, wherein each of the at least two cores includes an on-chip inter-core interconnection interface for inter-core interconnection. The on-chip inter-core interconnection interface has an interface conversion module, wherein the on-chip inter-core interconnection interface uses the interface conversion module to convert first data and a first address into a first data packet having a first custom data packet format, and sends the first data and the first address as the first data packet to the crossbar switch matrix bus; and / or, the on-chip inter-core interconnection interface receives a second data packet having a second custom data packet format from the crossbar switch matrix bus, and uses the interface conversion module to convert the second data packet into second data and a second address.

[0007] The advantages of the inter-core interconnect system disclosed herein are as follows: By equipping the cores with an on-chip inter-core interconnect interface with an interface conversion module, and by replacing the crossbar switch matrix bus of related technologies that uses a direct routing method with the crossbar switch matrix bus of this disclosure that uses a packet-switched routing method, data and addresses can be transmitted using a custom packet format. In this way, the inter-core interconnect system of this disclosure can avoid parallel transmission of these data and addresses while maintaining bus efficiency, thereby greatly reducing the required channel width and thus significantly reducing the number of buses required, up to the number of bytes corresponding to the data packets. Compared with the traditional AXI3 bus protocol, this can greatly reduce the number of lines, thereby facilitating back-end layout and routing.

[0008] In some embodiments, the on-chip inter-core interconnect interface may include a FIFO (First In First Out) cache for caching the first data packet and / or the second data packet according to the depth of the FIFO cache.

[0009] In some embodiments, the crossbar switch matrix bus may have an ID routing function for routing based on the target ID of the first data packet and / or the second data packet.

[0010] In some embodiments, the first data packet and / or the second data packet may contain at least one of the following data packet types: A write request packet is used to indicate a write request; Write data packet, used to contain data transmitted in response to the write request; A write return packet is used to confirm whether the core, as the recipient of the data, has successfully received the data transmitted in response to the write request; A read request packet is used to indicate a read request; Read data packets, used to contain data transmitted in response to the read request; and A read return packet is used to confirm whether the core, as the recipient of the data, has successfully received the data transmitted in response to the read request.

[0011] In some embodiments, the write request packet, the write data packet, the write return packet, the read request packet, the read data packet, and the read return packet may have the same number of bits.

[0012] In some embodiments, the bus width of the crossbar switch matrix bus connected to each of the at least two cores may be related to the number of bits.

[0013] In some embodiments, the number of bits may correspond to the bus width of the crossbar switch matrix bus connected to each of the at least two cores.

[0014] In some embodiments, the bus width can be 48 lines.

[0015] In some embodiments, one of the at least two cores can use the on-chip inter-core interconnect interface to send one of the write request packets, the write data packets, the write return packets, the read request packets, the read data packets, and the read return packets to the crossbar switch matrix bus in multiple cycles, wherein the bus width of the crossbar switch matrix bus connected to each of the at least two cores is related to the number of bits of the data packets sent in each cycle.

[0016] In some embodiments, the write request packet may include: a source ID field for representing the source ID of the write request packet; and a destination ID field for representing the destination ID of the write request packet.

[0017] In some embodiments, the write request packet may further include: a type field for indicating the data packet type; a length field for indicating the number of write data packets belonging to the write request packet; a write request packet ID field for indicating the ID of the write request packet; and an address field for indicating the write address of the write request corresponding to the write request packet.

[0018] In some embodiments, the write data packet may include: a source ID field for representing the source ID of the write data packet; and a destination ID field for representing the destination ID of the write data packet.

[0019] In some embodiments, the write data packet may further include: a type field for indicating the data packet type; a write data start bit for indicating the start of the write operation, i.e., the first write data packet of the write request corresponding to the write request packet; a write data end bit for indicating the end of the write operation, i.e., the last write data packet of the write request corresponding to the write request packet; and a data field, the data field containing at least a portion of the data to be sent in order to perform the write operation, wherein the data is sent sequentially through all write data packets belonging to the write request packet of the write operation.

[0020] In some embodiments, the write data packet may further include: a mask field for indicating whether the data field of the write data packet is valid; and a reserved field or reserved bit for indicating fields or bits that are not used in the write data packet.

[0021] In some embodiments, the write return packet may include: a write request packet ID field, used to represent the ID of the write request packet corresponding to the write return packet; and a target ID field, used to represent the target ID of the write return packet.

[0022] In some embodiments, the write return packet may further include: a type field for indicating the data packet type; a count field for indicating the number of write data packets actually received by the core as the receiver of the data in response to the write request packet; and a receive success bit for indicating whether the core as the receiver of the data has successfully received the data transmitted by the core as the sender of the data in response to the write request packet.

[0023] In some embodiments, the read request packet may include: a source ID field for representing the source ID of the read request packet; and a target ID field for representing the target ID of the read request packet.

[0024] In some embodiments, the read request packet may further include: a type field for indicating the data packet type; a length field for indicating the number of read data packets requested by the read request packet; a read request packet ID field for indicating the ID of the read request packet; and an address field for indicating the read address of the read request corresponding to the read request packet.

[0025] In some embodiments, the read data packet may include: a source ID field for representing the source ID of the read data packet; and a destination ID field for representing the destination ID of the read data packet.

[0026] In some embodiments, the read data packet may further include: a type field for indicating the data packet type; a read data packet ID field for indicating the ID of the read data packet; and a data field containing at least a portion of the data to be received in order to perform the read operation, wherein the data is received sequentially through all read data packets belonging to the read request packet of the read operation.

[0027] In some embodiments, the read return packet may include: a read request packet ID field, used to represent the ID of the read request packet corresponding to the read return packet; and a target ID field, used to represent the target ID of the read return packet.

[0028] In some embodiments, the read return packet may further include: a type field for indicating the data packet type; a count field for indicating the number of read data packets actually received by the core as the receiver of the data in response to the read request packet; and a reception success bit for indicating whether the core as the receiver of the data has successfully received the data transmitted by the core as the sender of the data in response to the read request packet.

[0029] In accordance with a second aspect of this disclosure, in order to solve the above-mentioned problems, a graphics card device is proposed, which may include the inter-core interconnect system described in the first aspect of this disclosure.

[0030] According to a third aspect of this disclosure, in order to solve the above-mentioned problems, a write operation method for inter-core interconnect is proposed, wherein the write operation method can be executed in the inter-core interconnect system according to a first aspect of this disclosure. The write operation method is designed for a write operation from a first core to a second core among the at least two cores, and the write operation method may include: A write request packet is sent through the on-chip inter-core interconnect interface of the first core, and the write request packet is configured to indicate a write request. One or more write data packets corresponding to the write request packet are sent through the on-chip inter-core interconnect interface of the first core. The write data packets are configured to contain data transmitted by the first core in response to the write request.

[0031] In some embodiments, the write request packet and one or more write data packets corresponding to the write request packet are sent sequentially through the on-chip inter-core interconnect interface of the first core; and / or Multiple write request packets are first sent through the on-chip inter-core interconnect interface of the first core, followed by one or more write data packets corresponding to the multiple write request packets; and / or Multiple write request packets and one or more write data packets corresponding to the multiple write request packets are sent crosswise through the on-chip inter-core interconnect interface of the first core. The order of the plurality of write request packets is consistent with the order of one or more write data packets corresponding to the plurality of write request packets.

[0032] In some embodiments, the write operation method may further include: converting the first data and the first address into the write request packet and the write data packet through the interface conversion module of the on-chip inter-core interconnection interface of the first core.

[0033] In some embodiments, the write operation method may further include: receiving a write return packet through the on-chip inter-core interconnect interface of the first core, wherein the write return packet is configured to confirm whether the second core has successfully received the data transmitted in response to the write request.

[0034] In some embodiments, the write operation method may further include: converting the write return packet into the second data and the second address through the interface conversion module of the on-chip inter-core interconnection interface of the first core.

[0035] According to the fourth aspect of this disclosure, in order to solve the above-mentioned problems, a read operation method for inter-core interconnect is proposed, wherein the read operation method can be executed in the inter-core interconnect system according to the first aspect of this disclosure. The read operation method is designed for a read operation from a first core to a second core among the at least two cores, and the read operation method may include: A read request packet is sent through the on-chip inter-core interconnect interface of the first core, and the read request packet is configured to indicate a read request. The first core receives one or more read data packets corresponding to the read request packet through its on-chip inter-core interconnect interface. The read data packets are configured to contain data transmitted by the second core in response to the read request.

[0036] In some embodiments, the read operation method may further include: sending a read return packet through the on-chip inter-core interconnect interface of the first core, the read return packet being configured to confirm whether the first core has successfully received the data transmitted by the second core in response to the read request.

[0037] In some embodiments, the read operation method may further include: converting the first data and the first address into the read request packet and the read return packet through the interface conversion module of the on-chip inter-core interconnection interface of the first core.

[0038] In some embodiments, the read operation method may further include: converting the read data packet into the second data and the second address through the interface conversion module of the on-chip inter-core interconnection interface of the first core.

[0039] The features, details, and advantages described for the on-chip inter-core interconnect interface also apply to the graphics card device, the write operation method, and the read operation method.

[0040] It is readily understood that the features mentioned above and to be described below can be used not only in combinations described separately but also in other combinations or individually, without departing from the scope of protection of this disclosure. Attached Figure Description

[0041] The present disclosure will then be described in more detail based on the embodiments shown in the accompanying drawings.

[0042] in: Figure 1 A schematic diagram of an inter-core interconnect system in the form of a crossbar switch matrix bus according to relevant technologies is shown. Figure 2 A schematic diagram of an inter-core interconnection system in the form of a crossbar switch matrix bus using packet switching according to the present disclosure is shown; Figure 3 A schematic diagram is shown of an on-chip inter-core interconnect interface in the form of a crossbar switch matrix bus using a packet switching method according to an embodiment of the present disclosure; Figure 4 A schematic diagram is shown of an on-chip inter-core interconnect interface in the form of a crossbar switch matrix bus employing packet switching, according to another embodiment of the present disclosure. Figure 5 A schematic flowchart of a method for write operations for inter-core interconnection according to this disclosure is shown; and Figure 6 A schematic flowchart of a method for a read operation for inter-core interconnection according to this disclosure is shown. Detailed Implementation

[0043] Figure 1 A schematic diagram of an inter-core interconnect system in the form of a crossbar switch matrix bus for inter-core interconnection, according to related technologies, is shown. Figure 1 In the example, the crossbar switch matrix in the middle connects eight cores, namely cores 0 to 7. These cores are interconnected in a star topology via a crossbar switch matrix bus of related technology. When using the standard AXI3 bus protocol, cores 0 to 7 send data and addresses via direct routing using the crossbar switch matrix bus of related technology, resulting in a large bus width and requiring more than 220 lines per core (in...). Figure 1 (Used as a bold double arrow in the middle).

[0044] Figure 2 A schematic diagram of an inter-core interconnect system employing a crossbar switch matrix bus configuration according to this disclosure is shown. Figure 2 In the middle section, the crossbar switch matrix using packet switching is disclosed in this invention, which can complete data transmission between any two cores. This crossbar switch matrix exemplarily connects eight cores, namely cores 0 to 7, where the number of cores can be adjusted according to specific circumstances.

[0045] These cores 0 to 7 may each include on-chip inter-core interconnect interfaces 10 to 17 for inter-core interconnection, and the on-chip inter-core interconnect interface may have an interface conversion module. The on-chip inter-core interconnect interface uses the interface conversion module to convert first data and a first address into a first data packet with a first custom data packet format, and sends the first data and the first address as the first data packet to the crossbar switch matrix bus. And / or, the on-chip inter-core interconnect interface receives a second data packet with a second custom data packet format from the crossbar switch matrix bus, and uses the interface conversion module to convert the second data packet into second data and a second address. The first address may, for example, include the address of the receiving core, and additionally, may also include the address of the sending core. The second address may also, for example, include the address of the receiving core, and additionally, may also include the address of the sending core. The inter-core interconnect system according to this disclosure may be part of a graphics card device.

[0046] By equipping the cores with an on-chip inter-core interconnect interface with an interface conversion module, and by replacing the crossbar switch matrix bus of related technologies that employs a direct routing method with the crossbar switch matrix bus of this disclosure that employs a packet-switched routing method, data and addresses can be transmitted using a custom packet format. In this way, the inter-core interconnect system according to this disclosure can avoid parallel transmission of these data while maintaining bus efficiency, thereby significantly reducing the required channel width and consequently significantly reducing the number of buses required (in...). Figure 2 (Used as a non-bold double arrow in the text), it can be reduced to the number of bytes corresponding to the data packet.

[0047] In some embodiments, the crossbar switch matrix bus may have an ID routing function for routing based on the destination ID of the first data packet and / or the second data packet. Thus, instead of the aforementioned first and / or second addresses, routing can be performed using the destination ID of the data packet itself.

[0048] In some embodiments, the first data packet and / or the second data packet may contain at least one of the following data packet types: The write request packet (AW) is used to indicate a write request. Write data packet W, which contains data transmitted in response to the write request; A write return packet (BW) is used to confirm whether the core, as the recipient of the data, has successfully received the data transmitted in response to the write request. The Read Request (AR) packet is used to indicate a read request. A read data packet R, used to contain data transmitted in response to the read request; and The Read Return Packet (BR) is used to confirm whether the core, as the recipient of the data, has successfully received the data transmitted in response to the read request.

[0049] In some embodiments, the write request packet AW, write data packet W, write return packet BW, read request packet AR, read data packet R, and read return packet BR may have the same number of bits or bytes. In some embodiments, the bus width of the crossbar switch matrix bus connected to each of cores 0 to 7 according to this disclosure may be related to this number of bits or bytes. In particular, this number of bits or bytes may correspond to the bus width of the crossbar switch matrix bus connected to each of cores 0 to 7. Thus, the bus width of the crossbar switch matrix bus connected to each of cores 0 to 7 is the same. In this way, individual buses are not wasted due to uneven bus widths, while maximizing bus utilization efficiency is ensured.

[0050] In some embodiments, the aforementioned data packet types may, for example, all have 6 bytes, or 48 bits. It is also conceivable that these data packet types may each have an additional number of bytes, which can be adjusted according to specific circumstances without departing from the scope of this disclosure. In this case, the bus width can be 48 lines. Compared to the more than 220 lines required for a single core in related technologies, the bus width of the inter-core interconnect system of this disclosure can be significantly reduced.

[0051] In some embodiments, each of cores 0 to 7 can further utilize its on-chip inter-core interconnect interface to send a single data packet (Write Request Packet AW, Write Data Packet W, Write Return Packet BW, Read Request Packet AR, Read Data Packet R, and Read Return Packet BR) to the crossbar switch matrix bus in multiple cycles. The bus width of the crossbar switch matrix bus connected to each core is related to the number of bits of the data packet sent in each cycle. Therefore, by setting multiple cycles to send a single data packet, the bus width can be further reduced.

[0052] In some embodiments, the custom format of the write request packet (AW) can be, for example: The left column indicates the number of bits corresponding to a field in the data packet; for example, [19:0] indicates bits 0 to 19, a total of 20 bits. The right column indicates the meaning of the corresponding field. Other tables below are constructed in the same way and will not be repeated here.

[0053] The write request packet AW may include: a source ID field src_id, used to represent the source ID of the write request packet; and a destination ID field dst_id, used to represent the destination ID of the write request packet. Therefore, the cross-connect matrix bus employing packet switching according to this disclosure can use the destination ID field dst_id to route the write request packet AW.

[0054] In the current embodiment, for the write request packet AW, 3 bits, such as [35:33], can be used as the source ID field src_id. Similarly, 3 bits, such as [32:30], can be used as the destination ID field dst_id. Thus, the 3-bit width can support a maximum of 2 3 =8 cores interconnected.

[0055] The write request packet AW may also include: a type field, which indicates the data packet type; a length field, which indicates the number of write data packets belonging to the write request packet; a write request packet ID field, aw_id, which indicates the ID of the write request packet; and an address field, addr, which indicates the write address of the write request corresponding to the write request packet.

[0056] In the current embodiment, there can be six packet types (write request packet AW, write data packet W, write return packet BW, read request packet AR, read data packet R, and read return packet BR). Therefore, for example, 3 bits, such as [47:45], can be used to represent the type field. The encoding format of the type field can be, for example, as follows: coding meaning 000 AW 001 W 010 AR 011 R 100 BW 101 BR

[0057] Therefore, for a write request packet (AW), the encoding of its type field can be, for example, 000.

[0058] Furthermore, in the current embodiment, for a write request packet AW, the length field can be, for example, 9 bits, such as [44:36], indicating that a write request packet can correspond to a maximum of 2 9 =512 write data packets. In the current embodiment, the write request ID field aw_id can be, for example, 10 digits, such as [29:20], indicating that a maximum of 2 data packets can be transmitted in a single write operation. 10=1024 write request packets (i.e., outstanding number = 1024, that is, the number of write request packets that have been sent but not yet completed or responded to). In the current embodiment, the address field addr can be, for example, 20 bits, such as [19:0]. Thus, a write address of up to 20 bits can be used.

[0059] It is also conceivable that these fields may have other bit lengths, which can be adjusted according to specific circumstances. Similarly, the bit length of fields in other data packet types according to this disclosure can also be adjusted according to specific circumstances without departing from the protection scope of this disclosure.

[0060] In some embodiments, the custom format for writing data packet W can be, for example:

[0061] The write data packet W may include: a source ID field src_id, used to represent the source ID of the write data packet; and a destination ID field dst_id, used to represent the destination ID of the write data packet. Similarly, the cross-connect matrix bus employing packet switching according to this disclosure can use the destination ID field dst_id to route the write data packet W.

[0062] In the current embodiment, for the write data packet W, 3 bits, such as [38:36], can be used as the source ID field src_id. Similarly, 3 bits, such as [44:42], can be used as the destination ID field dst_id. Thus, the 3-bit width can support a maximum of 2 3 =8 cores interconnected.

[0063] The write data packet W may further include: a type field, indicating the data packet type; a start bit, indicating the start of the write operation, i.e., the first write data packet of the write request corresponding to the write request packet; an end bit, indicating the end of the write operation, i.e., the last write data packet of the write request corresponding to the write request packet; and a data field, the data field containing at least a portion of the data to be sent in order to perform the write operation, wherein the data is sent sequentially through all write data packets belonging to the write request packet of the write operation.

[0064] In the current embodiment, the type field of the write data packet W can be the same as that of the write request packet AW, for example, 3 bits, such as [47:45], and its encoding is, for example, 001. The start bit of the write data can be, for example, 1 bit, such as

[40] . The end bit of the write data can also be, for example, 1 bit, such as

[39] . The data field can be, for example, 32 bits, such as [31:0], that is, 4 bytes.

[0065] The write packet may also include: a mask field, used to indicate whether the data field data of the write packet is valid; and a reserved field or reserved bit, used to indicate fields or bits that are not used in the write packet.

[0066] In the current embodiment, for the write data packet W, the mask field mask can be, for example, 4 bits, such as [35:32]. Thus, for the 4-byte data field data, collision detection using the mask field mask can be more granular at the byte level. The reserved field or reserved bit can be, for example, at least 1 bit, such as

[41] , which is used to ensure that the corresponding data packets are the same size, that is, to ensure that the data packets are 48 bits (6 bytes) in the current case, and can also be used for future expansion of the write data packet W.

[0067] In another embodiment, if the write data packet W has an additional number of bytes, the write data packet W may, for example, include multiple reserved bits or a reserved field with multiple reserved bits, which can be adjusted as needed. Similarly, other data packet types according to this disclosure may also include suitable reserved bits or reserved fields, especially when these data packet types have an additional number of bytes, to ensure that the corresponding data packets are of the same size and are also used for future expansion of the corresponding data packets.

[0068] In some embodiments, the custom format for writing the return packet BW can be, for example:

[0069] The write return packet BW may include: a write request packet ID field aw_id, used to represent the ID of the write request packet corresponding to the write return packet; and a destination ID field dst_id, used to represent the destination ID of the write return packet. Therefore, the cross-connect matrix bus using packet switching according to this disclosure can use the destination ID field dst_id to route the write return packet BW. It is worth noting that the destination ID field dst_id of the write return packet BW can be the source ID field src_id of the write request packet AW and / or the write data packet W corresponding to the write return packet.

[0070] In the current embodiment, for the write return packet BW, for example, 3 bits, such as [44:42], can be used as the target ID field dst_id. Thus, the 3-bit width can support a maximum of 2... 3 =8 cores interconnected. The write request packet ID field aw_id can be 10 bits, for example, [41:32].

[0071] The write return packet (BW) may also include: a type field, which indicates the data packet type; a count field, which indicates the number of write data packets actually received by the core, which is the receiver of the data, in response to the write request packet; and a success bit, which indicates whether the core, which is the receiver of the data, has successfully received the data transmitted by the core, which is the sender of the data, in response to the write request packet.

[0072] In the current embodiment, the type field of the write return packet BW can have the same number of bits as the write request packet AW and the write data packet W, for example, 3 bits, such as [47:45], and its encoding is, for example, 100. The count field can be, for example, 9 bits, such as [9:1], and can have a maximum of 2... 9 =512 write data packets are counted. The write return packet BW returns the number of write data packets W actually received via the count field. The success bit can be 1 bit, for example, [0]. If the number of write data packets W received by the receiving core in response to the corresponding write request packet AW matches the number of write data packets W contained in the corresponding write request, then the success bit indicates successful reception; otherwise, the success bit indicates reception failure. This success bit determines whether the corresponding write operation was successfully completed. Based on this, the sending core can decide whether to re-execute the corresponding write operation.

[0073] Additionally, the write return packet BW may also include: reserved fields or reserved bits, used to indicate fields or bits that are not used in the write return packet.

[0074] In the current embodiment, the reserved field or reserved bit can be at least 22 bits, for example [31:10], which is used to ensure that the corresponding data packets are the same size, that is, to ensure that the data packets are 48 bits (6 bytes) in the current case, and can also be used to write future extensions of the return packet BW.

[0075] In some embodiments, the custom format of the read request packet AR can be, for example:

[0076] The read request packet AR may include: a source ID field src_id, used to represent the source ID of the read request packet; and a destination ID field dst_id, used to represent the destination ID of the read request packet. Therefore, the cross-connect matrix bus employing packet switching according to this disclosure can use the destination ID field dst_id to route the read request packet AR.

[0077] In the current embodiment, for the read request packet AR, 3 bits, such as [35:33], can be used as the source ID field src_id. Similarly, 3 bits, such as [32:30], can be used as the destination ID field dst_id. Thus, a 3-bit width can support a maximum of 2... 3 =8 cores interconnected.

[0078] The read request packet AR may also include: a type field, which indicates the type of the data packet; a length field, which indicates the number of read data packets requested by the read request packet; a read request packet ID field, ar_id, which indicates the ID of the read request packet; and an address field, addr, which indicates the read address of the read request corresponding to the read request packet.

[0079] In the current embodiment, the type field of the read request packet AR can be, for example, 3 bits, such as [47:45], and its encoding is, for example, 010. The length field can be, for example, 9 bits, such as [44:36], indicating that a read request packet can correspond to a maximum of 2 9 =512 read data packets. In the current embodiment, the read request ID field ar_id can be, for example, 10 bits, such as [29:20], indicating that a maximum of 2 data packets can be transmitted in a single read operation. 10 =1024 read request packets (i.e., outstanding number of pending requests = 1024). In the current embodiment, the address field addr can be, for example, 20 bits, such as [19:0]. Thus, a read address of up to 20 bits can be used.

[0080] In some embodiments, the custom format of the read data packet R can be, for example:

[0081] The read data packet R may include: a source ID field src_id, used to represent the source ID of the read data packet; and a destination ID field dst_id, used to represent the destination ID of the read data packet. Similarly, the cross-connect matrix bus employing packet switching according to this disclosure can use the destination ID field dst_id to route the read data packet R.

[0082] In the current embodiment, for reading data packet R, 3 bits, such as [41:39], can be used as the source ID field src_id. Similarly, 3 bits, such as [44:42], can be used as the destination ID field dst_id. Thus, a 3-bit width can support a maximum of 2... 3 =8 cores interconnected.

[0083] The read data packet R may further include: a type field, type, for indicating the data packet type; a read data packet ID field, r_id, for indicating the ID of the read data packet; and a data field, data field, which contains at least a portion of the data to be received in order to perform the read operation, wherein the data is received sequentially through all read data packets belonging to the read request packet of the read operation.

[0084] In the current embodiment, the type field of the read data packet R can have the same number of bits as the read request packet AR, for example, 3 bits, such as [47:45], and its encoding is, for example, 011. The read data packet ID field r_id can be, for example, 9 bits, such as [38:30], indicating that one read request packet can correspond to a maximum of 2 9 =512 read data packets. The data field can be 30 bits, for example, [29:0].

[0085] In some embodiments, the custom format of the read return packet BR can be, for example:

[0086] The read return packet BR may include: a read request packet ID field ar_id, used to represent the ID of the read request packet corresponding to the read return packet; and a destination ID field dst_id, used to represent the destination ID of the read return packet. Therefore, the cross-connect switch matrix bus using packet switching according to this disclosure can use the destination ID field dst_id to route the read return packet BR. It is worth noting that the destination ID field dst_id of the read return packet BR can be the destination ID field dst_id of the read request packet AR corresponding to the read return packet.

[0087] In the current embodiment, for the read return packet BR, for example, 3 bits, such as [44:42], can be used as the target ID field dst_id. Thus, the 3-bit width can support a maximum of 2... 3 =8 cores interconnected. The read request packet ID field ar_id can be 10 bits, for example, [41:32].

[0088] The read return packet (BR) may also include: a type field, which indicates the data packet type; a count field, which indicates the number of read data packets actually received by the core that is the receiver of the data in response to the read request packet; and a success bit, which indicates whether the core that is the receiver of the data has successfully received the data transmitted by the core that is the sender of the data in response to the read request packet.

[0089] In the current embodiment, the type field of the read return packet BR can have the same number of bits as the read request packet AR and the read data packet R, for example, 3 bits, such as [47:45], and its encoding is, for example, 101. The count field can be, for example, 9 bits, such as [9:1], and can have a maximum of 2... 9 =512 read data packets are counted. The read return packet BR returns the number of read data packets R actually received via the count field. The success bit can be 1 bit, for example, [0]. Similar to the success bit in the write return packet BW, a failure can also be indicated by the success bit in the read return packet BR. This success bit determines whether the corresponding read operation was successfully completed. Based on this, the core, as the sender, can decide whether to re-execute the corresponding read operation.

[0090] Additionally, the read return packet BR may also include a reserved field or reserved bit, used to indicate a field or bit that is not used in the read return packet.

[0091] In the current embodiment, the reserved field or reserved bit can be at least 22 bits, for example [31:10], which is used to ensure that the corresponding data packets are the same size, that is, to ensure that the data packets are 48 bits (6 bytes) in the current case, and can also be used for future expansion of reading the return packet BR.

[0092] The significance of write return packets (BW) and / or read return packets (BR) lies in their ability to serve as a basis for deciding whether to continue sending outstanding requests. The term "outstanding" refers to the core's ability to initiate multiple read / write operations without receiving a response, or it can represent the burst size of a core's read / write requests. In other words, the on-chip inter-core interconnect interface can determine whether to continue initiating read / write operations based on the received write and / or read return packets. If read / write operations can continue, i.e., outstanding requests can continue to be sent, the bus arbitration mechanism can be set to prioritize address packets over data packets, with write and / or read return packet channels having the lowest priority.

[0093] Figure 3 A schematic diagram of an on-chip inter-core interconnect interface according to an embodiment of the present disclosure is shown for an inter-core interconnect in the form of a crossbar switch matrix bus employing a packet switching method based on the present disclosure. The on-chip inter-core interconnect interface 10 of core 0 is described here as an example of a packet sender when performing write and / or read operations. Other on-chip inter-core interconnect interfaces of other cores have the same structure and function. The on-chip inter-core interconnect interface 10 is designed to convert first data and a first address into a packet and send the packet to the crossbar switch matrix bus according to the present disclosure (i.e., represented by UDI_TX). In the current embodiment, the packet is 48 bits.

[0094] For a write request packet AW, the on-chip inter-core interconnect interface 10 can, for example, use its interface conversion module to convert at least the write address aw_addr and the ID of the write request packet AW, i.e., aw_id, into the corresponding write request packet AW, and send it to the crossbar switch matrix bus. For a write data packet W, the on-chip inter-core interconnect interface 10 can, for example, use its interface conversion module to convert at least the data w_data of the write data packet W into the corresponding write data packet W, and send it to the crossbar switch matrix bus. For a read request packet AR, the on-chip inter-core interconnect interface 10 can, for example, use its interface conversion module to convert at least the read address ar_addr and the ID of the read request packet AR, i.e., ar_id, into the corresponding read request packet AR, and send it to the crossbar switch matrix bus. For a read return packet BR, the on-chip inter-core interconnect interface 10 can, for example, use its interface conversion module to convert at least the ID of the read request packet AR corresponding to the read return packet BR, i.e., ar_id, into the corresponding read return packet AR, and send it to the crossbar switch matrix bus.

[0095] Figure 4 A schematic diagram of an on-chip inter-core interconnect interface according to another embodiment of the present disclosure for an inter-core interconnection in the form of a crossbar switch matrix bus employing a packet switching method based on the present disclosure is shown. Here, the on-chip inter-core interconnect interface 10 of core 0 is described as an example of a packet receiver performing write and / or read operations. Other on-chip inter-core interconnect interfaces of other cores have the same structure and function. The on-chip inter-core interconnect interface 10 is designed to receive (i.e., represented by UDI_RX) data packets from the crossbar switch matrix bus according to the present disclosure and convert the data packets into second data and a second address. In the current embodiment, the data packet is 48 bits.

[0096] For a write return packet BW, the on-chip inter-core interconnect interface 10 can, for example, receive the write return packet BW from the crossbar switch matrix bus, and use its interface conversion module to at least convert the write return packet into the ID of the corresponding write request packet AW, i.e., aw_id. For a read data packet R, the on-chip inter-core interconnect interface 10 can, for example, receive the read data packet R from the crossbar switch matrix bus, and use its interface conversion module to at least convert the read data packet into the data r_data and the ID of the read data packet R, i.e., r_id.

[0097] For in Figure 3 and Figure 4 In embodiments of the on-chip inter-core interconnect interface 10, the on-chip inter-core interconnect interface 10 may, for example, include a FIFO buffer for an interface conversion module to resolve data latency caused by arbitration. This arbitration includes not only arbitration at the interface conversion module but also arbitration in the topology of the cross-connect matrix bus. The FIFO buffer may, for example, have the same buffer depth `fifo_depth` for each of the aforementioned custom packet types, or different buffer depths `fifo_depth`.

[0098] exist Figure 3 In the embodiment of the on-chip inter-core interconnect interface 10 shown, the cache depth of the corresponding FIFO cache is indicated. For example, the cache depth of the FIFO cache used for write request packets AW, read request packets AR, and read return packets BR can be fifo_depth = 8 bits. The cache depth of the FIFO cache used for write data packets W can be fifo_depth = 32 bits. Other cache depths for the FIFO cache used for the corresponding data packets are also feasible.

[0099] exist Figure 4 In the embodiment of the on-chip inter-core interconnect interface 10 shown, the corresponding FIFO buffer depth is also indicated. For example, the FIFO buffer depth for reading data packet R can be fifo_depth = 32 bits. The FIFO buffer depth for writing return packet BW can be, for example, fifo_depth = 8 bits. Other buffer depths for the corresponding data packet's FIFO buffer are also possible.

[0100] The depth of a FIFO cache generally represents the overall backpressure resistance of the interconnect bus. Backpressure refers to the receiver instructing the sender (in this example, a core) to stop sending data. Since the receiver (in this example, another core) may be temporarily unable to receive data packets due to some special circumstances, packets can be temporarily stored in the FIFO cache. This avoids directly pressuring the sender and does not affect the sender's normal operation. Generally, the amount of data is greater than the number of requests; therefore, the FIFO cache used for caching data will be larger than the FIFO cache used for caching requests. The specific value depends on the specific scenario, and its significance lies in minimizing backpressure on the sender with as few resources as possible.

[0101] Figure 5 A schematic flowchart of a write operation method for inter-core interconnect according to the present disclosure is shown. The write operation method can, for example, be performed in an inter-core interconnect system according to the present disclosure. The write operation method can, for example, be designed for a write operation from a first core of at least two cores to a second core of at least two cores in the inter-core interconnect system. The write operation method may, for example, include the following steps: Step 601: Send a write request packet AW through the on-chip inter-core interconnect interface of the first core, wherein the write request packet is configured to indicate a write request; Step 602: Send one or more write data packets W corresponding to the write request packet AW through the on-chip inter-core interconnect interface of the first core. The write data packets are configured to contain the data transmitted by the first core in response to the write request.

[0102] Additionally, the write operation method may, for example, include in step 601 converting the corresponding data and address into a write request packet via the interface conversion module of the on-chip inter-core interconnect interface of the first core. Similarly, the write operation method may, for example, include in step 602 converting the corresponding data and address into a write data packet via the interface conversion module of the on-chip inter-core interconnect interface of the first core.

[0103] In step 601, the write request packet W sent by the first core may be designed to indicate the source and destination of the write request, while also telling the second core how much data to write. In step 602, each write packet W may contain, for example, a source and destination ID. Each write packet W may also contain bits or fields indicating whether the write packet is the first and / or last write packet of the corresponding write request.

[0104] In embodiments of this method, write request packets and one or more write data packets belonging to each write request packet are sequentially sent via the on-chip inter-core interconnect interface. Alternatively or supplementarily, multiple write request packets may be sent first, followed by one or more write data packets belonging to each of the multiple write request packets, wherein the order of the multiple write request packets corresponds to the order of the one or more write data packets belonging to each of the multiple write request packets. Alternatively or supplementarily, multiple write request packets and one or more write data packets belonging to each of the multiple write request packets may be sent in an alternating manner, wherein the order of the multiple write request packets corresponds to the order of the one or more write data packets corresponding to each of the multiple write request packets.

[0105] Additionally, the write operation method may also include, for example: Step 603: Receive a write return packet BW from the second core through the on-chip inter-core interconnect interface of the first core. The write return packet is configured to confirm whether the second core has successfully received the data transmitted in response to the write request.

[0106] Additionally, the write operation method may, for example, include in step 603: converting the write return packet BW into corresponding data and address through the interface conversion module of the on-chip inter-core interconnection interface of the first core.

[0107] For a write return packet BW from the second core, the second core determines the source of the data packet based on the source ID field src_id of the write request packet AW and begins counting. When a write data packet W with an end-of-write bit is received, the total number of write data packets W received is compared with the number of write data packets W contained in the corresponding write request. If they match, a success bit indicates successful reception; otherwise, the success bit indicates reception failure. The actual number of write data packets W received is included in the count field of the write return packet BW. The first core performing the write operation, especially its on-chip inter-core interconnect interface, can decide whether to re-execute the corresponding write operation.

[0108] Figure 6 A schematic flowchart of a method for a read operation for inter-core interconnect according to the present disclosure is shown. The read operation method can, for example, be performed in an inter-core interconnect system according to the present disclosure. The read operation method can, for example, be designed for a read operation from a first core of at least two cores to a second core of the at least two cores in the inter-core interconnect system. The read operation method may, for example, include the following steps: Step 701: Send a read request packet AR through the on-chip inter-core interconnect interface of the first core, wherein the read request packet is configured to indicate a read request; Step 702: Receive one or more read data packets R corresponding to the read request packet AR through the on-chip inter-core interconnect interface of the first core, wherein the read data packets are configured to contain data transmitted by the second core in response to the read request.

[0109] Additionally, the read operation method may, for example, include in step 701 converting the corresponding data and address into a read request packet AR via the interface conversion module of the on-chip inter-core interconnect interface of the first core. Similarly, the read operation method may, for example, include in step 702 converting the corresponding data and address into a read return packet R via the interface conversion module of the on-chip inter-core interconnect interface of the first core.

[0110] Additionally, the read operation method may also include, for example: Step 703: Send a read return packet BR through the on-chip inter-core interconnect interface of the first core. The read return packet is configured to confirm whether the first core has successfully received the data transmitted by the second core in response to the read request.

[0111] Additionally, the read operation method may, for example, include in step 703: converting the read return packet BR into corresponding data and address through the interface conversion module of the on-chip inter-core interconnection interface of the first core.

[0112] Similar to Figure 5 The write operation method in Figure 6 In the read operation method shown, for the write return packet BW sent by the first core, the number of read data packets R received for the corresponding read request can be compared with the number of requested read data packets R in the length field of the read request packet AR via the on-chip inter-core interconnect interface of the first core. If they match, a reception success bit indicates successful reception; otherwise, the reception success bit indicates reception failure. The count field in the read return packet BR contains information about the actual number of read data packets R received. The first core performing the read operation, especially the on-chip inter-core interconnect interface of the first core, can decide whether to re-execute the corresponding read operation.

[0113] Through the above embodiments, by transmitting data and addresses via custom data packets in the form of packet exchange, the required number of buses can be significantly reduced, while the data packet format is more flexible. Alternatively or additionally, if needed, multiple cycles can be configured to send a data packet to further reduce the bus width.

[0114] This disclosure is not limited to the embodiments described herein and the aspects highlighted therein. Rather, numerous variations are possible within the scope of protection set forth in the claims, all of which are within the purview of those skilled in the art.

Claims

1. An inter-core interconnection system, characterized in that, The inter-core interconnect system has: at least two cores; and a crossbar switch matrix bus for connecting the at least two cores. Each of the at least two cores includes an on-chip inter-core interconnect interface for inter-core interconnection. The on-chip inter-core interconnect interface has an interface conversion module, wherein the on-chip inter-core interconnect interface uses the interface conversion module to convert first data and a first address into a first data packet with a first custom data packet format, and sends the first data and the first address to the crossbar switch matrix bus in the first data packet. And / or, the on-chip inter-core interconnect interface receives a second data packet with a second custom data packet format from the crossbar switch matrix bus, and uses the interface conversion module to convert the second data packet into second data and a second address.

2. The inter-core interconnection system according to claim 1, characterized in that, The on-chip inter-core interconnect interface includes a FIFO cache for caching the first data packet and / or the second data packet according to the depth of the FIFO cache.

3. The inter-core interconnection system according to claim 1 or 2, characterized in that, The crossbar switch matrix bus has an ID routing function, which is used to route data according to the target ID of the first data packet and / or the second data packet.

4. The inter-core interconnection system according to claim 1 or 2, characterized in that, The first data packet and / or the second data packet contains at least one of the following data packet types: A write request packet is used to indicate a write request; Write data packet, used to contain data transmitted in response to the write request; A write return packet is used to confirm whether the core, as the recipient of the data, has successfully received the data transmitted in response to the write request; A read request packet is used to indicate a read request; A read data packet, used to contain data transmitted in response to the read request; and A read return packet is used to confirm whether the core, as the recipient of the data, has successfully received the data transmitted in response to the read request.

5. The inter-core interconnection system according to claim 4, characterized in that, The write request packet, the write data packet, the write return packet, the read request packet, the read data packet, and the read return packet all have the same number of bits.

6. The inter-core interconnection system according to claim 5, characterized in that, The bus width of the crossbar switch matrix bus connected to each of the at least two cores is related to the number of bits.

7. The inter-core interconnection system according to claim 6, characterized in that, The number of bits corresponds to the bus width of the crossbar switch matrix bus connected to each of the at least two cores.

8. The inter-core interconnection system according to claim 7, characterized in that, The bus width is 48 lines.

9. The inter-core interconnection system according to claim 4, characterized in that, One of the at least two cores uses the on-chip inter-core interconnect interface to send one of the write request packets, the write data packets, the write return packets, the read request packets, the read data packets, and the read return packets to the crossbar switch matrix bus in multiple cycles, wherein the bus width of the crossbar switch matrix bus connected to each of the at least two cores is related to the number of bits of the data packets sent in each cycle.

10. The inter-core interconnection system according to claim 4, characterized in that, The write request packet includes: a source ID field, used to represent the source ID of the write request packet; and a destination ID field, used to represent the destination ID of the write request packet.

11. The inter-core interconnection system according to claim 10, characterized in that, The write request packet further includes: a type field for indicating the data packet type; a length field for indicating the number of write data packets belonging to the write request packet; a write request packet ID field for indicating the ID of the write request packet; and an address field for indicating the write address of the write request corresponding to the write request packet.

12. The inter-core interconnection system according to claim 4, characterized in that, The write data packet includes: a source ID field, used to represent the source ID of the write data packet; and a destination ID field, used to represent the destination ID of the write data packet.

13. The inter-core interconnection system according to claim 12, characterized in that, The write data packet further includes: a type field for indicating the data packet type; a write data start bit for indicating the start of the write operation, i.e., the first write data packet of the write request corresponding to the write request packet; a write data end bit for indicating the end of the write operation, i.e., the last write data packet of the write request corresponding to the write request packet; and a data field, the data field containing at least a portion of the data to be sent in order to perform the write operation, wherein the data is sent sequentially through all write data packets belonging to the write request packet of the write operation.

14. The inter-core interconnection system according to claim 13, characterized in that, The write data packet further includes: a mask field for indicating whether the data field of the write data packet is valid; and a reserved field or reserved bit for indicating fields or bits that are not used in the write data packet.

15. The inter-core interconnection system according to claim 4, characterized in that, The write return packet includes: a write request packet ID field, used to represent the ID of the write request packet corresponding to the write return packet; and a target ID field, used to represent the target ID of the write return packet.

16. The inter-core interconnection system according to claim 15, characterized in that, The write return packet further includes: a type field for indicating the data packet type; a count field for indicating the number of write data packets actually received by the core as the receiver of the data in response to the write request packet; and a reception success bit for indicating whether the core as the receiver of the data has successfully received the data transmitted by the core as the sender of the data in response to the write request packet.

17. The inter-core interconnection system according to claim 4, characterized in that, The read request packet includes: a source ID field, used to represent the source ID of the read request packet; and a target ID field, used to represent the target ID of the read request packet.

18. The inter-core interconnection system according to claim 17, characterized in that, The read request packet further includes: a type field for indicating the data packet type; a length field for indicating the number of read data packets requested by the read request packet; a read request packet ID field for indicating the ID of the read request packet; and an address field for indicating the read address of the read request corresponding to the read request packet.

19. The inter-core interconnection system according to claim 4, characterized in that, The read data packet includes: a source ID field, used to represent the source ID of the read data packet; and a destination ID field, used to represent the destination ID of the read data packet.

20. The inter-core interconnection system according to claim 19, characterized in that, The read data packet further includes: a type field for indicating the data packet type; a read data packet ID field for indicating the ID of the read data packet; and a data field containing at least a portion of the data to be received in order to perform the read operation, wherein the data is received sequentially through all read data packets belonging to the read request packet of the read operation.

21. The inter-core interconnection system according to claim 4, characterized in that, The read return packet includes: a read request packet ID field, used to represent the ID of the read request packet corresponding to the read return packet; and a target ID field, used to represent the target ID of the read return packet.

22. The inter-core interconnection system according to claim 21, characterized in that, The read return packet further includes: a type field for indicating the data packet type; a count field for indicating the number of read data packets actually received by the core as the data receiver in response to the read request packet; and a reception success bit for indicating whether the core as the data receiver has successfully received the data transmitted by the core as the data sender in response to the read request packet.

23. A graphics card device, characterized in that, The graphics card device includes an inter-core interconnect system according to any one of claims 1 to 22.

24. A write operation method for inter-core interconnection, characterized in that, The write operation method is performed in the inter-core interconnect system according to any one of claims 1 to 22. The write operation method is designed for a write operation from a first core to a second core among the at least two cores, wherein the write operation method includes: A write request packet is sent through the on-chip inter-core interconnect interface of the first core, and the write request packet is configured to indicate a write request. One or more write data packets corresponding to the write request packet are sent through the on-chip inter-core interconnect interface of the first core. The write data packets are configured to contain data transmitted by the first core in response to the write request.

25. The write operation method according to claim 24, characterized in that, The write request packet and one or more write data packets corresponding to the write request packet are sent sequentially through the on-chip inter-core interconnect interface of the first core; and / or Multiple write request packets are first sent through the on-chip inter-core interconnect interface of the first core, followed by one or more write data packets corresponding to the multiple write request packets; and / or Multiple write request packets and one or more write data packets corresponding to the multiple write request packets are sent crosswise through the on-chip inter-core interconnect interface of the first core. The order of the plurality of write request packets is consistent with the order of one or more write data packets corresponding to the plurality of write request packets.

26. The write operation method according to claim 24 or 25, characterized in that, The write operation method further includes: converting the first data and the first address into the write request packet and the write data packet through the interface conversion module of the on-chip inter-core interconnection interface of the first core.

27. The write operation method according to claim 24 or 25, characterized in that, The write operation method further includes: receiving a write return packet through the on-chip inter-core interconnect interface of the first core, wherein the write return packet is configured to confirm whether the second core has successfully received the data transmitted in response to the write request.

28. The write operation method according to claim 27, characterized in that, The write operation method further includes: converting the write return packet into the second data and the second address through the interface conversion module of the on-chip inter-core interconnection interface of the first core.

29. A read operation method for inter-core interconnection, characterized in that, The read operation method is performed in the inter-core interconnect system according to any one of claims 1 to 22. The read operation method is designed for a read operation from a first core to a second core among the at least two cores, wherein the read operation method includes: A read request packet is sent through the on-chip inter-core interconnect interface of the first core, and the read request packet is configured to indicate a read request. The first core receives one or more read data packets corresponding to the read request packet through its on-chip inter-core interconnect interface. The read data packets are configured to contain data transmitted by the second core in response to the read request.

30. The read operation method according to claim 29, characterized in that, The read operation method further includes: A read return packet is sent through the on-chip inter-core interconnect interface of the first core. The read return packet is configured to confirm whether the first core has successfully received the data transmitted by the second core in response to the read request.

31. The write operation method according to claim 30, characterized in that, The read operation method further includes: converting the first data and the first address into the read request packet and the read return packet through the interface conversion module of the on-chip inter-core interconnection interface of the first core.

32. The write operation method according to any one of claims 29 to 31, characterized in that, The read operation method further includes: converting the read data packet into the second data and the second address through the interface conversion module of the on-chip inter-core interconnection interface of the first core.

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