Methods, apparatus, and servers for constructing DDR parameter evaluation models

Abstract

This invention provides a method, apparatus, and server for constructing a DDR parameter evaluation model, relating to the technical field of parameter evaluation. The method includes: obtaining a set of timing parameters in a chip's DDR module, wherein the timing parameter set includes explicit timing parameters and implicit timing parameters; encoding the explicit and implicit timing parameters respectively to obtain a target training data set; performing vector feature encoding on the target training data set using a deep learning network based on a deep learning network with attention mechanism and a CNN network for dual-stream feature extraction to obtain a feature encoding vector; and inputting the feature encoding vector into the deep learning network for model training to obtain a DDR parameter evaluation model, wherein the DDR parameter evaluation model is used to evaluate the DDR parameters of the chip. This invention can significantly improve the evaluation efficiency and accuracy of DDR parameters.

Description

Technical Field

[0001] This invention relates to the technical field of parameter evaluation, and in particular to a method, apparatus and server for constructing a DDR parameter evaluation model. Background Technology

[0002] DDR modules are an important memory technology in the chip industry, widely used in PCs and mobile devices. Currently, some technologies suggest manually debugging the parameters of each module in the DDR, verifying them on a DV platform, and finally verifying them on an actual EVB board. However, this approach relies heavily on human experience, resulting in low evaluation efficiency and uncertain results. Furthermore, the dependencies between parameters in DDR are difficult to uncover, especially since most PHY parameters lack publicly available information, creating blind spots for manual debugging. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a method, apparatus and server for constructing a DDR parameter evaluation model, which can significantly improve the evaluation efficiency and accuracy of DDR parameters.

[0004] In a first aspect, embodiments of the present invention provide a method for constructing a DDR parameter evaluation model. The method includes: obtaining a set of timing parameters in a chip's DDR module, wherein the set of timing parameters includes: explicit timing parameters and implicit timing parameters; encoding the explicit timing parameters and implicit timing parameters respectively to obtain a target training data set; performing vector feature encoding on the target training data set through a deep learning network based on a deep learning network with attention mechanism and a CNN network for dual-stream feature extraction to obtain a feature encoding vector; and inputting the feature encoding vector into the deep learning network for model training to obtain a DDR parameter evaluation model, wherein the DDR parameter evaluation model is used to evaluate the DDR parameters of the chip.

[0005] In one implementation, the step of encoding explicit and implicit time-series parameters to obtain a target training data set includes: performing data annotation and adjustment processing on the time-series parameter set using an automated script to obtain a training data set; and encoding the explicit and implicit time-series parameters in the training data set to unify the dimensions of the explicit and implicit time-series parameters to obtain the target training data set.

[0006] In one implementation, the step of using an automated script to perform data annotation and adjustment on a timing parameter set to obtain a training data set includes: obtaining the memory clock cycle range of the timing parameter set, performing read / write tests on the timing parameter set based on the memory clock cycle range, and annotating reasonable timing parameters that pass the read / write tests and unreasonable timing parameters that fail the read / write tests; performing parameter adjustment on the annotated parameters, and performing data expansion based on the number of explicit timing parameters in the adjusted parameters and the memory clock cycle corresponding to each explicit timing parameter to obtain the training data set.

[0007] In one implementation, the step of adjusting the parameters after annotation includes: performing deviation estimation processing on unreasonable time series parameters, and performing parameter adjustment processing based on the deviation estimation results to make the ratio of reasonable time series parameters to unreasonable time series parameters the same.

[0008] In one implementation, the steps of encoding explicit and implicit time-series parameters in the training dataset to unify their dimensions and obtain the target training dataset include: obtaining the first and second vector dimensions corresponding to the explicit and implicit time-series parameters, as well as the memory clock cycle corresponding to each parameter; using the first and second vector dimensions to perform parameter vector encoding on the explicit and implicit time-series parameters, and normalizing the encoded parameters based on the memory clock cycle to obtain the target training dataset.

[0009] In one implementation, the step of performing vector feature encoding processing on the target training dataset using a deep learning network based on an attention mechanism and a CNN network for dual-stream feature extraction to obtain a feature encoding vector includes: encoding explicit temporal parameters in the target training dataset using an attention mechanism-based deep learning network to obtain a first encoding result; encoding implicit temporal parameters in the target training dataset using a CNN network for dual-stream feature extraction to obtain a second encoding result; and decoding the first and second encoding results using a fully connected neural network to obtain a feature encoding vector.

[0010] In one implementation, the step of inputting the feature encoding vector into a deep learning network for model training to obtain a DDR parameter evaluation model includes: inputting the feature encoding vector into a deep learning network for model training; at the beginning of training, increasing the learning rate of the model training through a warm-up algorithm; and when the learning rate reaches a preset learning rate threshold, decreasing the learning rate through an annealing algorithm to iteratively train the feature encoding vector; and when a preset number of iterations is reached, outputting the DDR parameter evaluation model.

[0011] Secondly, embodiments of the present invention also provide a device for constructing a DDR parameter evaluation model. The device includes: a parameter acquisition module for acquiring a set of timing parameters in the DDR module of a chip, wherein the set of timing parameters includes: explicit timing parameters and implicit timing parameters; a parameter encoding module for encoding the explicit and implicit timing parameters respectively to obtain a target training data set; a feature extraction module for performing vector feature encoding processing on the target training data set through a deep learning network based on a deep learning network with attention mechanism and a CNN network for dual-stream feature extraction to obtain a feature encoding vector; and a model training module for inputting the feature encoding vector into the deep learning network for model training to obtain a DDR parameter evaluation model, wherein the DDR parameter evaluation model is used to evaluate the DDR parameters of the chip.

[0012] Thirdly, embodiments of the present invention also provide a server, including a processor and a memory, the memory storing computer-executable instructions executable by the processor, the processor executing the computer-executable instructions to implement any of the methods provided in the first aspect.

[0013] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing computer-executable instructions, which, when invoked and executed by a processor, cause the processor to implement any of the methods provided in the first aspect.

[0014] The embodiments of the present invention bring the following beneficial effects:

[0015] This invention provides a method, apparatus, and server for constructing a DDR parameter evaluation model. The method involves obtaining a set of timing parameters from the DDR module of a chip, encoding both explicit and implicit timing parameters to obtain a target training data set. Then, a deep learning network using a dual-stream feature extraction mechanism (attention-based deep learning network and CNN network) is used to encode the target training data set into vector features, resulting in a feature encoding vector. Finally, the feature encoding vector is input into the deep learning network for model training to obtain a DDR parameter evaluation model. This trained DDR parameter evaluation model is then used to evaluate the DDR parameters of the chip. This invention significantly improves the evaluation efficiency and accuracy of DDR parameters.

[0016] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1 A flowchart illustrating a method for constructing a DDR parameter evaluation model according to an embodiment of the present invention;

[0020] Figure 2 A flowchart illustrating a feature extraction method for DDR parameters provided in an embodiment of the present invention;

[0021] Figure 3 A schematic diagram of explicit timing parameter encoding provided in an embodiment of the present invention;

[0022] Figure 4 A schematic diagram illustrating an implicit timing parameter encoding method provided in an embodiment of the present invention;

[0023] Figure 5 A schematic diagram of a device for constructing a DDR parameter evaluation model provided in an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the structure of a server provided in an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Currently, DDR modules are an important memory technology in the chip industry, widely used in PCs and everyday mobile devices. Their main components are generally divided into a DDR controller, a DDR PHY, and DDR SDRAM chips. These three parts follow JEDEC specifications, and the main components are designed, developed, and manufactured by different manufacturers. DDR has evolved from DDR to DDR5, supporting increasingly higher I / O rates, thus its design has become more complex. Especially in high-speed modes, there are many timing control parameters related to signal integrity, which consumes significant resources during chip design and chip bringing-up. Furthermore, while the parameters of the CTRL controller module and SDRAM module are generally explicitly stated in the manufacturer's specifications, the parameters of the PHY module are not explicitly stated in the specifications due to trade secrets, making this part an implicit parameter and creating a blind spot in DDR verification.

[0027] Existing technologies primarily rely on manual debugging of various module parameters in DDR, followed by verification on a DV platform, and finally verification on actual EVB boards. Therefore, existing technologies heavily depend on experienced personnel for DDR design, verification, and debugging. Furthermore, when DDR parameters fail to function correctly, adjustments may be required from a large pool of parameters, with little guidance provided during the debugging process, leading to uncertainty. Moreover, the dependencies between parameters in DDR are difficult to uncover, especially since most PHY parameters lack publicly available information, creating blind spots in the debugging process. Based on this, the DDR parameter evaluation model construction method, apparatus, and server provided in this invention can specifically identify potential inconsistencies in a timing sequence, rank these sequences by their degree of inconsistency, and provide guidance on debugging parameters. This reduces reliance on experienced DDR personnel and can extract the correlation between CTRL / PHY parameters, thereby significantly improving the efficiency of DDR parameter evaluation.

[0028] See Figure 1 The diagram shows a flowchart of a method for constructing a DDR parameter evaluation model. The method mainly includes the following steps S102 to S108:

[0029] Step S102: Obtain the timing parameter set in the DDR module of the chip. The timing parameter set includes explicit timing parameters and implicit timing parameters. DDR stands for Double Data Rate Synchronous Dynamic Random Access Memory, a type of memory access medium commonly used in PCs or mobile devices. DDR has many timing parameters that need to be adjusted to ensure the normal operation of the module. You can think of DDR as the memory stick of a computer or mobile phone. It has many timing parameters (like the interval of traffic lights). These parameters must be adjusted just right for the system to run stably. In chip design, DDR parameters are used to determine the performance, stability, and compatibility of the memory. Therefore, evaluating DDR parameters using a deep learning network model with gradient descent algorithm as the core can assist in the verification work, provide data on the relationship between DDR parameters, and reduce the difficulty of DDR parameter debugging.

[0030] In one implementation, to improve the generalization performance of the model, a large amount of training data required for the deep learning task is prepared. The model training data needs to take into account the manufacturer, type, timing and other information of different DDRs. The data is mainly based on the DDR parameters that can be verified by the EVB board in the chip project. The data is mainly divided into two parts: CTRL (i.e., explicit timing parameters) and PHY (i.e., implicit timing parameters). The CTRL parameters include initialization timing, DFI timing, self-refresh timing, ZQ calibration timing and other parameters, as well as the corresponding control signal timing, function control input, etc. At the same time, in order to meet the parsing of the timing information of the MR register, the timing parameters of the MR0 to MR6 registers configured in the PHY module are also considered as CTRL module parameters. The PHY module parameters are provided by the DDR manufacturer, and no further data collection is required except for the MR register.

[0031] Step S104: Encode the explicit and implicit time-series parameters respectively to obtain the target training data set. In one embodiment, the main purpose of the encoding process is to unify the dimensions of the explicit and implicit time-series parameters by encoding, since the explicit and implicit time-series parameters have different dimensions, and the input training data should be data of the same dimension when training the model. This prepares for further model training.

[0032] Step S106: The target training data set is processed by vector feature encoding through a deep learning network based on attention mechanism and CNN network for dual-stream feature extraction, resulting in a feature encoding vector. Through vector feature encoding, the collected data can conform to the input format of the deep learning network, thus obtaining the feature encoding vector. Deep learning network is a commonly used core method in the field of artificial intelligence. It mainly implements its working mechanism in a computer by simulating the working mechanism of biological neurons. It has the method of extracting high-dimensional information from data and can perform inference and prediction through the extracted feature information. Many neurons can be combined in various forms to form different neural network modules, and many modules can form a deep learning network.

[0033] In one implementation, a deep learning network (DDRT) based on dual-stream feature extraction using a transformer network (i.e., a deep learning network based on an attention mechanism) and a CNN network is structured into two parts: an encoder and a decoder. 1. Due to the relatively small number of parameters in the DDR CTRL module, a feature extraction network encoder is designed based on the transformer module to obtain its strong feature information. Considering that the DDR PHY module has a large number of implicit parameters, a two-dimensional CNN convolutional kernel network encoder capable of acquiring global parameter features is designed. 2. Based on the feature value output of this dual-stream network encoder, a fully connected network decoder is also designed. The decoder outputs the confidence score and the top 30 rankings of parameter unreasonableness for the current input parameters.

[0034] Step S108: Input the feature encoding vector into the deep learning network for model training to obtain the DDR parameter evaluation model. The DDR parameter evaluation model is used to evaluate the DDR parameters of the chip. In one embodiment, the feature encoding vector is input into the deep learning network for model training. At the beginning of training, the learning rate of the model training is increased by a warm-up algorithm. When the learning rate reaches a preset learning rate threshold, the learning rate is reduced by an annealing algorithm to iteratively train the feature encoding vector. When the preset number of iterations is reached, the DDR parameter evaluation model is output.

[0035] In practical applications, training can be performed based on the collected data and the deep learning network (DDRT). The training data is based on a 1:1 ratio of passable and failable data from the EVB board test. This design mainly addresses the data bias problem encountered during deep learning network training. The training optimizer uses the Adam algorithm (i.e., gradient descent algorithm, which automatically adjusts the learning speed based on the historical performance of each parameter), and the learning rate uses the warmup algorithm (i.e., a warm-up algorithm used to gradually increase the model's learning rate until the model stabilizes before training at normal speed). Initially, the learning rate increases from 0 to 10e-3, and then the cosine annealing algorithm is used to reduce the learning rate. A total of 200,000 iterations are performed on the data. In addition, considering that there are no similar neural network models for the previous task and no usable pre-trained models, the parameters in the network are initialized using the Kaiming parameter initialization algorithm to accelerate model training convergence. The final trained neural network model can be directly used as the DDR parameter evaluation model. Furthermore, sample data that can still pass the test after deliberate perturbation can be added to the training set of the DDR parameter evaluation model to prevent model overfitting.

[0036] The method for constructing the DDR parameter evaluation model provided in this embodiment of the invention can significantly improve the evaluation efficiency and accuracy of DDR parameters.

[0037] This invention also provides an implementation method for parameter collection encoding, as detailed in (A) to (B) below:

[0038] (A) The time series parameter set is processed by an automated script to perform data annotation and adjustment to obtain the training data set, as detailed in (1) to (2) below:

[0039] (1) Obtain the memory clock cycle range of the timing parameter set, and perform read and write tests on the timing parameter set based on the memory clock cycle range. Mark the reasonable timing parameters that pass the read and write tests and the unreasonable timing parameters that fail the read and write tests. In one implementation, in order to reduce the huge workload of manually marking data, first configure a set of parameters that can pass the read and write tests on any type of DDRCTRL, PHY, and chip model. At the same time, based on these parameters, use an automated script to fine-tune the timing parameters in CTRL and PHY. For example, set the read latency timing in MR0 from 6 mem clk to 18 mem clk. The target read latency that can be run is 12 mem clk. Under this setting, 13 sets of training data can be obtained. The data includes 4 sets of data that can pass the test and 9 sets of data that fail the read and write tests. Similarly, other parameters are arranged and combined in a similar manner, and the parameters are marked as running or not. Here, mem clk is the memory clock cycle, which is the basic time unit of DDR memory operation.

[0040] (2) Parameter adjustment processing is performed on the labeled parameters, and data expansion processing is performed based on the number of explicit timing parameters in the adjusted parameters and the memory clock cycle corresponding to each explicit timing parameter to obtain the training data set. In addition, deviation estimation processing can be performed on unreasonable timing parameters, and parameter adjustment processing can be performed based on the deviation estimation results to make the ratio of reasonable timing parameters to unreasonable timing parameters the same. In one implementation, deviation estimation is performed on timing names that deviate from the appropriate value. The larger the deviation value, the higher the unreasonableness. All of the above can be implemented automatically. Here, we consider that the adjustable mem clk range for each timing parameter is N, and the timing parameter in CTRL is M, then we can take For the quantity parameter, as a reference, this system sets M to 110 and N to an average of 8. Under these conditions, the amount of training data required for deep learning can be fully met. The final obtained data is controlled at a 1:1 ratio based on the pass and fail data ratio.

[0041] (B) Encode the explicit and implicit time-series parameters in the training dataset respectively, unify the dimensions of the explicit and implicit time-series parameters, and obtain the target training dataset. In one implementation, the first and second vector dimensions corresponding to the explicit and implicit time-series parameters, as well as the memory clock cycle corresponding to each parameter, can be obtained respectively. Then, the first and second vector dimensions are used to encode the explicit and implicit time-series parameters, and the encoded parameters are normalized based on the memory clock cycle to obtain the target training dataset. See (3) to (4) below for details:

[0042] (3) The data collected in the training dataset is encoded in the form of parameter vectors. Each DDR parameter can be encoded as a 150-dimensional (i.e., the first vector dimension of the corresponding explicit timing parameter) one-dimensional vector. The one-hot position of the parameter contains its corresponding parameter value. This value is normalized in MEM CLK units. The corresponding function setting parameters are marked with discrete values. The following formula is the vector after normalization of the MR0 register read delay timing parameter. Except for the 0.12 value, the rest are 149 zero values.

[0043]

[0044] (4) For PHY module parameters, considering that there are many implicit parameters without clear meaning, the vector of PHY parameters is set to a 20-dimensional vector (that is, the second vector dimension corresponding to the implicit timing parameters). The value of the 0th dimension of the vector is the normalized value of the parameter. The values ​​of the last 19 dimensions are marked with the value 1 from dimension 1 to dimension 20, and this process is repeated. This marking process mainly records the positional relationship between implicit parameters.

[0045] See Figure 2 The flowchart of a feature extraction method for DDR parameters is shown. The dual-stream network for DDR parameter feature extraction is divided into an encoder and a decoder. The encoder uses a transformer network module and a CNN network module. The outputs of the two are connected by a cat operation and then input to the decoder. The decoder is composed of a convolutional kernel and a fully connected neural network. The present invention also provides an implementation method for extracting feature encoding vectors. See (1) to (3) below for details:

[0046] (1) The explicit temporal parameters in the target training dataset are encoded using a deep learning network based on an attention mechanism to obtain a first encoding result. In one implementation, see [link to implementation details]. Figure 3 The diagram illustrates an explicit temporal parameter encoding method, showing the transformer's encoding of CTRL module parameters and the form of the input-output matrix. The transformer encoder network is implemented based on an attention mechanism. The input parameter vector matrix Mat1 is transformed to obtain a new parameter vector matrix Mat2. The encoder can receive 150 parameter vectors at a time, which form the parameter matrix. The Mat1 matrix is ​​first processed by the network's parameter matrices WK, WQ, and WV in parallel, and then undergoes another self-attention calculation. The dimensions of these three matrices are 150×150. Due to attention... The on mechanism allows each parameter vector in the first layer of the transformer to perform an inner product operation with other parameter vectors. Therefore, the trained Mat2 matrix contains a wealth of information about the correlation between parameters. Specifically, positions with larger values ​​in the matrix indicate a higher degree of correlation between parameters. This matrix can also be used as an important basis for adjusting DDR parameters. Furthermore, the transformer encoder has four layers with an attention head set to 1. After passing through the encoder, a 150×150 matrix is ​​obtained, which serves as the feature value output of the transformer network encoder. The transformation model of the parameter vector matrix Mat1 is as follows:

[0047]

[0048] (2) The latent temporal parameters in the target training dataset are encoded using a deep learning network that extracts dual-stream features through a CNN network to obtain a second encoding result. In one implementation, see [link to implementation details]. Figure 4 The diagram illustrates an implicit temporal parameter encoding process, showing the extraction and encoding flow of PHY module parameters by a CNN network, as well as the output matrix form. For a CNN network extracting DDR PHY module parameters, its network input is a parameter matrix of the convolution kernel input size. The number of parameters is consistent with the number of parameters in the PHY, and the form is similar to the CTRL parameter matrix. The first layer of the network uses two-dimensional dilated convolution kernels of sizes 5×20, 7×20, and 9×20 to extract parameter information, for a total of 150 convolution kernels, resulting in an N×150 three-dimensional matrix, where N is determined by the specific number of PHY parameters. The second layer uses ordinary two-dimensional convolution kernels to perform feature extraction again, and after max pooling, a 150×1 CNN network encoder feature output is obtained.

[0049] (3) The first and second encoding results are decoded using a fully connected neural network to obtain the feature encoding vector. In one embodiment, the decoder can perform a cat operation on the outputs of the two encoders to obtain a 150×151 parameter matrix. The decoder first calculates the matrix using 151 one-dimensional convolution kernels, and then performs max_pooling to obtain a 150×1 matrix. At the same time, it connects to an output layer with 31 neurons to form a fully connected neural network. The first meaning of the output of the 31 network layers is the rationality of the DDR parameters, and the remaining 30 are the positions of unreasonable parameter values. Furthermore, before giving guidance on debugging parameters based on rationality, it is also necessary to automatically check whether the JEDEC upper or lower limit is violated to prevent the chip from burning out.

[0050] In summary, this invention can specifically identify potential irrationalities in a given timing sequence, rank these sequences by their degree of irrationality, provide guidance on debugging parameters, reduce reliance on experienced DDR personnel, and extract the correlation between CTRL / PHY parameters, thereby significantly improving the efficiency of DDR parameter evaluation. In other words, it: 1. Can be adjusted without relying on human experience; 2. Automatically identifies problematic parameters; 3. Lowers the threshold for parameter evaluation; 4. Performs parameter correlation analysis on PHY parameters not disclosed by the manufacturer.

[0051] Regarding the method for constructing the DDR parameter evaluation model provided in the foregoing embodiments, this embodiment of the invention provides an apparatus for constructing the DDR parameter evaluation model, see [link to relevant documentation]. Figure 5 The diagram shows a structural schematic of a device for constructing a DDR parameter evaluation model. The device includes the following parts:

[0052] The parameter acquisition module 502 acquires the timing parameter set in the chip's DDR module, wherein the timing parameter set includes: explicit timing parameters and implicit timing parameters;

[0053] The parameter encoding module 504 encodes the explicit and implicit time-series parameters respectively to obtain the target training data set.

[0054] The feature extraction module 506 performs vector feature encoding on the target training data set through a deep learning network based on attention mechanism and CNN network for dual-stream feature extraction, and obtains the feature encoding vector.

[0055] The model training module 508 inputs the feature encoding vector into the deep learning network for model training to obtain the DDR parameter evaluation model, which is used to evaluate the DDR parameters of the chip.

[0056] The apparatus for constructing the DDR parameter evaluation model provided in this application embodiment can significantly improve the evaluation efficiency and accuracy of DDR parameters.

[0057] In one embodiment, when performing the step of encoding explicit and implicit time-series parameters separately to obtain the target training data set, the parameter encoding module 504 is further configured to: perform data annotation and adjustment processing on the time-series parameter set through an automated script to obtain the training data set; and encode the explicit and implicit time-series parameters in the training data set separately to unify the dimensions of the explicit and implicit time-series parameters to obtain the target training data set.

[0058] In one embodiment, when performing the step of data annotation and adjustment processing of the timing parameter set through automated scripts to obtain the training data set, the parameter encoding module 504 is further configured to: obtain the memory clock cycle range of the timing parameter set, and perform read / write test processing on the timing parameter set based on the memory clock cycle range, annotating reasonable timing parameters that pass the read / write test and unreasonable timing parameters that fail the read / write test; perform parameter adjustment processing on the annotated parameters, and perform data expansion processing based on the number of explicit timing parameters in the adjusted parameters and the memory clock cycle corresponding to each explicit timing parameter to obtain the training data set.

[0059] In one embodiment, when performing the parameter adjustment process for the labeled parameters, the parameter encoding module 504 is further used to: perform deviation estimation processing for unreasonable time series parameters, and perform parameter adjustment processing based on the deviation estimation results, so that the ratio of reasonable time series parameters to unreasonable time series parameters is the same.

[0060] In one embodiment, when performing the steps of encoding the explicit and implicit time-series parameters in the training dataset separately, unifying the dimensions of the explicit and implicit time-series parameters, and obtaining the target training dataset, the parameter encoding module 504 is further configured to: obtain the first vector dimension and the second vector dimension corresponding to the explicit and implicit time-series parameters, and the memory clock cycle corresponding to each parameter; perform parameter vector encoding on the explicit and implicit time-series parameters using the first vector dimension and the second vector dimension respectively, and normalize the encoded parameters based on the memory clock cycle to obtain the target training dataset.

[0061] In one embodiment, when performing vector feature encoding on the target training dataset using a deep learning network that extracts features through a dual-stream feature extraction mechanism based on an attention-based deep learning network and a CNN network, to obtain a feature encoding vector, the feature extraction module 506 is further configured to: encode explicit temporal parameters in the target training dataset using an attention-based deep learning network to obtain a first encoding result; encode implicit temporal parameters in the target training dataset using a deep learning network that extracts features through a dual-stream feature extraction mechanism based on a CNN network to obtain a second encoding result; and decode the first encoding result and the second encoding result using a fully connected neural network to obtain a feature encoding vector.

[0062] In one embodiment, when performing the step of inputting the feature encoding vector into the deep learning network for model training to obtain the DDR parameter evaluation model, the model training module 508 is further configured to: input the feature encoding vector into the deep learning network for model training; at the beginning of training, increase the learning rate of the model training through a warm-up algorithm; when the learning rate reaches a preset learning rate threshold, decrease the learning rate through an annealing algorithm to iteratively train the feature encoding vector; and when a preset number of iterations is reached, output the DDR parameter evaluation model.

[0063] The device provided in this embodiment of the invention has the same implementation principle and technical effect as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the device embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0064] This invention provides a server, specifically, the server includes a processor and a storage device; the storage device stores a computer program, which, when run by the processor, executes the method described in any of the above embodiments.

[0065] Figure 6This is a schematic diagram of the structure of a server provided in an embodiment of the present invention. The server 100 includes: a processor 60, a memory 61, a bus 62, and a communication interface 63. The processor 60, the communication interface 63, and the memory 61 are connected through the bus 62. The processor 60 is used to execute executable modules, such as computer programs, stored in the memory 61.

[0066] The memory 61 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 63 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc.

[0067] Bus 62 can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 6 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0068] The memory 61 is used to store programs. After receiving an execution instruction, the processor 60 executes the program. The method executed by the device for defining the flow process disclosed in any of the foregoing embodiments of the present invention can be applied to the processor 60 or implemented by the processor 60.

[0069] Processor 60 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 60 or by instructions in software form. Processor 60 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 61. Processor 60 reads the information in memory 61 and, in conjunction with its hardware, completes the steps of the above method.

[0070] The computer program product of the readable storage medium provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods described in the foregoing method embodiments. For specific implementation, please refer to the foregoing method embodiments, which will not be repeated here.

[0071] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0072] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for constructing a DDR parameter evaluation model, characterized in that, The method includes: Obtain the timing parameter set in the DDR module of the chip, wherein the timing parameter set includes: explicit timing parameters and implicit timing parameters; The explicit and implicit time-series parameters are encoded separately to obtain the target training data set; The target training dataset is processed by a deep learning network that uses a deep learning network based on an attention mechanism and a CNN network for dual-stream feature extraction to obtain a feature encoding vector. The feature encoding vector is input into a deep learning network for model training to obtain a DDR parameter evaluation model, wherein the DDR parameter evaluation model is used to evaluate the DDR parameters of the chip; The step of encoding the explicit and implicit time-series parameters to obtain the target training data set includes: performing data annotation and adjustment processing on the time-series parameter set using an automated script to obtain a training data set; encoding the explicit and implicit time-series parameters in the training data set to unify the dimensions of the explicit and implicit time-series parameters to obtain the target training data set. The step of encoding the explicit and implicit time-series parameters in the training dataset to unify their dimensions and obtain the target training dataset includes: obtaining the first and second vector dimensions corresponding to the explicit and implicit time-series parameters, as well as the memory clock cycle corresponding to each parameter; using the first and second vector dimensions to perform parameter vector encoding on the explicit and implicit time-series parameters, and normalizing the encoded parameters based on the memory clock cycle to obtain the target training dataset. The steps of encoding explicit and implicit temporal parameters using the first and second vector dimensions respectively include: encoding the data collected in the training dataset in the form of parameter vectors, encoding each explicit temporal parameter into a 150-dimensional one-dimensional vector, with the parameter value normalized in MEM CLK units at the one-hot position corresponding to the parameter; encoding the implicit temporal parameters into 20-dimensional vectors, with the 0th dimension value being the normalized parameter value, and the 1st to 19th dimension values ​​being sequentially labeled with the value 1, and then cycling sequentially to record the positional relationship between the implicit temporal parameters; The step of performing vector feature encoding processing on the target training data set using a deep learning network with attention-based deep learning network and CNN network for dual-stream feature extraction to obtain a feature encoding vector includes: encoding explicit temporal parameters in the target training data set using a deep learning network with attention-based deep learning network to obtain a first encoding result; encoding implicit temporal parameters in the target training data set using a deep learning network with CNN network for dual-stream feature extraction to obtain a second encoding result; and decoding the first encoding result and the second encoding result using a fully connected neural network to obtain the feature encoding vector.

2. The method according to claim 1, characterized in that, The step of using automated scripts to perform data annotation and adjustment on the time series parameter set to obtain the training data set includes: Obtain the memory clock cycle range of the timing parameter set, and perform read and write tests on the timing parameter set based on the memory clock cycle range, marking reasonable timing parameters that pass the read and write tests and unreasonable timing parameters that fail the read and write tests; The labeled parameters are adjusted, and data expansion is performed based on the number of explicit timing parameters in the adjusted parameters and the memory clock cycle corresponding to each explicit timing parameter to obtain the training data set.

3. The method according to claim 2, characterized in that, The steps for adjusting the labeled parameters include: Deviation estimation processing is performed on the unreasonable time series parameters, and parameter adjustment processing is performed based on the deviation estimation results to make the ratio of the number of reasonable time series parameters to the number of unreasonable time series parameters the same.

4. The method according to claim 1, characterized in that, The step of inputting the feature encoding vector into a deep learning network for model training to obtain the DDR parameter evaluation model includes: The feature encoding vector is input into a deep learning network for model training. At the beginning of training, a warm-up algorithm is used to increase the learning rate of the model training. When the learning rate reaches a preset learning rate threshold, an annealing algorithm is used to reduce the learning rate to iteratively train the feature encoding vector. When the preset number of iterations is reached, the DDR parameter evaluation model is output.

5. An apparatus for constructing a DDR parameter evaluation model, characterized in that, The device includes: The parameter acquisition module acquires a set of timing parameters in the DDR module of the chip, wherein the set of timing parameters includes: explicit timing parameters and implicit timing parameters; The parameter encoding module encodes the explicit and implicit time-series parameters respectively to obtain the target training data set. The feature extraction module performs vector feature encoding processing on the target training dataset through a deep learning network that uses a deep learning network based on an attention mechanism and a CNN network for dual-stream feature extraction, to obtain a feature encoding vector. The model training module inputs the feature encoding vector into a deep learning network for model training to obtain a DDR parameter evaluation model, wherein the DDR parameter evaluation model is used to evaluate the DDR parameters of the chip; The step of encoding the explicit and implicit time-series parameters to obtain the target training data set includes: performing data annotation and adjustment processing on the time-series parameter set using an automated script to obtain a training data set; encoding the explicit and implicit time-series parameters in the training data set to unify the dimensions of the explicit and implicit time-series parameters to obtain the target training data set. The step of encoding the explicit and implicit time-series parameters in the training dataset to unify their dimensions and obtain the target training dataset includes: obtaining the first and second vector dimensions corresponding to the explicit and implicit time-series parameters, as well as the memory clock cycle corresponding to each parameter; using the first and second vector dimensions to perform parameter vector encoding on the explicit and implicit time-series parameters, and normalizing the encoded parameters based on the memory clock cycle to obtain the target training dataset. The steps of encoding explicit and implicit temporal parameters using the first and second vector dimensions respectively include: encoding the data collected in the training dataset in the form of parameter vectors, encoding each explicit temporal parameter into a 150-dimensional one-dimensional vector, with the parameter value normalized in MEM CLK units at the one-hot position corresponding to the parameter; encoding the implicit temporal parameters into 20-dimensional vectors, with the 0th dimension value being the normalized parameter value, and the 1st to 19th dimension values ​​being sequentially labeled with the value 1, and then cycling sequentially to record the positional relationship between the implicit temporal parameters; The step of performing vector feature encoding processing on the target training data set using a deep learning network with attention-based deep learning network and CNN network for dual-stream feature extraction to obtain a feature encoding vector includes: encoding explicit temporal parameters in the target training data set using a deep learning network with attention-based deep learning network to obtain a first encoding result; encoding implicit temporal parameters in the target training data set using a deep learning network with CNN network for dual-stream feature extraction to obtain a second encoding result; and decoding the first encoding result and the second encoding result using a fully connected neural network to obtain the feature encoding vector.

6. A server, characterized in that, The method includes a processor and a memory, the memory storing computer-executable instructions executable by the processor, the processor executing the computer-executable instructions to implement the method of any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions that, when invoked and executed by a processor, cause the processor to perform the method described in any one of claims 1 to 4.

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