Rag-based few-sample processor design ppa prediction method

Abstract

The application discloses a kind of based on RAG's few-sample processor design PPA prediction method.The technical scheme is: the processor design paradigm, EDA tool module, RAG module, the input module of processor design to be measured and PPA prediction module are formed based on RAG's few-sample processor design PPA prediction system.RAG module carries out sampling to the design space of processor design paradigm, obtains processor design sample, the feature vector coding of sample, utilizes EDA tool module to obtain the PPA value of design sample, constructs the knowledge base required for PPA prediction;RAG module detects the knowledge matched with the processor design code of the PPA value to be predicted in knowledge base, generates prompt word based on the matched knowledge.PPA prediction module and prompt word interaction, obtain the PPA prediction value of the PPA value processor design to be predicted.The application can be based on a few samples to carry out accurate PPA prediction, shortens design cycle.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip design, and in particular to a method for quickly predicting specific PPA indicators involved in any chip design in the design space under the condition of a small number of chip design samples containing PPA (Performance, Power and Area) information. BACKGROUND

[0002] Currently, in actual chip design production, the front-end design of a processor is mainly based on hardware description language (HDL) for design. The processor design mode based on HDL has been very reliable after a long period of development. And with the emergence of HDL with higher abstraction level and higher degree of parameterization (for example, Chisel proposed by J. Bachrach et al. in the paper “Chisel: constructing hardware in a scala embedded language” published in Design Automation Conference (DAC) in 2012), the processor design paradigm implemented based on such language (for example, Rocket Chip Core and Rocket Chip BOOM processor design template proposed by Krste Neculae et al. in the technical report “The rocket chip generator” published by the University of California, Berkeley, Electrical Engineering & Computer Sciences (EECS)) has the characteristics of modularity and high degree of parameterization. The processor design paradigm is composed of several modules, such as core module, instruction cache module, data cache module, branch prediction module, etc., each module has several configurable parameters, and the combination of all the configurable parameters of all modules is called the feature vector of the processor design paradigm, and all feasible values of the feature vector of the processor design paradigm are called the design space of the processor design paradigm. After configuring the values of the configurable parameters in the processor design paradigm as the values of the corresponding elements in the feature vector, the processor design under the configuration of the feature vector is obtained, and the processor design paradigm will automatically generate the verilog source code of the corresponding processor design. Therefore, the processor design based on the processor design paradigm can be represented by the corresponding feature vector.

[0003] In the processor design process based on the processor design paradigm, the PPA index of the processor is an important index to evaluate the pros and cons of the design. Generally, the PPA index of the processor design under different feature vectors is obtained through the logic synthesis link, however, the logic synthesis link is time-consuming, and generally one round of logic synthesis link takes several to tens of hours, which leads to slow iteration optimization process for PPA index in the processor design process based on the processor design paradigm. In order to save time, the PPA prediction method is generally used to predict the PPA index of the processor design under different feature vectors in the existing chip design process, instead of actually obtaining the PPA index through the logic synthesis link and repeatedly iterating and optimizing. The existing PPA prediction method is generally based on a regression model (for example, the paper "Rapid and Accurate PPA Prediction for the Template-Based Processor Design Methods" published by Tang, M, et al. in SCI Journal Applied Sciences), and the regression model must be trained to achieve a certain prediction accuracy, so design samples with PPA labels are needed to train the regression model, and these samples need to obtain PPA labels through the logic synthesis link. Therefore, the more the number of design samples with PPA labels needed to train the regression model in the PPA prediction method, the higher the time cost of prediction. At present, the PPA prediction method still needs to collect 1% to 5% of the design samples with PPA labels in the design space as the training data set, which has a high time cost, for example, in the paper "Rapid and Accurate PPA Prediction for the Template-Based Processor Design Methods", PPA prediction is performed on a simple sequential execution processor design template in Rocket Chip Core. There are 3981312 legal designs in the design space of Rocket Chip Core, and the method in the paper needs to collect 134 samples, that is, 3.42% of the samples in the design space, and the time cost of obtaining the PPA of 134 samples through logic simulation is about 400 hours. Therefore, how to further reduce the time cost of predicting the PPA index of the processor design is a technical problem that technicians in the field are extremely concerned about.

[0004] With the rapid development of large language models in artificial intelligence technology, existing large language models have strong analysis and reasoning capabilities. At the same time, existing high-performance large language models have learned rich processor architecture knowledge in the training process (for example, Blocklove, Jason et al. in 2023 ACM / IEEE 5th Workshop on Machine Learning for CAD (MLCAD) conference published the paper “Chip-Chat: Challenges and Opportunities in Conversational Hardware Design” (translated as “Chip-Chat: Challenges and Opportunities in Conversational Hardware Design”), which uses a large language model GPT4.0 to directly complete the design of a five-stage pipeline processor, and Tang, M et al. in 2025 CCF-B class journal ACM Transactions on Design Automation of Electronic Systems published the paper “ChatDSE: A Zero-Shot Microarchitecture Design Space Explorer Powered by GPT4.0” (translated as “ChatDSE: A Zero-Shot Microarchitecture Design Space Explorer Powered by GPT4.0”), which uses a large language model GPT4.0 to directly implement the design space exploration of Rocket Chip BOOM processor design template). Therefore, using the analysis and reasoning capabilities of existing high-performance large language models and the rich processor architecture knowledge contained in them in various aspects of processor design has become one of the directions explored by those skilled in the art (for example, Wu, H et al. in 2024 CCF-A class journal IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems published the paper “ChatEDA: A Large Language Model Powered Autonomous Agent for EDA” (translated as “ChatEDA: A Large Language Model Powered Autonomous Agent for EDA”), which uses a large language model for electronic design automation in processor design).

[0005] ChatEDA:A Large Language Model Powered Autonomous Agent for EDA adopts the fine-tuning strategy to apply the large language model to the processor design electronic design automation. The fine-tuning strategy is to train the large language model by constructing a training data set, and to optimize and adjust the parameters of the large language model so that the large language model can output correct answers. When the fine-tuning strategy is used to apply the large language model to a specific field, a data set of the specific field is first needed to be constructed, and the large language model is trained using the data set to adjust the parameters of the large language model. Therefore, when the fine-tuning strategy is used to apply the large language model to a specific field, the accuracy of the answer of the large language model to the specific field is high, but the application cost is high, and the generalization ability of the model decreases. The retrieval augmented generation (RAG) strategy combines information retrieval (such as vector database) with the large language model to retrieve relevant knowledge from the external knowledge base in real time to generate the corresponding context-based prompt words to guide the large language model to make accurate answers. The RAG strategy for applying the large language model needs to construct an application domain knowledge base (such as a vector database), a matching algorithm, and a prompt word generation method, does not need to fine-tune the large language model, has low application cost, and has high answer accuracy due to the knowledge base.

[0006] Currently, in the application of large language models in specific fields such as code summarization (e.g., Wang, Y, et al. 2023. CodeT5+: Open Code Large Language Models for Code Understanding and Generation. In Proceedings of the 2023 Conference on Empirical Methods in Natural Language Processing) and medical biology (e.g., Zhou, Z, et al. 2024. IHILLM-RAG: A safe and private medical large language model based on intelligent hardware interaction and retrieval-augmented generation (RAG). In Fourth International Computational Imaging Conference (CITA 2024)), RAG can efficiently integrate knowledge in specific fields with large language models, improving the performance of large language models in specific field applications. However, there is no public report on the application of RAG in processor design, and there is no public literature related to the technology of predicting PPA in the processor design process based on RAG. SUMMARY

[0007] The technical problem to be solved by the present application is how to obtain PPA indicators of different processor designs with low time cost based on the processor design paradigm, and to provide a few-sample processor design PPA prediction method based on RAG. The present application can accurately predict the PPA of different designs in the processor design process based on the processor design paradigm based on a small amount of design samples with PPA labels, reduce the time overhead of the iterative optimization process for PPA indicators in the processor design process, and shorten the cycle of processor design.

[0008] The technical scheme of the application is: first, a RAG-based few-sample processor design PPA prediction system is constructed, which is composed of a processor design paradigm, an EDA tool module, a RAG module, a processor design under test input module, and a PPA prediction module. The RAG module includes a knowledge base construction submodule, a retrieval matching submodule, and a prompt word generation submodule. The knowledge base construction submodule in the RAG module samples the design space of the processor design paradigm, obtains a plurality of processor design samples, encodes the feature vectors of the processor design samples to obtain the encoding of the feature vectors, and finally uses the simulation and synthesis tools in the EDA tool module to obtain the PPA values of the processor design samples to construct the knowledge base required for PPA prediction. The processor design under test input module receives the processor design feature vector of the PPA value to be predicted input by the designer and sends it to the retrieval matching submodule in the RAG module; the retrieval matching submodule in the RAG module receives the processor design feature vector of the PPA value to be predicted, detects the knowledge matched with the processor design encoding of the PPA value to be predicted in the knowledge base. The prompt word generation submodule in the RAG module generates prompt words for interaction with the PPA prediction module based on the matched knowledge obtained from the retrieval matching submodule. The PPA prediction module is a large language model, and the PPA prediction module obtains the PPA prediction value of the processor design of the PPA value to be predicted by interacting with the prompt words generated by the prompt word generation submodule.

[0009] The application comprises the following steps:

[0010] First, a RAG-based few-sample processor design PPA prediction system is constructed. The RAG-based few-sample processor design PPA prediction system is composed of a processor design paradigm, an EDA tool module, a RAG module, a processor design under test input module, and a PPA prediction module. The RAG module includes a knowledge base construction submodule, a retrieval matching submodule, and a prompt word generation submodule.

[0011] The processor design under test input module is connected to the retrieval matching submodule in the RAG module, receives the processor design feature vector of the PPA value to be predicted input by the designer, and sends the processor design feature vector of the PPA value to be predicted to the retrieval matching submodule in the RAG module.

[0012] The RAG module is connected to the processor design paradigm, the EDA tool module, the processor design under test input module, and the PPA prediction module.

[0013] The knowledge base construction submodule in the RAG module is connected with the processor design paradigm, the EDA tool module, and the retrieval matching submodule. The knowledge base construction submodule samples the design space of the processing design paradigm to obtain a plurality of feature vectors (length N, N is the number of configurable parameters (such as the number of channels of the cache (Cache), the block size, and other parameters) in the processor design paradigm) of the processor design paradigm, encodes the feature vectors of the processor design paradigm to obtain the encoding of the feature vectors, and sends the processor design under the configuration of the feature vectors of the processor design paradigm to the EDA tool module. The knowledge base construction submodule receives the PPA indicators (i.e., performance, power consumption, and area evaluation) of the processor design under the configuration of the feature vectors from the EDA tool module, and constructs a five-tuple of the feature vectors of the processor design paradigm, the encoding of the feature vectors, the performance, the power consumption, and the area evaluation in the PPA indicators of the processor design under the configuration of the feature vectors as a piece of knowledge to build a knowledge base for retrieval matching by the retrieval matching submodule.

[0014] The retrieval matching submodule is connected with the knowledge base construction submodule, the prompt word generation submodule, and the input module of the processor design to be tested. The retrieval matching submodule receives the processor design feature vector of the PPA value to be predicted from the input module of the processor design to be tested, encodes the processor design feature vector of the PPA value to be predicted to obtain the encoding of the processor design feature vector of the PPA value to be predicted, and performs retrieval matching in the knowledge base according to the Euclidean distance between the encoding of the feature vector of all knowledge in the knowledge base and the encoding of the processor design feature vector of the PPA value to be predicted. The knowledge obtained by retrieval matching and the processor design feature vector of the PPA value to be predicted are sent to the prompt word generation submodule.

[0015] The prompt word generation submodule is connected with the retrieval matching submodule and the PPA prediction module. The knowledge obtained by retrieval matching and the processor design feature vector of the PPA value to be predicted are received from the retrieval matching submodule, the PPA prediction prompt word corresponding to the processor design feature vector of the PPA value to be predicted is generated according to the knowledge obtained by retrieval matching, and the PPA prediction prompt word corresponding to the processor design feature vector of the PPA value to be predicted is sent to the PPA prediction module.

[0016] The EDA tool module is composed of simulation tools (such as Verilator 4.218 and above, ModelSim 2022.2 and above, etc.), synthesis tools (such as open source tools YoSys 0.33 and above, commercial tools Design Compiler 2016 and above, etc.), and is connected to the knowledge base construction submodule in the RAG module. The EDA tool module receives the processor design under the feature vector configuration of the processor design paradigm from the knowledge base construction submodule, simulates the processor design under the feature vector configuration of the processor design paradigm using the simulation tool, obtains the performance evaluation, and synthesizes the processor design under the feature vector configuration of the processor design paradigm using the synthesis tool, and obtains the power consumption and area evaluation. The PPA index, i.e., the performance, power consumption, and area evaluation, is sent to the knowledge base construction submodule.

[0017] The PPA prediction module is a large language model with processor architecture knowledge and strong reasoning ability, such as GPT4.0, DeepSeek, Qwen-72B, etc. It is connected to the prompt word generation submodule in the RAG module. The PPA prediction module receives the PPA prediction prompt word corresponding to the processor design feature vector to be predicted from the prompt word generation submodule, and generates a PPA prediction result according to the PPA prediction prompt word corresponding to the processor design feature vector to be predicted.

[0018] Secondly, the knowledge base construction submodule samples the design space of the processor design paradigm and constructs a knowledge base for retrieval matching submodule retrieval. The method is:

[0019] 2.1 The processor design paradigm is composed of M modules, M is a positive integer, and the configurable parameter combinations of each module form a feature vector with a length of N, N is the number of configurable parameters in the processor design paradigm. The knowledge base construction submodule samples the design space of the processor design paradigm to obtain V feature vectors F1, F2, …, FV of the processor design paradigm. v ,…,F V , V is a positive integer, 1≤v≤V, where F v =(p v1 ,p v2 ,…,p vn ,…,p vN ), 1≤n≤N, p v1 ,p v2 ,…,p vn ,…,p vN respectively represent the values of the 1st to Nth parameters of the processor design under the vth feature vector configuration. The sampling method is:

[0020] 2.1.1 The knowledge base construction submodule puts all the feature vectors (a total of K feature vectors) in the design space of the processor design paradigm into the feature vector set DS, encodes all the feature vectors in DS to obtain the corresponding encoding vectors, and puts these encoding vectors into the feature vector encoding vector set CS. The method is as follows:

[0021] 2.1.1.1 Initialize m = 1.

[0022] 2.1.1.2 List all feasible value combinations of the configurable parameters of the mth module in the processor design paradigm, and record all the feasible value combinations as encodings, i.e., 1, 2, 3, …, Code m , where Code m is the number of all feasible combinations of the configurable parameters in the mth module.

[0023] 2.1.1.3 Let m = m + 1. If m > M, it means that all feasible value combinations of the configurable parameters of the M modules of the processor paradigm have been recorded as corresponding encodings, and go to 2.1.1.4. If m < M, go to 2.1.1.2 to continue recording all feasible combinations of the configurable parameters of other modules in the processor paradigm as corresponding encodings.

[0024] 2.1.1.4 Initialize k = 1.

[0025] 2.1.1.5 Initialize the encoding C k = (c k , c k1 , …, c k2 , …, c km , …, c kM ) = (0, 0, …, 0) of the kth feature vector F k in DS.

[0026] 2.1.1.6 Initialize m = 1.

[0027] 2.1.1.7 List the values in F k that belong to the configurable parameters in the mth module, find the encoding corresponding to the values in F k that belong to the configurable parameters in the mth module in the encoding generated in step 2.1.1, let Code km , where Code m_k is a positive integer, 1 ≤ Code m_k ≤ Code m , and let c km = Code m_k .

[0028] 2.1.1.8 Let m = m + 1. If m > M, it means that F kThe values of the configurable parameters of the M modules belonging to the processor design paradigm have all been encoded to obtain F k the encoded C k , and put C k into the feature vector encoding set CS, then go to 2.1.1.9; if m ≤ M, go to 2.1.1.7 and continue to encode the values of the configurable parameters of the other modules in F k .

[0029] 2.1.1.9 Let k = k + 1. If k > K, it means that all the feature vectors in DS have been encoded to obtain CS, CS = {C1,…,C k ,…,C K}, 1 ≤ k ≤ K, go to 2.2; otherwise go to 2.1.1.5 and continue to encode the remaining feature vectors in DS

[0030] 2.1.2 Cluster CS to obtain V clusters, and record the encoding with the smallest Euclidean distance from the center point in these V clusters, denoted as C1, C2, …, C v ,…,C V in turn, where V < K, and V is generally preferably 0.1% - 0.5% of the number of feature vectors K in the design space of the processor design paradigm

[0031] 2.1.3 Decode C1, C2, …, C v ,…,C V by the following method

[0032] 2.1.3.1 Initialize v = 1

[0033] 2.1.3.2 Initialize the feature vector F v corresponding to C v =(p v1 ,p v2 ,…,p vn ,…,p vN )=(0,0,…0), 1 ≤ n ≤ N, where p v1 ,p v2 ,…,p vn ,…,p vN respectively represent the values of the 1st to the Nth parameters of the processor design under the vth feature vector configuration

[0034] 2.1.3.3 Initialize m = 1

[0035] 2.1.3.4 List the encoding c v corresponding to the mth module in C vm , and find the combination of the values of the configurable parameters in the mth module corresponding to c vm in the encoding recorded in step 2.1.1, and update Fv The configurable parameter in the m-th module is assigned this combination of values.

[0036] 2.1.3.5 Let m = m + 1. If m > M, it means C v Decoding completed, C obtained v The encoding F v Proceed to 2.1.3.6; if m ≤ M, proceed to 2.1.3.4 and continue with C. v Decode the encoding that belongs to other modules.

[0037] 2.1.3.6 Let v = v + 1. If v > V, explain why C1, C2, ..., C v ,…,C V Decoding has been completed, and the corresponding feature vectors F1, F2, ..., F have been obtained. v ,…,F V If the code is not found in the CS, proceed to step 2.2; otherwise, proceed to step 2.1.3.3 to continue decoding the remaining code in the CS.

[0038] 2.2 Using F1, F2, ..., F v ,…,F V Configure the processor design paradigm to obtain F1, F2, ..., F v ,…,F V Under the configuration, the processor design paradigm will automatically generate the corresponding Verilog source code for the processor design, including F1, F2, ..., F v ,…,F V The Verilog source code of the processor design under the configuration is sent to the EDA tool module.

[0039] 2.3 The EDA tool module uses simulation tools to obtain F1, F2, ..., F v ,…,F V Performance evaluation of processor designs under configurations Per1, Per2, ..., Per v ,…,Per V Use synthesis tools to obtain F1, F2, ..., F v ,…,F V The power consumption of the processor design under the configuration is Pow1, Pow2, ..., Pow. v ,…,Pow V Area assessment: Area1, Area2, ..., Area v ,…,Area V And set the quadruple set {(F1, Per1, Pow1, Area1), (F2, Per2, Pow2, Area2), ..., (F... v Per v Powv Area v ), …, (F V Per V Pow V Area V Send it back to the knowledge base construction submodule.

[0040] 2.4 The knowledge base construction submodule constructs the knowledge base KB, let KB = {(C1, F1, Per1, Pow1, Area1), (C2, F2, Per2, Pow2, Area2), ..., (C v F v Per v Pow v Area v ), …, (C V F V Per V Pow V Area V )}, where the quintuple (C v F v Per v Pow v Area v ) represents the vth knowledge entry in KB. KB contains a total of V knowledge entries.

[0041] The third step involves the retrieval and matching submodule receiving the processor design feature vector of the PPA value to be predicted from the processor design input module, encoding the feature vector to obtain its encoding, and performing a retrieval and matching operation in the knowledge base based on the encoding. The retrieved and matched knowledge, along with the processor design feature vector of the PPA value to be predicted, is then sent to the prompt word generation submodule. The method is as follows:

[0042] 3.1 The retrieval and matching submodule receives the processor design feature vector F, from the processor design input module, to predict the PPA value. target .

[0043] 3.2 Retrieval and Matching Submodule for F target Encode to obtain F target The encoding C target The method is:

[0044] 3.2.1 Initialize m = 1.

[0045] 3.2.2 List F target The value of the configurable parameter belonging to the m-th module is found in the code generated in step 2.1.1, where F is located. targetLet be the code corresponding to the value of the configurable parameter in the m-th module. target_m Code target_m Is a positive integer, 1≤Code target_m ≤Code m And let c targetm =Code target_m , will c targetm Place it in F target The encoding C target middle.

[0046] 3.2.3 Let m = m + 1. If m > M, it means F target The configurable parameter values ​​of the M modules belonging to the processor design paradigm have all been encoded, resulting in F. target The encoding C target Go to 3.3; if m≤M, go to 3.2.2 and continue with F. target The values ​​of configurable parameters belonging to other modules are encoded.

[0047] 3.3 The retrieval and matching submodule uses C target Using the KB knowledge base as a keyword, T relevant knowledge entries are obtained (T is a positive integer, generally between 5 and 10). The method is as follows:

[0048] 3.3.1 Calculate the encoding in the quintuple of KB and C target Euclidean distance, compare the quintuples in KB with C according to their encoding. target Sort the Euclidean distance values ​​in ascending order to obtain a sorted sequence of quintuples.

[0049] 3.3.2 The first T knowledge entries in the sorted quintuple sequence are used as the knowledge entries obtained through retrieval matching, (C find_1 F find_1 Per find_1 Pow find_1 Area find_1 ), (C find_2 F find_2 Per find_2 Pow find_2 Area find_2 ), ..., (C find_t F find_t Per find_t Pow find_t Area find_t ), ..., (C find_T F find_T Per find_T Pow find_T Area find_T ),T <V。

[0050] 3.4 The retrieval matching sub-module will send F target and T pieces of knowledge entries obtained by retrieval matching to the prompt generation sub-module.

[0051] In the fourth step, the prompt generation sub-module receives the processor design feature vector F target and T pieces of knowledge entries obtained by retrieval matching, generates the prompt for the PPA prediction of the processor design to be predicted PPA value, and the method is:

[0052] 4.1 Generate the role background prompt of the large language model (for example, “You are an artificial intelligence good at analyzing the performance and power consumption of processor architecture A (for the convenience of the large model to understand, the specific processor paradigm is named as “processor architecture A”). Your task is to analyze the performance and power consumption of processor architecture A based on some parameter designs of processor architecture A and the performance and power consumption values of the corresponding processor, and estimate the performance and power consumption of processor architecture A under the received parameter design of processor architecture A.”), and write the role background prompt of the large language model into the PPA prediction prompt of the processor design to be predicted PPA value.

[0053] 4.2 Generate the relevant knowledge prompt of the large language model, and the method is:

[0054] 4.2.1 Write “The following are some parameter designs of processor architecture A and the performance, power consumption and area values of the corresponding processor:” after the role background prompt generated in step 4.1.

[0055] 4.2.2 Initialize t = 1.

[0056] 4.2.3 Write “Parameter design t: processor design paradigm, the first configurable parameter name = F find_t [0], the second configurable parameter name = F find_t [1], …, the nth configurable parameter name = F find_t [n-1], …, the Nth configurable parameter name = F find_t [N-1]” into the PPA prediction prompt of the processor design to be predicted PPA value.

[0057] 4.2.4 Write “The performance value of parameter design t is: Per find_t , the power consumption value is: Pow find_t , and the area value is: Area find_t ” into the PPA prediction prompt of the processor design to be predicted PPA value.

[0058] 4.2.5 Let t = t + 1, if t > T, it means that the information in the T pieces of retrieved matching knowledge entries has formed the prompt word, go to 4.3, otherwise go to 4.2.3.

[0059] 4.3 Generate the prompt word of the PPA prediction question of the large language model, such as "When the parameter design of the processor architecture A is: the 1st parameter name = F target [0], the 2nd parameter name = F target [1], …, the n-th parameter name = F target [n-1], …, the N-th parameter name = F target [N-1], please give the estimated values of the performance value, power consumption value and area value of the corresponding processor." Write at the end of the PPA prediction prompt word of the processor design to be predicted PPA value.

[0060] 4.4 Send the PPA prediction prompt word of the processor design to be predicted PPA value to the PPA prediction module.

[0061] Step 5, the PPA prediction module receives the PPA prediction prompt word of the processor design to be predicted PPA value from the prompt word generation submodule, generates the PPA prediction, and the method is:

[0062] 5.1 The large language model receives the PPA prediction prompt word of the processor design to be predicted PPA value through the API interface.

[0063] 5.2 The large model answers the prompt word according to the PPA prediction prompt word of the processor design to be predicted PPA value and the basic knowledge of processor architecture possessed in the large language model, and obtains the PPA prediction value of the processor design to be predicted PPA value.

[0064] The present application can achieve the following technical effects:

[0065] 1. The second step and the third step of the present application encode the feature vector based on the processor design paradigm architecture characteristics, on the one hand, shorten the length of the feature vector when retrieving and matching, reduce the calculation overhead, thereby reducing the time overhead of PPA prediction; on the other hand, the processor design paradigm architecture characteristic information is integrated into the code, which improves the relevance of the knowledge entries in the subsequent retrieval and matching, so that the retrieval and matching submodule can retrieve more relevant knowledge of the processor design to be tested, and the prediction accuracy of PPA is improved.

[0066] 2. The second step, the third step and the fourth step of the present application respectively form the construction of a knowledge base, the retrieval of knowledge and the enhanced generation of prompt words in the RAG strategy, which can efficiently and accurately interact the knowledge required by the processor PPA prediction task with the large language model, improve the interaction efficiency and prediction accuracy of the large language model, and further reduce the time overhead of PPA prediction and improve the accuracy of PPA prediction.

[0067] 3. The PPA prediction module of the present application adopts existing high-performance large language models such as GPT4.0, DeepSeek, Qwen-72B, etc. Such large language models have basic knowledge of processor architecture, such as the impact of key component parameters in the processor (such as the number of channels and block size of Cache) on the processor, and have strong reasoning and computing capabilities. Therefore, after adopting the RAG strategy, only a small number of processor design samples with PPA index information are needed, and the PPA prediction module can obtain the final PPA prediction value through the information in the PPA prediction prompt word corresponding to the processor design feature vector generated by the prompt word generation submodule and the basic knowledge of processor architecture in the large language model through reasoning and computing. By utilizing the basic knowledge of processor architecture and the reasoning and computing capabilities of the existing high-performance large language model, the present application can significantly reduce the number of processor design samples with PPA index information required to build the PPA prediction method, thereby significantly reducing the time cost of building the PPA prediction method. BRIEF DESCRIPTION OF DRAWINGS

[0068] Figure 1 The logical structure diagram of the present application for constructing a RAG-based few-sample processor design PPA prediction system is constructed in the first step.

[0069] Figure 2 The present application is a general flowchart. DETAILED DESCRIPTION

[0070] To verify the effect of the present application, the processor design paradigm is predicted by the present application, the EDA tool module adopts the simulation tool Verilator 4.218, the synthesis tool YoSys0.33, and the processor design paradigm selected is single-core in Rocket Chip Generator. Table 1 is the parameter list of single-core and its candidate values, the first value in the candidate value is the value of the default design of single-core, which can be divided into M=4 modules (i.e. core module, instruction cache module, data cache module, branch prediction module), there are N=14 configurable parameters in the processor design paradigm, which cover the main aspects of processor chip design.

[0071] Table 1

[0072]

[0073]

[0074] In the above experimental environment, the flow of the present application is as shown in Figure 2 , comprising the following steps:

[0075] First, the RAG-based few-shot processor design PPA prediction system is constructed. The RAG-based few-shot processor design PPA prediction system is as shown in Figure 1 , which is composed of a processor design paradigm, an EDA tool module, an RAG module, a to-be-tested processor design input module, and a PPA prediction module. The RAG module includes a knowledge base construction submodule, a retrieval matching submodule, and a prompt word generation submodule.

[0076] The RAG module is connected to the processor design paradigm, the EDA tool module, the to-be-tested processor design input module, and the PPA prediction module.

[0077] The knowledge base construction submodule in the RAG module is connected to the processor design paradigm, the EDA tool module, and the retrieval matching submodule. The knowledge base construction submodule samples the design space of the processor design paradigm to obtain a plurality of feature vectors (length N, N=14 in this embodiment) of the processor design paradigm, encodes the feature vectors of the processor design paradigm to obtain the encoding of the feature vectors, and sends the processor design under the configuration of the feature vectors of the processor design paradigm to the EDA tool module. The knowledge base construction submodule receives the PPA indicators (i.e., performance, power consumption, and area evaluation) of the processor design sent back from the EDA tool module, and forms a five-tuple of the feature vectors of the processor design paradigm, the encoding of the feature vectors, the performance, power consumption, and area evaluation of the PPA indicators of the processor design under the configuration of the feature vectors as a piece of knowledge, and constructs a knowledge base for retrieval matching by the retrieval matching submodule.

[0078] The retrieval matching submodule is connected to the knowledge base construction submodule, the prompt word generation submodule, and the to-be-tested processor design input module. The retrieval matching submodule receives the processor design feature vector of the to-be-predicted PPA value from the to-be-tested processor design input module, encodes the processor design feature vector of the to-be-predicted PPA value to obtain the encoding of the feature vector, and performs retrieval matching in the knowledge base constructed by the knowledge base construction submodule according to the size of the Euclidean distance between the encoding of the feature vector of all knowledge in the knowledge base constructed by the knowledge base construction submodule and the encoding of the processor design feature vector of the to-be-predicted PPA value. The knowledge obtained by retrieval matching is sent to the prompt word generation submodule together with the processor design feature vector of the to-be-predicted PPA value.

[0079] The prompt word generation submodule is connected with the retrieval matching submodule and the PPA prediction module. The processor design feature vector of the PPA value to be predicted and the knowledge obtained by retrieval matching are received from the retrieval matching submodule, the PPA prediction prompt word corresponding to the processor design feature vector of the PPA value to be predicted is generated according to the knowledge obtained by retrieval matching, and the PPA prediction prompt word is sent to the PPA prediction module.

[0080] The EDA tool module is composed of a simulation tool (in this embodiment, Verilator 4.218) and a synthesis tool (in this embodiment, YoSys 0.33), and is connected with the knowledge base construction submodule in the RAG module. The processor design under the feature vector configuration of the processor design paradigm is received from the knowledge base construction submodule, the processor design under the feature vector configuration of the processor design paradigm is simulated by using the simulation tool to obtain performance evaluation, and the processor design under the feature vector configuration of the processor design paradigm is synthesized by using the synthesis tool to obtain power consumption and area evaluation. The PPA indicators, i.e., performance, power consumption and area evaluation, are sent to the knowledge base construction submodule.

[0081] The PPA prediction module is a large language model with processor architecture knowledge and strong reasoning ability, DeepSeek large language model. The PPA prediction module is connected with the prompt word generation submodule in the RAG module. The PPA prediction module receives the PPA prediction prompt word from the prompt word generation submodule, and generates the PPA prediction result according to the PPA prediction prompt word.

[0082] In the second step, the knowledge base construction submodule samples the design space of the processor design paradigm, and constructs a knowledge base for retrieval by the retrieval matching submodule. The method is as follows:

[0083] 2.1 The processor design paradigm is composed of M=4 modules, and the configurable parameter combinations of each module are combined to form a feature vector with a length of N=14. The knowledge base construction submodule samples the design space of the processor design paradigm to obtain V=15 feature vectors F1, F2, …, FV of the processor design paradigm. v ,…,F V ,1≤v≤V, wherein F v =(p v1 ,p v2 ,…,p vn ,…,p v14 ),1≤n≤14,p v1 ,p v2 ,…,p vn ,…,p v14 represent the values of the 1st to N=14th parameters of the processor design under the vth feature vector configuration. The sampling method is as follows:

[0084] 2.1.1 All feature vectors (a total of K feature vectors, K = 3918 in this embodiment) in the design space of the processor design paradigm are placed into the feature vector set DS. All feature vectors in DS are encoded to obtain corresponding encoded vectors, and these encoded vectors are placed into the feature vector encoding vector set CS. The method is as follows:

[0085] 2.1.1.1 Initialize m = 1.

[0086] 2.1.1.2 List all feasible combinations of configurable parameters for the m-th module in the processor design paradigm, and record all feasible combinations as codes, 1, 2, 3, ..., Code. m Code m The value is the number of all feasible combinations of configurable parameters in the m-th module. In this embodiment, Code1 = 32, Code2 = 16, Code3 = 41, and Code4 = 9. Because the parameters of each module are mutually constrained—for example, when the branchPredictionCSR parameter in the core module is 0, the parameters of the branch prediction module are meaningless—the design space size of the processor design paradigm is K = 3918, rather than the product of the feasible combinations of values ​​for each module.

[0087] 2.1.1.3 Let m = m + 1. If m > M, it means that all feasible combinations of configurable parameters of the M modules in the processor paradigm have been recorded as corresponding codes. Proceed to 2.1.1.4. If m ≤ M, then continue to record all feasible combinations of configurable parameters of other modules in the processor paradigm as corresponding codes. Proceed to 2.1.1.2.

[0088] 2.1.1.4 Initialize k = 1.

[0089] 2.1.1.5 Initialize the k-th eigenvector F in DS k The encoding C k =(c k1 ,c k2 ,…,c km ,…,c kM ) = (0,0,…0).

[0090] 2.1.1.6 Initialize m = 1.

[0091] 2.1.1.7 List F k The value of the configurable parameter belonging to the m-th module is found in step 2.1.1. k The code is the encoding corresponding to the value of the configurable parameter in the m-th module. km Code km Is a positive integer, 1≤Codemk ≤Code m , and let c km = Code km .

[0092] 2.1.1.8 Let m = m + 1, if m > 4, it means that the encoding of the configurable parameters belonging to the 4th module in F k has been completed, get the encoding C k of F k , put this C k into the feature vector encoding set CS, go to 2.1.1.9; if m ≤ M, go to 2.1.1.7, continue to encode the configurable parameters belonging to other modules in F k .

[0093] 2.1.1.9 Let k = k + 1, if k > K, it means that all the feature vectors in DS have been completed encoding, go to 2.2; otherwise, continue to encode the remaining feature vectors in DS, go to 2.1.1.5.

[0094] 2.1.2 Cluster CS using K-means algorithm to get V = 15 clusters, and record the encoding of the center point with the smallest Euclidean distance in the V clusters, recorded in turn as C1, C2, …, C v , …, C V .

[0095] 2.1.3 Decode C1, C2, …, C v , …, C V , the method is:

[0096] 2.1.3.1 Initialize v = 1.

[0097] 2.1.3.2 Initialize C v corresponding feature vector F v = (p v1 , p v2 , …, p vn , …, p vN ) = (0, 0, …0).

[0098] 2.1.3.3 Initialize m = 1.

[0099] 2.1.3.4 List the encoding c v in C vm corresponding to the mth module, find the value combination of the configurable parameters in the mth module corresponding to c vm in the encoding recorded in 2.1.1, and assign the configurable parameters in F v belonging to the mth module to this value combination.

[0100] 2.1.3.5 Let m = m + 1, if m > M, it means that C v has been decoded, get F v , go to 2.1.3.6; if m ≤ M, go to 2.1.3.4, continue to decode the encoding in C v which belongs to other modules. v

[0101] 2.1.3.6 Let v = v + 1, if v > V, it means that C1, C2, …, C v , go to 2.2; if v ≤ V, go to 2.1.3.3, continue to decode the remaining encoding in CS. V has been decoded, get F1, F2, …, F v , go to 2.2; if v ≤ V, go to 2.1.3.3, continue to decode the remaining encoding in CS. V

[0102] 2.2 Use F1, F2, …, F v , to configure the processor design paradigm, get F1, F2, …, F V , under the configuration of the processor design. v V The processor design paradigm will automatically generate the verilog source code of the corresponding processor design, and send the verilog source code of the processor design under the configuration of F1, F2, …, F v to the EDA tool module. V

[0103] 2.3 The EDA tool module uses simulation tools to obtain the performance evaluation Per1, Per2, …, Per v of the processor design under the configuration of F1, F2, …, F V ; uses synthesis tools to obtain the power consumption Pow1, Pow2, …, Pow v and area evaluation Area1, Area2, …, Area V of the processor design under the configuration of F1, F2, …, F v , and send the four-tuple set {(F1, Per1, Pow1, Area1), (F2, Per2, Pow2, Area2), …, (F V , Per v , Pow V , Area v ), …, (F V , Per v , Pow v , Area v} to the user. v V ​​​​​​V , Pow V , Area V )} back to the knowledge base construction submodule.

[0104] 2.4 The knowledge base construction submodule constructs the knowledge base KB, let KB = {(C1, F1, Per1, Pow1, Area1), (C2, F2, Per2, Pow2, Area2), …, (C v , F v , Per v , Pow v , Area v ), …, (C V , F V , Per V , Pow V , Area V )}, where the five-tuple (C v , F v , Per v , Pow v , Area v ) is the vth knowledge entry in KB, and KB contains a total of V = 15 knowledge entries.

[0105] Third step, the retrieval matching submodule receives the processor design feature vector of the PPA value to be predicted from the processor design input module to be tested, encodes the processor design feature vector of the PPA value to be predicted, obtains the encoding of the feature vector, and performs retrieval matching in the knowledge base constructed by the knowledge base construction submodule according to the encoding of the feature vector. The knowledge obtained by retrieval matching and the processor design feature vector of the PPA value to be predicted are sent to the prompt word generation submodule, and the method is:

[0106] 3.1 The retrieval matching submodule receives the processor design feature vector F target of the PPA value to be predicted from the processor design input module to be tested.

[0107] 3.2 The retrieval matching submodule encodes F target , obtains the encoding C target of F target , and the method is:

[0108] 3.2.1 Initialize m = 1, C target = (c target1 , c target2 , …, c targetm , …, c targetM ).

[0109] 3.2.2 List F targetThe value of the configurable parameter belonging to the m-th module is found in the code generated in step 2.1.1, where F is located. target Let be the code corresponding to the value of the configurable parameter in the m-th module. target_m Code target_m Is a positive integer, 1≤Code target_m ≤Code m And let c targetm =Code target_m .

[0110] 3.2.3 Let m = m + 1. If m > M, it means F target The configurable parameters of the four modules M (belonging to the processor design paradigm) have all been encoded, resulting in F. target The encoding C target Go to 3.3; if m≤M, go to 3.2.2 and continue with F. target The values ​​of configurable parameters belonging to other modules are encoded.

[0111] 3.3 The retrieval and matching submodule uses C target Using the keyword to retrieve knowledge base KB, T (T=5 in this embodiment) relevant knowledge entries are obtained. The method is as follows:

[0112] 3.3.1 Retrieve the quintuples in KB according to their encoding and C. target Sort the Euclidean distance values ​​in ascending order.

[0113] 3.3.2 The first T knowledge entries in the sorted quintuple sequence are used as the knowledge obtained through retrieval matching, (C find_1 F find_1 Per find_1 Pow find_1 Area find_1 ), (C find_2 F find_2 Per find_2 Pow find_2 Area find_2 ), ..., (C find_t F find_t Per find_t Pow find_t Area find_t ), ..., (C find_5 F find_5 Per find_5 Pow find_5 Area find_5 ).

[0114] 3.4 The retrieval and matching submodule will retrieve F targetand 5 knowledge entries obtained in step 3.3, to the prompt generation submodule.

[0115] In the fourth step, the prompt generation submodule receives the processor design feature vector F of the PPA value to be predicted from the retrieval matching submodule target and the T = 5 knowledge entries obtained by retrieval matching, generates the prompt for the PPA prediction of the processor design of the PPA value to be predicted, which is:

[0116] 4.1 Generate the role background prompt of the large language model (for example, "You are an artificial intelligence good at analyzing the performance and power consumption of processor architecture A (for the convenience of the large model to understand, the specific processor paradigm is named "processor architecture A"). Your task is to analyze the performance and power consumption of processor architecture A under the received parameter design of processor architecture A, and estimate the performance and power consumption of processor architecture A under the received parameter design of processor architecture A.") Write the role background prompt of the large language model to the PPA prediction prompt of the processor design of the PPA value to be predicted.

[0117] 4.1 Generate the role background prompt of the large language model, such as "You are an artificial intelligence good at analyzing the performance and power consumption of processor architecture A under different parameter designs. Your task is to analyze the performance and power consumption of processor architecture A under the received parameter design of processor architecture A, and estimate the performance and power consumption of processor architecture A under the received parameter design of processor architecture A." Write the PPA prediction prompt of the processor design of the PPA value to be predicted.

[0118] 4.2 Generate the relevant knowledge prompt of the large language model, which is:

[0119] 4.2.1 Write "The following are some parameter designs of processor architecture A and the performance, power consumption and area values of the corresponding processors:" after the role background prompt generated in step 4.1.

[0120] 4.2.2 Initialize t = 1.

[0121] 4.2.3 Write "Parameter design t: branchPredictionCSR = F find_t [0], fastLoadByte = F find_t [1], mulEarlyOut = F find_t [2], …, counterLength = F find_t

[13] ." in the PPA prediction prompt of the processor design of the PPA value to be predicted.

[0122] 4.2.4 Write "The performance value of parameter design t is: Perfind_t The power consumption value is: Pow find_t The area value is: Area find_t "The processor design writes PPA prediction prompts to the PPA value to be predicted."

[0123] 4.2.5 Let t = t + 1. If t > T, it means that the information in the T search results has formed prompt words. Proceed to 4.3. Otherwise, proceed to 4.2.3.

[0124] 4.3 Generate prompt words for PPA prediction questions in large language models, such as "When the parameters of processor architecture A are designed as: branchPredictionCSR = F target [0],fastLoadByte=F target [1], mulEarlyOut=F target [2],…,counterLength=F target

[13] When this is the case, please provide estimated values ​​for the performance, power consumption, and area of ​​the corresponding processor. "Write the PPA prediction prompt at the end of the processor design for which the PPA value is to be predicted."

[0125] 4.4 Send the PPA prediction prompt words designed by the processor to predict the PPA value to the PPA prediction module.

[0126] Step 5: The PPA prediction module receives the PPA prediction prompts designed by the processor from the prompt word generation submodule, and generates the PPA prediction. The method is as follows:

[0127] 5.1 The large language model receives PPA prediction prompts designed by the processor through the API interface to receive the PPA value to be predicted.

[0128] 5.2 The large model performs inference calculations based on the PPA prediction prompts for the processor design to be predicted, answers the prompts, and obtains the predicted PPA value for the processor design. Table 2 shows the prediction accuracy of the RAG-based few-sample processor design PPA prediction method for processor design paradigms, single-core processors, and the generated processor design PPA indicators. The average prediction accuracy for performance indicators is 99.01%, the average prediction accuracy for power consumption is 98.74%, and the average prediction accuracy for area indicators is 98.23%.

[0129] Table 2

[0130]

[0131]

[0132] Table 3 shows the number of samples with PPA labels required by the RAG-based few-sample processor design PPA prediction method of the present application and the Rapid and Accurate PPA Prediction for the Template-Based Processor Design Methods to build the model, and the time cost per unit, where the present application only requires 15 samples and the time cost is only 11% of the method described in Rapid and Accurate PPA Prediction for the Template-Based Processor Design Methods (the time cost refers to the construction time of the method, including the time cost of collecting samples and the time cost of algorithm training).

[0133] Table 3

[0134]

[0135] Table 4 is the parameter configuration, PPA index, and PPA prediction value of a specific design in the single-core processor design paradigm design space, and the prediction accuracy of the PPA index corresponding to the RAG-based few-sample processor design PPA prediction method. The prediction accuracy of the performance index of the specific design in Table 4 by the RAG-based few-sample processor design PPA prediction method of the present application is 100%, the prediction accuracy of the power consumption index is 99.41%, and the prediction accuracy of the area index is 98.88%.

[0136] Table 4

[0137]

[0138]

Claims

1. A RAG-based few-shot processor design (PPA) prediction method, characterized by The method comprises the following steps: Step 1: constructing a RAG-based few-shot processor design PPA prediction system, which comprises a processor design paradigm, an EDA tool module, a RAG module, a processor design under test input module and a PPA prediction module; the RAG module comprises a knowledge base construction submodule, a retrieval matching submodule and a prompt word generation submodule; The knowledge base construction submodule samples the design space of the processor design paradigm, obtains a plurality of processor design samples, encodes the feature vectors of the processor design samples to obtain the encoding of the feature vectors, obtains the PPA values of the processor design samples by using the simulation and synthesis tools in the EDA tool module, and constructs the knowledge base required for PPA prediction; the processor design under test input module receives the processor design feature vector of the PPA value to be predicted input by the designer and sends it to the retrieval matching submodule in the RAG module; the retrieval matching submodule receives the processor design feature vector of the PPA value to be predicted, detects the matching knowledge in the knowledge base with the processor design encoding of the PPA value to be predicted; The prompt word generation submodule generates the prompt word for interacting with the PPA prediction module based on the matching knowledge obtained from the retrieval matching submodule; the PPA prediction module obtains the PPA prediction value of the processor design of the PPA value to be predicted by interacting with the prompt word generated by the prompt word generation submodule; Step 2: the knowledge base construction submodule samples the design space of the processor design paradigm and constructs the knowledge base for retrieval by the retrieval matching submodule, and the method is: Step 2.1 The processor design paradigm is composed of M modules, M is a positive integer, and the configurable parameters of each module are combined together to form a feature vector with a length of N, ; the knowledge base construction submodule samples the design space of the processor design paradigm to obtain feature vectors of V processor design paradigms , V is a positive integer, 1≤v≤V, wherein 1≤n≤N, respectively represent the values of the 1st to Nth parameters of the processor design under the configuration of the vth feature vector; the sampling method is: Step 2.1.1 Put all feature vectors in the design space of the processor design paradigm into a feature vector set DS, record all feasible combinations of configurable parameters of each module and the one-to-one correspondence with the encoding, encode all feature vectors in DS based on the above-mentioned correspondence, obtain the corresponding encoding vectors, and put these encoding vectors into a feature vector encoding vector set CS, CS={ }, the encoding of the feature vector, 1≤k≤K, K is the number of feature vectors in the design space of the processor design paradigm;​ Step 2.1.2 Cluster the CS to get V clusters, and record the code of the center point in each cluster, denoted as , V < K; Step 2.1.3 Decode the feature vector to obtain the corresponding feature vector, and let The corresponding feature vector is yes The corresponding feature vector; Step 2.2 uses configuring a processor design paradigm, obtaining a processor design under the configuration, the processor design paradigm automatically generating verilog source code of the corresponding processor design, and sending the verilog source code of the processor design under the configuration to an EDA tool module; Step 2.

3. The EDA tool module obtains the performance evaluation of the processor design under the configuration using simulation tools Step 2.

4. The EDA tool module obtains the power consumption of the processor design under the configuration Step 2.

5. The EDA tool module obtains the area evaluation of the processor design under the configuration Step 2.

6. The EDA tool module sends the set of quadruples { (A, B, C, D), (A, B, E, F), …, (G, H, I, J), …, (K, L, M, N)} back to the knowledge base building submodule ​​​​​​​​​​ Step 2.4 The knowledge base construction submodule constructs the knowledge base KB, let KB = {( , , (), , , ), ... , ( , ), ... , ( , )}, where the quintuple ( , ) represents the vth knowledge entry in KB, and KB contains a total of V knowledge entries; Step 3: the retrieval matching submodule receives the processor design feature vector of the PPA value to be predicted from the processor design under test input module, encodes the processor design feature vector of the PPA value to be predicted to obtain the encoding of the feature vector, and performs retrieval matching in the knowledge base according to the encoding of the feature vector, and sends the knowledge obtained by retrieval matching and the processor design feature vector of the PPA value to be predicted to the prompt word generation submodule, and the method is: Step 3.1 The retrieve match sub-module receives the processor design feature vector of the PPA values to be predicted from the processor design input module ; Step 3.2 Retrieving matching sub-module pair Encoding is performed to obtain ; Step 3.3 The retrieval matching sub-module is used to retrieve the knowledge base KB as a key word, and the retrieval matching obtains T knowledge entries, i.e. , , , , , , , , T is a positive integer and T < V; Step 3.4 The retrieval matching submodule sends the T knowledge entries matched to the prompt word generation submodule. and the T knowledge entries matched are sent to the prompt word generation submodule. In the fourth step, the cue generation submodule receives the T pieces of knowledge entries from the retrieval matching submodule and the T pieces of knowledge entries obtained by retrieval matching, generates the cue for the PPA prediction of the processor design of the to-be-predicted PPA value, by the method of: Step 4.1: generating a role background prompt word of a large language model, and writing the role background prompt word of the large language model into the PPA prediction prompt word of the processor design of the PPA value to be predicted; Step 4.2: generating a related knowledge prompt word of a large language model, and the method is: Step 4.2.1: writing "The following are some parameter designs of processor architecture A and the performance values, power consumption values and area values of the corresponding processors:" after the role background prompt word generated in step 4.1; Step 4.2.2: initializing t = 1; Step 4.2.3 Write into the PPA prediction hint word of the processor design whose PPA value is to be predicted, "Parameter design t: 1st Parameter name [0], 2nd Parameter name [1], …, nth Parameter name [n-1], …, Nth Parameter name [N-1]"; Step 4.2.4 writes into the PPA prediction cue of the processor design whose PPA value is to be predicted, the performance value of the parameter design t as: , the power consumption value as: , and the area value as: ; Step 4.2.5: setting t = t+1, if t>T, it means that the information in the T pieces of knowledge obtained by retrieval matching has formed a prompt word, and step 4.3 is turned, otherwise step 4.2.3 is turned; Step 4.3: generating a PPA prediction question prompt word of a large language model, and writing the PPA prediction question prompt word of the large language model at the end of the PPA prediction prompt word of the processor design of the PPA value to be predicted; Step 4.4: sending the PPA prediction prompt word of the processor design of the PPA value to be predicted to the PPA prediction module; In the fifth step, the PPA prediction module receives the PPA prediction prompt of the processor design for which the PPA value is to be predicted from the prompt generation submodule, generates a PPA prediction, and the method is as follows: In step 5.1, the large language model receives the PPA prediction prompt of the processor design for which the PPA value is to be predicted through an API interface. In step 5.2, the large model performs inference calculation according to the PPA prediction prompt of the processor design for which the PPA value is to be predicted and the basic knowledge of the processor architecture possessed by the large language model, answers the prompt, and obtains the PPA prediction value of the processor design for which the PPA value is to be predicted.

2. The RAG-based few-shot processor design (PPA) prediction method of claim 1, wherein The RAG module is connected to the processor design paradigm, the EDA tool module, the input module of the processor design to be tested, and the PPA prediction module. The knowledge base construction submodule in the RAG module is connected to the processor design paradigm, the EDA tool module, and the retrieval matching submodule. The knowledge base construction submodule samples the design space of the processing design paradigm to obtain a plurality of feature vectors of the processor design paradigm, encodes the feature vectors of the processor design paradigm to obtain the encoding of the feature vectors, and sends the processor design under the configuration of the feature vectors of the processor design paradigm to the EDA tool module. The knowledge base construction submodule receives the PPA indicators of the processor design under the configuration of the feature vectors, i.e., performance, power consumption, and area evaluation, from the EDA tool module, and constructs a five-tuple of the feature vectors of the processor design paradigm, the encoding of the feature vectors, the performance, power consumption, and area evaluation of the PPA indicators of the processor design under the configuration of the feature vectors as a piece of knowledge, and builds it into a knowledge base for retrieval and matching by the retrieval matching submodule. The retrieval matching submodule is connected to the knowledge base construction submodule, the prompt generation submodule, and the input module of the processor design to be tested. The retrieval matching submodule receives the feature vector of the processor design for which the PPA value is to be predicted from the input module of the processor design to be tested, encodes the feature vector of the processor design for which the PPA value is to be predicted, obtains the encoding of the feature vector of the processor design for which the PPA value is to be predicted, and performs retrieval and matching in the knowledge base according to the Euclidean distance between the encoding of the feature vector of all knowledge in the knowledge base and the encoding of the feature vector of the processor design for which the PPA value is to be predicted. The knowledge obtained by retrieval and matching is sent to the prompt generation submodule together with the feature vector of the processor design for which the PPA value is to be predicted. The prompt generation submodule is connected to the retrieval matching submodule and the PPA prediction module. The prompt generation submodule receives the knowledge obtained by retrieval and matching from the retrieval matching submodule and the feature vector of the processor design for which the PPA value is to be predicted, generates a PPA prediction prompt corresponding to the feature vector of the processor design for which the PPA value is to be predicted according to the knowledge obtained by retrieval and matching, and sends the PPA prediction prompt corresponding to the feature vector of the processor design for which the PPA value is to be predicted to the PPA prediction module. The EDA tool module is composed of a simulation tool and a synthesis tool, and is connected to the knowledge base construction submodule in the RAG module. The EDA tool module receives a processor design in a feature vector configuration of a processor design paradigm from the knowledge base construction submodule, simulates the processor design in the feature vector configuration of the processor design paradigm using the simulation tool to obtain performance evaluation, and synthesizes the processor design in the feature vector configuration of the processor design paradigm using the synthesis tool to obtain power consumption and area evaluation. The PPA index, i.e., performance, power consumption and area evaluation, is sent to the knowledge base construction submodule. The PPA prediction module is a large language model with processor architecture knowledge and reasoning ability, and is connected to the prompt word generation submodule in the RAG module. The PPA prediction module receives a PPA prediction prompt word corresponding to a processor design feature vector of a PPA value to be predicted from the prompt word generation submodule, and generates a PPA prediction result according to the PPA prediction prompt word corresponding to the processor design feature vector of the PPA value to be predicted.

3. The RAG-based few-shot processor design (PPA) prediction method of claim 2, wherein The simulation tool in the EDA tool module includes Verilator 4.218 and above, and ModelSim 2022.2 and above. The synthesis tool includes an open source tool YoSys 0.33 and above, and a commercial tool Design Compiler 2016 and above. The large language model used by the PPA prediction module is any one of GPT4.0, DeepSeek and Qwen-72B.

4. The RAG-based few-shot processor design (PPA) prediction method of claim 1, wherein The method of step 2.1.1.1 is to put all feature vectors in the design space of the processor design paradigm into a feature vector set DS, encode all feature vectors in DS to obtain corresponding encoded vectors, and put the encoded vectors into a feature vector encoded vector set CS. Step 2.1.1.1 initializes m=1. Step 2.1.1.2 lists all possible value combinations of the configurable parameters of the mth module in the processor design paradigm, and records all the possible value combinations as encodings, i.e. wherein is the number of all possible combinations of the configurable parameters in the mth module. Step 2.1.1.3 sets m=m+1. If m>M, it means that all feasible combinations of the configurable parameters of the M modules of the processor paradigm have been recorded as corresponding codes, and step 2.1.1.4 is turned. If m<M, step 2.1.1.2 is turned to continue recording all feasible combinations of the configurable parameters of other modules in the processor paradigm as corresponding codes. Step 2.1.1.4 initializes k=1. Step 2.1.1.5 Initialize the kth feature vector in the DS of the encoding ; Step 2.1.1.6 initializes m=1. Step 2.1.1.7 lists the value of the configurable parameter belonging to the mth module in the code generated in Step 2.1.1.2 the code corresponding to the value of the configurable parameter belonging to the mth module, let the code be where 1≤ ≤ , and let ; Step 2.1.1.8 Let m = m + 1. If m > M, it means... The configurable parameter values ​​of the M modules belonging to the processor design paradigm have all been encoded, resulting in... encoding ,Will Place it into the feature vector encoding set CS, then proceed to step 2.1.1.9; if m ≤ M, proceed to step 2.1.1.7 and continue processing. The values ​​of configurable parameters belonging to other modules are encoded. Step 2.1.1.9 Let k = k + 1. If k > K, where K is the number of eigenvectors in the design space of the processor design paradigm, it means that all eigenvectors in DS have been encoded, resulting in CS, where CS = { }, 1≤k≤K; otherwise, go to step 2.1.1.5 and continue encoding the remaining feature vectors in DS.

5. The RAG-based few-shot processor design (PPA) prediction method of claim 1, wherein Step 2.1.2.1 V is 0.1%-0.5% of the number K of feature vectors in the design space of the processor design paradigm.

6. The RAG-based few-shot processor design (PPA) prediction method of claim 1, wherein The method described in step 2.1.3 is applied to The method of decoding is: Step 2.1.3.1 initializes v=1. Step 2.1.3.2 initialization , 1≤n≤N, respectively represent the values of the 1st to the Nth parameters of the processor design under the vth feature vector configuration. Step 2.1.3.3 initializes m=1. Step 2.1.3.4 lists the encoding corresponding to the mth module in the middle finds the value combination of the configurable parameters in the corresponding mth module in the encoding recorded in step 2.1.1 corresponding to the value combination of the configurable parameters in the mth module, will be the configurable parameters in the mth module in the middle are assigned the value combination Step 2.1.3.5 Let m = m + 1. If m > M, it means... Decoding completed, obtained encoding Proceed to step 2.1.3.6; if m ≤ M, proceed to step 2.1.3.4 and continue with the process. Decode the encoding that belongs to other modules; Step 2.1.3.6 Let v = v + 1, if v > V, it means the decoding is finished, and the corresponding eigenvector is obtained , end; otherwise, go to step 2.1.3.3 to continue decoding the remaining codes in CS.

7. The RAG-based few-shot processor design (PPA) prediction method of claim 1, wherein The search matching submodule described in step 3.2 is used to Encode to get The method is: Step 3.2.1 initializes m=1. Step 3.2.2 lists the value of the configurable parameter belonging to the mth module in the encoding generated in step 2.1.1 the encoding corresponding to the value of the configurable parameter belonging to the mth module, let be where 1≤ ≤ , and let , and ; Step 3.2.3 Let m = m + 1. If m > M, it means... The configurable parameter values ​​of the M modules belonging to the processor design paradigm have all been encoded, resulting in... encoding End; if m≤M, go to step 3.2.2 and continue. The values ​​of configurable parameters belonging to other modules are encoded.

8. The RAG-based few-shot processor design (PPA) prediction method of claim 1, wherein Step 3.3, the T value is 5-10, the search matching sub-module is used to The method for retrieving the knowledge base KB as a keyword to obtain relevant T knowledge items is: Step 3.3.1 calculates the encoding in the five-tuple in the KB and Euclidean distance, sorts the five-tuples in the KB according to their encoding and Euclidean distance values from small to large, to obtain a sorted five-tuple sequence; Step 3.3.2 takes the first T knowledge entries in the sorted quintuple sequence as the retrieved matching knowledge entries, (T , ), (T , ), …, (T , ), …, (T , ).

9. The RAG-based few-shot processor design (PPA) prediction method of claim 1, wherein The role background prompt word of the large language model generated in step 4.1 is "You are an artificial intelligence good at analyzing the performance and power consumption of processor architecture A under different parameter designs; your task is to analyze the performance and power consumption of processor architecture A under the received parameter design of processor architecture A based on the performance and power consumption values of the processor corresponding to the received parameter design of processor architecture A, and approximately estimate the performance and power consumption values of processor architecture A under the received parameter design." "Processor architecture A" is the naming of a specific processor paradigm.

10. The RAG-based few-shot processor design (PPA) prediction method of claim 1, wherein The PPA prediction prompt word for the large language model generated in step 4.3 is "When the parameter design of the processor architecture A is: the 1st parameter name = [0], the 2nd parameter name = [1], …, the n-th parameter name = [n-1],…, the N-th parameter name= [N-1], please give the estimated values of the performance value, power consumption value and area value of the corresponding processor;".

Images