Radio frequency switch bare chip and radio frequency switch bare chip preparation method

Abstract

The invention discloses a radio frequency switch bare chip and a radio frequency switch bare chip preparation method, and belongs to the field of radio frequency switches. According to the invention, by multiplexing the first radio frequency switch group module and / or the second radio frequency switch group module on the same substrate, the function multiplexing capability can be realized. Meanwhile, a scribing groove is additionally formed in the middle area of the first area and the second area of the functional layer, the scribing groove is formed by etching the functional layer and completely exposing the substrate, namely, an air gap is formed, and equivalently, a dielectric material with a high dielectric constant in the middle area is replaced by air. On one hand, stray capacitance can be reduced, so that isolation of the functional unit can be improved; and on the other hand, the dielectric material in the middle region is etched, so that when the scribing groove is mechanically cut, the stress influence of cutting on the multilayer dielectric can be avoided, the stripping risk is avoided, the layering probability is reduced, a reliable cutting surface without a layering path is formed, and later water vapor erosion is prevented, thereby improving the packaging reliability.

Description

Technical Field

[0001] This application relates to the field of radio frequency switches, and in particular to a bare RF switch chip and a method for fabricating the bare RF switch chip. Background Technology

[0002] Due to varying application scenarios, the requirements for RF switch types also differ. The diversity of RF switch types increases the cost and complexity of RF switch design and manufacturing processes. To reduce cost and complexity, a proposed RF switch chip and module achieves SP2T (Single Pole Double Throw) and SP4T (Single Pole Four Throw) compatible designs by multiplexing a first and / or second RF switch group on the same substrate, saving mask costs and reducing wafer manufacturing and inventory management costs. This design incorporates structural symmetry, control multiplexing, and a dicable architecture. Specifically, when designing the RF switch chip as a dicable compatible structure for both SP4T and dual SP2T, a dicing channel must be reserved in the middle region of the chip for later physical dicing to achieve structural separation.

[0003] However, because this intermediate region is still covered by multiple layers of high-dielectric-constant dielectric material, it is prone to delamination, peeling, or moisture intrusion during dicing or temperature cycling, severely affecting the long-term reliability of the product. Furthermore, since the various functional units of the circuit require a certain level of isolation, this is typically achieved by increasing the physical distance between them. However, the blank area left after this separation—the middle region of the chip—is still covered by high-dielectric-constant dielectric material, resulting in a large parasitic capacitance and sacrificing isolation. Therefore, a universal structural solution is needed that can simultaneously improve structural reliability and RF isolation performance while also considering functional multiplexing capabilities. Summary of the Invention

[0004] The purpose of this application is to provide a bare RF switch chip and a method for fabricating a bare RF switch chip. By reusing a first RF switch module and / or a second RF switch module on the same substrate, and forming an air gap by creating a dicing groove in the middle region between the first and second regions of the functional layer, the isolation is improved. When the first and second RF switch modules are cut and used separately, mechanical cutting of the multilayer dielectric avoids damage to the interface, thus improving structural reliability. Therefore, the pre-designed dicing groove also considers functional reuse capability.

[0005] To achieve the above objectives, this application provides a bare radio frequency switch chip, comprising: a substrate, wherein a functional layer is disposed on the surface of the substrate; the functional layer includes a first region and a second region; a first radio frequency switch module is disposed in the first region; a second radio frequency switch module is disposed in the second region; a dicing groove is disposed between the first region and the second region; and the bottom of the dicing groove exposes the substrate.

[0006] Optionally, the substrate includes a base and an epitaxial layer disposed on the surface of the base; the functional layer includes a first passivation layer, a first metal layer, an interlayer dielectric layer, a second metal layer, and a second passivation layer disposed sequentially along a direction away from the epitaxial layer.

[0007] Optionally, the first radio frequency switch group module includes N first radio frequency switch units and N groups of first control ports; the first control ports are connected to the first radio frequency switch units in a one-to-one correspondence; N is a positive integer greater than 1.

[0008] The second radio frequency switch group module includes M second radio frequency switch units and M groups of second control ports; the second control ports are connected to the second radio frequency switch units in a one-to-one correspondence; M is a positive integer greater than 1.

[0009] Optionally, the first RF switch group module further includes M groups of first redundant ports; the first redundant ports are connected one-to-one with the second RF switch unit through first interconnects;

[0010] And / or, the second RF switch module further includes N sets of second redundant ports; the second redundant ports are connected one-to-one with the first RF switch unit through the first interconnect line.

[0011] Optionally, the dicing groove is disposed in the area between the first region and the second region, excluding the region corresponding to the first interconnect line;

[0012] Alternatively, the dicing groove includes a first dicing groove and a second dicing groove; the first dicing groove is disposed in the region between the first region and the second region, excluding the region corresponding to the first interconnect; the second dicing groove is disposed in the region between the first region and the second region corresponding to the first interconnect; the bottom of the first dicing groove exposes the substrate; the bottom of the second dicing groove exposes a portion of the functional layer.

[0013] Optionally, the width of the region corresponding to the first interconnect line satisfies:

[0014] W×t<60μm 2 ;

[0015] In the formula, W represents the width of the region corresponding to the first interconnect; t represents the thickness of all dielectric layers in the functional layer.

[0016] Optionally, the first RF switch unit and the second RF switch unit have the same structure, both including an RF terminal, a common terminal and a ground terminal, and adjacent first RF switch units share a common terminal, and adjacent second RF switch units share a common terminal.

[0017] Optionally, the common terminal shared by adjacent first RF switch units is connected to the common terminal shared by adjacent second RF switch units one-to-one via a second interconnection line.

[0018] Optionally, the dicing groove is disposed in the area between the first region and the second region, excluding the region corresponding to the second interconnect line;

[0019] Alternatively, the dicing groove includes a first dicing groove and a second dicing groove; the first dicing groove is disposed in the region between the first region and the second region, excluding the region corresponding to the second interconnect; the second dicing groove is disposed in the region between the first region and the second region corresponding to the second interconnect; the bottom of the first dicing groove exposes the substrate; the bottom of the second dicing groove exposes a portion of the functional layer.

[0020] Optionally, the width of the region corresponding to the second interconnect is less than 15 μm.

[0021] To achieve the above objectives, this application also provides a method for fabricating a bare radio frequency switch chip, comprising:

[0022] An initial RF switch bare chip is provided; the initial RF switch bare chip includes a substrate, and a functional layer is disposed on the surface of the substrate; the functional layer includes a first region and a second region, and a third region between the first region and the second region; a first RF switch group module is disposed in the first region; and a second RF switch group module is disposed in the second region.

[0023] The functional layer etching window is defined in the third region;

[0024] The functional layer corresponding to the etching window of the functional layer is etched along the thickness direction to expose the substrate corresponding to the etching window of the functional layer, forming a dicing groove.

[0025] Optionally, the method for fabricating the RF switch bare chip further includes: cutting the initial RF switch bare chip along the dicing groove to obtain a first bare chip and a second bare chip.

[0026] Obviously, the RF switch bare chip provided in this application can achieve functional multiplexing capability by reusing the first RF switch group module and / or the second RF switch group module on the same substrate. Simultaneously, a dicing groove is added in the middle region between the first and second regions of the functional layer. This dicing groove is formed by etching away the functional layer to completely expose the substrate, thus creating an air gap. This is equivalent to replacing the high dielectric material of the original middle region with air. On the one hand, this reduces parasitic capacitance, thereby improving the isolation of the functional units; on the other hand, since the dielectric material of the middle region is etched away, the stress effect of cutting on the multilayer dielectric can be avoided during mechanical cutting of the dicing groove, avoiding the risk of peeling, reducing the probability of delamination, forming a reliable cutting surface without delamination paths, and preventing subsequent moisture erosion, thereby improving packaging reliability. Existing RF switch chips require reserved isolation areas to ensure functional unit isolation, while this application combines the function of the isolation area with the dicing groove design. The dicing groove can perform both functional cutting and RF isolation functions without additional area overhead; without increasing the chip size, it can simultaneously improve isolation and packaging dicing capability.

[0027] This application also provides a method for fabricating a bare RF switch chip. In the back-end process, the functional layer of the intermediate region between the first region and the second region is etched to fully expose the substrate and form a dicing groove to obtain the above-mentioned bare RF switch chip, which also has the above-mentioned beneficial effects. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a first type of radio frequency switch bare chip provided in the embodiments of this application;

[0030] Figure 2 This is a schematic diagram of the structure of a second type of radio frequency switch bare chip provided in the embodiments of this application;

[0031] Figure 3 A partial structural schematic diagram of the second type of radio frequency switch bare chip provided in the embodiments of this application;

[0032] Figure 4 This is a schematic diagram of the structure of a third type of radio frequency switch bare chip provided in the embodiments of this application;

[0033] Figure 5A partial structural schematic diagram of the third type of radio frequency switch bare chip provided in the embodiments of this application;

[0034] Figure 6 This is a schematic diagram of the structure of a fourth type of radio frequency switch bare chip provided in the embodiments of this application;

[0035] Figure 7 This is a schematic diagram of the structure of the fifth type of radio frequency switch bare chip provided in the embodiments of this application;

[0036] Figure 8 A flowchart illustrating a method for fabricating a bare RF switch chip, as provided in this application embodiment;

[0037] Figure 9 This is a layout of an existing RF switch bare chip;

[0038] Figure 10 This is a schematic diagram of the structure of an existing radio frequency switch bare chip;

[0039] Figure 11 This is a schematic diagram of the SP2T RF switch bare chip obtained by cutting the lower half of an existing RF switch bare chip.

[0040] Figure 12 This is a schematic diagram of the structure of the SP2T RF switch bare chip obtained by cutting off the upper half of the existing RF switch bare chip and rotating it 180 degrees.

[0041] Figure 13 This is a schematic diagram showing the location of four SP4T RF switch bare chips on a wafer.

[0042] Figure 14 This is a schematic diagram of the SP4T RF switch bare chip cutting process;

[0043] Figure 15 This is a schematic diagram of the cutting process of the bare chip for the SP2T RF switch.

[0044] The annotations in the attached figures are explained as follows:

[0045] 1-Substrate; 11-First RF switch module; 12-Second RF switch module; 13-Scribble groove; 14-Sealing ring;

[0046] 111 - First RF switch unit; 112 - First control port; 113 - First redundant port;

[0047] 121 - Second RF switch unit; 122 - Second control port; 123 - Third redundant port;

[0048] 1111 - Radio frequency terminal; 1112 - Common terminal; 1113 - Ground terminal; 1114 - First interconnect; 1115 - Second interconnect. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a first type of radio frequency switch bare chip provided in the embodiments of this application. The structure may include: a substrate 1, on the surface of the substrate 1, a functional layer is disposed thereon; the functional layer includes a first region and a second region; a first radio frequency switch group module 11 is disposed thereon in the first region; a second radio frequency switch group module 12 is disposed thereon in the second region; a dicing groove 13 is disposed between the first region and the second region; the bottom of the dicing groove 13 exposes the substrate 1.

[0051] It should be noted that the substrate 1 in this embodiment includes a substrate and an epitaxial layer disposed on the surface of the substrate. The substrate 1 in this embodiment is a stacked structure composed of a substrate and an epitaxial layer disposed sequentially along the thickness direction. The functional layer is disposed on the side surface of the epitaxial layer away from the substrate, so the bottom of the dicing groove 13 exposes the epitaxial layer.

[0052] This embodiment does not limit the specific type of substrate; the substrate may be, but is not limited to, a Si substrate. This embodiment also does not limit the specific type of epitaxial layer; the epitaxial layer may include a GaN epitaxial layer or a GaAs epitaxial layer.

[0053] This embodiment is applicable to various substrate processes such as GaAs, GaN, SOI (Silicon-On-Insulator), and CMOS (Complementary Metal-Oxide-Semiconductor), and has versatility.

[0054] This embodiment does not limit the specific type of functional layer, which can be determined according to the actual situation. For example, the functional layer may include a first passivation layer, a first metal layer, an interlayer dielectric layer, a second metal layer, and a second passivation layer arranged sequentially along the direction away from the epitaxial layer. It should be noted that the first RF switch group module 11 and the second RF switch group module 12 in this embodiment are circuit functional units formed by the functional layer.

[0055] This embodiment does not limit the specific type of the first passivation layer, as long as it can ensure insulation. For example, the first passivation layer may include a SiN layer.

[0056] This embodiment does not limit the specific type of interlayer dielectric layer, as long as it can ensure insulation. For example, the interlayer dielectric layer may include stacked SiN layer, and / or SiO2 layer, and / or BCB (Benzocyclobutene) layer, and / or PI (Polyimide) layer.

[0057] It should be noted that this embodiment does not limit the specific number of metal layers. In addition to including a first metal layer and a second metal layer, a third metal layer, a fourth metal layer, etc., may also be included between the first passivation layer and the second passivation layer. It should also be noted that an interlayer dielectric layer needs to be provided between adjacent metal layers.

[0058] This embodiment does not limit the specific type of the second passivation layer, as long as it can protect the underlying film layer. For example, the second passivation layer may include a stacked BCB layer, and / or a PI layer, and / or a SiN layer.

[0059] It should be noted that the SiN layer is a dense film. While it can block moisture, its high dielectric constant leads to significant parasitic capacitance. Therefore, adding a thicker layer of a low-dielectric-constant material, such as a BCB or PI layer, to the surface of the SiN layer can reduce parasitic capacitance. A thicker BCB or PI layer reduces stress concentration, prevents crack propagation, reduces parasitic capacitance, improves high-frequency characteristics, and provides good leveling and surface smoothness.

[0060] Please refer to the following content. Figure 2 , Figure 2 This is a schematic diagram of the structure of a second type of radio frequency switch bare chip provided in an embodiment of this application.

[0061] This embodiment does not limit the specific structure of the first RF switch group module 11, as long as it can implement multiple types of RF switches. For example, the first RF switch group module 11 may include N first RF switch units 111 and N sets of first control ports 112; the first control ports 112 are connected one-to-one with the first RF switch units 111; N is a positive integer greater than 1. It should be noted that the first RF switch units 111 can be controlled through the first control ports 112. Each set of first control ports 112 may include a control terminal 112S of the first series branch and a control terminal 112P of the first parallel branch.

[0062] This embodiment does not limit the specific structure of the second RF switch group module 12, as long as it can implement multiple types of RF switches. For example, the second RF switch group module 12 may include M second RF switch units 121 and M groups of second control ports 122; the second control ports 122 are connected one-to-one with the second RF switch units 121; M is a positive integer greater than 1. It should be noted that the second RF switch units 121 can be controlled through the second control ports 122. Each group of second control ports 122 may include the control terminal 122S of the second series branch and the control terminal 122P of the second parallel branch.

[0063] It should be noted that in this embodiment, a dicing groove 13 is provided between the first region and the second region. When an SPNT and / or SPMT type RF switch is required, the dicing groove 13 can be physically cut to separate the first region and the second region, forming two independent bare RF switch chips. The first region obtained after cutting and its covering substrate 1 constitute an SPNT RF switch bare chip; the second region obtained after cutting and its covering substrate 1 constitute an SPMT RF switch bare chip. When an SP(N+M)T type RF switch is required, an uncut RF switch bare chip can be used directly. This embodiment is applicable to various multi-channel RF chip structures (such as SP2T, SP4T, etc.) and has versatility.

[0064] In this embodiment, N and M can be the same or different, depending on the actual situation. Preferably, N and M can be the same, and the first RF switch group and the second RF switch group can be symmetrically arranged to make full use of the entire wafer and substrate 1.

[0065] Furthermore, in this embodiment, the first RF switch group module 11 may further include M groups of first redundant ports 113; the first redundant ports 113 are connected one-to-one with the second RF switch unit 121 through the first interconnecting line 1114; and / or, the second RF switch group module 12 may further include N groups of second redundant ports; the second redundant ports are connected one-to-one with the first RF switch unit 111 through the first interconnecting line 1114. It should be noted that in this embodiment, the first redundant port 113 can be used as the control port of the second RF switch unit 121, and the second redundant port can be used as the control port of the first RF switch unit 111. By setting the first redundant port 113 and / or the second redundant port, the control ports of the first RF switch unit 111 and the second RF switch unit 121 can be integrated into one area, which facilitates the simultaneous control of all RF switch units. Each group of first redundant ports 113 may include a control terminal 113S of the third series branch and a control terminal 113P of the third parallel branch; the first interconnecting line 1114 may include a first line 1114S and a second line 1114P; the first line 1114S connects the control terminal 122S of the second series branch and the control terminal 113S of the third series branch; the second line 1114P connects the control terminal 122P of the second parallel branch and the control terminal 113P of the third parallel branch. The second redundant ports are similar and will not be described in detail here.

[0066] It should be noted that in this embodiment, the first interconnect line 1114 crosses the dicing groove 13, and the first interconnect line 1114 will be disconnected after the dicing groove 13 is physically cut.

[0067] This embodiment does not limit the specific type of the first interconnect 1114, as long as it can conduct electricity. For example, the first interconnect 1114 may include a metal wire. This embodiment does not limit the specific location of the first interconnect 1114. For example, the first interconnect 1114 may be located in the first metal layer and / or the second metal layer.

[0068] When this embodiment includes the first interconnect line 1114, the dicing groove 13 may include the following two structures:

[0069] (1) The dicing groove 13 can be set in the area between the first region and the second region other than the area corresponding to the first interconnection line 1114;

[0070] (2) The dicing groove 13 may include a first dicing groove and a second dicing groove; the first dicing groove is disposed in the area between the first region and the second region other than the area corresponding to the first interconnect 1114; the second dicing groove is disposed in the area between the first region and the second region corresponding to the first interconnect 1114; the bottom of the first dicing groove exposes the substrate 1; the bottom of the second dicing groove exposes part of the functional layer.

[0071] It should be noted that in this embodiment, structure (1) retains the functional layer of the region corresponding to the first interconnect 1114 between the first region and the second region, and removes the functional layer of the remaining region between the first region and the second region. This ensures that the first interconnect 1114 can be covered by the dielectric, thereby protecting the first interconnect 1114 and preventing its oxidation; at the same time, it ensures a larger dicing groove area 13. In this embodiment, structure (2) further removes part of the functional layer of the region corresponding to the first interconnect 1114 between the first region and the second region based on structure (1). This can minimize the dielectric, thereby reducing the risk of stripping and reducing parasitic capacitance.

[0072] For structure (2), when the first interconnect 1114 is located in the first metal layer, this embodiment can remove the second passivation layer of the region corresponding to the first interconnect 1114 between the first region and the second region, so that the bottom of the second dicing groove 13 can expose the interlayer dielectric layer. The retained interlayer dielectric layer can protect the first interconnect 1114 and prevent the first interconnect 1114 from oxidizing.

[0073] Furthermore, in this embodiment, when only the first RF switch group module 11 includes the first redundant port 113, the second RF switch group module 12 may also include a third redundant port 123; or in this embodiment, when only the second RF switch group module 12 includes the second redundant port, the first RF switch group module 11 may also include a third redundant port 123. The third redundant port 123 may be an empty pin. Adding the third redundant port 123 can ensure that the ports of the first RF switch group module 11 and the ports of the second RF switch group module 12 are symmetrical. Furthermore, for ease of connection, in this embodiment, the first control port 112, the second control port 122, the first redundant port 113, the second redundant port, and the third redundant port 123 may all be provided with pads (metal blocks).

[0074] In this embodiment, the structures of the first RF switch unit 111 and the second RF switch unit 121 can be the same or different, depending on the actual situation. Preferably, the structures of the first RF switch unit 111 and the second RF switch unit 121 can be the same to ensure product consistency when cut into two independent RF switch bare chips.

[0075] This embodiment does not limit the specific structure of the first RF switch unit 111 and the second RF switch unit 121, as long as the switching function can be achieved. For example, both the first RF switch unit 111 and the second RF switch unit 121 may include an RF terminal 1111, a common terminal 1112, and a ground terminal 1113, and adjacent first RF switch units 111 and adjacent second RF switch units 121 may share the common terminal 1112. It should be noted that in this embodiment, the RF terminal 1111 can be used as an input terminal or an output terminal; the common terminal 1112 can be used to connect an antenna.

[0076] This embodiment does not limit the specific arrangement of the RF terminal 1111, the common terminal 1112 and the ground terminal 1113 within the same RF switch unit. It can be determined according to the actual situation. For example, the RF terminal 1111 and the ground terminal 1113 can be set on the same side, and the common terminal 1112 can be set on the opposite side.

[0077] In this embodiment, the common terminal 1112 shared by adjacent first RF switch units 111 can be connected one-to-one with the common terminal 1112 shared by adjacent second RF switch units 121 through the second interconnection line 1115; the common terminal 1112 shared by adjacent first RF switch units 111 can also be not connected to the common terminal 1112 shared by adjacent second RF switch units 121, but can be led out through bonding wires and connected together inside the package.

[0078] It should be noted that in this embodiment, the second interconnect line 1115 crosses the dicing groove 13, and the second interconnect line 1115 will be disconnected after the dicing groove 13 is physically cut.

[0079] This embodiment does not limit the specific type of the second interconnect 1115, as long as it can conduct electricity. For example, the second interconnect 1115 may include a metal wire. This embodiment does not limit the specific location of the second interconnect 1115. For example, the second interconnect 1115 may be located in the first metal layer and / or the second metal layer.

[0080] When this embodiment includes the second interconnect line 1115, the dicing groove 13 may include the following two structures:

[0081] (1) The dicing groove 13 can be set in the area between the first region and the second region other than the area corresponding to the second interconnection line 1115;

[0082] (2) The dicing groove 13 may include a first dicing groove and a second dicing groove; the first dicing groove is disposed in the area between the first region and the second region other than the area corresponding to the second interconnect 1115; the second dicing groove is disposed in the area between the first region and the second region corresponding to the second interconnect 1115; the bottom of the first dicing groove exposes the substrate 1; the bottom of the second dicing groove exposes part of the functional layer.

[0083] It should be noted that in this embodiment, structure (1) retains the functional layer of the region corresponding to the second interconnect 1115 between the first region and the second region, and removes the functional layer of the remaining region between the first region and the second region. This ensures that the second interconnect 1115 can be covered by the dielectric, thereby protecting the second interconnect 1115 and preventing its oxidation; at the same time, it ensures a larger dicing groove area 13. In this embodiment, structure (2) further removes part of the functional layer of the region corresponding to the second interconnect 1115 between the first region and the second region based on structure (1). This can minimize the dielectric, thereby reducing the risk of stripping and reducing parasitic capacitance.

[0084] For structure (2), when the second interconnect 1115 is located in the first metal layer, this embodiment can remove the second passivation layer of the region corresponding to the second interconnect 1115 between the first region and the second region, so that the bottom of the second dicing groove 13 can expose the interlayer dielectric layer. The retained interlayer dielectric layer can protect the second interconnect 1115 and prevent the second interconnect 1115 from oxidizing.

[0085] Based on the above embodiments, this application achieves functional multiplexing capability by reusing the first RF switch group module and / or the second RF switch group module on the same substrate. Simultaneously, a dicing groove is added in the middle region between the first and second regions of the functional layer. This dicing groove is formed by etching away the functional layer to completely expose the substrate, creating an air gap. This is equivalent to replacing the high-dielectric-constant dielectric material in the original middle region with air. On the one hand, this reduces parasitic capacitance, thereby improving the isolation of the functional units; on the other hand, because the dielectric material in the middle region is etched away, the stress effect of cutting on the multilayer dielectric can be avoided during mechanical cutting of the dicing groove, avoiding the risk of peeling, reducing the probability of delamination, forming a reliable cut surface without delamination paths, and preventing subsequent moisture erosion, thereby improving packaging reliability. This application enables a multi-functional RF chip structure that balances high isolation and dicability without increasing area; it reduces the risk of packaging failures such as dielectric stripping, improves packaging reliability, and increases yield; it maintains multi-mode functional reuse and packaging uniformity, facilitating mass production and unified inventory management; its structural design is highly versatile and can be widely used in PA (Power Amplifier), switches, LNA (Low-Noise Amplifier), etc.; it is compatible with large-scale tape-out platforms (such as GaN, GaAs, SOI) and has product platformization capabilities.

[0086] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of the second type of RF switch bare chip provided in this application embodiment. Unlike the first type of RF switch bare chip embodiment, this embodiment further adds a sealing ring 14. The sealing ring 14 can be the sealing ring in patent CN119890145A. The remaining details have been described in detail in the first type of RF switch bare chip embodiment and will not be repeated here.

[0087] In this embodiment, a sealing ring 14 is also provided on the surface of the substrate 1.

[0088] This embodiment does not limit the specific arrangement of the sealing ring 14. For example, the sealing ring 14 can surround the functional layer; and / or, the sealing ring 14 can cover the side wall of the dicing groove 13 near the first region and the side wall near the second region.

[0089] It should be noted that in this embodiment, sealing rings 14 are provided around the functional layer, which can suppress crack propagation, achieve passivation of the package boundary, prevent moisture intrusion, and prevent lateral dielectric failure. In this embodiment, sealing rings 14 can also be added to both sides of the pre-reserved dicing groove 13 in the middle. When used for SPNT or SPMT RF switch bare chips, the sealing rings 14 can also perform the above-mentioned functions when cutting the dicing groove 13.

[0090] This embodiment does not limit the specific type of the sealing ring 14, as long as it can achieve a sealing function. For example, the sealing ring 14 may include multiple stacked virtual metal layers. It should be noted that the virtual metal layer refers to a redundant metal layer that does not actually participate in the circuit connection.

[0091] It should be noted that the edge sealing ring 14 is a stacked multi-layer virtual metal layer. For the edge sealing ring 14 set in the middle area, the edge sealing ring 14 is interrupted at the position of the first interconnect line 1114, as shown below. Figure 3 As shown.

[0092] In this embodiment, the sealing ring 14 surrounding the functional layer may be discontinuous or continuously closed.

[0093] Furthermore, in order to ensure the best effect of the sealing ring 14, in this embodiment the sealing ring 14 can be grounded to maintain the lowest potential, which can improve the resistance to water vapor diffusion.

[0094] Based on the above embodiments, this application further adds a sealing ring on the basis of the above-mentioned dicing groove, which can greatly enhance the packaging reliability.

[0095] Please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of a third type of RF switch bare chip provided in this application embodiment. Unlike the first type of RF switch bare chip embodiment, this embodiment further specifies the structure of the first RF switch group module 11 and the second RF switch group module 12 based on the first type of RF switch bare chip embodiment. The remaining details have been described in detail in the first type of RF switch bare chip embodiment and will not be repeated here.

[0096] In this embodiment, the first radio frequency switch group module 11 includes N first radio frequency switch units 111 and N groups of first control ports 112; the first control ports 112 are connected to the first radio frequency switch units 111 in a one-to-one correspondence; N is a positive integer greater than 1; the second radio frequency switch group module 12 includes M second radio frequency switch units 121 and M groups of second control ports 122; the second control ports 122 are connected to the second radio frequency switch units 121 in a one-to-one correspondence; M is a positive integer greater than 1;

[0097] The first RF switch group module 11 further includes M groups of first redundant ports 113; the first redundant ports 113 are connected one-to-one with the second RF switch unit 121 through the first interconnect line 1114; and / or, the second RF switch group module 12 further includes N groups of second redundant ports; the second redundant ports are connected one-to-one with the first RF switch unit 111 through the first interconnect line 1114.

[0098] Meanwhile, the first radio frequency switch unit 111 and the second radio frequency switch unit 121 have the same structure, both including a radio frequency terminal 1111, a common terminal 1112 and a ground terminal 1113, and adjacent first radio frequency switch units 111 share the common terminal 1112, and adjacent second radio frequency switch units 121 share the common terminal 1112.

[0099] The common terminal 1112 shared by adjacent first RF switch units 111 is not connected to the common terminal 1112 shared by adjacent second RF switch units 121. Instead, they are led out through bonding wires and connected together inside the package.

[0100] In this embodiment, the dicing groove 13 is located in the area between the first region and the second region, excluding the region corresponding to the first interconnect line 1114.

[0101] It should be noted that in this embodiment, the wire-passing window is only retained at the edge position where the first interconnect 1114 needs to be retained. This can ensure that the first interconnect 1114 can be covered by the medium, thereby protecting the first interconnect 1114 and preventing the first interconnect 1114 from oxidation; at the same time, it ensures a larger dicing groove area 13.

[0102] Furthermore, such as Figure 5 As shown, in this embodiment, the width of the region corresponding to the first interconnect 1114 can satisfy:

[0103] W×t<60μm 2 ;

[0104] In the formula, W represents the width of the region corresponding to the first interconnect 1114; t represents the thickness of all dielectric layers in the functional layer. The thicker the dielectric layer, the smaller the width W that needs to be reserved. For example, for a dielectric layer with a total thickness of 3μm (including stacked SiN, BCB, PI, and SiN layers), the width W that needs to be reserved is less than 20μm.

[0105] Please refer to Figure 6 , Figure 6 This is a schematic diagram of the structure of the fourth type of RF switch bare chip provided in this application embodiment. The structure of the first RF switch group module 11 and the second RF switch group module 12 in this embodiment is the same as that of the third type of RF switch bare chip embodiment.

[0106] Unlike the second RF switch bare chip embodiment, in this embodiment the dicing groove 13 includes a first dicing groove and a second dicing groove; the first dicing groove is disposed in the area between the first region and the second region other than the area corresponding to the first interconnect 1114; the second dicing groove is disposed in the area between the first region and the second region corresponding to the first interconnect 1114; the bottom of the first dicing groove exposes the substrate 1; the bottom of the second dicing groove exposes part of the functional layer.

[0107] It should be noted that this embodiment further removes part of the functional layer of the region corresponding to the first interconnect 1114 between the first region and the second region, which can minimize the dielectric, thereby reducing the risk of stripping and reducing parasitic capacitance.

[0108] Please refer to Figure 7 , Figure 7 This is a schematic diagram of the structure of the fifth type of RF switch bare chip provided in this application embodiment. Unlike the third type of RF switch bare chip embodiment, this embodiment further defines that the common terminal 1112 shared by adjacent first RF switch units 111 is connected to the common terminal 1112 shared by adjacent second RF switch units 121 through the second interconnect line 1115.

[0109] In this embodiment, the dicing groove 13 is located in the area between the first region and the second region, excluding the areas corresponding to the first interconnect line 1114 and the second interconnect line 1115.

[0110] It should be noted that in this embodiment, the wire-passing window is reserved only at the edge position where the first interconnect 1114 needs to be retained and at the middle position where the second interconnect 1115 needs to be retained. That is, the dicing groove 13 is set between adjacent wire-passing windows, which can ensure that the first interconnect 1114 and the second interconnect 1115 can be covered by the medium, thereby protecting the first interconnect 1114 and the second interconnect 1115 and preventing oxidation of the first interconnect 1114 and the second interconnect 1115; at the same time, it ensures a large dicing groove 13 area.

[0111] Furthermore, in this embodiment, the width of the region corresponding to the second interconnect 1115 can be less than 15μm.

[0112] Furthermore, in this embodiment, the dicing groove 13 may include a first dicing groove, a second dicing groove, and / or a third dicing groove; the first dicing groove is disposed in the region between the first region and the second region, excluding the regions corresponding to the first interconnect 1114 and the second interconnect 1115; the bottom of the first dicing groove exposes the substrate 1; the second dicing groove is disposed in the region corresponding to the first interconnect 1114 between the first region and the second region; the bottom of the second dicing groove exposes a portion of the functional layer; the third dicing groove is disposed in the region corresponding to the second interconnect 1115 between the first region and the second region; the bottom of the third dicing groove exposes a portion of the functional layer.

[0113] Please refer to Figure 8 , Figure 8 A flowchart illustrating a method for fabricating a radio frequency switch bare chip, provided in this application embodiment, includes:

[0114] S101: Provides an initial RF switch bare chip; the initial RF switch bare chip includes a substrate, and a functional layer is disposed on the surface of the substrate; the functional layer includes a first region and a second region, and a third region between the first region and the second region; a first RF switch group module is disposed in the first region; a second RF switch group module is disposed in the second region.

[0115] This embodiment does not limit the specific types and structures of substrate 1, functional layer, first RF switch group module 11 and second RF switch group module 12. You can refer to the above embodiment of RF switch bare chip, which will not be repeated here.

[0116] This embodiment does not limit the specific method of providing the initial RF switch bare chip, and can be determined according to the specific structure of the initial RF switch bare chip, for example, it may include:

[0117] Substrate 1 is provided;

[0118] A functional layer and a sealing ring are formed on the surface of the substrate 1, and the sealing ring 14 surrounds the functional layer; and / or, the sealing ring 14 covers the side wall of the dicing groove 13 near the first region and the side wall near the second region.

[0119] It should be noted that the sealing ring 14 in this embodiment can suppress crack propagation, achieve passivation of the encapsulation boundary, block moisture intrusion, and prevent lateral failure of the medium.

[0120] S102: Define the functional layer etching window in the third region.

[0121] It should be noted that the specific structure of the first RF switch group module 11 and the second RF switch group module 12 in this embodiment determines the specific structure of the dicing groove 13, and the specific structure of the dicing groove 13 determines the specific structure of the functional layer etching window.

[0122] When this embodiment includes the first interconnect line 1114, the dicing groove 13 may include the following two structures:

[0123] (1) The dicing groove 13 can be set in the area between the first region and the second region other than the area corresponding to the first interconnect 1114; correspondingly, the functional layer etching window can be the area in the third region other than the area corresponding to the first interconnect 1114.

[0124] (2) The dicing groove 13 may include a first dicing groove and a second dicing groove; the first dicing groove is disposed in the area between the first region and the second region other than the area corresponding to the first interconnect 1114; the second dicing groove is disposed in the area between the first region and the second region corresponding to the first interconnect 1114; the bottom of the first dicing groove exposes the substrate 1; the bottom of the second dicing groove exposes part of the functional layer.

[0125] Accordingly, the functional layer etching window may include a first functional layer etching window and a second functional layer etching window; the first functional layer etching window is the area in the third region other than the area corresponding to the first interconnect 1114; the second functional layer etching window is the area in the third region corresponding to the first interconnect 1114.

[0126] In this process, the functional layer corresponding to the etching window of the first functional layer can be etched along the thickness direction to expose the substrate 1 corresponding to the etching window of the first functional layer and form the first dicing groove.

[0127] The second functional layer can be etched along the thickness direction to expose the second functional layer corresponding to the etching window, thus forming the second dicing groove.

[0128] When this embodiment includes the second interconnect line 1115, the dicing groove 13 may include the following two structures:

[0129] (1) The dicing groove 13 can be set in the area between the first region and the second region other than the area corresponding to the second interconnect 1115; correspondingly, the functional layer etching window can be the area in the third region other than the area corresponding to the second interconnect 1115.

[0130] (2) The dicing groove 13 may include a first dicing groove and a second dicing groove; the first dicing groove is disposed in the area between the first region and the second region other than the area corresponding to the second interconnect 1115; the second dicing groove is disposed in the area between the first region and the second region corresponding to the second interconnect 1115; the bottom of the first dicing groove exposes the substrate 1; the bottom of the second dicing groove exposes part of the functional layer.

[0131] Accordingly, the functional layer etching window may include a first functional layer etching window and a second functional layer etching window; the first functional layer etching window is the area in the third region other than the area corresponding to the second interconnect 1115; the second functional layer etching window is the area in the third region corresponding to the second interconnect 1115.

[0132] In this process, the functional layer corresponding to the etching window of the first functional layer can be etched along the thickness direction to expose the substrate 1 corresponding to the etching window of the first functional layer and form the first dicing groove.

[0133] The second functional layer can be etched along the thickness direction to expose the second functional layer corresponding to the etching window, thus forming the second dicing groove.

[0134] When this embodiment includes the first interconnect 1114 and the second interconnect 1115, the dicing groove 13 may include the following two structures:

[0135] (1) The dicing groove 13 is set in the area between the first region and the second region other than the area corresponding to the first interconnect 1114 and the second interconnect 1115; correspondingly, the functional layer etching window can be the area in the third region other than the area corresponding to the first interconnect 1114 and the second interconnect 1115.

[0136] (2) The dicing groove 13 may include a first dicing groove, a second dicing groove and / or a third dicing groove; the first dicing groove is disposed in the region between the first region and the second region other than the regions corresponding to the first interconnect 1114 and the second interconnect 1115; the bottom of the first dicing groove exposes the substrate 1; the second dicing groove is disposed in the region corresponding to the first interconnect 1114 between the first region and the second region; the bottom of the second dicing groove exposes a portion of the functional layer; the third dicing groove 13 is disposed in the region corresponding to the second interconnect 1115 between the first region and the second region; the bottom of the third dicing groove exposes a portion of the functional layer;

[0137] Accordingly, the functional layer etching window may include a first functional layer etching window, a second functional layer etching window, and / or a third functional layer etching window; the first functional layer etching window is the area in the third region other than the areas corresponding to the first interconnect 1114 and the second interconnect 1115; the second functional layer etching window is the area corresponding to the first interconnect 1114 in the third region; and the third functional layer etching window is the area corresponding to the second interconnect 1115 in the third region.

[0138] In this process, the functional layer corresponding to the etching window of the first functional layer can be etched along the thickness direction to expose the substrate 1 corresponding to the etching window of the first functional layer and form the first dicing groove.

[0139] A portion of the functional layer corresponding to the etching window of the second functional layer can be etched along the thickness direction to expose the portion of the functional layer corresponding to the etching window of the second functional layer, thus forming a second dicing groove.

[0140] The third functional layer can be etched along the thickness direction to expose the third functional layer corresponding to the etching window, thus forming the second dicing groove.

[0141] S103: Etch the functional layer corresponding to the etching window along the thickness direction to expose the substrate corresponding to the etching window and form a dicing groove.

[0142] It should be noted that the specific type of functional layer in this embodiment, as well as the positions of the first interconnect 1114 and the second interconnect 1115, determine the specific film layer to be etched.

[0143] When the functional layer in this embodiment includes a first passivation layer, a first metal layer, an interlayer dielectric layer, a second metal layer, and a second passivation layer arranged sequentially along the direction away from the epitaxial layer, the second passivation layer, the interlayer dielectric layer, and the first passivation layer corresponding to the functional layer etching window (the functional layer corresponding to the functional layer etching window includes the first passivation layer, the interlayer dielectric layer, and the second passivation layer) can be etched sequentially along the thickness direction to expose the substrate 1 corresponding to the functional layer etching window.

[0144] Furthermore, when this embodiment includes a first interconnect 1114 and / or a second interconnect 1115, and both the first interconnect 1114 and the second interconnect 1115 are located in the first metal layer, the second passivation layer corresponding to the functional layer etching window (the functional layer corresponding to the functional layer etching window includes a first passivation layer, a first metal layer, an interlayer dielectric layer, a second metal layer, and a second passivation layer) can be etched along the thickness direction to expose the interlayer dielectric layer corresponding to the functional layer etching window.

[0145] This embodiment does not limit the specific etching method, as long as the corresponding functional layer can be removed. For example, plasma etching can be used to etch the functional layer corresponding to the etching window along the thickness direction, exposing the substrate 1 corresponding to the etching window of the functional layer, and forming a dicing groove 13.

[0146] Furthermore, in this embodiment, different plasma etching methods can be used for different films in the functional layer. For example, for the SiN layer, a dry plasma etching method can be used; for the PI layer, an O2 plasma ashing method can be used; and for the BCB layer, a mixed etching method of O2, Ar and CF4 plasma can be used.

[0147] It should be noted that the functional layer is etched using semiconductor technology in this embodiment, which has high precision, and the edges of the etched functional layer remain dense. For the SP(N+M)T RF switch bare chip, the dicing groove 13 does not need to be cut, the edges of the functional layer remain dense, and moisture intrusion can also be prevented.

[0148] Furthermore, when SPNT and / or SPMT type RF switches are required, this embodiment may further include: cutting the initial RF switch bare chip along the dicing groove to obtain a first bare chip and a second bare chip; wherein, the first bare chip may be an SPNT RF switch bare chip; and the second bare chip may be an SPMT RF switch bare chip.

[0149] Based on the above embodiments, in the back-end process, this application obtains the above-mentioned RF switch bare chip by etching the functional layer of the intermediate region between the first region and the second region and fully exposing the substrate to form a dicing groove, which also has the above-mentioned beneficial effects.

[0150] The following examples illustrate the beneficial effects of the radio frequency switch bare chip and its fabrication method provided in this application compared to the prior art.

[0151] Please refer to Figure 9 and Figure 10 , Figure 9 This is a layout of an existing RF switch bare chip. Figure 10 This is a schematic diagram of the structure of a conventional RF switch bare chip. The first region of this RF switch bare chip includes: a first RF switch unit 111, comprising RF switch unit A and RF switch unit B; a first control port 112, comprising control port AS, control port AP, control port BS, and control port BP; and a first redundant port 113, comprising control port CS, control port CP, control port DS, and control port DP. The first redundant port 113 is connected to RF switch unit C and RF switch unit D via a first interconnect line 1114.

[0152] The second area is provided with: a second radio frequency switch unit 121, including radio frequency switch unit C and radio frequency switch unit D; a second control port 122, including control port CS, control port CP, control port DS and control port DP; and a third redundant port 123, including an empty pin NC.

[0153] RF switch unit A includes an RF terminal RFA and a ground terminal GNDA, as well as a common terminal ANT_AB shared with RF switch unit B; RF switch unit B includes an RF terminal RFB and a ground terminal GNDB, as well as a common terminal ANT_AB shared with RF switch unit A.

[0154] Radio frequency switch unit C includes a radio frequency terminal RFC and a ground terminal GNDC, as well as a common terminal ANT_CD shared with radio frequency switch unit D; radio frequency switch unit D includes a radio frequency terminal RFD and a ground terminal GNDD, as well as a common terminal ANT_CD shared with radio frequency switch unit C.

[0155] The common terminal ANT_AB shared by RF switch unit A and RF switch unit B is connected to the common terminal ANT_CD shared by RF switch unit C and RF switch unit D through the second interconnect line.

[0156] The entire RF switch bare chip can be used as an SP4T RF switch bare chip. The first and second regions adopt a completely symmetrical design, and the corresponding parts can be used as SP2T RF switch bare chips respectively. The SP2T RF switch bare chips and SP4T RF switch bare chips reuse masks and wafers.

[0157] All structures on the same substrate 1 are treated as a single die, with a dicing channel introduced in the middle of the die. When used as a bare SP4T RF switch chip, the dicing channel in the middle is not cut, and the upper and lower second interconnects 1115 remain connected, allowing the control port below to perform the control functions of the bare SP4T RF switch chip.

[0158] When used as a bare SP2T RF switch chip, it is cut in the middle, and both the first interconnect 1114 and the second interconnect 1115 are cut, resulting in the following... Figure 11 and Figure 12 The two complete SP2T RF switch bare chips are shown. Figure 11 The SP2T RF switch bare chip shown is controlled using the control ports AP, AS, BS, and BP shown below. Figure 12 The SP2T RF switch bare chip shown is a... Figure 9 The SP2T RF switch bare chip obtained from the upper and middle sections was rotated 180 degrees. After the 180-degree rotation, it was compared with... Figure 11 The SP2T RF switch bare chips shown are completely identical, and control is achieved using the control ports CP, CS, DS, and DP on the top. Therefore, after cutting, the SP4T RF switch bare chip can be used as two SP2T RF switch bare chips, facilitating mass production and unified inventory management.

[0159] However, although a gap is set in the middle, which can be used as a dicing groove 13, there are two problems:

[0160] 1. Parasitic capacitance of the dielectric degrades isolation:

[0161] In the intermediate interval region, there are still intact dielectric materials, such as SiN, PI and BCB, with dielectric constants of 7, 4 and 2.9 respectively. These materials will introduce parasitic capacitance, which will lead to a deterioration in the isolation between the upper and lower functional units of the switch.

[0162] 2. Cutting stress causes delamination, affecting reliability:

[0163] When used for bare chips in SP2T RF switches, cutting introduces mechanical stress, causing the entire dielectric layer to peel off, ultimately leading to delamination. Although the stress from laser cutting is relatively small, it cannot be completely eliminated, and laser cutting also has thickness limitations. Mechanical cutting is the most serious.

[0164] To enhance the isolation between two functional units, a certain physical distance is usually placed between them. For example, placing a certain distance between RF switch unit A and RF switch unit C, or between RF switch unit B and RF switch unit D, can improve the isolation between RF switch unit A and RF switch unit C, and between RF switch unit B and RF switch unit D.

[0165] Based on this, this application uses this physical distance to pre-define a dicing slot 13 as a cutting channel for multiplexing SP4T RF switch bare chips and SP2T RF switch bare chips, which will not significantly increase the additional area; however, the design of redundant ports will increase the area compared to dedicated SP4T RF switch bare chips.

[0166] Please refer to Figures 13 to 15 , Figure 13 This is a schematic diagram showing the location of four SP4T RF switch bare chips on a wafer. Figure 14 This is a schematic diagram of the SP4T RF switch bare chip cutting process; Figure 15 This is a schematic diagram of the SP2T RF switch bare chip dicing process. Dicing grooves 13 are provided around each SP4T die to dice the wafer into four independent SP4T dies. In this application, dicing grooves 13 formed by etching medium are added between RF switch units A and B and RF switch units C and D inside each SP4T die. The specific etching process includes:

[0167] (1) Define a dielectric etching window in the dicing area in the middle of the RF switch bare chip (such as the middle area of ​​the SP4T RF switch bare chip);

[0168] (2) In the subsequent process, plasma etching is used to remove the following media in sequence: the passivation layer on top of the second metal layer, the interlayer dielectric layer between the second metal layer and the first metal layer, and the passivation layer at the bottom of the first metal layer, so that the middle area is completely exposed to the epitaxial layer, forming a reliable cutting surface without delamination path, and replacing the high dielectric constant dielectric material with air.

[0169] The above-mentioned dielectric etching process is carried out in the fab (fabrication) plant using semiconductor processes such as dry and wet methods, which have high precision. The edges of the etched dielectric should still be dense. For the SP4T RF switch bare chip, no cutting is done in the middle, and the edges of the dielectric are still dense, which can also prevent moisture intrusion.

[0170] Furthermore, etching the dielectric material effectively creates an air gap. This is equivalent to replacing the dielectric with air, reducing parasitic capacitance and thus improving isolation. Simultaneously, because the dielectric in the middle region is etched away, the stress on the multi-layered dielectric is avoided during mechanical cutting, preventing the risk of delamination, reducing the probability of delamination, and creating a reliable cut surface without delamination paths. This prevents subsequent moisture erosion and improves packaging reliability.

[0171] This document uses specific examples to illustrate the principles and implementation methods of this application. The various embodiments are progressive, with each embodiment focusing on its differences from others. Similar or identical parts between embodiments can be referred to interchangeably. The descriptions of the embodiments above are merely illustrative of the method and core ideas of this application. For those skilled in the art, various improvements and modifications can be made to this application without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims of this application.

[0172] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

Claims

1. A radio frequency switch bare chip, characterized in that, include: A substrate (1) has a functional layer on its surface; the functional layer includes a first region and a second region; a first radio frequency switch module (11) is provided in the first region; a second radio frequency switch module (12) is provided in the second region; a dicing groove (13) is provided between the first region and the second region; the bottom of the dicing groove (13) exposes the substrate (1).

2. The RF switch bare chip according to claim 1, characterized in that, The substrate (1) surface is also provided with a sealing ring (14); The sealing ring (14) surrounds the functional layer; and / or, the sealing ring (14) covers the side wall of the dicing groove (13) near the first region and the side wall near the second region.

3. The RF switch bare chip according to claim 1, characterized in that, The substrate (1) includes a base and an epitaxial layer disposed on the surface of the base; the functional layer includes a first passivation layer, a first metal layer, an interlayer dielectric layer, a second metal layer and a second passivation layer disposed sequentially along the direction away from the epitaxial layer.

4. The radio frequency switch bare chip according to any one of claims 1 to 3, characterized in that, The first radio frequency switch group module (11) includes N first radio frequency switch units (111) and N groups of first control ports (112); the first control ports (112) are connected to the first radio frequency switch units (111) in a one-to-one correspondence; N is a positive integer greater than 1; The second radio frequency switch group module (12) includes M second radio frequency switch units (121) and M groups of second control ports (122); the second control ports (122) are connected to the second radio frequency switch units (121) in a one-to-one correspondence; M is a positive integer greater than 1.

5. The RF switch bare chip according to claim 4, characterized in that, The first radio frequency switch group module (11) further includes M groups of first redundant ports (113); the first redundant ports (113) are connected one-to-one with the second radio frequency switch unit (121) through the first interconnection line (1114); And / or, the second RF switch group module (12) further includes N sets of second redundant ports; the second redundant ports are connected one-to-one with the first RF switch unit (111) through the first interconnect (1114).

6. The RF switch bare chip according to claim 5, characterized in that, The dicing groove (13) is disposed in the area between the first region and the second region, excluding the area corresponding to the first interconnect line (1114); Alternatively, the dicing groove (13) includes a first dicing groove and a second dicing groove; the first dicing groove is disposed in the region between the first region and the second region other than the region corresponding to the first interconnect (1114); the second dicing groove is disposed in the region between the first region and the second region corresponding to the first interconnect (1114); the bottom of the first dicing groove exposes the substrate (1); the bottom of the second dicing groove exposes a portion of the functional layer.

7. The RF switch bare chip according to claim 6, characterized in that, The width of the region corresponding to the first interconnect (1114) satisfies: W×t<60μm 2 ; In the formula, W represents the width of the region corresponding to the first interconnect (1114); t represents the thickness of all dielectric layers in the functional layer.

8. The radio frequency switch bare chip according to claim 4, characterized in that, The first radio frequency switch unit (111) and the second radio frequency switch unit (121) have the same structure, both including a radio frequency terminal (1111), a common terminal (1112) and a ground terminal (1113), and adjacent first radio frequency switch units (111) share the common terminal (1112), and adjacent second radio frequency switch units (121) share the common terminal (1112).

9. The radio frequency switch bare chip according to claim 8, characterized in that, The common terminal (1112) shared by adjacent first radio frequency switch units (111) is connected one-to-one with the common terminal (1112) shared by adjacent second radio frequency switch units (121) through the second interconnection line (1115).

10. The radio frequency switch bare chip according to claim 9, characterized in that, The dicing groove (13) is disposed in the area between the first region and the second region, excluding the area corresponding to the second interconnect line (1115); Alternatively, the dicing groove (13) includes a first dicing groove and a second dicing groove; the first dicing groove is disposed in the area between the first region and the second region other than the area corresponding to the second interconnect line (1115); the second dicing groove is disposed in the area between the first region and the second region corresponding to the second interconnect line (1115); The bottom of the first dicing groove exposes the substrate (1); the bottom of the second dicing groove exposes a portion of the functional layer.

11. The radio frequency switch bare chip according to claim 10, characterized in that, The width of the region corresponding to the second interconnect (1115) is less than 15 μm.

12. A method for fabricating a radio frequency switch bare chip, characterized in that, include: Provide initial RF switch bare chips; The initial RF switch bare chip includes a substrate (1), and a functional layer is disposed on the surface of the substrate (15); the functional layer includes a first region and a second region, and a third region between the first region and the second region; a first RF switch group module (11) is disposed in the first region; and a second RF switch group module (12) is disposed in the second region. The functional layer etching window is defined in the third region; The functional layer corresponding to the etching window of the functional layer is etched along the thickness direction to expose the substrate (1) corresponding to the etching window of the functional layer, forming a dicing groove (13).

13. The method for fabricating a radio frequency switch bare chip according to claim 12, further comprising: The initial RF switch bare chip is cut along the dicing groove (13) to obtain the first bare chip and the second bare chip.

Images