A test structure for detecting si dislocations and a method for detecting si dislocations

Abstract

The application provides a test structure for detecting Si dislocations and a Si dislocation detection method. The test structure is integrated in a cutting path of a wafer to be tested and is formed synchronously with a device in the wafer to be tested. The test structure comprises an isolation groove and an active region. The active region is located on both sides of the isolation groove and is interconnected. A source-drain doped region is arranged in the active region. The length of the isolation groove is greater than a set value, and the isolation groove is a discrete structure. A filling layer is arranged in the isolation groove. The application can avoid wafer scrapping, realize zero-loss defect monitoring of the wafer, and quantify Si dislocation defects through electrical parameters, thereby helping to improve the wafer yield.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a test structure for detecting Si dislocation and a method for detecting Si dislocation. BACKGROUND

[0002] In the semiconductor industry, silicon (Si) substrate is the core basic material for manufacturing integrated circuit chips, and the integrity of its crystal structure directly determines the electrical performance and reliability of the chips. With the development of semiconductor devices towards high integration and small size, dislocation defects are prone to occur in the silicon substrate during the manufacturing process, such as Shallow Trench Isolation (STI) process, high-temperature annealing, epitaxial growth, etc., due to uneven stress distribution. Such defects are particularly concentrated in the top and bottom regions of the active area, and become one of the key factors affecting the yield of the chips.

[0003] Currently, the detection of dislocation defects in silicon substrates in the industry mainly relies on two technical means: one is to slice the wafer after hot spot positioning, and then observe the defects using a transmission electron microscope, as shown in FIG. 1; the other is to treat the wafer surface with acid corrosion, and then observe the dislocation traces exposed after corrosion through a microscope, as shown in FIG. 2. Figure 1 Figure 2

[0004] However, the above two detection methods are destructive detection, which requires irreversible processing of the wafer and can only be implemented after the wafer is scrapped, and cannot be used for online monitoring of normal production wafers. Secondly, these two detection methods can only determine whether there are dislocations by observation, and cannot quantify the density and impact range of the defects, making it difficult to meet the demand for quantitative data for high-precision process optimization. Finally, the offline operation mode leads to a lag in the detection results, which cannot provide timely feedback on process problems, and is prone to cause continuous defects in subsequent batches of wafers, increasing production costs and yield loss. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a test structure for detecting Si dislocation and a method for detecting Si dislocation, which can avoid wafer scrapping, realize zero-loss defect monitoring of wafers, and quantify Si dislocation defects through electrical parameters, thereby helping to improve wafer yield.

[0006] In a first aspect, the embodiments of the present application provide a test structure for detecting Si dislocation, which is integrated in a scribe lane of a wafer to be tested and formed synchronously with a device in the wafer to be tested. The test structure comprises an isolation trench and an active area, the active area is located on both sides of the isolation trench and interconnected, and a source-drain doped region is provided in the active area. The length of the isolation trench is greater than a set value, and the isolation trench is a discrete structure, and a filling layer is provided in the isolation trench. ​​

[0007] In an alternative embodiment, the length of the isolation trench is greater than or equal to 50 μm.

[0008] In an alternative embodiment, the test structure further comprises a polysilicon gate, which cooperates with the active region to form a current control path to control current on-off.

[0009] In an alternative embodiment, the polysilicon gate is in the form of a strip, and the length direction of the polysilicon gate is perpendicular to the length direction of the isolation trench.

[0010] In an alternative embodiment, the test structure further comprises a contact hole, through which the test structure is internally electrically connected, and cooperates with an external special measurement circuit to read the electrical parameters of the test structure.

[0011] In a second aspect, the embodiments of the present application provide a Si dislocation detection method, which applies the test structure as described above to detect Si dislocations of a wafer to be measured, and the detection method comprises:

[0012] The test structure is arranged in the form of an exposure unit in the scribe lane of the wafer to be measured, and at least one test structure is arranged in each exposure unit; a source-drain voltage signal is applied to the device in the test structure under the condition that the gate voltage is zero, and an electrical characteristic curve is output, which represents the variation of the electrical parameter with the source-drain voltage;

[0013] According to the size relationship between the electrical parameter value on the electrical characteristic curve and a preset parameter threshold, it is determined whether the wafer region corresponding to the exposure unit where the test structure is located has Si dislocations.

[0014] In an alternative embodiment, the electrical parameter comprises a drain current, and the electrical characteristic curve comprises a first characteristic curve, which represents the variation of the drain current with the source-drain voltage.

[0015] The determination of whether the wafer region corresponding to the exposure unit where the test structure is located has Si dislocations according to the electrical parameter value on the electrical characteristic curve comprises:

[0016] If the drain current on the first characteristic curve exceeds a first preset threshold, it is determined that the wafer region corresponding to the exposure unit where the test structure is located has Si dislocations.

[0017] In an alternative embodiment, the electrical parameter comprises a drain current and a substrate current, and the electrical characteristic curve comprises a first characteristic curve and a second characteristic curve, the first characteristic curve representing the variation of the drain current with the source-drain voltage, and the second characteristic curve representing the variation of the substrate current with the source-drain voltage.

[0018] The method further comprises:

[0019] If the drain current on the first characteristic curve exceeds the first preset threshold and the substrate current on the second characteristic curve is within the normal range, it is determined that the wafer region corresponding to the exposure unit where the test structure is located has Si dislocations.

[0020] In an optional embodiment, the electrical parameters include drain current, substrate current, gate current and source current, and the electrical characteristic curves include a first characteristic curve, a second characteristic curve, a third characteristic curve and a fourth characteristic curve, the first characteristic curve representing the change of the drain current with the source-drain voltage, the second characteristic curve representing the change of the substrate current with the source-drain voltage, the third characteristic curve representing the change of the gate current with the source-drain voltage, and the fourth characteristic curve representing the change of the source current with the source-drain voltage.

[0021] The method further comprises:

[0022] If the drain current on the first characteristic curve exceeds the first preset threshold, the substrate current on the second characteristic curve is within the normal range, the gate current on the third characteristic curve exceeds the second preset threshold, and the source current on the fourth characteristic curve exceeds the third preset threshold, it is determined that the wafer region corresponding to the exposure unit where the test structure is located has Si dislocations.

[0023] In an optional embodiment, the detection method further comprises:

[0024] The number of failed test structures in the wafer under test whose electrical parameter values exceed the preset parameter threshold is counted, and the failure rate of the chip in the wafer under test is calculated according to the total number of test structures on the wafer under test.

[0025] The electrical parameter abnormal value of each failed test structure is extracted.

[0026] According to a pre-established mapping model of electrical parameter abnormal value and dislocation density, the electrical parameter abnormal value of each failed test structure is converted into the dislocation density of the corresponding exposure unit.

[0027] According to the dislocation density of each exposure unit and the failure rate of the chip, the overall defect degree of the wafer under test is evaluated.

[0028] The embodiment of the present application provides a test structure for detecting Si dislocation and a Si dislocation detection method. The test structure combines a discrete isolation groove with an interconnected active region, uses the stress concentration effect of the bottom of the isolation groove to enhance the electrical response signal of the Si dislocation, is integrated in a wafer cutting channel and formed synchronously with a device in the wafer, does not need an additional process step, and can realize non-destructive detection. Compared with the existing destructive methods such as slicing and acid corrosion, the test structure can avoid wafer scrapping, realize zero-loss defect monitoring of the wafer, and can quantify the Si dislocation defects through electrical parameters.

[0029] In order to make the above objectives, characteristics and advantages of the present application more apparent, clear and easy to understand, the following will specifically describe a preferred embodiment in combination with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0031] Figure 1 A semiconductor dislocation slicing photograph provided by the prior art;

[0032] Figure 2 A semiconductor dislocation defect bubble acid photograph provided by the prior art;

[0033] Figure 3 A structure diagram of a test structure for detecting Si dislocation provided by the embodiment of the present application;

[0034] Figure 4 A flowchart of a Si dislocation detection method provided by the embodiment of the present application;

[0035] Figure 5 A schematic diagram of a plurality of characteristic curves provided by the embodiment of the present application;

[0036] Figure 6 A flowchart of another Si dislocation detection method provided by the embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the purposes, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, every other embodiment obtained by a person skilled in the art without creative work belongs to the scope of protection of the present application.

[0038] As shown in Figure 3 The embodiments of the present application provide a test structure for detecting Si dislocation, which is integrated in a scribe lane of a wafer to be tested and formed synchronously with a device in the wafer to be tested. The test structure 30 includes an isolation trench 301, an active region 302, a source-drain doped region (not shown in the figure), and a filling layer (not shown in the figure). The active region 302 is located on both sides of the isolation trench 301 and interconnected. The source-drain doped region is arranged in the active region 302. The length of the isolation trench 301 is greater than a set value and is a discrete structure. The filling layer is arranged in the isolation trench 301.

[0039] The scribe lane of the wafer to be tested is a reserved area on the wafer for separating adjacent dies, for separating the dies in a subsequent cutting process. This area is not used to form functional chips, but only carries auxiliary components such as test structures or alignment marks, so as to avoid occupying the effective area of the chip. For example, the scribe lanes are distributed in a grid shape along the radial and circumferential directions of the wafer, dividing the wafer into a plurality of exposure units. The test structure is arranged in these grid-shaped scribe lanes, consistent with the extension direction of the scribe lane. Moreover, the manufacturing process of the test structure is integrated into the standard manufacturing process of the wafer device, such as the shallow trench isolation, doping, deposition, and other processes, without the need for additional process steps after the completion of device manufacturing.

[0040] In an optional embodiment, when the wafer is subjected to a shallow trench isolation (STI) process to form an isolation structure of the device, the isolation trench 301 of the test structure is etched synchronously in the scribe lane area. When the source-drain doping is performed on the active region of the device, the same doping process is performed on the active region 302 of the test structure 30, so as to ensure that the process environment of the test structure 30 is consistent with that of the device, and the dislocation formation rule of the test structure 30 is matched with the device.

[0041] Here, the isolation trench 301 refers to the trench structure etched in the wafer substrate, which is used to achieve physical separation and electrical isolation of the active regions 302 on both sides. Its discrete structure means that the transistors are distributed on the upper and lower sides of the long STI trench, which can enhance the stress concentration effect at the bottom of the trench and make it easier to induce the formation of Si dislocations.

[0042] Optionally, long STI trenches are the main structure for detecting Si dislocations. Specifically, long STI trenches themselves will induce certain stress. If there are dislocations in silicon, the behavior of dislocations will be more easily observed under the stress environment of long STI trenches. By observing the condition of silicon near long STI trenches, it can be determined whether there are dislocations.

[0043] Among them, such as Figure 3 As shown, the active region 302 refers to the doped region in the wafer substrate that has conductive properties. It is the core region for current conduction in the test structure 30. The interconnection of the active regions 302 refers to the electrical connection between the two active regions 302 through metal wires or contact holes 304 to form a complete current path, ensuring that current changes can be detected by external circuits.

[0044] For example, the active region is doped with P-type or N-type doping, consistent with the doping type of the active region of the device, to ensure good conductivity; it is connected to the aluminum wire through contact holes located at the edge of the active region to ensure no significant loss during current transmission. For instance, when the test structure is used to detect dislocation defects in an N-type device, the active region is doped with phosphorus, with doping process parameters completely consistent with those of the device's active region, so that the electrical characteristics of the test structure match those of the device.

[0045] Specifically, the source and drain doped regions are regions formed by further high-concentration doping within the active region. They serve as the source and drain of the test structure, respectively, for applying voltage signals and outputting current signals. Their doping concentration is higher than that of the main active region to reduce contact resistance.

[0046] Specifically, the filler layer is an insulating material filled within the isolation trench, used to achieve physical filling and electrical insulation of the isolation trench, preventing current crosstalk between active regions on both sides of the trench through the bottom or sidewalls of the trench. For example, the filler layer can be made of silicon oxide, filled using a chemical vapor deposition process, with the deposition thickness consistent with the depth of the isolation trench. After filling, it undergoes chemical mechanical polishing to make the surface of the filler layer flush with the wafer surface, ensuring the flatness of subsequent processes and preventing short circuits in subsequent metal interconnects due to uneven filler layer surfaces.

[0047] In one optional embodiment, the length of the isolation trench is greater than or equal to 50 μm.

[0048] Here, the length of the isolation groove is greater than or equal to 50 μm, and the stress effect can be amplified. In this way, when detecting defects such as Si dislocations related to stress, the stress effect amplified by the longer isolation groove can make the dislocations in the silicon substrate more easily excited and detected. For example, in the detection structure, when the length of the isolation groove is greater than or equal to 50 μm, the stress effect is amplified, and even a smaller dislocation can have a more significant impact on the electrical performance of the device due to the larger stress effect, thereby facilitating detection by electrical testing means.

[0049] In an alternative embodiment, the test structure further comprises a polysilicon gate 303, which cooperates with the active region 302 to form a current control path to control the on-off of the current.

[0050] The polysilicon gate 303 is a gate structure made of polysilicon material, located above the active region 302 and separated from the active region 302 by a gate oxide layer. Its function is to control the formation and conduction of the channel in the active region 302 by applying a gate voltage, thereby regulating the current between the source and the drain, so that the test structure has current control characteristics similar to field effect transistors, and it is convenient to fix the test conditions by the gate voltage, such as 0V, to ensure the stability of the current detection.

[0051] In an alternative embodiment, the width of the polysilicon gate 303 can be related to the target device type and the typical size of the chip to avoid test failure due to parameter deviation. The specific content is as follows:

[0052] First, the width of the polysilicon gate is related to the target device type, specifically: there are different types of devices in a semiconductor chip, and the gate width design of different types of devices itself has differences. The test structure can design the gate width for the target device type to be detected, so as to accurately capture the situation of the device affected by dislocations.

[0053] Second, the width of the polysilicon gate is consistent with the typical size of the device used in the chip. For example, for 180 nm 5V devices, i.e. chips using 180 nm process and working voltage of 5 volts, the standard value of PMOS gate width is 0.5 μm, and the standard value of NMOS gate width is 0.6 μm. The gate width of the test structure can directly use this value. If the PMOS gate width of the test structure is changed to be larger, such as 1 μm, which is much larger than the standard value of 0.5 μm, the leakage signal caused by dislocations may be diluted by the large size of the device itself, and the defect situation of 0.5 μm PMOS in mass production cannot be truly reflected; if the gate width is changed to be smaller, such as 0.2 μm, additional process defects may be introduced due to the small size, which interferes with the test results.

[0054] In addition, the thickness of the gate oxide (the silicon oxide insulation layer between the gate and the substrate) can also be determined by the characteristics of the device itself, covering the common thickness range of the device. Specifically, the thickness of the gate oxide can directly affect the threshold voltage, breakdown voltage, leakage characteristics, and the like of the device. For devices with different performance requirements, the thickness of the gate oxide can be designed differently. For example, for high-frequency logic devices, the thickness of the gate oxide can be only a few nanometers, such as 5 nm, 8 nm; for high-voltage power devices, the thickness of the gate oxide needs to be several tens of nanometers, such as 20 nm, 50 nm.

[0055] In another optional embodiment, the polysilicon gate can be subjected to a doping process to reduce the gate resistance and avoid the influence of gate voltage drop on the detection result; the alignment accuracy of the gate and the active area is controlled within ±0.1 μm, ensuring that the gate can accurately cover the current conduction area of the active area. For example, in the test structure of the high-voltage device wafer, the polysilicon gate is subjected to boron doping (P type), and the thickness of the gate oxide layer is 20 nm to withstand a higher source-drain voltage, adapting to the test requirements of high-voltage devices.

[0056] Specifically, the polysilicon gate is in a strip shape, and the length direction of the polysilicon gate is perpendicular to the length direction of the isolation trench.

[0057] Here, the polysilicon gate structure is in a long strip shape, the length direction of which is perpendicular to the current conduction direction, which can maximize the coverage of the current conduction area of the active area and ensure effective control of the current; the polysilicon gate is arranged along the direction perpendicular to the extension direction of the isolation trench, so that the gate can cover part of the areas of the active areas on both sides at the same time, further optimizing the current control effect.

[0058] Moreover, the length direction of the polysilicon gate is perpendicular to the length direction of the isolation trench, and the central axis of the gate is aligned with the central axis of the isolation trench, with a deviation range of 10 nm to 30 nm, which can ensure the symmetry of the control of the gate on the active areas on both sides and avoid the current detection deviation caused by the offset of the gate. For example, in a high-precision detection scenario, the center of the strip-shaped gate is aligned with the center of the isolation trench through photolithography alignment technology, so that the areas covered by the gate on the active areas on both sides are both 1 μm x 1.5 μm, ensuring the consistency of the current conduction characteristics on both sides and improving the detection accuracy.

[0059] In an optional embodiment, the test structure further includes a contact hole 304, and the test structure 30 is internally electrically connected through the contact hole 304 and cooperates with an external special measurement circuit to read the electrical parameters of the test structure 30.

[0060] Among them, contact hole 304 refers to a hole-like structure that penetrates the dielectric layer on the wafer surface, such as the silicon oxide layer, with the inner wall covered by metal, such as titanium, titanium nitride, or aluminum. It is used to realize the electrical connection between the internal components of the test structure, such as the active region, the source and drain doped regions, the polysilicon gate, and the external metal connection, and is a key interface for current signal transmission. The external dedicated measurement circuit is mainly used to apply voltage and collect current, and can accurately control the voltage signal and detect minute current changes.

[0061] For example, the contact hole can be formed using a dry etching process, with titanium, titanium nitride, and aluminum deposited sequentially on the inner wall to form a low-resistance metal contact; such as Figure 3 As shown, the contact holes are located at the center of the source / drain doped region and the end of the polysilicon gate, respectively. Two contact holes are provided in each region to ensure stable current transmission. For example, an external dedicated measurement circuit applies a source / drain voltage (Vds) of 0-5V to the source / drain doped region through the contact holes, while applying a gate voltage (Vg) of 0V through the gate contact hole, and detecting the substrate current (Ib) through the substrate contact hole, thereby achieving accurate reading of electrical parameters.

[0062] Optionally, the contact hole is connected to an external dedicated measurement circuit via metal wiring; the external dedicated measurement circuit can have nanoampere-level current detection accuracy to meet the current detection requirements under normal and abnormal conditions. For example, when there are no Si dislocations at the bottom of the isolation trench of the test structure, the Ib detected by the external circuit is less than 10nA; when there are Si dislocations, Ib increases to more than 100nA, and the circuit can quickly identify this abnormal change and record the data.

[0063] This application provides a test structure for detecting Si dislocations. By combining discrete isolation trenches with interconnect active regions, the stress concentration effect at the bottom of the isolation trenches is used to enhance the electrical response signal of Si dislocations. Simultaneously, it is integrated into the wafer dicing channel and formed synchronously with the devices in the wafer, requiring no additional process steps and enabling non-destructive testing. Compared with existing destructive methods such as slicing and acid etching, it can avoid wafer scrapping, achieve zero-loss defect monitoring of the wafer, and quantify Si dislocation defects through electrical parameters.

[0064] Secondly, embodiments of this application provide a Si dislocation detection method, which applies as follows: Figure 1 The test structure described above performs Si dislocation detection on the wafer under test, such as... Figure 4 As shown, the method includes:

[0065] S401. The test structure is arranged in the dicing path of the wafer to be tested according to the layout of the exposure units, wherein at least one test structure is arranged in each exposure unit.

[0066] S402, apply a source-drain voltage signal to the device in the test structure under the condition that the gate voltage is zero, output an electrical characteristic curve, and the electrical characteristic curve represents the change of the electrical parameter with the source-drain voltage;

[0067] S403, determine whether the wafer area corresponding to the exposure unit where the test structure is located exists Si dislocation according to the size relationship between the electrical parameter value on the electrical characteristic curve and the preset parameter threshold.

[0068] In step S401, the exposure unit (shot) is a wafer area that can be covered by one exposure of a photolithography machine, each exposure unit contains multiple chips (die) and peripheral cutting tracks, and is a basic unit of pattern transfer in wafer manufacturing. In the present embodiment, the test structure is arranged according to the layout form of the exposure unit, so that the position of the test structure corresponds to the boundary of the exposure unit, and the test structure of each exposure unit can reflect the dislocation condition of the chip in the unit.

[0069] For example, the exposure units of the wafer to be tested can be arranged in a matrix, each exposure unit contains multiple chips, and the cutting tracks are distributed along the boundary of the exposure unit. At least one test structure is arranged at the intersection of the cutting tracks of each exposure unit, so that the stress environment of the test structure is consistent with the stress environment of the chip in the exposure unit. For example, for a 12-inch wafer, 10x10=100 exposure units are divided, and one test structure is arranged at the intersection of the cutting tracks of each exposure unit, a total of 100 test structures, covering the dislocation detection requirements of the entire wafer.

[0070] It should be noted that at least one test structure is arranged in each exposure unit. If the area of the exposure unit is large or the number of chips is large, the number of test structures can be increased to improve the accuracy and coverage of detection, and to avoid missing detection due to failure of a single test structure. For example, for a large exposure unit containing a large number of chips, five test structures are arranged at the four corners and the center position of the cutting tracks, respectively, to detect the dislocation conditions of different regions of the exposure unit. If one of the test structures fails due to process deviation, the remaining four test structures can still detect normally, ensuring that the dislocation condition of the exposure unit is not missed. By arranging multiple test structures, the high-risk dislocation area in the exposure unit can be accurately located, and the chip yield can be improved.

[0071] In step S402, the zero gate voltage is a standardized condition for testing. At this time, the polysilicon gate cannot form a conductive channel on the surface of the active region, and the current between the source and the drain is only conducted by the main body of the active region, which can exclude the influence of the gate voltage on the current and ensure that the electrical characteristic curve only reflects the dislocation condition of the active region and the isolation trench.

[0072] For example, a 0V direct current voltage can be applied to the polysilicon gate of the test structure through the gate interface of the external special measurement circuit, the voltage accuracy is controlled within ±0V, and the gate current (Ig) is monitored at the same time to ensure that the gate insulating layer has no leakage and to avoid the influence of gate voltage deviation on the test results. For example, 0V voltage is applied to the gate before testing and Ig is detected. If Ig is less than 1nA, it indicates that the gate insulation is normal, and the subsequent test can be started. If Ig is greater than 10nA, it indicates that the gate has defects, and the data of the test structure needs to be excluded.

[0073] Here, the source-drain voltage signal is a direct current voltage signal applied to the source-drain doped region of the test structure, which can be gradually increased to obtain electrical parameters at different voltages. The electrical characteristic curve is a curve with the source-drain voltage (Vds) as the abscissa and the electrical parameters (such as Ib, Id, Ig, and Is) as the ordinate, which can directly reflect the variation law of the electrical parameters with the voltage. The electrical parameters can include substrate current (Ib), drain current (Id), gate current (Ig), and source current (Is). Data is collected and four electrical characteristic curves are drawn. For example, when Vds increases from 0V to 5V, 50 data points are collected to form Ib-Vds, Id-Vds, Ig-Vds, and Is-Vds curves. The Ib-Vds curve is used to determine whether there is a dislocation, the Id-Vds curve and the Is-Vds curve are used for auxiliary verification, and the Ig-Vds curve is used to exclude the interference of gate defects.

[0074] In step S403, the preset parameter threshold refers to a critical value determined based on the electrical parameters of a normal test structure without Si dislocation, which is a standard for distinguishing between normal and abnormal states. The preset parameter threshold needs to be calibrated through a large number of experiments to ensure the accuracy and reliability of the threshold.

[0075] The embodiment of the present application locates the exposure unit where the test structure with abnormal electrical parameters is located, and then determines that the chip region in the exposure unit has a Si dislocation risk, thereby realizing the qualitative positioning of the dislocation and providing accurate regional guidance for subsequent process adjustment.

[0076] For example, the test structure corresponding to the exposure unit in the 5th row and the 3rd column of the wafer has Ib exceeding the first preset threshold, which indicates that the chip region in the exposure unit has a Si dislocation. The chip in the exposure unit can be further intensively inspected to confirm the actual dislocation of the chip. At the same time, the process parameters of the exposure unit, such as STI etching depth and annealing temperature, are recorded to analyze the cause of the dislocation. For example, if the STI etching depth of the exposure unit is deeper than the normal value, it can be judged that the etching process deviation is the main cause of the dislocation, and the etching parameters need to be adjusted.

[0077] The following will be exemplarily described taking different currents as examples of electrical parameters:

[0078] In an optional embodiment, the electrical parameter comprises a drain current, and the electrical characteristic curve comprises a first characteristic curve representing a variation of the drain current with respect to a source-drain voltage; and the step S403 specifically comprises: if the drain current on the first characteristic curve exceeds a first preset threshold, determining that the wafer region corresponding to the exposure unit where the test structure is located has Si dislocations.

[0079] Here, the drain current (Id) is a current between a source and a drain of a device in the test structure, and when there is no dislocation, because Vg=0V, there is no conductive channel, Id is mainly a reverse saturation current of a source-drain PN junction, and the value is small and changes gently with Vds; when there is a Si dislocation, the dislocation forms an additional conductive path between the source and the drain, resulting in a significant increase in Id and a change in the slope of Vds, as shown in FIG. 2, a first characteristic curve takes Vds (unit: V) as an abscissa and Id (unit: A) as an ordinate, and the curve trend can reflect a variation rate of the drain current with respect to Vds, and under normal circumstances, the curve is gentle, and when there is a Si dislocation, the curve slope significantly increases. Figure 5

[0080] The first preset threshold refers to a preset parameter threshold set for the drain current, and is a standard for judging whether the drain current is abnormal, and the value is determined according to the statistical results of the drain current of the normal test structure without dislocation defects under different source-drain voltages, and is used to distinguish between normal drain current and abnormal drain current caused by dislocation defects.

[0081] In an optional embodiment, to avoid misjudgment caused by voltage fluctuation, Ids of consecutive 3 or more boosting steps can be set to exceed the threshold to determine that there is a Si dislocation. In this way, the test structure under consecutive multiple Vg, multiple Ids exceed the threshold in succession, which can rule out accidental errors and accurately determine that there is a Si dislocation.

[0082] In an optional embodiment, the electrical parameter comprises a drain current and a substrate current, and the electrical characteristic curve comprises a first characteristic curve representing a variation of the drain current with respect to a source-drain voltage and a second characteristic curve representing a variation of the substrate current with respect to the source-drain voltage; and the step S403 specifically comprises: if the drain current on the first characteristic curve exceeds a first preset threshold and the substrate current on the second characteristic curve exceeds a second preset threshold, determining that the wafer region corresponding to the exposure unit where the test structure is located has Si dislocations.

[0083] ​Wherein, the substrate current is the current formed between the device substrate and other electrodes in the test structure, which is a parameter reflecting whether there is a defect in the substrate area. Specifically, the substrate current is the current caused by the carrier recombination or generation inside the substrate, which is normally in the order of nA and can be ignored. If there is a Si dislocation in the substrate, the dislocation will become a carrier generation center, causing the substrate current to increase significantly, as shown in Figure 5

[0084] Here, the second characteristic curve is a curve specially representing the relationship between the substrate current and the source-drain voltage, as shown in Figure 5

[0085] Wherein, the second preset threshold is a preset parameter threshold set for the substrate current, which is a standard for judging whether the substrate current is abnormal. Since the substrate current is very small (in the order of nA) under normal circumstances, the threshold setting needs to be combined with the statistical results of the normal substrate current to ensure that the increase in the substrate current caused by the dislocation defect can be accurately captured.

[0086] Wherein, the second preset threshold is a preset parameter threshold set for the substrate current, which is a standard for judging whether the substrate current is abnormal. Since the substrate current is very small (in the order of nA) under normal circumstances, the threshold setting needs to be combined with the statistical results of the normal substrate current to ensure that the increase in the substrate current caused by the dislocation defect can be accurately captured.

[0087] In another optional embodiment, the electrical parameter includes a drain current, a substrate current, a gate current and a source current, the electrical characteristic curve includes a first characteristic curve, a second characteristic curve, a third characteristic curve and a fourth characteristic curve, the first characteristic curve represents the change of the drain current with the source-drain voltage, the second characteristic curve represents the change of the substrate current with the source-drain voltage, the third characteristic curve represents the change of the gate current with the source-drain voltage, and the fourth characteristic curve represents the change of the source current with the source-drain voltage; step S403 specifically includes:

[0088] If the drain current on the first characteristic curve exceeds the first preset threshold, the substrate current on the second characteristic curve exceeds the second preset threshold, the gate current on the third characteristic curve is within the normal range, and the source current on the fourth characteristic curve exceeds the third preset threshold, it is determined that there is a Si dislocation in the wafer area corresponding to the exposure unit where the test structure is located.

[0089] ​​Wherein, the gate current is the current flowing out or flowing into from the gate when the gate applies a fixed voltage (such as Vg=0V) and the source-drain applies Vds, and under normal circumstances, the gate current is extremely small (pA level) due to the good insulation of the gate oxide layer, and if the gate oxide layer is damaged, the gate current will significantly increase, and the value thereof can be used to determine whether the abnormality is caused by the gate fault. Here, under normal circumstances, Ig is extremely small due to the insulation of the gate and other regions, and if Ig abnormally increases, it indicates that the leakage is caused by the gate defect rather than the Si dislocation, and such a situation needs to be ruled out; only when the leakage is caused by the Si dislocation, i.e., Ib, Id, and Is are abnormal and Ig is normal, it is determined that the test structure fails.

[0090] Optionally, the source current and the drain current are related, and under normal circumstances, the absolute value of the source current is close to the drain current, and if there is an additional leakage path formed by the Si dislocation, the source current will deviate from the normal value due to the current diversion of the carriers, which can be used as an auxiliary verification basis for the abnormality of the drain current.

[0091] As shown in Figure 5 The third characteristic curve takes Vds (unit: V) as the horizontal coordinate and the gate current (Ig, unit: A) as the vertical coordinate, and under the condition that the gate is defect-free, the value of the Is-Vds curve is extremely low and basically does not change with Vds. The fourth characteristic curve takes Vds (unit: V) as the horizontal coordinate and the source current (Is, unit: A) as the vertical coordinate, and under normal circumstances, the curve is symmetrical to the first characteristic curve (Id-Vds) (the values are close and the directions are opposite), and when there is a Si dislocation, the curve deviates from the symmetrical trend.

[0092] The detection method provided by the embodiment of the application further includes:

[0093] S601, the number of failed test structures with an electrical parameter value exceeding a preset parameter threshold in the wafer to be tested is counted, and the failure rate of the chips in the wafer to be tested is calculated according to the total number of test structures on the wafer to be tested;

[0094] S602, the electrical parameter abnormal value of each failed test structure is extracted;

[0095] S603, the electrical parameter abnormal value of each failed test structure is converted into the dislocation density of the corresponding exposure unit according to a pre-established mapping model of the electrical parameter abnormal value and the dislocation density;

[0096] S604, the overall defect degree of the wafer to be tested is evaluated according to the dislocation density of each exposure unit and the failure rate of the chips.

[0097] In the steps S601-S604, the failure test structure refers to a test structure meeting an abnormality determination condition, and the abnormality determination condition includes but is not limited to: a drain current exceeding a first preset threshold, a drain current exceeding a first preset threshold and a substrate current exceeding a second preset threshold, and a drain current exceeding a first preset threshold, a substrate current exceeding a second preset threshold, a gate current being in a normal range, and a source current exceeding a third preset threshold. The failure of the test structure is directly related to the failure of the chip in the corresponding exposure unit. The failure number is the total number of all failure test structures on the wafer, the total test structure number is the total number of test structures arranged on the wafer, and the ratio of the two is the failure rate of the chip. Since each test structure corresponds to a chip of an exposure unit, this ratio can approximately reflect the proportion of chips with dislocation risk in the wafer.

[0098] In the formula, the electrical parameter abnormal value refers to the difference between the actual electrical parameter value of the failure test structure and the normal parameter reference value, and the normal parameter reference value is the parameter mean value of the test structure without dislocation. The larger the abnormal value is, the more serious the dislocation defect is.

[0099] Further, the mapping model of the electrical parameter abnormal value and the dislocation density refers to a mathematical relationship model established through experiments. The establishment process is as follows: a plurality of wafer samples with known dislocation densities are prepared, the dislocation density can be determined by TEM detection, the electrical parameter abnormal value of each sample is tested, and data fitting is performed on the two to obtain a conversion formula of the abnormal value to the dislocation density. The model can convert the abstract electrical signal into a specific dislocation density value, realizing quantitative evaluation.

[0100] For example, a linear regression model can be used to establish the mapping relationship between the Id abnormal value and the dislocation density (p). Through the model, the electrical abnormality of different failure test structures can be converted into a unified dislocation density index, facilitating the horizontal comparison of the defect severity of different exposure units.

[0101] Finally, the overall defect degree is evaluated. Specifically, the dislocation density of each exposure unit, such as the maximum value, the minimum value, the average value, the distribution concentration, and the chip failure rate, are combined to comprehensively judge the dislocation defect grade of the wafer, such as mild, moderate, and severe. If the failure rate is less than a first set proportion and the average dislocation density is less than a first set average, it is determined to be a mild defect. If the failure rate is greater than the first set proportion and less than a second set proportion, and the average dislocation density is greater than the first set average and less than a second set average, it is determined to be a moderate defect. If the failure rate is greater than the second set proportion and the average dislocation density is greater than the second set average, it is determined to be a severe defect, and the process needs to be stopped for optimization. The first set proportion is less than the second set proportion, and the first set average is less than the second set average.

[0102] For example, by analyzing in the above manner, if the etching depth deviation in the STI process causes stress concentration, adjusting the etching parameters can reduce the failure rate of the next batch of wafers, and the average dislocation density is also reduced, so that the defect level can be improved to be mild. Further, through the evaluation logic, the process problem can be quickly located, providing a quantitative basis for process optimization, and achieving full-process defect prevention.

[0103] The embodiments of the present application can achieve full coverage of dislocation detection in different areas of the wafer by arranging the test structure according to the exposure unit, ensuring that the dislocation risk of each chip in the exposure unit can be accurately captured. Taking the zero gate voltage as the standardized test condition can exclude the interference of the gate voltage on the current signal, ensure the consistency of the electrical characteristic curve, and provide a reliable reference for subsequent parameter comparison. By comparing the electrical parameters with the preset threshold to determine whether the dislocation exists, the wafer does not need to be sliced or acid-etched as in the prior art, realizing non-destructive qualitative positioning detection, avoiding wafer scrapping and realizing zero-loss monitoring of the wafer, and laying a foundation for subsequent quantitative evaluation, solving the problem of relying on destructive means and being unable to quantify in the prior art. At the same time, the test structure is formed synchronously with the wafer device, and the detection process can be embedded in the WAT stage, compatible with online process monitoring, and can feedback the dislocation defect situation in real time, helping process optimization and full-process defect prevention.

[0104] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

[0105] In the several embodiments provided by the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between the units can be indirect couplings or communication connections through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0106] The units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0107] In addition, each function unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit.

[0108] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a nonvolatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application or the part of the present application that essentially contributes to the prior art or the part of the technical solutions of the present application can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

[0109] Finally, it should be noted that the above-described embodiments are merely specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, but not to limit the same. The protection scope of the present application is not limited thereto, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily think of changes to the technical solutions recorded in the foregoing embodiments within the technical scope disclosed by the present application, or replace some technical features with equivalent replacements; and these modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A test structure for detecting Si dislocations, characterized by, The test structure is integrated in a scribe lane of a wafer to be tested and is formed synchronously with a device in the wafer to be tested, and the test structure comprises: an isolation trench and an active region, the active region is located on both sides of the isolation trench and is interconnected, and a source-drain doped region is arranged in the active region; the length of the isolation trench is greater than a set value, and the isolation trench is a discrete structure, and a filling layer is arranged in the isolation trench; The length of the isolation trench is greater than or equal to 50 μm. The discrete structure means that transistors are distributed on both sides of the long STI trench. The test structure further comprises: a polysilicon gate and a contact hole, the polysilicon gate is in a strip shape, the length direction of the polysilicon gate is perpendicular to the length direction of the isolation trench; the test structure is internally electrically connected through the contact hole, and an external special measurement circuit is used to read electrical parameters of the test structure.

2. The test structure of claim 1, wherein, The polysilicon gate cooperates with the active region to form a current control path to control current on-off.

3. A Si dislocation detection method, characterized by, The test structure is used for Si dislocation detection of a wafer to be tested, and the detection method comprises: The test structure is arranged in a scribe lane of the wafer to be tested according to the layout form of an exposure unit, wherein at least one test structure is arranged in each exposure unit; the exposure unit is a wafer area that can be covered by one-time exposure of a photolithography machine, and each exposure unit contains a plurality of chips and peripheral scribe lanes; the test structure is arranged in the scribe lane of the wafer to be tested according to the layout form of the exposure unit, so that the position of the test structure corresponds to the boundary of the exposure unit; under the condition that the gate voltage is zero, a source-drain voltage signal is applied to the device in the test structure, and a step-by-step voltage boosting mode is used to obtain electrical parameters under different voltages; under the condition that the gate voltage is zero, a source-drain voltage signal is applied to the device in the test structure, and an electrical characteristic curve is output, which represents the change of the electrical parameters with the source-drain voltage; According to the size relationship between the electrical parameter value on the electrical characteristic curve and a preset parameter threshold, it is determined whether the wafer area corresponding to the exposure unit where the test structure is located exists Si dislocation; The electrical parameters include drain current, substrate current, gate current and source current, and the electrical characteristic curve includes a first characteristic curve, a second characteristic curve, a third characteristic curve and a fourth characteristic curve, the first characteristic curve represents the change of the drain current with the source-drain voltage, the second characteristic curve represents the change of the substrate current with the source-drain voltage, the third characteristic curve represents the change of the gate current with the source-drain voltage, and the fourth characteristic curve represents the change of the source current with the source-drain voltage. The determination whether the wafer area corresponding to the exposure unit where the test structure is located exists Si dislocation according to the electrical parameter value on the electrical characteristic curve comprises: If the drain current on the first characteristic curve exceeds a first preset threshold, the substrate current on the second characteristic curve exceeds a second preset threshold, the gate current on the third characteristic curve is in a normal range, and the source current on the fourth characteristic curve exceeds a third preset threshold, it is determined that a wafer region corresponding to the exposure unit where the test structure is located has Si dislocations.

4. The detection method according to claim 3, characterized in that, The detection method further comprises: counting the number of failed test structures in the wafer under test whose electrical parameter values exceed a preset parameter threshold, and calculating the failure rate of the chips in the wafer under test according to the total number of test structures on the wafer under test; extracting the electrical parameter abnormal value of each failed test structure; According to a pre-established mapping model of electrical parameter abnormal value and dislocation density, the electrical parameter abnormal value of each failed test structure is converted into the dislocation density of the corresponding exposure unit; According to the dislocation density of each exposure unit and the failure rate of the chips, the overall defect level of the wafer under test is evaluated.

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