Balancing method combining dynamic cyclic redundancy and carrier modulation

Abstract

According to the dynamic cyclic redundancy and carrier modulation combined equalization method, a central control unit generates a global equalization scheduling matrix and a dynamic security key based on a global equalization optimization algorithm and broadcasts the global equalization scheduling matrix and the dynamic security key to all distributed equalization modules, and the distributed equalization modules construct modulation energy data packets; a source end distributed equalization module couples a modulation energy data packet to a public energy bus for transmission, a distributed equalization module connected with the public energy bus continuously monitors the public energy bus, and a target end distributed equalization module matched with an address is determined; the target end distribution equalization module calculates the received modulation energy data packet by applying a cyclic redundancy check algorithm, and when the modulation energy data packet is determined to be valid, energy carried by an energy load frame in the modulation energy data packet is drawn from a public energy bus and stored in a corresponding target end energy storage monomer; dependence on an independent communication bus can be eliminated, and the accuracy, robustness and safety of the equalization process are ensured.

Description

Technical Field

[0001] This invention relates to the field of energy storage technology, and in particular to an equalization method combining dynamic cyclic redundancy and carrier modulation. Background Technology

[0002] Against the backdrop of a global energy structure transitioning towards low-carbon and clean energy, novel electrochemical energy storage technologies, represented by ion batteries, hybrid ion capacitors, and supercapacitors, are becoming key enabling technologies for building large-scale energy storage power plants, supporting grid peak and frequency regulation, and mitigating renewable energy fluctuations, thanks to their comprehensive advantages in resource abundance, cost-effectiveness, and safety. Energy storage systems typically consist of hundreds or thousands of individual energy storage cells connected in series and parallel to form battery clusters to meet the demands of high-voltage, high-capacity applications. However, due to limitations in manufacturing process consistency, slight batch variations in materials, temperature gradient distribution during operation, and differences in the self-discharge rate of individual cells, inconsistencies in the State of Charge (SOC) between energy storage cells are inevitable. This inconsistency is an inherent challenge in energy storage system applications. Its direct consequence is that during charging and discharging, the usable capacity of the entire battery cluster will be limited by the cell with the lowest or highest SOC, leading to the "weakest link" effect and significantly reducing the overall energy utilization rate of the system. More seriously, long-term SOC imbalance can exacerbate overcharging or over-discharging of some cells, accelerate their performance degradation, shorten system cycle life, and in extreme cases induce serious safety accidents such as thermal runaway.

[0003] To address these challenges, integrating active balancing functionality into the Battery Management System (BMS) has become a standard technical approach in the industry. Compared to passive balancing, which only consumes excess energy from high-SOC cells, active balancing technology actively and efficiently transfers energy from high-SOC cells to low-SOC cells through non-dissipative energy transfer, thereby achieving convergence of the SOC of the entire battery cluster. Specifically, existing active balancing systems typically employ a distributed topology, equipping each or each energy storage cell with an independent micro-energy converter controlled by a central BMS, such as a flyback or buck-boost converter. The workflow is generally as follows: the central BMS periodically collects voltage information from all cells via a high-speed communication bus (such as a CAN bus), identifies cells with "surplus" or "deficient" energy after internal algorithm analysis, generates corresponding control commands, and sends them via the communication bus to the energy converter corresponding to the target cell, driving it to operate at a specific power and duration to complete a precise energy transfer. This closed-loop control model based on "measurement-decision-communication-execution" can theoretically effectively compensate for individual differences and improve the overall performance and safety of the system.

[0004] However, with the continuous expansion of energy storage system scale and the continuous improvement of energy density, the aforementioned mainstream active balancing technologies have gradually revealed a deep-seated inherent contradiction in practice. The reason lies in the fact that this technical architecture separates the physical energy transmission channel from the logical transmission channel of control information. Large-scale energy storage power stations operate in an extremely complex electromagnetic environment where strong and weak currents coexist. Hundreds of energy converters operate in high-frequency switching states, which are themselves powerful sources of electromagnetic interference (EMI). This high-frequency noise couples to the communication bus, which carries weak control signals and is distributed among the battery clusters, leading to a significant increase in the bit error rate of data transmission. Although traditional communication protocols include certain error detection mechanisms, in environments with strong interference, control commands may still be lost, delayed, or severely distorted. For example, a "start balancing" command may fail to be correctly received by the target converter due to interference, exacerbating the imbalance; more dangerously, a command specifying a precise balancing time may be misinterpreted, causing the energy converter to operate continuously for an extended period, leading to over-discharge of the source cells and overcharging of the target cells, creating new safety hazards. Therefore, existing active balancing technologies generally face a fundamental dilemma: the precise transport of balancing energy highly depends on the reliable transmission of control commands, while the strong electromagnetic interference generated during the energy transmission process itself is precisely the key factor that undermines the reliability of commands. This technical means (high-frequency switching converter) introduced to solve a problem (SOC inconsistency) has side effects (electromagnetic interference), which in turn damage the execution basis (control communication) of the means itself, forming an irreconcilable technical bottleneck.

[0005] Therefore, designing a balancing method that can break free from dependence on independent and fragile communication buses, deeply integrate control command information with the balancing energy carrier, and thus achieve efficient energy scheduling while fundamentally avoiding the vulnerability of traditional discrete architectures in complex electromagnetic environments, and ensuring the accuracy and safety of the balancing process, has become a key challenge and an urgent technical problem for those skilled in the art. Summary of the Invention

[0006] In view of this, the present invention proposes an equalization method that combines dynamic cyclic redundancy with carrier modulation. By deeply embedding the equalization control command information into the physical layer characteristics of the energy transmission carrier, a new equalization paradigm of information and energy transmission in the same body is constructed, thereby completely eliminating the real-time dependence on independent and fragile external communication buses and ensuring the absolute accuracy, robustness and security of the equalization process in complex electromagnetic environments.

[0007] The technical solution of this invention is implemented as follows: A leveling method combining dynamic cyclic redundancy and carrier modulation is applied to an energy storage system consisting of a central control unit, several energy storage cells, a distributed leveling module, and a common energy bus. The leveling method includes the following steps: Step A: The central control unit collects the status parameters of the energy storage units, generates a global balance scheduling matrix that defines the energy transfer task and a dynamic security key that is synchronized with the global balance scheduling matrix based on the preset global balance optimization algorithm, and broadcasts it to all distributed balance modules. Step B: The distributed balancing module of the source-end energy storage unit constructs a modulated energy data packet according to the received task. The modulated energy data packet includes a preamble frame, a target address frame, a data payload frame, an energy payload frame, and a dynamic cyclic redundancy check frame. Step C: The source-end distributed equalization module couples the modulated energy data packets to the common energy bus for transmission; Step D: All distributed equalization modules connected to the common energy bus are awakened after detecting the preamble frame and decode the subsequent target address frame to obtain the target distributed equalization module with the matching address. Step E: The target-end distributed equalization module applies a cyclic redundancy check (CR) algorithm to the received modulated energy data packets. The initial seed value of the CR algorithm is dynamically generated by the received dynamic security key and the decoded source information, and the calculation result is compared with the value in the received dynamic CR frame. Step F: The target-side distributed equalization module extracts the energy carried by the energy payload frame in the modulated energy data packet from the public energy bus and stores it in its corresponding target-side energy storage unit.

[0008] Preferably, the state parameters in step A include state of charge, terminal voltage, temperature, and health status. The objective function of the global equalization optimization algorithm is set to minimize the variance of the state of charge of all energy storage cells in the energy storage system in the shortest time, with additional constraints. These constraints include: the total transferred energy in a single equalization cycle does not exceed a preset percentage of the system's rated power, and when the health status of any energy storage cell is lower than a preset threshold, its priority as a source energy storage cell is dynamically reduced.

[0009] Preferably, the global balanced scheduling matrix is ​​a sparse matrix, where the row index represents the source end unit address, the column index represents the target end unit address, and the matrix element values ​​are the corresponding preset transfer energy values. The algorithm for generating the dynamic security key is as follows: the start timestamp of the current balancing cycle, the average state of charge of all energy storage cells, and the average temperature of all energy storage cells are concatenated, and a one-way hash function is applied to generate a 256-bit hash value, which is the dynamic security key for the current balancing cycle. When the central control unit broadcasts the global equilibrium scheduling matrix and dynamic security key to all distributed equilibrium modules, it does so through a non-time-sensitive configuration channel.

[0010] Preferably, step B specifically involves the following steps: When the distributed balancing module located in the source-end energy storage unit discovers a balancing task to be executed in its local task list, its internal microprocessor acts as a modulation and coding engine to construct a structured modulation energy data packet carrying complete control instructions. The modulation energy data packet sequentially includes, in time sequence, a pre-synchronization code frame for receiver synchronization, a target address frame for specifying the receiver, a data payload frame for carrying control parameters, an energy payload frame for carrying the energy to be transferred, and a dynamic cyclic redundancy check frame for verifying data integrity and authenticity.

[0011] Preferably, in step C, the bidirectional energy converter inside the source-side distributed equalization module controller couples the modulated energy data packet to the common energy bus for transmission. The bidirectional energy converter adopts a synchronous four-switch bidirectional buck-boost topology based on silicon carbide metal oxide semiconductor field-effect transistors.

[0012] Preferably, step D specifically involves the following steps: the microprocessor of the distributed equalization module has a built-in high-performance analog-to-digital converter to collect modulated energy data packets. The collected digital signal is sent to a digital finite pulse response filter for preprocessing. The filtered signal is then sent to a digital phase-locked loop module to search for a preamble frame. After the preamble frame is found, the distributed equalization module is awakened. Its microprocessor decodes the target address and compares the decoded address with the unique address assigned to it during initialization to obtain the target distributed equalization module with a completely matching address.

[0013] Preferably, step E specifically involves the following steps: the target-end distributed balancing module decodes the data load frame to extract the preset transfer energy value and the source address as control parameters, performs a bitwise XOR operation between the source address and the dynamic security key, truncates the lowest 16 bits of the result as the initial seed value for the cyclic redundancy check algorithm, and compares the initial seed value with the value in the dynamic cyclic redundancy check frame to determine whether the modulated energy data packet is valid.

[0014] Preferably, step F specifically involves the following steps: After determining that the modulated energy data packet is valid, the microprocessor in the target-end distributed equalization module calculates the theoretical absorption time required to complete this energy transfer based on the preset transfer energy value decoded from the data load frame and the measured value of the current voltage of the target-end energy storage unit connected to it. Then, the microprocessor configures the bidirectional energy converter in the target-end distributed equalization module to energy absorption mode, extracts the energy carried by the energy load frame from the common energy bus and stores it in its corresponding target-end energy storage unit, and starts a hardware timer based on the theoretical absorption time. When the hardware timer ends in time, the microprocessor of the target-end distributed equalization module forcibly shuts down the bidirectional energy converter.

[0015] Preferably, the common energy bus is a stacked busbar structure in terms of physical structure. The stacked busbar structure consists of two parallel copper plate conductors as positive and negative conductors, respectively, and a polyimide film is disposed between the copper plate conductors.

[0016] Compared with the prior art, the beneficial effects of the present invention are: This invention discloses an equalization method combining dynamic cyclic redundancy check (CRD) and carrier modulation. It generates a global equalization scheduling matrix and a synchronization security key through a preset global equalization optimization algorithm, enabling global state assessment and task scheduling. When a distributed equalization module receives a task, it constructs a modulated energy data packet including a preamble frame, target address frame, data payload frame, energy payload frame, and dynamic CRD frame. The distributed equalization module then activates its modulation coding engine to couple the modulated energy data packet to a common energy bus. All distributed equalization modules connected to the common energy bus activate their demodulation decoding engines to continuously monitor and decode the common energy bus, obtaining a target distributed equalization module with a matching address. The target distributed equalization module applies a CRD algorithm to verify the modulated energy data packet. After verifying the validity of the modulated energy data packet, it extracts the energy from the packet and stores it in the corresponding energy storage unit. By deeply embedding equalization control command information into the physical layer characteristics of the energy transmission carrier, an equalization paradigm of information and energy transmission in tandem is constructed. The structured modulated energy data packet enables synchronous transmission of commands and energy on the common energy bus, eliminating reliance on independent communication buses and ensuring the accuracy, robustness, and security of the equalization process. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only preferred embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of an equalization method combining dynamic cyclic redundancy and carrier modulation according to the present invention; Figure 2 This is a schematic diagram of an energy storage system based on an equalization method combining dynamic cyclic redundancy and carrier modulation according to the present invention. Detailed Implementation

[0019] To better understand the technical content of this invention, a specific embodiment is provided below, and the invention will be further described in conjunction with the accompanying drawings.

[0020] See Figures 1 to 2 This invention provides an equalization method combining dynamic cyclic redundancy and carrier modulation, applicable to an energy storage system consisting of a central control unit, several energy storage units, a distributed equalization module, and a common energy bus. The equalization method includes the following steps: Step A: The central control unit collects the status parameters of the energy storage units, generates a global balance scheduling matrix that defines the energy transfer task and a dynamic security key that is synchronized with the global balance scheduling matrix based on the preset global balance optimization algorithm, and broadcasts it to all distributed balance modules. Step B: The distributed balancing module of the source-end energy storage unit constructs a modulated energy data packet according to the received task. The modulated energy data packet includes a preamble frame, a target address frame, a data payload frame, an energy payload frame, and a dynamic cyclic redundancy check frame. Step C: The source-end distributed equalization module couples the modulated energy data packets to the common energy bus for transmission; Step D: All distributed equalization modules connected to the common energy bus are awakened after detecting the preamble frame and decode the subsequent target address frame to obtain the target distributed equalization module with the matching address. Step E: The target-end distributed equalization module applies a cyclic redundancy check (CR) algorithm to the received modulated energy data packets. The initial seed value of the CR algorithm is dynamically generated by the received dynamic security key and the decoded source information, and the calculation result is compared with the value in the received dynamic CR frame. Step F: The target-side distributed equalization module extracts the energy carried by the energy payload frame in the modulated energy data packet from the public energy bus and stores it in its corresponding target-side energy storage unit.

[0021] This invention discloses a dynamic cyclic redundancy and carrier modulation equalization method applied to a corresponding energy storage system. The energy storage system macroscopically consists of a central control unit, multiple energy storage cells, multiple distributed equalization modules corresponding one-to-one with each energy storage cell, and a common energy bus. All distributed equalization modules are interconnected at the electrical level through the common energy bus. In a specific application scenario, the energy storage system can be a high-voltage battery pack composed of 96 series-connected lithium-ion battery cells with a rated bus voltage of 400V. The central control unit is responsible for the macroscopic management and strategy decision-making of the entire system, while each distributed equalization module acts as an execution node, directly interacting with its bound energy storage cell for energy and information exchange. The core hardware of each distributed equalization module includes a high-performance microprocessor, an energy storage interface for connecting to the energy storage cell, and a bidirectional energy converter for energy exchange with the common energy bus. This invention is based on the architecture of the aforementioned energy storage system and completely revolutionizes the traditional equalization control paradigm through an innovative information and energy transmission mechanism.

[0022] First, the central control unit periodically collects the state parameters of the individual energy storage units. The collection period can be set to 500 milliseconds. After collecting the real-time state data of all energy storage units, the central control unit runs a preset global equilibrium optimization algorithm. The mathematical model of this algorithm aims to solve a multi-objective optimization problem. Its core objective function is set to minimize the variance of the SOC values ​​of all energy storage units in the energy storage system in the shortest possible time. The final output of the algorithm is a global equilibrium scheduling matrix. Simultaneously generated with the scheduling matrix is ​​a dynamic security key. The dynamic security key is a core element used to ensure the integrity and authenticity of information during subsequent energy transmission. Finally, the central control unit uses the generated global equilibrium scheduling matrix... The dynamic security key is broadcast to all distributed equalization modules at once. Upon receiving the broadcast message, each distributed equalization module parses the content related to its own address and updates its local memory's list of equalization tasks accordingly. When a distributed equalization module finds an equalization task to be executed in its local task list (e.g., transferring specified energy from a source to a target), its internal microprocessor immediately switches roles, acting as a modulation and coding engine, and begins constructing a structured modulated energy data packet carrying complete control instructions. The construction of this modulated energy data packet has an extremely precise definition in terms of time series; it is not a simple energy pulse, but a composite wave containing multiple functional frames. The modulated energy data packet, in its structure, sequentially includes a preamble frame, a target address frame, a data payload frame, an energy payload frame, and a dynamic cyclic redundancy check frame. After completing the logical construction of the modulated energy data packet, the source-end distributed equalization module physically couples the modulated energy data packet to the common energy bus. When the modulated energy data packet propagates on the common energy bus, it can enter the parallel reception, decoding, and verification stage of the distributed equalization module. All distributed equalization modules connected to the common energy bus normally act as demodulation and decoding engines, continuously monitoring energy fluctuations on the common energy bus with low power consumption. Upon detecting a preamble frame, they can be awakened and simultaneously decode the subsequent target address frame to search for... The target-side distributed equalization module only executes the subsequent decoding process if the address matches perfectly. Any non-target-side modules with mismatched addresses immediately halt the decoding process and return to a low-power sleep monitoring state, significantly saving overall system energy. After decoding all information frames, the system enters the verification phase. The target-side distributed equalization module applies a preset cyclic redundancy check (CRC) algorithm to the received modulated energy data packet and compares the calculation result with the value in the dynamic CRC frame to determine the validity of the modulated energy data packet. Only after the modulated energy data packet passes valid verification will it proceed to step F, where the modulated energy data table is confirmed to be valid.The microprocessor of the target-side distributed equalization module immediately configures its bidirectional energy change period to energy absorption mode, drawing energy from the common energy bus carried by the energy payload frame and storing it in its corresponding target-side energy storage unit. After the energy transfer is completed, the entire equalization interaction process ends, the system returns to calm, and all modules return to low-power monitoring state, awaiting a new scheduling instruction initiated by the central control unit for the next equalization cycle.

[0023] Preferably, the state parameters in step A include state of charge, terminal voltage, temperature, and health status. The objective function of the global equalization optimization algorithm is set to minimize the variance of the state of charge of all energy storage cells in the energy storage system in the shortest time, with additional constraints. These constraints include: the total transferred energy in a single equalization cycle does not exceed a preset percentage of the system's rated power, and when the health status of any energy storage cell is lower than a preset threshold, its priority as a source energy storage cell is dynamically reduced.

[0024] The status parameters include the state of charge (SOC) as a percentage with an acquisition accuracy of 0.1%; the terminal voltage (U) in millivolts with an acquisition accuracy of 1mV; the temperature (T) in degrees Celsius with an acquisition accuracy of 0.5°C; and a state of health (SOH) index that comprehensively assesses the aging degree of each cell. After acquiring the real-time status parameters of all energy storage cells, the central control unit runs a preset global equalization optimization algorithm. The global equalization optimization algorithm is subject to a series of strict constraints. One key constraint is that, within a single equalization cycle, the sum of the total transferred energy involved in all equalization tasks must not exceed a preset safety factor of the system's rated power, such as 20%, to avoid excessive impact on the common energy bus and power devices. Another important constraint is related to the state of health (SOH) of the energy storage cells: when the SOH of any energy storage cell is detected to be lower than a preset health threshold (e.g., 80%), the algorithm will automatically dynamically reduce its weight or priority when acting as an energy "source," thereby protecting the aging cells and extending the service life of the entire system.

[0025] Preferably, the global balanced scheduling matrix is ​​a sparse matrix, where the row index represents the source end unit address, the column index represents the target end unit address, and the matrix element values ​​are the corresponding preset transfer energy values. The algorithm for generating the dynamic security key is as follows: the start timestamp of the current balancing cycle, the average state of charge of all energy storage cells, and the average temperature of all energy storage cells are concatenated, and a one-way hash function is applied to generate a 256-bit hash value, which is the dynamic security key for the current balancing cycle. When the central control unit broadcasts the global equilibrium scheduling matrix and dynamic security key to all distributed equilibrium modules, it does so through a non-time-sensitive configuration channel.

[0026] The final output of the global equilibrium optimization algorithm is a global equilibrium scheduling matrix. This matrix is ​​structurally a sparse matrix, where row indices precisely correspond to the addresses of the energy-output source storage cells, and column indices correspond to the addresses of the energy-receiving target storage cells. The values ​​of non-zero elements represent the preset energy transfer values ​​between the specific source and target cells within a single equilibrium cycle, precisely defined in joules (J). Simultaneously generated with this scheduling matrix is ​​a dynamic security key, a core element ensuring the integrity and authenticity of information during subsequent energy transfer. In one specific implementation, the dynamic security key is generated as follows: The central control unit concatenates the start timestamp of the current equilibrium cycle (accurate to microseconds), the arithmetic mean of the SOC of all storage cells collected within this cycle, and the arithmetic mean of the temperature of all storage cells in a fixed order to form a raw data string. This string is then input into a standard one-way hash function, such as the secure hash algorithm SHA-256, to generate a 256-bit hash value unique within this equilibrium cycle. This hash value is used as the dynamic security key for this cycle.

[0027] Finally, the central control unit broadcasts the generated global balancing scheduling matrix and dynamic security key to all distributed balancing modules via the aforementioned time-sensitive configuration channel. Each distributed balancing module, upon receiving the broadcast information, parses the content related to its own address and updates the balancing task list stored in its local memory accordingly. Specifically, the time-sensitive configuration channel can be a low-speed communication bus independent of the common energy bus, using the Controller Area Network (CAN) protocol. Its physical layer and data link layer fully comply with the ISO 11898 standard, and the data transmission rate is set to 250 kbps. The CAN bus is chosen due to its high reliability and multi-node communication capabilities, and its low speed is sufficient to meet the periodic, non-urgent configuration information distribution requirements, while avoiding unnecessary crosstalk with high-frequency energy transmission.

[0028] Preferably, step B specifically involves the following steps: When the distributed balancing module located in the source-end energy storage unit discovers a balancing task to be executed in its local task list, its internal microprocessor acts as a modulation and coding engine to construct a structured modulation energy data packet carrying complete control instructions. The modulation energy data packet sequentially includes, in time sequence, a pre-synchronization code frame for receiver synchronization, a target address frame for specifying the receiver, a data payload frame for carrying control parameters, an energy payload frame for carrying the energy to be transferred, and a dynamic cyclic redundancy check frame for verifying data integrity and authenticity.

[0029] When a distributed load balancing module finds a load balancing task to be executed in its local task list (e.g., transferring specified energy from a source to a target), its internal microprocessor immediately switches roles to act as a modulation and coding engine and begins to build a structured modulation energy data packet carrying complete control instructions.

[0030] Specifically, the preamble frame functions as a start delimiter for data packets and provides a reliable clock synchronization reference for all demodulation engines at the receiving end. Its physical implementation is a sequence of special energy pulses based on Biphase Level (Bi-L) coding. In one specific embodiment, this sequence consists of a 50-microsecond high-level energy pulse generated on the common energy bus, followed by a 50-microsecond zero-level gap (i.e., no energy transmission), and then another 50-microsecond high-level energy pulse. This unique "high-low-high" pattern is highly identifiable against bus noise. Once all distributed equalization modules in listening mode detect this perfectly matched energy pattern, they are awakened from low-power sleep mode and initiate their internal phase-locked loop circuits for precise clock synchronization.

[0031] Following the preamble frame is the target address frame. To achieve reliable transmission of the target address on an energy bus where significant voltage fluctuations may occur, a preferred embodiment of the invention employs robust Pulse Position Modulation (PPM) technology. The entire target address frame is defined within a fixed-length time window, for example, 102.4 microseconds. This time window is logically divided into 256 equally long time slots, each with a width of [missing information]. The address encoding method is as follows: a standardized, extremely low-energy, but steep-edge short energy pulse is generated within a specific time slot out of 256 time slots to uniquely represent an 8-bit target address. For example, a pulse appearing in time slot 0 represents address 0; if it appears in time slot 137, it represents address 137. The parameters of this standardized energy pulse are strictly set, for example, the duration is 100 nanoseconds, and its amplitude is precisely controlled to 1.2 times the bus rated voltage. Because information is carried through the "position" of the pulse on the time axis rather than its "amplitude," PPM modulation is naturally immune to amplitude noise and DC bias drift on the bus, greatly ensuring the accuracy of addressing.

[0032] Following the target address frame is the data payload frame carrying more complex control information. To increase information density within a limited transmission time, this invention employs four-level pulse amplitude modulation (PAM-4). This data payload frame consists of a series of continuous, amplitude-controlled energy pulses. The amplitude of each pulse is precisely modulated at one of four preset levels, allowing each pulse symbol to carry 2 bits of binary information. Specifically, level 1 is defined as 0.25 times the bus rated voltage, representing binary '00'; level 2 is 0.5 times the rated voltage, representing '01'; level 3 is 0.75 times the rated voltage, representing '10'; and level 4 is 1.0 times the rated voltage, representing '11'. By continuously generating such a series of amplitude-modulated pulses, the source module can efficiently encode the preset transfer energy value (e.g., represented using a 32-bit single-precision floating-point number conforming to the IEEE 754 standard), its own source address (for receiver verification), and other possible metadata (such as the task sequence number).

[0033] Following the data payload frame is the core of the entire modulated energy data packet: the energy payload frame. This frame is the longest in duration and carries the majority of the physical energy to be transferred. Its waveform is designed as a rectangular energy pulse with a constant duty cycle (e.g., up to 95% to maximize transmission efficiency) but a variable duration. The duration T_payload of this frame is a precisely calculated and controlled variable that directly determines the amount of energy transferred. The mathematical relationship is given by the formula T_payload = E_transfer / P_avg, where E_transfer is the preset transferred energy value (in joules) obtained from the scheduling matrix, and P_avg is the average power during energy transfer. The average power P_avg can be obtained by integrating the instantaneous power P(t) = V_bus(t)*I_out(t) of the source converter during the energy payload frame over time and dividing by the total time. In practice, the microprocessor can perform precise estimation and feedforward control based on the known bus voltage V_bus, the current voltage of the energy storage unit, and the efficiency η of the bidirectional energy converter under the current operating conditions. The modulation and coding engine achieves precise quantization of the transferred energy by strictly controlling the start and end times of the rectangular energy pulse by activating a high-precision hardware timer.

[0034] The modulated energy data packet ends with a dynamic cyclic redundancy check (CRC) frame. The purpose of this frame is to ensure that the entire data packet is not interfered with by noise or maliciously tampered with during transmission. Its physical encoding method is the same as the data payload frame, also using PAM-4 modulation to compactly transmit the checksum. The checksum it carries is a 16-bit cyclic redundancy check (CRC-16) code. For standardization and compatibility, its generator polynomial... The standard value is fixed to the widely used CRC-16-CCITT. The key innovation of this invention lies in the fact that the initial seed value for this CRC check process is dynamically generated, rather than a fixed 0x0000 or 0xFFFF. This dynamic mechanism, detailed in step E, is tightly coupled with the dynamic security key issued by the central control unit, providing robust security for the entire communication link, particularly enhancing its resistance to replay attacks.

[0035] Preferably, in step C, the bidirectional energy converter inside the source-side distributed equalization module controller couples the modulated energy data packet to the common energy bus for transmission. The bidirectional energy converter adopts a synchronous four-switch bidirectional buck-boost topology based on silicon carbide metal oxide semiconductor field-effect transistors.

[0036] The core device in step C is a bidirectional power converter. In a preferred embodiment of the invention, this converter employs a synchronous four-switch bidirectional buck-boost topology based on silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs). SiC MOSFETs are chosen because of their superior physical characteristics: their rated drain-source breakdown voltage can reach 1200V, sufficient to withstand the harsh environment of a high-voltage bus; their on-resistance is extremely low, typically less than 25 milliohms, significantly reducing conduction losses; and most importantly, their switching speed far exceeds that of traditional silicon-based devices, allowing the switching frequency to be set in a high-frequency range of 200kHz to 500kHz. Such a high switching frequency is a prerequisite for accurately generating nanosecond-level pulse edges and complex PAM-4 waveforms.

[0037] The complex digital control sequence generated by the source-side microprocessor (modulation coding engine) cannot directly drive the high-voltage SiC MOSFETs. Therefore, a high-speed, high common-mode transient rejection (CMTI) optocoupler-isolated gate driver is placed between the microprocessor and the power switches. This driver achieves absolute electrical isolation between the low-voltage digital domain where the microprocessor resides and the high-voltage domain of the power electronics, ensuring the safety of the control system. Furthermore, its excellent transmission characteristics enable the transmission of microsecond-level or even nanosecond-level control pulse signals to the gates of the four SiC MOSFETs without distortion or delay, precisely controlling their turn-on and turn-off timings, as well as their duty cycles in buck-boost operating modes. It is through this precise coordinated control of the four switches that the DC energy stored in the source-side energy storage unit is "carved" into modulated energy data packets with specific waveform envelopes, pulse positions, pulse amplitudes, and durations, and precisely injected into the common energy bus.

[0038] Preferably, step D specifically involves the following steps: the microprocessor of the distributed equalization module has a built-in high-performance analog-to-digital converter to collect modulated energy data packets. The collected digital signal is sent to a digital finite pulse response filter for preprocessing. The filtered signal is then sent to a digital phase-locked loop module to search for a preamble frame. After the preamble frame is found, the distributed equalization module is awakened. Its microprocessor decodes the target address and compares the decoded address with the unique address assigned to it during initialization to obtain the target distributed equalization module with a completely matching address.

[0039] All distributed equalization modules connected to the common power bus have their microprocessors routinely acting as demodulation and decoding engines, continuously monitoring energy fluctuations on the common power bus with low power consumption. The hardware foundation for this process is a high-performance analog-to-digital converter (ADC) and a programmable high-precision timer array built into the microprocessor. The ADC continuously converts the analog voltage signals on the common power bus into digital sequences at a sampling rate of at least 20 MHz (20 MSps).

[0040] Once a modulated energy data packet is transmitted, all modules' ADCs acquire it. The acquired digital signal stream is first preprocessed by a digital finite impulse response (FIR) filter. This filter is designed as a bandpass filter, with its passband covering the main spectral components of the modulated signal, effectively filtering out out-of-band high-frequency noise and low-frequency power line interference from outside the system or generated by other devices. The filtered signal stream is then fed into a digital phase-locked loop (DPLL) module. The core task of the DPLL is to search for and lock onto the unique "high-low-high" energy pattern of the preamble frame. Once locked, the DPLL can accurately recover the phase and frequency of the source's transmitting clock, ensuring strict synchronization between the receiver's internal clock and the transmitter.

[0041] After clock synchronization is complete, all awakened distributed equalization modules immediately begin decoding the subsequent PPM target address frame. The microprocessor starts an internal high-precision timer, counting from the beginning of the address frame to precisely measure the exact time of the unique, brief energy pulse. By dividing the measured time by the slot width (400ns), an integer between 0 and 255 is obtained; this is the decoded target address. Subsequently, each module compares the decoded address with its own unique address assigned during system initialization. Only the target-side distributed equalization module with a perfectly matching address will continue the subsequent decoding process. All non-target-side modules with mismatched addresses will immediately abort the decoding process and return to a low-power sleep monitoring state, thus significantly saving overall system energy consumption.

[0042] The selected target module's demodulation and decoding engine continues to decode subsequent PAM-4 data payload frames. For PAM-4 signals, the microprocessor performs a precise sample at the center stable time point of each pulse symbol, determined by the synchronization clock. The sampled voltage value is then compared to three pre-set voltage thresholds; for example, threshold 1 is set to 0.375 times the bus rated voltage, threshold 2 to 0.625 times, and threshold 3 to 0.875 times. By determining which interval the sampled value falls into, the original two-bit binary data '00', '01', '10', or '11' can be recovered. Through continuous demodulation of the entire frame, the encoded preset transfer energy value, source address, and other key control parameters can be fully recovered.

[0043] Preferably, step E specifically involves the following steps: the target-end distributed balancing module decodes the data load frame to extract the preset transfer energy value and the source address as control parameters, performs a bitwise XOR operation between the source address and the dynamic security key, truncates the lowest 16 bits of the result as the initial seed value for the cyclic redundancy check algorithm, and compares the initial seed value with the value in the dynamic cyclic redundancy check frame to determine whether the modulated energy data packet is valid.

[0044] After decoding all information frames, the verification phase begins. The microprocessor of the target module then applies a pre-defined cyclic redundancy check (CRC) algorithm to the entire received data packet (which includes the decoded target address frame, data payload frame, and characteristic parameters of the energy payload frame, such as duration measurements). The key innovation here lies in the dynamic generation of the initial CRC seed value. Specifically, the target microprocessor performs a bitwise XOR operation with the source address decoded from the data payload frame and the current cycle's dynamic security key (256-bit hash value) received and stored from the central control unit in step A. Then, the lowest 16 bits of the resulting 256-bit result are truncated and used as the initial seed value for this CRC-16 check calculation.

[0045] The advantage of this mechanism is that it firmly binds the validity of the modulated energy data packet to a specific time (represented by a dynamic security key) and a specific sender (represented by the source address). Even if an attacker records a perfectly legitimate data packet and attempts to replay it at a future point in time or by impersonating a different sender, the attack will inevitably fail. This is because the dynamic security key is different in different equalization periods; and the source addresses involved in the XOR operation are also different depending on the source. Both of these situations will result in completely different initial CRC seed values, making it impossible for the CRC value calculated from the replayed packet to match the original CRC value carried in the packet. Only when the locally calculated 16-bit CRC result is completely consistent with the 16-bit CRC value demodulated from the dynamic cyclic redundancy check frame is the entire received modulated energy data packet finally confirmed as a valid, tamper-free, and timely legitimate instruction.

[0046] Preferably, step F specifically involves the following steps: After determining that the modulated energy data packet is valid, the microprocessor in the target-end distributed equalization module calculates the theoretical absorption time required to complete this energy transfer based on the preset transfer energy value decoded from the data load frame and the measured value of the current voltage of the target-end energy storage unit connected to it. Then, the microprocessor configures the bidirectional energy converter in the target-end distributed equalization module to energy absorption mode, extracts the energy carried by the energy load frame from the common energy bus and stores it in its corresponding target-end energy storage unit, and starts a hardware timer based on the theoretical absorption time. When the hardware timer ends in time, the microprocessor of the target-end distributed equalization module forcibly shuts down the bidirectional energy converter.

[0047] If and only if the data packet passes all the above verifications and enters the final execution stage, the microprocessor of the target distributed equalization module immediately configures its bidirectional converter to energy absorption mode, i.e., buck mode. However, it does not simply open the energy path, but performs a controlled and endpoint energy absorption. The microprocessor will accurately calculate the theoretical absorption time required to complete this energy transfer based on the preset transfer energy value E_transfer decoded from the data load frame and the measured value of the current voltage of the target energy storage cell to which it is connected.

[0048] Subsequently, it activates the converter in buck mode, drawing the massive energy carried by the energy payload frame from the common energy bus and efficiently storing it in its corresponding target energy storage unit. Simultaneously, the microprocessor starts a hardware timer, loading a pre-calculated absorption time into it. When this timer expires, regardless of whether energy pulses still exist on the common energy bus, the microprocessor issues an undeniable forced shutdown signal, immediately stopping the bidirectional energy converter. This mechanism constitutes a crucial double safety guarantee for the equalization process. Even if the source module experiences an unknown hardware or software failure, causing its energy payload frame to be excessively prolonged, the target module can intelligently and proactively cut off the energy absorption process on time, thus completely avoiding the risk of overcharging the target energy storage unit and elevating the system's safety to a new level.

[0049] After the energy transfer task is completed, the entire equalization interaction process ends. The system returns to calm, and all modules return to low-power monitoring state, awaiting a new scheduling instruction initiated by the central control unit in the next equalization cycle. In this system, the confirmation mechanism for the success or failure of energy transfer is implicit. In its next state acquisition cycle (e.g., after 500ms), the central control unit indirectly but reliably confirms the successful execution of the previous equalization task by observing a predicted decrease in the SOC of the previously specified source-side energy storage unit and a predicted increase in the SOC of the target-side energy storage unit. If the observed SOC change does not reach the expected value, the optimization algorithm of the central control unit will consider re-initiating the energy transfer task or taking other compensatory measures in the scheduling matrix planning of the next equalization cycle, thus forming a complete closed-loop control.

[0050] Preferably, the common energy bus is a stacked busbar structure in terms of physical structure. The stacked busbar structure consists of two parallel copper plate conductors as positive and negative conductors, respectively, and a polyimide film is disposed between the copper plate conductors.

[0051] To carry such high-frequency, broadband energy signals, the physical structure of the public power bus has been specially designed. Instead of a traditional circular cable, it employs a low-impedance, low-inductance laminated busbar structure. This structure consists of two parallel copper plates with large surface areas (e.g., 1 mm thick and 50 mm wide), serving as the DC positive and negative conductors, respectively. A thin insulating medium, such as polyimide film (Kapton), with a dielectric constant of approximately 3.4 and a thickness controlled at 125 micrometers, is tightly sandwiched between the two copper plates. This structure minimizes the area of ​​the current loop, thereby significantly reducing distributed inductance (down to below 10 nH / m), providing an environment similar to a transmission line for high-frequency signal transmission. It ensures high signal integrity during transmission, from nanosecond-level narrow pulses of PPM to rapid level transitions of PAM-4. Simultaneously, the compact structure effectively suppresses electromagnetic interference (EMI), reducing interference to surrounding electronic equipment.

[0052] To illustrate the technical effects of the present invention more specifically, a specific implementation example of the present invention is provided below: Assume an energy storage system consisting of a battery pack made up of 96 lithium-ion battery cells connected in series, each with a rated capacity of 50Ah and a rated voltage of 3.7V. The rated operating voltage of the common energy bus is approximately 355V (96 * 3.7V ≈ 360V), but for ease of calculation, we will assume it to be 360V. The system is equipped with a central control unit and 96 distributed equalization modules, each corresponding to a single battery cell.

[0053] During a certain balancing cycle T_k, the central control unit collects the status of all individual units. The unit at address #15 has a SOC of 82.3%, while the unit at address #68 has a SOC of 55.1%, indicating a significant imbalance. The cycle's start timestamp is 1678886400.123456, the average SOC of all energy storage units is 68.5%, and the average temperature is 28.2°C. The central control unit's optimization algorithm determines that 720J of energy needs to be transferred from energy storage unit #15 to energy storage unit #68. Simultaneously, the central control unit concatenates the timestamp, average SOC, and average temperature, then performs a SHA-256 operation to generate a dynamic security key for this cycle, resulting in a 256-bit hash value (denoted as KEY_k for simplicity). Subsequently, the scheduling matrix containing the task {#15 -> #68: 720J} and KEY_k are broadcast to all distributed balancing modules.

[0054] After receiving the task, the distributed load balancer module at address #15 begins to operate as a modulation and coding engine via its microprocessor: Build the data packet: Preamble frame: Generates a sequence of energy pulses consisting of a 50µs high level, a 50µs zero level, and a 50µs high level. The high level amplitude is 360V.

[0055] Target address frame: The target address is 68. Within a time window of 102.4µs, at the 68th time slot, i.e., at 68*400ns=27.2µs, a PPM pulse with a duration of 100ns and an amplitude of 360V*1.2=432V is generated.

[0056] The data payload frame needs to encode information such as the transfer energy value 720.0 (32-bit floating-point number 0x44340000) and the source address 15. This data is converted into a PAM-4 symbol sequence, with the amplitude of each symbol selected from four levels: 90V, 180V, 270V, and 360V.

[0057] Energy Payload Frame: Assuming the average output power P_avg of the converter in module #15 under current operating conditions is calibrated to 100W, then the duration of the energy payload frame T_payload = 720J / 100W = 7.2s. The microprocessor will precisely control a rectangular energy pulse with a duty cycle of 95% to last for 7.2 seconds.

[0058] Dynamic CRC frame: The microprocessor takes the source address 15 (binary 00001111) and the pre-stored KEY_k and performs an XOR operation, truncating the lower 16 bits of the result as the initial CRC seed. Then, it performs CRC-16 calculation on the characteristics of the address frame, data payload frame, and energy payload frame to obtain a 16-bit checksum, which is then appended to the end of the packet using PAM-4 encoding.

[0059] Transmission and Reception: Module #15 injects the complete modulated energy data packet into the 360V stacked bus via a bidirectional power converter. All 96 modules simultaneously detect the preamble and synchronize. However, only module #68 finds an address match after decoding the PPM address frame and continues decoding.

[0060] Verification and Execution: Module #68 successfully decoded the transferred energy value as 720J and the source address as 15. Then, it used the decoded source address 15 and its stored KEY_k to generate a CRC seed and performed a local CRC calculation on the received data. The calculation result was completely consistent with the content of the received CRC frame, and the verification passed. Module #68 then configured its converter to buck mode and began absorbing energy from the common energy bus. Based on its own voltage, it calculated that absorbing 720J of energy would take approximately 7.25 seconds (considering absorption efficiency) and started a 7.25-second hardware timer. After 7.25 seconds, regardless of the bus status, module #68 forcibly stopped absorbing energy.

[0061] To illustrate the technical effects of the present invention more specifically, a comparative example is provided below for comparison with the above-described embodiments, as follows: The energy storage system uses the same physical hardware, but employs a traditional, control- and energy-separated equalization method. That is, all control commands (such as start, stop, target address, and energy value) are transmitted through a separate 1Mbps high-speed CAN bus, while the energy bus is used only for transmitting pure DC energy.

[0062] The same task was performed: transferring 720J of energy from energy storage cell #15 to energy storage cell #68.

[0063] Control commands: The central control unit sends a "start equalization" command (target #68, energy 720J) to module #15 via the CAN bus, and sends a "ready to receive" command to module #68.

[0064] Energy transfer: After receiving the instruction, module #15 turns on its DC / DC converter and supplies energy to the energy bus at a constant power of 100W.

[0065] Interference Introduction: During power transmission, the high-frequency switching operation (e.g., at 200 kHz) of the high-power DC / DC converter generates strong electromagnetic interference (EMI) in and around the power bus. This EMI is coupled to the parallel CAN bus.

[0066] Fault occurred: After 7.2 seconds of transmission by module #15, the central control unit calculated that the time had expired and sent a "stop equalization" command to module #15 via the CAN bus. However, due to EMI interference, a bit error occurred in the CAN message during transmission, causing the CRC check to fail. The CAN controller of module #15 discarded it as an error frame and failed to receive the "stop" command.

[0067] Fault Result: Module #15 continued to supply power to the bus. Module #68 may also not have received a stop command for the same reason, or its design logic is to continuously absorb power as long as there is power on the bus. Ultimately, this resulted in severe overcharging of the #68 cell, with its SOC potentially increasing from 55.1% to over 100%, triggering overvoltage protection and even causing safety risks such as thermal runaway.

[0068] Based on the analysis of the above implementation cases and comparative cases, the performance differences between the present invention and traditional technical solutions can be quantitatively compared as shown in Table 1: Table 1

[0069] As can be seen from the above, the equalization method combining dynamic cyclic redundancy and carrier modulation proposed in this invention fundamentally solves the inherent contradiction caused by the separation of control channel and energy channel by deeply integrating control information into the energy carrier itself. This significantly improves the reliability, robustness and safety of the equalization system in complex electromagnetic environments, and provides a new and superior technical path for the design of next-generation high-performance energy storage systems.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An equalization method combining dynamic cyclic redundancy and carrier modulation, characterized in that, Applied to an energy storage system consisting of a central control unit, several energy storage cells, a distributed balancing module, and a common energy bus, the balancing method includes the following steps: Step A: The central control unit collects the status parameters of the energy storage units, generates a global balance scheduling matrix that defines the energy transfer task and a dynamic security key that is synchronized with the global balance scheduling matrix based on the preset global balance optimization algorithm, and broadcasts it to all distributed balance modules. Step B: The distributed balancing module of the source-end energy storage unit constructs a modulated energy data packet according to the received task. The modulated energy data packet includes a preamble frame, a target address frame, a data payload frame, an energy payload frame, and a dynamic cyclic redundancy check frame. Step C: The source-end distributed equalization module couples the modulated energy data packets to the common energy bus for transmission; Step D: All distributed equalization modules connected to the common energy bus are awakened after detecting the preamble frame and decode the subsequent target address frame to obtain the target distributed equalization module with the matching address. Step E: The target-end distributed equalization module applies a cyclic redundancy check (CR) algorithm to the received modulated energy data packets. The initial seed value of the CR algorithm is dynamically generated by the received dynamic security key and the decoded source information, and the calculation result is compared with the value in the received dynamic CR frame. Step F: The target-side distributed equalization module extracts the energy carried by the energy payload frame in the modulated energy data packet from the public energy bus and stores it in its corresponding target-side energy storage unit.

2. The equalization method combining dynamic cyclic redundancy and carrier modulation according to claim 1, characterized in that, The state parameters in step A include state of charge, terminal voltage, temperature, and health status. The objective function of the global equalization optimization algorithm is set to minimize the variance of the state of charge of all energy storage cells in the energy storage system in the shortest time, with additional constraints. These constraints include: the total transferred energy in a single equalization cycle does not exceed a preset percentage of the system's rated power, and when the health status of any energy storage cell is lower than a preset threshold, its priority as a source energy storage cell is dynamically reduced.

3. The equalization method combining dynamic cyclic redundancy and carrier modulation according to claim 1, characterized in that, The global balanced scheduling matrix is ​​a sparse matrix, where the row index represents the source end unit address, the column index represents the target end unit address, and the matrix element value is the corresponding preset transfer energy value. The algorithm for generating the dynamic security key is as follows: the start timestamp of the current balancing cycle, the average state of charge of all energy storage cells, and the average temperature of all energy storage cells are concatenated, and a one-way hash function is applied to generate a 256-bit hash value, which is the dynamic security key for the current balancing cycle. When the central control unit broadcasts the global equilibrium scheduling matrix and dynamic security key to all distributed equilibrium modules, it does so through a non-time-sensitive configuration channel.

4. The equalization method combining dynamic cyclic redundancy and carrier modulation according to claim 1, characterized in that, The specific steps of step B are as follows: When the distributed balancing module located in the source-end energy storage unit finds a balancing task to be executed in its local task list, its internal microprocessor acts as a modulation and coding engine to construct a structured modulation energy data packet carrying complete control instructions. The modulation energy data packet includes, in time sequence, a pre-synchronization code frame for receiver synchronization, a target address frame for specifying the receiver, a data payload frame for carrying control parameters, an energy payload frame for carrying the energy to be transferred, and a dynamic cyclic redundancy check frame for verifying data integrity and authenticity.

5. The equalization method combining dynamic cyclic redundancy and carrier modulation according to claim 1, characterized in that, In step C, the bidirectional energy converter inside the source-side distributed equalization module controller couples the modulated energy data packet to the common energy bus for transmission. The bidirectional energy converter adopts a synchronous four-switch bidirectional buck-boost topology based on silicon carbide metal oxide semiconductor field-effect transistors.

6. The equalization method combining dynamic cyclic redundancy and carrier modulation according to claim 1, characterized in that, The specific steps of step D are as follows: The microprocessor of the distributed equalization module has a built-in high-performance analog-to-digital converter to collect the modulated energy data packets. The collected digital signal is sent to a digital finite pulse response filter for preprocessing. The filtered signal is sent to the digital phase-locked loop module to search for a preamble frame. After the preamble frame is found, the distributed equalization module is awakened. Its microprocessor decodes the target address and compares the decoded address with the unique address assigned to it during initialization to obtain the target distributed equalization module with a completely matching address.

7. The equalization method combining dynamic cyclic redundancy and carrier modulation according to claim 1, characterized in that, The specific steps of step E are as follows: The target-end distributed balancing module decodes the data load frame to extract the preset transfer energy value and the source address as control parameters, performs a bitwise XOR operation on the source address and the dynamic security key, truncates the lowest 16 bits of the result as the initial seed value of the cyclic redundancy check algorithm, compares the initial seed value with the value in the dynamic cyclic redundancy check frame, and determines whether the modulated energy data packet is valid.

8. The equalization method combining dynamic cyclic redundancy and carrier modulation according to claim 1, characterized in that, The specific steps of step F are as follows: After determining that the modulated energy data packet is valid, the microprocessor in the target-end distributed equalization module calculates the theoretical absorption time required to complete this energy transfer based on the preset transfer energy value decoded from the data load frame and the measured value of the current voltage of the target-end energy storage unit connected to it. Then, the microprocessor configures the bidirectional energy converter in the target-end distributed equalization module to energy absorption mode, extracts the energy carried by the energy load frame from the common energy bus and stores it in its corresponding target-end energy storage unit, and starts a hardware timer based on the theoretical absorption time. When the hardware timer ends in time, the microprocessor of the target-end distributed equalization module forcibly shuts down the bidirectional energy converter.

9. The equalization method combining dynamic cyclic redundancy and carrier modulation according to claim 1, characterized in that, The common energy bus is physically structured as a stacked busbar structure, which consists of two parallel copper plate conductors serving as the positive and negative conductors, respectively, with a polyimide film placed between the copper plate conductors.

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