A lightweight encryption and decryption method

Abstract

The present application relates to the technical field of information security, and more particularly to a lightweight encryption and decryption method, comprising: obtaining sensor continuity binary data stream and dividing it into fixed length packets; calling pre-generated round key sequence and whitening key, wherein the round key sequence is generated by main key shift operation and round constant iteration; performing XOR operation on the packet data and the whitening key to output initial confusion data; dividing the initial confusion data into four equal length subsegments to perform multi-round iteration processing, each round including 16-bit modulo addition operation and fixed bit cyclic shift; performing XOR operation on the shifted data and the current round key, updating the subsegment state according to a preset branch processing rule, and performing linear transformation on the updated state using a self-inverse matrix; splicing the subsegments output in the last round into ciphertext and transmitting to an execution mechanism; and calling the round key sequence in reverse direction during decryption, performing inverse transformation and inverse operation using the self-inverse matrix to restore the original data. The present application solves the problem of high encryption delay of industrial control equipment.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of information security technology, and in particular to a lightweight encryption and decryption method. BACKGROUND

[0002] Lightweight cryptography is a category of symmetric encryption algorithms developed for hardware environments with limited computing power and small memory, mainly used for Internet of Things devices or micro-sensor nodes. Existing encryption standards such as AES often require a large amount of computing resources, which may cause processing delays, excessive energy consumption and potential security vulnerabilities, and cannot adapt to the constraints of low-power devices. Lightweight alternatives maintain sufficient resistance to attacks with lower overhead by refining algorithm logic, reducing repetitive operation steps, and optimizing data paths, balancing security needs and system resource limitations to support trusted data protection and authentication mechanisms in edge computing and embedded applications.

[0003] Lightweight block cipher algorithms such as LBcipherB are designed specifically for resource-constrained industrial control embedded environments and use a generalized Feistel structure to process fixed-length block data. After inputting the plaintext, the encryption process is processed through multiple rounds of iteration, each round introducing a round key to drive a nonlinear F function to perform modulo addition, circular shift and XOR operations for complete data confusion and diffusion.

[0004] Existing cryptographic algorithms such as AES or RSA have high computational overhead and energy consumption problems, resulting from their complex operation structure (e.g. relying on multiple iteration operations and nonlinear transformations). When executed on resource-constrained industrial control embedded devices such as programmable logic controllers, algorithm processing consumes a large amount of processing unit resources and power, leading to increased latency and risk of energy reserves being depleted. For example, in real-time monitoring of production lines, embedded controllers need to continuously encrypt data streams transmitted by temperature sensors. Existing algorithms cannot respond in time due to slow computation within a millisecond time window, causing control command delay execution and potentially triggering device downtime or safety incidents. SUMMARY

[0005] To address the deficiencies of the prior art, the present application provides a lightweight encryption and decryption method that addresses the technical problem of real-time data processing delay and safety risk caused by high computational overhead and energy consumption of existing cryptographic algorithms for industrial control embedded devices, resource-constrained satellite devices, satellite communication portable or micro terminal devices.

[0006] To solve the above technical problems, the specific content of the present application is as follows:

[0007] The present application provides a lightweight encryption and decryption method, comprising:

[0008] Step 1, obtain the continuous binary data stream collected by the sensor, and cut the continuous binary data stream into fixed-length data packets.

[0009] Step 2, the fixed length data packet obtained in step 1 is input to the encryption processing unit, a pre-generated round key sequence and a whitening key are called, wherein the round key sequence is generated by iteration of main key shift operation and round constant, in the encryption processing unit, the fixed length data packet and the whitening key perform XOR, and the initial confusion data is output;

[0010] Step 3, the initial confusion data output in step 2 is divided into four equal length subsegments as iteration processing input, and a plurality of rounds of iteration processing is performed on the four equal length subsegments, each round of processing including: using 16-bit modulo addition operation to process the current subsegment data, performing fixed bit cyclic shift on the modulo addition operation result, and outputting the subsegment data after cyclic shift;

[0011] Step 4, the cyclic shift subsegment data output in step 3 is XORed with the current round key in the round key sequence, the subsegment state is updated according to the preset branch processing rule, the updated subsegment state is linearly transformed using the self-inverse matrix, and the transformed subsegment of this round is output;

[0012] Step 5, the four transformed subsegments output in the last round of iteration in step 4 are spliced to generate ciphertext data, and the ciphertext data is transmitted to the execution mechanism; when decrypting, the ciphertext data is received and the round key sequence is called in reverse, the inverse linear transformation is performed by multiplexing the self-inverse matrix, and the state restoration step corresponding to the branch processing rule, the XOR with the current round key, the cyclic shift operation and the modulo addition operation are sequentially performed in reverse, and the fixed length data packet is restored.

[0013] Further, the lightweight encryption and decryption method provided by the application, the generation of the round key sequence in step 2 comprises:

[0014] A 256-bit main key is read from a secure storage area, and the main key is divided into a front 128-bit segment and a rear 128-bit segment;

[0015] The front 128-bit segment obtained by division is subjected to a cyclic left shift of 8 bits, and the rear 128-bit segment is subjected to a cyclic right shift of 4 bits;

[0016] The shifted front 128-bit segment and the shifted rear 128-bit segment are input to a modulo addition operation unit to perform 16-bit modulo addition operation to generate an intermediate variable;

[0017] The intermediate variable is XORed with a preset round constant to output a current round key;

[0018] The current round key is written to a specified address in a round key storage area;

[0019] The left 64 bits of the current round key are extracted as input front segment data for the next round of iteration;

[0020] The shifting, modulo addition, XORing and storing steps are repeatedly performed until a complete round key sequence is generated.

[0021] Further, the whitening key generation in step 2 of the lightweight encryption and decryption method comprises:

[0022] During the round key sequence generation process, the left 64-bit segment and the right 64-bit segment of each round output are captured;

[0023] The captured left 64-bit segment of the current round is temporarily stored in a first register;

[0024] The captured right 64-bit segment of the current round is temporarily stored in a second register;

[0025] The data temporarily stored in the first register and the second register is read;

[0026] The read left 64-bit segment data and right 64-bit segment data are input into an XORing operation unit to perform XORing, a whitening key is generated, and the generated whitening key is written into a key buffer area.

[0027] Further, the preset branch processing rule updating sub-segment state in step 4 of the lightweight encryption and decryption method comprises:

[0028] Four equal-length sub-segments input in the current round iteration are received, the fourth sub-segment data is copied to a first sub-segment storage area to cover the original first sub-segment, the original first sub-segment value and the original second sub-segment value are read, the original first sub-segment value and the original second sub-segment value are input into an XORing unit, a mixed value is output, the mixed value is written into a second sub-segment storage area, the third sub-segment and the fourth sub-segment storage addresses are exchanged, the updated four sub-segments are output, and the sub-segment updating process defined in step 4 is a branch processing rule.

[0029] Further, the lightweight encryption and decryption method comprises that step 4 further comprises:

[0030] The machine code corresponding to the branch processing rule is fixed in the ARM Cortex-M4 instruction set;

[0031] The current round counter value is loaded at the beginning of iteration;

[0032] The loaded current round counter value is compared with a pre-stored total round number value;

[0033] If the comparison result is that the current round is less than the total round, a hard-coded instruction is called to execute the branch processing rule;

[0034] If the comparison result is that the current round is equal to the total round, the branch processing rule step is skipped.

[0035] Further, the lightweight encryption and decryption method of the present application, the step 4 further comprises:

[0036] In the encryption phase, the processor calls the sparse matrix coefficient library, writes the preset 16x16 binary matrix in the coefficient library into the FPGA configuration register, and activates the sparse matrix operation circuit through the register latch control signal;

[0037] In the decryption phase, the matrix coefficients stored in the FPGA configuration register are multiplexed, an inverse enable signal is input to the sparse matrix operation circuit, and the inverse transformation is triggered by the internal self-inverse logic gate array.

[0038] Further, the lightweight encryption and decryption method of the present application, the step 4 further comprises: the sparse matrix operation circuit integrates a barrel shifter component, linearly transforms the input data into the barrel shifter data bus, configures the barrel shifter to perform fixed 4-bit cyclic right shift, and outputs the shifted data to the modulo addition operator, with the bit width of the modulo addition operator being 16 bits, and the carry chain truncation mechanism being enabled to prevent overflow.

[0039] Further, the lightweight encryption and decryption method of the present application, the step 5 comprises:

[0040] During encryption, the address counter is initialized, and the counter value is set to the starting address 0x0000;

[0041] In the order of increasing encryption rounds, the round key storage area access address is calculated by the formula: target address = base address + round x 8 bytes;

[0042] The round key data stored in the target address calculated is read through memory-mapped IO;

[0043] During decryption, the address counter is reset, and the counter value is set to the end address 0x00FF;

[0044] In the order of decreasing decryption rounds, the round key storage area access address is calculated by the formula: target address = end address - round x 8 bytes;

[0045] The round key data stored in the target address calculated is read through memory-mapped IO.

[0046] Further, the lightweight encryption and decryption method of the present application, the step 2 further comprises:

[0047] On the rising edge of the encryption start signal, the whitening key is loaded into the R0-R3 general-purpose registers;

[0048] The register write protection latch is set, and the whitening key data in the R0-R3 registers is locked;

[0049] The value of the system clock cycle counter is continuously monitored;

[0050] When the value of the system clock cycle counter is less than the value of the predefined total cycle number, the power supply voltage of the R0-R3 registers is maintained;

[0051] After the encryption completion signal is triggered, the register write protection latch is cleared, and the storage space of the R0-R3 registers is released.

[0052] Further, the lightweight encryption and decryption method comprises the following steps:

[0053] After receiving the continuous binary data stream collected by the sensor, the DMA controller is enabled to cut the data stream into fixed-length data packets;

[0054] The data packets obtained by cutting are input into the encryption processing unit, and the whitening key pre-generated and resident in the register is called to perform XOR to generate initial confusion data;

[0055] In the encryption processing unit, the cyclic shift is performed through the integrated barrel shifter component;

[0056] The address pre-computation mechanism is used to generate the round key storage area access address, and the round key is read through the memory-mapped IO;

[0057] The total time consumption of the modulo addition operation, branch update and matrix transformation in the single-round iteration processing is constrained to be 187.5 microseconds;

[0058] The sixteen iteration processing units are scheduled in parallel to synchronously perform the multi-round operation processing;

[0059] The transformed subsegments output by the multi-round operation processing are spliced to generate the ciphertext data;

[0060] The hardware AES acceleration channel is activated, and the generated ciphertext data is transmitted to the execution mechanism.

[0061] The present application has the following advantages:

[0062] The present application shares the same set of sparse matrix operation circuits in the encryption and decryption stages through the self-inverse matrix multiplexing mechanism, realizes the zero-cycle-delay cyclic shift operation in combination with the barrel shifter component, effectively compresses the critical path of iteration processing in cooperation with the branch processing rule hard coding and the last-round skipping mechanism, pre-generates the round key sequence and adopts the whitening key register resident strategy to avoid real-time calculation overhead, realizes the single-cycle access of the round key storage area through the address pre-computation mechanism, and maximizes the hardware throughput efficiency through the DMA controller data cutting operation and the parallel scheduling of multiple iteration processing units. BRIEF DESCRIPTION OF DRAWINGS

[0063] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, for those skilled in the art, other drawings can also be obtained from the drawings without any creative effort.

[0064] Figure 1 The flowchart of the lightweight encryption and decryption method provided by the embodiments of the present application. DETAILED DESCRIPTION

[0065] In order to make the technical solutions of the present application clearer, the following will combine the embodiments of the present application and the corresponding drawings to make a clear and complete description of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort belong to the protection scope of the present application. The following will combine the drawings to specifically describe the present application provided by the embodiments of the present application. In order to better understand the purpose of the present application, the following will further describe the present application in detail.

[0066] Please refer to Figure 1 The present application provides a lightweight encryption and decryption method, which comprises:

[0067] Step 1, acquiring the continuous binary data stream collected by the sensor, and cutting the continuous binary data stream into fixed-length data packets;

[0068] Step 2, inputting the fixed-length data packet obtained in step 1 into an encryption processing unit, calling a pre-generated round key sequence and a whitening key, wherein the round key sequence is generated by iteration of main key shift operation and round constant, and in the encryption processing unit, the fixed-length data packet and the whitening key perform XOR operation, and output initial confusion data;

[0069] Step 3, dividing the initial confusion data output in step 2 into four equal-length subsegments as iteration processing input, and performing multi-round iteration processing on the four equal-length subsegments, each round of processing including: using 16-bit modulo addition operation to process the current subsegment data, performing fixed-bit cyclic shift on the modulo addition operation result, and outputting the subsegment data after cyclic shift;

[0070] Step 4, performing XOR operation between the subsegment data after cyclic shift output in step 3 and the current round key in the round key sequence, updating the subsegment state according to a pre-set branch processing rule, performing linear transformation on the updated subsegment state using a self-inverse matrix, and outputting the transformed subsegment of this round;

[0071] Step 5, the four transformed sub-segments output by the last round iteration of step 4 are spliced to generate ciphertext data, and the ciphertext data is transmitted to an execution mechanism; during decryption, the ciphertext data is received and the round key sequence is called reversely, inverse linear transformation is performed by using the self-inverse matrix, and the state restoration step corresponding to the branch processing rule, XOR operation with the current round key, cyclic shift operation and modulo addition operation are sequentially and reversely performed to restore the fixed-length data packet.

[0072] The lightweight encryption and decryption method provided by the application is implemented by the following technical solutions. First, continuous binary data stream collected by a sensor is obtained, and the data stream is divided into fixed-length data packets by a DMA controller to form regular data packets to adapt to the bit width requirement of a subsequent processing unit. The grouped data is input into an encryption processing unit, which calls a round key sequence and a whitening key, wherein the round key sequence is generated by shifting operation and round constant iteration of a master key, and the whitening key is synthesized from intermediate data in the round key generation process. In the encryption processing unit, the data packet and the whitening key perform a bitwise XOR operation to generate initial confusion data to eliminate the statistical characteristics of the plaintext.

[0073] The initial confusion data is then divided into four equal-length sub-segments, which are used as inputs for multiple round iterations. Each sub-segment is independently loaded into a register of an operation unit, and a sixteen-bit modulo addition operation is performed on the current sub-segment data in each round iteration. The modulo addition operation result is subjected to a fixed-bit cyclic shift operation by a barrel shifter. The shifted sub-segment data and the current round key in the round key sequence perform an XOR operation, and then the sub-segment state is updated according to a preset branch processing rule. The branch processing rule includes copying the fourth sub-segment data to overwrite the first sub-segment storage area, mixing the original first sub-segment value and the original second sub-segment value and writing them into the second sub-segment storage area, and exchanging the storage addresses of the third sub-segment and the fourth sub-segment. The updated sub-segment state is subjected to linear transformation by a self-inverse matrix, and the self-inverse matrix is realized by a sparse matrix operation circuit, which integrates a barrel shifter component to handle the shift requirement in linear transformation.

[0074] The four transformed sub-segments output by the last round iteration are spliced to generate ciphertext data, which is transmitted to an execution mechanism through a hardware AES acceleration channel. During decryption, the system receives the ciphertext data and calls the round key sequence reversely, performs inverse linear transformation by using the sparse matrix operation circuit, and sequentially and reversely performs the state restoration step corresponding to the branch processing rule, the XOR operation with the current round key, the cyclic shift operation and the modulo addition operation, and finally restores the original data packet. This encryption and decryption process cooperates with the round key pre-generation mechanism, the register resident strategy and the hardware acceleration component to realize low-delay and high-throughput data processing.

[0075] Specifically, in the lightweight encryption and decryption method, the generation of the round key sequence in step 2 includes:

[0076] Read the 256-bit master key from the secure storage area and divide the master key into a first 128-bit segment and a last 128-bit segment;

[0077] The first 128-bit segment obtained from the segmentation is circularly shifted left by 8 bits, and the last 128-bit segment is circularly shifted right by 4 bits.

[0078] The first 128 bits after shifting and the last 128 bits after shifting are input into the modulo addition unit, and a 16-bit modulo addition operation is performed to generate intermediate variables;

[0079] Perform an XOR operation between the intermediate variable and the preset round constant, and output the current round key;

[0080] Write the current round key to the specified address in the round key storage area;

[0081] Extract the left 64 bits of the current round key as the input front-end data for the next round iteration;

[0082] Repeat the shift, modulo addition, XOR, and storage steps until a complete round key sequence is generated.

[0083] This invention provides a lightweight encryption and decryption method. During the generation of the round key sequence, a 256-bit master key is read from the secure storage area. The master key is divided into a first 128-bit segment and a last 128-bit segment. The first 128-bit segment is circularly shifted left by 8 bits, and the last 128-bit segment is circularly shifted right by 4 bits. The shifted first 128-bit segment and the shifted last 128-bit segment are input into the modulo addition unit to perform a 16-bit modulo addition operation to generate an intermediate variable. The intermediate variable is XORed with a preset round constant to output the current round key. The current round key is written to a specified address in the round key storage area. The left 64 bits of the current round key are extracted as the input front-end data for the next round iteration. The complete round key sequence is generated by repeatedly executing the shift, modulo addition, XOR, and storage steps.

[0084] Specifically, in the lightweight encryption / decryption method of the present invention, the generation of the whitening key in step 2 includes:

[0085] During the generation of round key sequences, the left 64-bit segment and the right 64-bit segment of each round's output are captured;

[0086] The captured current left 64-bit segment is temporarily stored in the first register;

[0087] The captured right 64-bit segment of the current round is temporarily stored in the second register;

[0088] Read the data temporarily stored in the first and second registers;

[0089] The read left 64-bit segment data and right 64-bit segment data are input into an exclusive or operation unit to perform exclusive or, to generate a whitening key, and the generated whitening key is written into a key buffer area.

[0090] The present application synchronously generates a whitening key in a round key sequence generation process, temporarily stores a left 64-bit segment of a current round into a first register and a right 64-bit segment of the current round into a second register by capturing a left 64-bit segment and a right 64-bit segment of each round output, reads the temporarily stored data in the first register and the second register, inputs the read left 64-bit segment data and right 64-bit segment data into an exclusive or operation unit to perform exclusive or operation, generates a whitening key and writes the generated whitening key into a key buffer area.

[0091] Specifically, the preset branch processing rule updating subsegment state in the step 4 includes:

[0092] The four equal-length subsegments input in the current round iteration are received, the fourth subsegment data is copied to the first subsegment storage area to cover the original first subsegment, the original first subsegment value and the original second subsegment value are read, the original first subsegment value and the original second subsegment value are input into an exclusive or unit to output a mixed value, the mixed value is written into the second subsegment storage area, the third subsegment and the fourth subsegment storage addresses are exchanged, and the updated four subsegments are output.

[0093] The present application updates the subsegment state by a preset branch processing rule, receives the four equal-length subsegments input in the current round iteration, copies the fourth subsegment data to the first subsegment storage area to cover the original first subsegment, reads the original first subsegment value and the original second subsegment value, inputs the original first subsegment value and the original second subsegment value into an exclusive or unit to output a mixed value, writes the mixed value into the second subsegment storage area, exchanges the third subsegment and the fourth subsegment storage addresses, and outputs the updated four subsegments.

[0094] Specifically, the lightweight encryption and decryption method includes that the step 4 further includes:

[0095] The machine code corresponding to the branch processing rule is fixed in the ARMCortex-M4 instruction set;

[0096] The current round counter value is loaded at the beginning of iteration;

[0097] The loaded current round counter value is compared with a pre-stored total round number value;

[0098] If the comparison result is that the current round is less than the total round, a hard-coded instruction is called to execute the branch processing rule;

[0099] If the comparison result is that the current round is equal to the total round, the branch processing rule step is skipped.

[0100] The application solidifies the machine code corresponding to the branch processing rule in the ARM Cortex-M4 instruction set, loads the current round counter value at the beginning of iteration, compares the loaded current round counter value with the pre-stored total round number value, and decides to call the hard-coded instruction to execute the branch processing rule or skip the branch processing rule step according to the comparison result.

[0101] Specifically, the lightweight encryption and decryption method further comprises the following steps in the step 4:

[0102] In the encryption stage, the processor calls the sparse matrix coefficient library, writes the preset 16x16 binary matrix in the coefficient library into the FPGA configuration register, and activates the sparse matrix operation circuit through the register latch control signal;

[0103] In the decryption stage, the matrix coefficients stored in the FPGA configuration register are multiplexed, and a reverse enable signal is input to the sparse matrix operation circuit to trigger the internal self-inverse logic gate array to perform inverse transformation.

[0104] The linear transformation of the self-inverse matrix is realized by the sparse matrix operation circuit, the processor calls the sparse matrix coefficient library in the encryption stage, writes the preset 16x16 binary matrix in the coefficient library into the FPGA configuration register, activates the sparse matrix operation circuit through the register latch control signal, and in the decryption stage, the matrix coefficients stored in the FPGA configuration register are multiplexed, and a reverse enable signal is input to the sparse matrix operation circuit to trigger the internal self-inverse logic gate array to perform inverse transformation.

[0105] Specifically, the lightweight encryption and decryption method further comprises the following steps in the step 4: the sparse matrix operation circuit integrates a barrel shifter component, linearly transforms input data into a barrel shifter data bus, configures the barrel shifter to perform fixed 4-bit cyclic right shift, outputs the shifted data to a modulo addition operator, restricts the bit width of the modulo addition operator to 16 bits, and enables the carry chain truncation mechanism to prevent overflow.

[0106] The barrel shifter component is integrated in the sparse matrix operation circuit, linearly transforms input data into a barrel shifter data bus, configures the barrel shifter to perform fixed 4-bit cyclic right shift, outputs the shifted data to a modulo addition operator, restricts the bit width of the modulo addition operator to 16 bits, and enables the carry chain truncation mechanism to prevent overflow.

[0107] Specifically, the lightweight encryption and decryption method further comprises the following steps in the step 5:

[0108] In the encryption stage, the address counter is initialized, and the counter value is set to the starting address 0x0000;

[0109] The round key storage area access address is calculated in ascending order of encryption round according to the formula: target address = base address + round x 8 bytes;

[0110] The round key data stored in the target address calculated is read through memory mapping IO;

[0111] During decryption, the address counter is reset, and the counter value is set to the end address 0x00FF;

[0112] The round key storage area access address is calculated in descending order of decryption round according to the formula: target address = end address - round x 8 bytes;

[0113] The round key data stored in the target address calculated is read through memory mapping IO.

[0114] The round key is called by using the address pre-computation mechanism, the address counter is initialized to the start address during encryption, the round key storage area access address is calculated in ascending order of encryption round, the round key data stored in the target address is read through memory mapping IO, the address counter is reset to the end address during decryption, the round key storage area access address is calculated in descending order of decryption round, and the round key data stored in the target address is read through memory mapping IO.

[0115] Specifically, the lightweight encryption and decryption method comprises the following steps:

[0116] The whitening key is loaded into the R0-R3 general registers at the rising edge of the encryption start signal;

[0117] The register write protection latch is set to lock the whitening key data in the R0-R3 registers;

[0118] The value of the system clock cycle counter is continuously monitored;

[0119] When the value of the system clock cycle counter is less than the value of the total encryption cycle number, the power supply voltage of the R0-R3 registers is maintained;

[0120] After the encryption completion signal is triggered, the register write protection latch is cleared to release the R0-R3 register storage space.

[0121] The whitening key is maintained through the register management mechanism, the whitening key is loaded into the general registers at the rising edge of the encryption start signal, the register write protection latch is set to lock the whitening key data in the registers, the value of the system clock cycle counter is continuously monitored, the register power supply voltage is maintained when the value of the counter is less than the total encryption cycle number, and the register write protection latch is cleared to release the register storage space after the encryption completion signal is triggered.

[0122] Specifically, the lightweight encryption and decryption method further comprises the following steps in step 5:

[0123] After receiving the continuous binary data stream collected by the sensor, the DMA controller is enabled to cut the data stream into fixed-length data packets;

[0124] The cut data packets are input into the encryption processing unit, and the whitening key pre-generated and resident in the register is called to perform XOR operation to generate initial confusion data;

[0125] In the encryption processing unit, the integrated barrel shifter component is used to perform cyclic shift;

[0126] The address pre-computation mechanism is used to generate the round key storage area access address, and the round key is read through memory mapping IO;

[0127] The total time consumption of the modulo addition operation, branch update and matrix transformation in the single round iteration processing is 187.5 microseconds;

[0128] Sixteen iteration processing units are scheduled in parallel to synchronously execute the multi-round operation processing;

[0129] The transformed subsegments output by the multi-round operation processing are spliced to generate the ciphertext data;

[0130] The generated ciphertext data is transmitted to the execution mechanism through the activated hardware AES acceleration channel.

[0131] The present application processes the sensor data stream through the DMA controller, enables the DMA controller to cut the data stream into fixed-length data packets after receiving the continuous binary data stream collected by the sensor, inputs the cut data packets into the encryption processing unit, calls the pre-generated and resident whitening key in the register to perform XOR operation to generate initial confusion data, uses the integrated barrel shifter component in the encryption processing unit to perform cyclic shift, uses the address pre-computation mechanism to generate the round key storage area access address, reads the round key through memory mapping IO, restricts the single round iteration processing time, schedules multiple iteration processing units in parallel to synchronously execute the multi-round operation processing, splices the transformed subsegments output by the multi-round operation processing to generate the ciphertext data, and transmits the ciphertext data to the execution mechanism through the activated hardware AES acceleration channel.

[0132] The application solves the problem of high delay of industrial control equipment encryption through multi-layer technical synergy optimization. In the hardware architecture layer, a self-inverse matrix multiplexing mechanism is adopted to make the encryption stage and the decryption stage share the same set of sparse matrix operation circuit, the matrix coefficients are stored through the FPGA configuration register, and the transformation direction is controlled by combining the reverse enable signal, which significantly reduces the hardware resource occupation. In the data processing layer, branch processing rule hard coding technology is introduced to solidify the sub-section state update logic into the machine code of the ARM Cortex-M4 instruction set, and the last round of redundant operation is intelligently skipped through the round counter comparison mechanism to compress the iteration processing critical path.

[0133] In the key management layer, a round key sequence pre-generation strategy is implemented to generate a complete key sequence through differential shifting operation of the master key and iteration of the round constant, and a whitening key register residency mechanism is used to make the key data reside in the general register and maintain power supply through the write protection latch, thereby eliminating the real-time key calculation and loading delay. In the data flow layer, a DMA controller is used to perform sensor data flow division, and multiple iteration processing units are parallelly scheduled to synchronously perform modular addition operation, branch update and matrix transformation operation, and a bucket shifter component is used to realize zero cycle delay of cyclic shift.

[0134] An address pre-computation mechanism realizes single-cycle access to the round key storage area in the encryption and decryption stages through forward increment and reverse decrement address generation strategies. The hardware AES acceleration channel guarantees the efficiency of ciphertext data transmission. This technical measure forms a closed-loop optimization, which significantly reduces the end-to-end processing delay by reducing circuit redundancy, avoiding real-time calculation, compressing processing path and improving parallelism, thereby meeting the dual requirements of real-time performance and security in industrial control scenarios.

[0135] The specific embodiments of the application aim to meet the real-time encryption requirements in the industrial control embedded environment, and realize low-delay encryption and decryption processing through multi-level technical optimization. The continuous binary data stream collected by the sensor is divided into fixed-length data packets by the DMA controller, which avoids the direct involvement of the processor in data transfer and reduces the interrupt processing overhead. The encryption processing unit calls the pre-generated round key sequence and whitening key, wherein the round key sequence adopts a master key segment shifting strategy, the first 128-bit segment performs a cyclic left shift by 8 bits, and the second 128-bit segment performs a cyclic right shift by 4 bits, thereby enhancing the randomness of the key through differential shifting.

[0136] The whitening key is generated synchronously during the round key generation process, and the left and right 64-bit segments of each round output are used to perform XOR operation. This method synchronously completes the derivation of the whitening key in the key expansion process, avoiding additional calculation overhead. The whitening key is maintained through a register residency mechanism, loaded into the general register at the encryption start stage and enabled with a write protection latch, and the power supply stability is maintained during the encryption period.

[0137] The initial confusion data is divided into four equal-length subsegments to enter multiple rounds of iterative processing, and each round of iteration adopts 16-bit modulo addition operation combined with fixed bit cyclic shift.

[0138] The self-inverse matrix linear transformation is realized by a sparse matrix operation circuit, which integrates a barrel shifter component, directly inputs linear transformation data into the barrel shifter data bus, and performs fixed 4-bit cyclic right shift.

[0139] The round key calling adopts an address pre-computation mechanism, and the access address is generated in an increasing order according to the round in encryption, and is inversely accessed in a decreasing order in decryption, and single-cycle key reading is realized through memory mapping IO.

[0140] This embodiment realizes low-delay encryption and decryption in a resource-limited environment through algorithm optimization and hardware collaborative design, and meets the dual requirements of real-time performance and security of industrial control systems.

[0141] The technical features of the present application are explained as follows:

[0142] The round key generation model in the present application is based on main key segmentation and round constant iteration, and the 256-bit main key is segmented into front and rear 128-bit segments and differential shift operation is performed, the front segment is cyclically left shifted by 8 bits, the rear segment is cyclically right shifted by 4 bits, and the shift result is XORed with the round constant to generate the round key.

[0143] The whitening key generation model is based on the intermediate data of the round key generation process, and the left 64-bit segment and the right 64-bit segment output by each round are captured, temporarily stored in the register, and then subjected to XOR operation to synthesize the whitening key.

[0144] The branch processing rule model is constructed based on sub-segment state update logic, the fourth sub-segment data is copied to cover the first sub-segment storage area, the original first sub-segment value and the second sub-segment value are mixed to update the second sub-segment storage area, and the third sub-segment and the fourth sub-segment storage addresses are exchanged to realize data confusion. The model is realized by hard coding of the ARM Cortex-M4 instruction set, intelligently skips the last round operation according to the round count, and compresses the processing path.

[0145] The self-inverse matrix operation model is constructed based on sparse matrix and reversible linear transformation, a preset 16x16 binary matrix is used to configure the FPGA register, and the self-inverse logic gate array is used to realize linear transformation and inverse transformation in the encryption and decryption stages. The model integrates a barrel shifter component to process the circular shift requirement, controls the transformation direction through forward and reverse enable signals, and realizes hardware resource reuse.

[0146] The generalized Feistel structure adopted by the application is a block cipher design framework, which realizes encryption by dividing input data into multiple sub-segments and performing multiple rounds of iteration. In the encryption process, each sub-segment is mixed with other sub-segments after being processed by a round function, which includes modulo addition operation, circular shift and XOR operation. This structure uses the same algorithm to perform reverse execution when decrypting, without the need to design an inverse round function, significantly reducing the complexity of hardware implementation.

[0147] Modulo addition operation as a core of nonlinear transformation, after performing addition operation with 16-bit width, the modulo operation is taken, which effectively prevents linear analysis attack. The modulo addition operation processes the sub-segment data of the main key in the round key generation stage, and acts on the current sub-segment data in the iteration processing stage, and enhances the algorithm's ability to resist differential analysis through finite field operation.

[0148] Circular shift operation is realized by barrel shifter hardware component, which performs fixed bit circular shift on the result of modulo addition operation. Circular shift operation changes the bit position relationship of data, enhances the diffusion characteristics of the algorithm, and realizes the redistribution of data bits in cooperation with XOR operation, eliminating the statistical characteristics of plaintext.

[0149] XOR operation as a basis of linear transformation is widely used in key expansion, whitening processing and round key mixing stage. XOR operation realizes fast bit flipping, combines intermediate variables and round constants in the round key generation stage, combines data groups and whitening keys in the whitening stage, and combines shifted data and round keys in the iteration processing stage.

[0150] Sparse matrix operation uses a preset 16x16 binary matrix as a linear transformation layer, and the matrix coefficients are optimized to include a large number of zero elements. Sparse matrix operation loads matrix coefficients through FPGA configuration register, performs forward linear transformation in the encryption stage, triggers inverse transformation through reverse enable signal in the decryption stage, and reduces the number of logic gates by using the sparsity of matrix.

[0151] The round key sequence is a key expansion mechanism generated by the main key segment shift and round constant iteration. The 256-bit main key is divided into two 128-bit segments. The front segment performs a cyclic left shift of 8 bits, and the rear segment performs a cyclic right shift of 4 bits. After the shift, the data is subjected to a 16-bit modulo addition operation and XOR with the round constant to generate the round key. The complete key sequence is generated by iteration for multi-round encryption operations.

[0152] The whitening key is an auxiliary key derived from the intermediate data generated during the round key generation process. It is generated by capturing the left 64-bit segment and the right 64-bit segment of each round output, storing the segmented data in registers, and performing an XOR operation. It is used to perform an XOR operation on data packets in the initial encryption stage to eliminate the statistical characteristics of plaintext.

[0153] The branch processing rule is a sub-segment state update algorithm. It copies the fourth sub-segment data to overwrite the first sub-segment storage area, mixes the original first sub-segment value with the second sub-segment value to update the second sub-segment storage area, and exchanges the third sub-segment and fourth sub-segment storage addresses to achieve data confusion. This rule is hard-coded in the ARM Cortex-M4 instruction set.

[0154] The self-inverse matrix is a linear transformation component implemented by a sparse matrix operation circuit. It configures FPGA registers with a pre-set 16x16 binary matrix. In the encryption stage, it performs a forward linear transformation, and in the decryption stage, it triggers an inverse transformation through an inverse enable signal. It uses the self-inverse property of the matrix to achieve hardware reuse for encryption and decryption.

[0155] The barrel shifter is a hardware component integrated into the sparse matrix operation circuit. It takes linear transformation input data into the barrel shifter data bus and performs a fixed 4-bit cyclic right shift operation to achieve zero clock cycle delay bit shifting. The shift result is directly output to the modulo addition operator.

[0156] The address pre-computation mechanism is a round key scheduling strategy. During encryption, it generates access addresses in ascending order of round number, and during decryption, it accesses in reverse order. It achieves single-cycle key reading through memory-mapped IO and efficient key calling with the sequential storage structure of the round key storage area.

[0157] The register residency strategy is a whitening key maintenance method. It loads the whitening key into the general-purpose register and enables write protection latching at the start of encryption. It maintains the register power stability during the encryption period to avoid the time overhead caused by repeated key loading.

[0158] The DMA controller is a data preprocessing component that directly processes continuous binary data streams collected by sensors. It cuts the data stream into fixed-length packets, reducing the processor's data handling burden and enabling direct transmission between data packets and the encryption processing unit.

[0159] The sparse matrix coefficient library is a preset linear transformation parameter set, and stores optimized 16x16 binary matrix coefficients. The matrix design includes a large number of zero elements to reduce the use of logic gates. The coefficient library is loaded into the operation circuit through the FPGA configuration register.

[0160] The hardware AES acceleration channel is a special channel for ciphertext transmission. The spliced ciphertext data is directly transmitted to the execution mechanism through the hardware acceleration module, bypassing the existing data transmission path, and reducing the transmission delay.

Claims

1. A lightweight encryption and decryption method, characterized by, The method comprises the following steps: Step 1, obtaining the continuous binary data stream collected by the sensor, and cutting the continuous binary data stream into fixed-length data packets; Step 2, inputting the fixed-length data packet obtained in step 1 into an encryption processing unit, calling a pre-generated round key sequence and a whitening key, wherein the round key sequence is generated by shifting the main key and iterating the round constant, and in the encryption processing unit, the fixed-length data packet and the whitening key perform XOR operation, and the initial confusion data is outputted; Step 3, dividing the initial confusion data outputted in step 2 into four equal-length subsegments as iteration processing input, and performing multi-round iteration processing on the four equal-length subsegments, wherein each round of processing comprises: using 16-bit modulo addition operation to process the current subsegment data, performing fixed-bit cyclic shift on the modulo addition operation result, and outputting the subsegment data after the cyclic shift; Step 4, performing XOR operation between the subsegment data outputted in step 3 after the cyclic shift and the current round key in the round key sequence, updating the subsegment state according to a preset branch processing rule, performing linear transformation on the updated subsegment state by using a self-inverse matrix, and outputting the transformed subsegment of this round; Step 5, splicing the four transformed subsegments outputted in step 4 of the last round of iteration to generate ciphertext data, and transmitting the ciphertext data to an execution mechanism; when decrypting, the ciphertext data is received, the round key sequence is called reversely, the inverse linear transformation is performed by multiplexing the self-inverse matrix, and the state restoration step corresponding to the branch processing rule, the XOR operation with the current round key, the cyclic shift operation and the modulo addition operation are sequentially performed reversely, and the fixed-length data packet is restored.

2. The lightweight encryption and decryption method of claim 1, wherein, The generation of the round key sequence in step 2 comprises: reading a 256-bit main key from a secure storage area, and dividing the main key into a front 128-bit segment and a rear 128-bit segment; performing 8-bit cyclic left shift on the front 128-bit segment obtained by division, and performing 4-bit cyclic right shift on the rear 128-bit segment; inputting the shifted front 128-bit segment and the shifted rear 128-bit segment into a modulo addition operation unit to perform 16-bit modulo addition operation and generate an intermediate variable; performing XOR operation between the intermediate variable and a preset round constant to output a current round key; writing the current round key to a specified address of a round key storage area; extracting the left 64 bits of the current round key as input front segment data for the next round of iteration; repeating the steps of shifting, modulo addition, XOR operation and storage until the complete round key sequence is generated.

3. The lightweight encryption and decryption method of claim 2, wherein, The generation of the whitening key in step 2 comprises: capturing the left 64-bit segment and the right 64-bit segment outputted in each round during the generation of the round key sequence; temporarily storing the captured left 64-bit segment of the current round in a first register; temporarily storing the captured right 64-bit segment of the current round in a second register; reading the temporarily stored data in the first register and the second register; inputting the read left 64-bit segment data and right 64-bit segment data into an XOR operation unit to perform XOR operation and generate a whitening key, and writing the generated whitening key into a key buffer area.

4. The lightweight encryption and decryption method of claim 3, wherein, The preset branch processing rule for updating the subsegment state in step 4 comprises: Receiving four equal-length sub-segments of current round iteration input, copying the fourth sub-segment data to the first sub-segment storage area, covering the original first sub-segment, reading the original first sub-segment value and the original second sub-segment value, inputting the original first sub-segment value and the original second sub-segment value into an XOR unit, outputting a mixed value, writing the mixed value into the second sub-segment storage area, swapping the third sub-segment and the fourth sub-segment storage addresses, and outputting the updated four sub-segments, wherein the sub-segment updating process defined in step 4 is a branch processing rule.

5. The lightweight encryption and decryption method of claim 4, wherein, The step 4 in the step 4 further comprises: Solidifying the machine code corresponding to the branch processing rule in the ARM Cortex-M4 instruction set; Loading the current round counter value at the beginning of iteration; Comparing the loaded current round counter value with the pre-stored total round number value; If the comparison result is that the current round is less than the total round, calling the hard-coded instruction to execute the branch processing rule; If the comparison result is that the current round is equal to the total round, skipping the branch processing rule step.

6. The lightweight encryption and decryption method of claim 5, wherein, The step 4 further comprises: In the encryption stage, the processor calls the sparse matrix coefficient library, writes the pre-stored 16x16 binary matrix in the coefficient library into the FPGA configuration register, and activates the sparse matrix operation circuit through the register latch control signal; In the decryption stage, the matrix coefficients stored in the FPGA configuration register are multiplexed, an inverse enable signal is input to the sparse matrix operation circuit, and the internal self-inverse logic gate array of the circuit is triggered to perform inverse transformation.

7. The lightweight encryption and decryption method of claim 6, wherein, The step 4 further comprises: The sparse matrix operation circuit integrates a bucket shifter component, inputs linear transformation input data into the bucket shifter data bus, configures the bucket shifter to perform fixed 4-bit cyclic right shift, and outputs the shifted data to the modulo addition operator, with the bit width of the modulo addition operator constrained to 16 bits and the carry chain truncation mechanism enabled to prevent overflow.

8. The lightweight encryption and decryption method of claim 7, wherein, The step 5 comprises: During encryption, initializing the address counter and setting the counter value to the starting address 0x0000; In the order of increasing round number, calculating the round key storage area access address using the formula: target address = base address + round number x 8 bytes; Reading the round key data stored in the target address calculated through memory-mapped IO; During decryption, resetting the address counter and setting the counter value to the end address 0x00FF; In the order of decreasing round number, calculating the round key storage area access address using the formula: target address = end address - round number x 8 bytes; Reading the round key data stored in the target address calculated through memory-mapped IO.

9. The lightweight encryption and decryption method of claim 8, wherein, The step 2 further comprises: At the rising edge of the encryption start signal, load the whitening key into R0-R3 general-purpose registers; Set the register write protection latch to lock the whitening key data in R0-R3 registers; Continuously monitor the value of the system clock cycle counter; When the system clock cycle counter value is less than the pre-defined total encryption cycle value, maintain the power supply voltage of R0-R3 registers; After the encryption completion signal is triggered, clear the register write protection latch to release the R0-R3 register storage space.

10. The lightweight encryption and decryption method of claim 9, wherein, Step 5 further comprises: After receiving the continuous binary data stream collected by the sensor, enable the DMA controller to cut the data stream into fixed-length data packets; The sliced data packet is input into the encryption processing unit, and the pre-generated whitening key is called to perform XOR operation, and initial confusion data is generated; In the encryption processing unit, the cyclic shift is performed by integrating the barrel shifter component; The address pre-computation mechanism is used to generate the round key storage area access address, and the round key is read through memory mapping IO; The total time consumption of the modulo addition operation, branch update and matrix transformation in the single round iteration processing is 187.5 microseconds; Sixteen iteration processing units are synchronously executed in parallel scheduling to perform multi-round operation processing; The transformed sub-segments output by the multi-round operation processing are spliced to generate ciphertext data; The hardware AES acceleration channel is activated, and the generated ciphertext data is transmitted to the execution mechanism.

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