Precise delay and throughput control method based on calendar queue and gating mechanism

Abstract

The application discloses a precise delay and throughput control method based on a calendar queue and a gating mechanism, and comprises the following steps: S1, processing a message descriptor, calculating a planned sending time of the message according to a delay, a bandwidth packet loss value and a packet loss state; S2, buffering the message in a calendar queue according to the planned sending time, and gating the message in a queue in a sending state; and S3, taking out a message body according to a message pointer, and sending the message out from a network interface of a network processor through a PHY interface. The application realizes precise delay control of the message according to the delay and the bandwidth parameters by combining the calendar queue and the gating mechanism.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computer and communication technology, in particular to a precise delay and throughput control method based on calendar queue and gating mechanism. BACKGROUND

[0002] Packet scheduling is a key research topic in network processors, which is directly related to the efficiency, delay and resource optimization of network data transmission. In network communication, packet scheduling algorithm is responsible for determining when and in what order to transmit each packet to ensure effective management and control of network traffic. This involves complex strategies such as queue management, priority allocation, traffic shaping and congestion control.

[0003] Most traffic control methods sort all packets according to their priority, such as first-in-first-out, priority queue, weighted fair queue, etc. These methods have the problem of not being able to support a large number of priorities while ensuring priority accuracy. The scheme based on multi-level calendar queue in the present application solves this problem. At the same time, the packet control method in the present application is based on the forwarding time of the packet, which can achieve the allocation of packet forwarding time with the minimum forwarding time deviation as the target. SUMMARY

[0004] The present application aims to overcome the shortcomings of the prior art. The present application provides a precise delay and throughput control method based on calendar queue and gating mechanism, which realizes accurate delay control of packets according to delay and bandwidth parameters by combining calendar queue and gating mechanism.

[0005] To achieve the above purpose, the present application provides a precise delay and throughput control method based on calendar queue and gating mechanism, which comprises the following steps:

[0006] S1. Process the packet descriptor, calculate the planned sending time of the packet and the packet loss state according to the delay, bandwidth and packet loss value;

[0007] S2. Buffer the packet in the calendar queue according to the planned sending time, and gate the packet in the queue in the sending state;

[0008] S3. Take out the packet body according to the packet pointer, and transmit the packet out from the network interface of the network processor through the PHY interface.

[0009] Further, in step S1, the packet descriptor includes a packet pointer, a packet planning time and a packet loss state, and the packet pointer is an index pointing to the whole packet in the network processor storage space.

[0010] Further, the message descriptor is processed by the logical circuit of the bandwidth operation unit, the delay operation unit and the packet loss operation unit in turn after entering the bandwidth operation unit.

[0011] Further, step S1 includes:

[0012] S1.1 The bandwidth operation unit processes the message descriptor, controls the bandwidth of each flow, ensures that the traffic of each flow does not exceed the preset bandwidth value, and processes the traffic exceeding the bandwidth value according to the leaky bucket model;

[0013] S1.2 After the message descriptor leaves the bandwidth operation unit, it carries the calculated planning sending time to the delay operation unit, and the delay operation unit calculates the planning time of each message under the preset delay value;

[0014] S1.3 After the message descriptor leaves the delay operation unit, it carries the calculated planning sending time to the packet loss operation unit, and the packet loss operation unit selects whether to discard the data packet according to the preset packet loss rate.

[0015] Further, in step S1.2, the delay operation unit increases a delay amount on the basis of the planning sending time of the bandwidth operation unit, and the new planning sending time is equal to the original planning sending time plus the preset delay. Each message entering the delay operation unit will match a corresponding delay amount, and then update the planning sending time according to the delay amount.

[0016] Further, in step S1.3, the packet loss operation unit is provided with a linear shift register module, which can generate a random value at each beat according to a preset seed value. When the message enters the packet loss operation unit, it will match a corresponding packet loss rate, and the matched packet loss rate will be compared with the random value. If the packet loss rate is greater than the random value, the message will be marked as discarded, otherwise it will not be discarded.

[0017] Further, in step S2, the message descriptor not marked as discarded by the bandwidth operation unit, the delay operation unit and the packet loss operation unit will enter the logical circuit of the time slot discrimination circuit, the first-in-first-out queue and the dequeue gate for processing.

[0018] Further, step S2 includes:

[0019] S2.1 The time slot discrimination circuit selects a first-in-first-out queue for the message to enter according to the planning forwarding time calculated in the previous stage circuit; each first-in-first-out queue corresponds to a time slot, and the first-in-first-out queue will be opened within the time slot to transfer all messages in it;

[0020] S2.2 The width and depth of the first-in-first-out queue are the bit width of the forwarding outlet and the maximum number of bytes that can be forwarded under the bit width of the outlet, respectively;

[0021] S3.3 Dequeue gate opens the gate of the first-in-first-out queue in the corresponding time slot.

[0022] Further, the time slot discrimination circuit saves the start time and end time state of each queue; when a message arrives at the time slot discrimination circuit, the scheduled sending time of the message is compared with the start time and end time of all queues in parallel, and the scheduled time of the message is determined to fall in which time slot of which queue according to the comparison result.

[0023] Further, the dequeue gate includes two modes, one is the best-effort gate, and the messages stored in the first-in-first-out queue are dequeued in a non-interval manner; the other is a dequeue method deploying a gate control algorithm, the gate control circuit generates a dequeue time table according to the scheduled sending time of all messages stored in the first-in-first-out queue and the order of entering the queue, and the gate control circuit sends out the messages stored in the first-in-first-out queue according to the dequeue time table, and there is a time interval between the dequeued messages.

[0024] Beneficial effects:

[0025] The present application realizes accurate delay control of messages according to delay and bandwidth parameters by combining the calendar queue and the gate control mechanism. The present application can realize message scheduled sending time operation and allocation of an allocated sending time to each message according to the scheduled sending time in the network processor, and can realize fine-grained message forwarding time control under the condition of limited hardware resources. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 is the overall framework schematic diagram of the accurate delay and throughput control method of the present application based on the calendar queue and the gate control mechanism;

[0027] Figure 2 is the circuit logic schematic diagram of the bandwidth operation unit in the present application;

[0028] Figure 3 is the circuit logic schematic diagram of the delay operation unit in the present application;

[0029] Figure 4 is the circuit logic schematic diagram of the packet loss operation unit in the present application. DETAILED DESCRIPTION

[0030] The technical solutions of the present application will be described clearly and completely in combination with the drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0031] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0032] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0033] The specific embodiments of the present application are described in detail below. Figures 1-4 The specific embodiments described herein are intended to illustrate and explain the present application, and are not intended to limit the present application.

[0034] The present application is aimed at packet scheduling in the precise delay throughput scenario, and the design of multi-queue algorithm. The calendar queue is like a real calendar that stores events in each small time period within a period of time from now on. In hardware implementation, the calendar queue is composed of a series of buckets or queues, each queue can store a specific time period in order, and the event can be scheduled to a certain time slot in the future by inserting the event into the queue corresponding to the time period. The abstract model of the calendar queue is a fixed number of buckets or first-in-first-out queues, which is denoted as Based on the calendar queue, a response scheduling algorithm can be deployed. The scheduling algorithm decides which time in the future the packet should be scheduled, that is, to select a queue from the queue. At the same time, the calendar queue will periodically update the time interval corresponding to each queue, which can be logically updated, such as updating after the queue is emptied, or updating the time interval corresponding to the queue according to the clock, after the clock passes a fixed time length.

[0035] The present application provides a precise delay and throughput control method based on calendar queue and gating mechanism. As shown in Figure 1As shown, the system architecture of the present application includes bandwidth operation unit, delay operation unit, packet loss operation unit, time slot discrimination circuit, first-in-first-out queue and de-queue gating logic circuit. Among them, the bandwidth operation unit is used to process the message descriptor, control the bandwidth of each flow, ensure that the traffic of each flow does not exceed the preset bandwidth value, and process the traffic exceeding the bandwidth value according to the leaky bucket model; the delay operation unit is used to calculate the planning time of each message under the preset delay value; the packet loss operation unit is used to select whether to discard the data packet according to the preset packet loss rate; the time slot discrimination circuit is used to select a first-in-first-out queue for the message to enter according to the planning forwarding time calculated in the previous stage circuit; and the de-queue gating opens the gating of the first-in-first-out queue in the corresponding time slot. According to the entering time of the message and the set delay and bandwidth value, the present application calculates the planning time of the message, and the message enters the corresponding calendar queue according to the planning time. The queue generates the allocation time of the gating for each message according to the length of each message and the queue gating mechanism. The gating is opened at each allocation time node, and is closed after the corresponding message is sent. By combining the calendar queue and the gating mechanism, the present application realizes the delay and bandwidth parameters corresponding to the message calculated in the bandwidth operation unit and the delay operation unit based on the message information carried in the message descriptor, and unifies the delay and bandwidth parameters into the planning time control of the message, so as to achieve the purpose of accurate delay control of the message.

[0036] The accurate delay and throughput control method based on the calendar queue and the gating mechanism according to the present application comprises the following steps:

[0037] S1. Processing the message descriptor, calculating the planning sending time of the message and the packet loss state according to the delay, bandwidth and packet loss values;

[0038] S2. Buffering the message in the calendar queue according to the planning sending time, and gating the message in the queue in the sending state;

[0039] S3. Taking out the message body according to the message pointer, and sending the message out from the network interface of the network processor through the PHY interface.

[0040] Specifically, in step S1, the message descriptor includes the message pointer, the message planning time and the packet loss state. The message pointer is an index pointing to the whole message in the storage space of the network processor. After the message descriptor enters the bandwidth operation unit, it will be processed by the logic circuits of the bandwidth operation unit, the delay operation unit and the packet loss operation unit in turn. The functions and implementation algorithms of each part of the logic circuit are introduced as follows.

[0041]

[0042] Step S1 further comprises the following sub-steps:

[0043] The S1.1 bandwidth calculation unit processes packet descriptors, controls the bandwidth of each flow, and ensures that the traffic of each flow does not exceed a preset bandwidth value. Traffic exceeding the bandwidth value is handled according to the leaky bucket model. The leaky bucket model's processing strategy is to buffer traffic whose throughput exceeds the bandwidth value in a short period of time; the limit of the buffer is called the leaky bucket capacity. Packets exceeding the leaky bucket capacity are discarded. Figure 2 As shown, in the bandwidth calculation unit, a unified time upper bound is set for all flows. All data packets exceeding this time upper bound are marked by the bandwidth calculation unit as packets that should be discarded. In this invention, a packet is the smallest unit of packet communication in a computer network. A collection of packets with the same source MAC address and destination MAC address constitutes a flow. The packets in a flow have a sequential order. The information such as MAC address and IP address contained in the packet, after being extracted by the network processing device, is called a packet descriptor. The first packet of each flow creates a minimum forwarding time for this flow in the bandwidth calculation unit. The minimum forwarding time flow.l_s represents that data packets arriving after this flow should be forwarded at least after the minimum forwarding time, which is the time pkt.t_g when the packet leaves the control circuit. The bandwidth calculation unit also stores the bandwidth value corresponding to each flow. The first minimum forwarding time of this flow is the arrival time of the packet pkt.t_c plus the forwarding interval pkt.interval. The forwarding interval is the data packet length pkt.len divided by the bandwidth value of the flow. If the arrival time of the next packet belonging to this flow is less than the minimum forwarding time, then the planned transmission time of that packet will be updated to the minimum forwarding time. If it is greater than the minimum forwarding time, the planned transmission time of that packet will remain the packet's arrival time. If the planned transmission time of a packet exceeds the upper bound, the packet will be marked as discarded. Packets not marked as discarded will have their minimum forwarding time for this flow changed, and the minimum forwarding time will be updated to the packet's planned transmission time plus the required forwarding time. Subsequent packets belonging to this flow will obtain their planned transmission time and discard status, as well as the minimum forwarding time stored in the bandwidth calculation unit, according to the above logic.

[0044] After the S1.2 message descriptor leaves the bandwidth calculation unit, it carries the calculated first planned transmission time into the delay calculation unit. The delay calculation unit further processes this planned transmission time. The function of the delay calculation unit is to calculate the second planned transmission time for each message at a preset delay value. Setting the delay calculation unit allows for changing the preset delay amount, achieving dynamic delay of the messages. Figure 3As shown in the delay operation unit receives the message and message descriptor, the MAC address of the message will be extracted according to the message corresponding delay value, for the start of the jitter mode delay circuit, also will generate a delay jitter value. According to the two read value calculation second planning send time. Delay operation unit will be in the bandwidth operation unit planning send time on the basis of increasing a delay, the new planning send time is equal to the original planning send time plus a preset delay, each message into the delay operation unit for it to match a corresponding delay, then according to this delay update planning send time. Delay is divided into two parts, one part is fixed delay, fixed delay directly to the first planning time, the other part is delay jitter, this part of the function will be according to the user's demand to choose to enable or not to enable, enable delay jitter function, delay operation unit according to the user given delay distribution calculation delay jitter. Delay jitter supports two modes, one mode is fixed jitter value, random generation of jitter value sign, according to is positive or negative, will be added or subtracted to the planning send time corresponding to the jitter value. Another mode is to generate jitter value according to a normal distribution, the mean of the normal distribution is zero, the variance is the user defined variance. The choice of fixed and normal distribution mode depends on the user's demand for delay value generation, from the statistical point of view, the normal distribution mode of jitter value generation is more close to the actual jitter state. Delay operation unit internal logic circuit can produce the expected value of 0, variance of 1 standard normal distribution, according to the standard normal distribution and the transformation between different standard deviation distribution, the specific formula is , wherein σ is the standard deviation of the target distribution, Z is the standard normal distribution value generated by the logic circuit, so as to obtain the required jitter value X。

[0045] S1.3 message descriptor leaves the delay operation unit and carries the planning send time into the packet loss operation unit. The packet loss operation unit will further process the packet loss state. As shown in Figure 4 , after receiving the message and message descriptor, the packet loss operation unit will read the packet loss rate corresponding to the message according to the MAC address of the message, and generate a random value according to the following method. When the packet loss rate is greater than the random value, the message and the corresponding descriptor are discarded. Otherwise, the message enters the next stage of circuit normally.

[0046] The function of the packet loss operation unit is to select whether to discard a data packet according to a preset packet loss rate. The packet loss operation unit has a linear shift register module. The linear shift register module is to arrange a plurality of registers in a row. Each register stores a binary number 0 or 1. The shift register outputs the rightmost number each time, and then moves one bit to the right as a whole. After the shift register moves one bit to the right, a left bit is emptied. At this time, a feedback function is used. The existing sequence in the register is input into the feedback function. After a certain operation of the function, the result output by the feedback function is filled into the leftmost end of the shift register. In this way, the shift register has continuous output. According to the preset initial value of the shift register, a random value can be generated at each hardware beat. When the packet enters the packet loss operation unit, it is matched to the corresponding packet loss rate. The matched packet loss rate is compared with the random value. If the packet loss rate is greater than the random value, the packet is marked as discarded. Otherwise, the packet is not discarded.

[0047] In step S2, the packet descriptors not identified as discarded by the bandwidth operation unit, the delay operation unit and the packet loss operation unit enter the time slot discrimination circuit, the first-in-first-out queue and the logic circuit of the dequeue gate for processing. Next, the functions and implementation algorithms of each part of the logic circuit are introduced. Step S2 specifically includes the following sub-steps:

[0048] S2.1 The time slot discrimination circuit selects a first-in-first-out queue for the packet to enter according to the planning forwarding time calculated in the previous stage circuit. Each first-in-first-out queue corresponds to a time slot. The first-in-first-out queue opens in the time slot to make all the packets inside it go out. The start time and end time of the time slot can also be called the start time and end time of the queue. The time slot discrimination circuit saves the start time and end time state of each queue. When a packet arrives at the time slot discrimination circuit, the planning sending time of the packet is compared with the start time and end time of all the queues in parallel. According to the comparison result, it is determined in which time slot of the queue the planning time of the packet falls. The algorithm of the time slot discrimination circuit is as follows:

[0049]

[0050] The running process of the above code is as follows: for all the first-in-first-out queues in the calendar queue, if the planning sending time of the incoming packet is in the time slot corresponding to a queue, then the total storage length in the queue is calculated. If the length of the incoming packet exceeds the maximum total packet length in the queue after being added, the packet is stored in the calendar queue. Otherwise, the adjacent queue of the queue is checked. If the length of the incoming packet exceeds the maximum total packet length in the adjacent queue after being added, the packet is stored in the adjacent queue.

[0051] It should be noted that the next queue queue.next_queue of the queue refers to the queue which is continuous with the time slot corresponding to the queue queue. When the system time passes through a time slot, the time slot corresponding to a queue is refreshed. In the refreshed time slot, the queue has no next queue next_queue attribute. When the system time passes through another time slot, a new queue becomes the next queue next_queue of the queue.

[0052] The logic of maintaining the time slot corresponding to each queue in the time slot discrimination circuit is as follows: all the time slots corresponding to the queues are initialized. If there are N queues in total, the length of the time slot corresponding to a queue is timeslot. Then the total delay time that the system can handle is N x timeslot. The N queues correspond to a timeslot respectively. After the system clock passes through a timeslot, the time slot corresponding to the queue with the smallest time slot is connected after the queue with the largest time slot in the current system. With the increase of the system clock, queues are continuously corresponding to new timeslots.

[0053] S2.2 The width and depth of the first-in-first-out queue are the bit width of the forwarding exit and the maximum number of bytes that can be forwarded under the premise of the exit bit width respectively. The width and depth of the queue ensure that the packet can be sent at full speed and within a time slot. Before the packet enters the corresponding first-in-first-out queue, a length discrimination is performed. If the remaining capacity of the queue is insufficient for the packet to enter the corresponding current queue, it is determined whether the packet can enter the next queue, which is the queue with the start time equal to the end time of the current queue. If the remaining capacity of the next queue is also insufficient for the packet to enter the queue, it is considered that the current network processor does not have the ability to process the packet, and the packet is discarded.

[0054] S3.3 The exit control opens the control of the first-in-first-out queue in the corresponding time slot. The exit control has two modes. One is the best-effort control, and the packet stored in the first-in-first-out queue is dequeued without interval. The other control method is to deploy the exit way of the control algorithm. The control circuit generates an exit time table according to the planned sending time of all the packets stored in the first-in-first-out queue and the order of entering the queue. The control circuit sends the packets stored in the first-in-first-out queue according to the exit time table, and there is a time interval between the dequeued packets. This algorithm has the characteristics that each iteration can reduce the average absolute error of the total delay deviation of the packets in the time slot, and the result of the exit control can be obtained in a limited step. The deployment of the control algorithm is as follows:

[0055] The gate circuit collects the planning sending time of all the packets and the order in the first-in first-out queue, and finally assigns a sending time to all the packets as the time when the packet leaves the out-gate of the queue. The involved terms and the corresponding English and codes are as follows:

[0056]

[0057] The packet transmission time is the time period required for sending a packet with a length of L under the current port rate setting. The packet sending completion time is the time point when the packet is sent completely, which is equal to the packet assigned sending time plus the packet transmission time The packet waiting queue time is the time required for the packet to wait in the queue under the condition of non-interval sending. The algorithm for assigning a sending time to each packet is shown in Algorithm 1, which is recursively executed until all the packets have assigned sending times. The packet waiting time refers to the total packet transmission time of all the packets arranged in front of the packet in the first-in first-out queue. The functions Assign_time_1, Assign_time_2 and Middle_pkt are called in Algorithm 1.

[0058]

[0059] The symbol in the algorithm represents a time slot from to .

[0060]

[0061]

[0062]

[0063] The function is to sort the contents in from small to large according to . is the index of the element arranged in the middle of .

[0064] In step S3, after the processing is completed, the packet body is taken out according to the packet pointer, and the packet is transferred out from the network interface of the network processor through the PHY interface. After the packet is processed by the out-gate gate circuit, the logic circuit extracts the packet body from the network processor memory according to the packet address pointer carried in the packet descriptor, and re-transmits the packet to the corresponding interface through the PHY interface.

[0065] So far, the precise delay and throughput control method based on the calendar queue and the gating mechanism is introduced.

[0066] The application can realize the operation of message planning sending time and the distribution of a distribution sending time to each message according to the planning sending time in the network processor, and can realize the fine-grained message forwarding time control under the condition of limited hardware resources.

[0067] Any process or method described in the flowchart diagrams of the present application or otherwise described herein can be understood as representing code modules, segments, or portions of code that include one or more executable instructions for implementing specific logic functions or steps within the associated process or method. The code modules, segments, or portions of code can be implemented in any computer readable medium, including memory or storage inside a computer, in order to be executed by an instruction execution system, apparatus, or device. The computer readable medium can be any medium that includes storage, communication, propagation, or transmission for use by or in connection with an instruction execution system, apparatus, or device including, but not limited to, a read-only memory, a magnetic disk, or an optical disk.

[0068] In the description of the present application, the description of the terms "embodiment", "example", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms is not necessarily directed to the same embodiment or example. In addition, those skilled in the art can combine or combine different embodiments or features described in the present specification without producing contradictions.

[0069] Although the above has shown and described the embodiments of the present application, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application, and those skilled in the art can make changes, modifications, replacements, and modifications of the above embodiments within the scope of the present application.

Claims

1. A method for accurate delay and throughput control based on calendar queue and gating mechanism, characterized in that, The method comprises the following steps: S1. processing the message descriptor, calculating the planned sending time of the message according to the delay, bandwidth packet loss value and packet loss state; S2. buffering the message in the calendar queue according to the planned sending time, and gating the message in the queue in the sending state; S3. taking out the message body according to the message pointer, and transmitting the message out from the network interface of the network processor through the PHY interface; In step S2, the time slot discrimination circuit selects a first-in-first-out queue for the message to enter according to the planned forwarding time calculated in the previous stage circuit; each first-in-first-out queue corresponds to a time slot, and the first-in-first-out queue opens in the time slot to transmit all the messages in the first-in-first-out queue; The width and depth of the first-in-first-out queue are the bit width of the forwarding outlet and the maximum number of bytes that can be forwarded under the premise of the outlet bit width, respectively; The out queue gating opens the first-in-first-out queue in the corresponding time slot. In step S1, the message descriptor comprises a message pointer, a message planning time and a packet loss state, and the message pointer is an index pointing to the overall message in the network processor storage space.

2. The method for accurate delay and throughput control based on calendar queue and gating mechanism according to claim 1, wherein, The message descriptor is processed by the logic circuits of the bandwidth operation unit, the delay operation unit and the packet loss operation unit in turn after entering the bandwidth operation unit.

3. The method for accurate delay and throughput control based on calendar queue and gating mechanism according to claim 2, characterized in that, Step S1 comprises:

4. The method for accurate delay and throughput control based on calendar queue and gating mechanism according to claim 1, wherein, S1.1 The bandwidth operation unit processes the message descriptor to control the bandwidth of each flow and ensure that the traffic of each flow does not exceed the preset bandwidth value, and processes the traffic exceeding the bandwidth value according to the leaky bucket model; S1.2 After the message descriptor leaves the bandwidth operation unit, it carries the calculated planning sending time into the delay operation unit, and the delay operation unit calculates the planning time of each message under the preset delay value; S1.3 After the message descriptor leaves the delay operation unit, it carries the calculated planning sending time into the packet loss operation unit, and the packet loss operation unit selects whether to discard the data packet according to the preset packet loss rate. In step S1.2, the delay operation unit increases a delay amount on the basis of the planning sending time of the bandwidth operation unit, and the new planning sending time is equal to the original planning sending time plus the preset delay. Each message is matched with a corresponding delay amount after entering the delay operation unit, and then the planning sending time is updated according to the delay amount.

5. The method for accurate delay and throughput control based on calendar queue and gating mechanism according to claim 4, wherein, In step S1.3, the packet loss operation unit is provided with a linear shift register module, which can generate a random value at each beat according to a preset seed value. The message enters the packet loss operation unit, matches a corresponding packet loss rate, and the matched packet loss rate is compared with the random value. If the packet loss rate is greater than the random value, the message will be marked as discarded, otherwise it will not be discarded.

6. The method for accurate delay and throughput control based on calendar queue and gating mechanism according to claim 4, wherein, In step S2, the message descriptor not marked as discarded by the bandwidth operation unit, the delay operation unit and the packet loss operation unit will enter the logic circuits of the time slot discrimination circuit, the first-in-first-out queue and the out queue gating.

7. The method for accurate delay and throughput control based on calendar queue and gating mechanism according to claim 1, wherein, ​ 8. The method for accurate delay and throughput control based on calendar queue and gating mechanism according to claim 1, wherein, The time slot discrimination circuit stores the start time and end time state of each queue; when a message arrives at the time slot discrimination circuit, the message's scheduled sending time is compared with the start time and end time of all queues in parallel, and the message's scheduled sending time is determined to fall in which queue's time slot according to the comparison result.

9. The method for accurate delay and throughput control based on calendar queue and gating mechanism according to claim 1, wherein, The de-queue control includes two modes, one is the best-effort control, the messages stored in the first-in-first-out queue are de-queued without interval; the other control method is to deploy the de-queue mode of the control algorithm, the control circuit generates a de-queue time table according to the scheduled sending time of all messages stored in the first-in-first-out queue and the order of entering the queue, and the control circuit de-queues the messages stored in the first-in-first-out queue according to the de-queue time table, and there is a time interval between the de-queued messages.

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