Data processing method and device, computer equipment, readable storage medium and program product
By determining the data read/write mode and empty space discrimination strategy of the target buffer unit in video encoding and decoding, and calculating operation instructions, the data read/write problem under multiple tree partitioning methods is solved, achieving efficient data processing and hardware resource optimization.
Patent Information
- Application Number
- CN202511069722.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-14
AI Technical Summary
Existing video encoding and decoding technologies struggle to efficiently read and write data when faced with various tree partitioning methods, leading to wasted hardware resources and data corruption.
By determining the data read/write mode, data block size information, and preset empty space discrimination strategy of the target cache unit, the target operation instruction is calculated to realize the data empty space discrimination of the cache unit and the corresponding read/write operation, supporting data processing under multiple types of tree partitioning methods.
It improves the orderliness of data reading and writing, avoids data corruption, optimizes hardware resource utilization, and adapts to data processing needs under multiple tree partitioning methods.
Smart Images
Figure CN120956918A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of video processing, and in particular to a data processing method, apparatus, computer equipment, readable storage medium, and program product. Background Technology
[0002] With the development of video editing technology, video encoding and decoding technology has become increasingly widespread, becoming an important technology in video processing. In the process of video encoding and decoding, the video image is first divided into segments, and then transformation and transpose calculations are performed based on the resulting image blocks to achieve image encoding. To conserve hardware resources for transpose calculations, time-division multiplexing schemes for horizontal and vertical data access, or vice versa, based on a single buffer unit, are typically used for data reading and writing. For example, an 8x8 matrix (8 rows and 8 columns) can be used in a single buffer unit to achieve either horizontal or vertical data access using time-division multiplexing.
[0003] However, the above read / write method only supports N*N image blocks. With the emergence of new demands such as 4K / 8K, HDR, and 360° video, multi-type tree partitioning (MTT) is becoming increasingly popular. MTT reduces prediction residual energy through finer block partitioning, improving compression efficiency and adaptability to complex scenes. Therefore, there is an urgent need for a data read / write method suitable for multi-type tree partitioning. Summary of the Invention
[0004] Therefore, it is necessary to provide a data processing method, apparatus, computer equipment, readable storage medium, and program product that can be applied to multiple types of tree partitioning methods to address the above-mentioned technical problems.
[0005] In a first aspect, this application provides a data processing method, the method comprising:
[0006] Determine the current data read / write mode of the target cache unit;
[0007] Based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and the preset empty space discrimination strategy, the data empty space discrimination result of the target cache unit is determined;
[0008] Based on the data gap discrimination result, a target operation instruction is determined, wherein the target operation instruction is a write instruction and / or a read instruction;
[0009] Data operations are performed on the target cache unit based on the target operation instructions.
[0010] In one embodiment, determining the data space discrimination result of the target cache unit based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and a preset space discrimination strategy includes:
[0011] Based on the data read / write mode, the current number of data writes, the size information of the first data block to be written in the target cache unit, and the number of pixels written in a single write corresponding to the first data block, the target write position identifier is calculated.
[0012] Calculate the target read location identifier based on the data read / write mode and the current number of data reads;
[0013] Based on the target write location identifier and the target read location identifier, the data gap identification result is determined.
[0014] In one embodiment, the target write location identifier includes a target write row and column index; the target read location identifier includes a target read row and column index;
[0015] The step of determining the data gap identification result based on the target write position identifier and the target read position identifier includes:
[0016] The data empty space discrimination result is determined based on the target write row and column index, the target read row and column index, and the current data read and write status of the target cache unit.
[0017] In one embodiment, determining the data space discrimination result of the target cache unit based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and a preset space discrimination strategy includes:
[0018] Based on the size information of the first data block to be written to the target cache unit, the write strategy corresponding to the first data block is determined, and the amount of data to be written to the first data block is determined according to the write strategy and the number of times the first data block is written.
[0019] Based on the size information of the second data block to be read in the target cache unit, the reading strategy corresponding to the second data block is determined, and the amount of data to be read from the second data block is determined according to the reading strategy and the number of times the second data block is read;
[0020] Based on the amount of data written, the amount of data read, and the data read / write mode, the data empty space discrimination result of the target cache unit is determined.
[0021] In one embodiment, the target operation instruction is a write instruction, and the method further includes:
[0022] When the current first data block is written, the data write mode of the target cache unit is switched, and the current first data block is configured to be valid; the data write mode includes row-by-row writing and column-by-column writing.
[0023] In one embodiment, the target operation instruction is a read instruction, and the method further includes:
[0024] Once the data reading is complete, the data reading mode of the target storage unit is switched, and the data reading mode includes reading by row and reading by column.
[0025] In one embodiment, the method further includes:
[0026] Get the size of the data block to be calculated;
[0027] If the size of the data block to be calculated is greater than a preset size threshold, then during the transformation calculation process, the calculation results in the target region are stored, and the calculation results of other regions in the data block to be calculated, excluding the target region, are set to 0. The target region is a data region containing non-high-frequency coefficients.
[0028] Secondly, this application also provides a data processing apparatus, the apparatus comprising:
[0029] The first determining module is used to determine the current data read / write mode of the target cache unit;
[0030] The second determining module is used to determine the data empty space discrimination result of the target cache unit based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and the preset empty space discrimination strategy.
[0031] The third determining module is used to determine the target operation instruction based on the data gap discrimination result, wherein the target operation instruction is a write instruction and / or a read instruction;
[0032] An operation module is used to perform data operations on the target cache unit based on the target operation instruction.
[0033] In one embodiment, the second determining module is specifically used for:
[0034] Based on the data read / write mode, the current number of data writes, the size information of the first data block to be written in the target cache unit, and the number of pixels written in a single write corresponding to the first data block, the target write position identifier is calculated.
[0035] Calculate the target read location identifier based on the data read / write mode and the current number of data reads;
[0036] Based on the target write location identifier and the target read location identifier, the data gap identification result is determined.
[0037] In one embodiment, the target write location identifier includes a target write row and column index; the target read location identifier includes a target read row and column index;
[0038] The second determining module is specifically used for:
[0039] The data empty space discrimination result is determined based on the target write row and column index, the target read row and column index, and the current data read and write status of the target cache unit.
[0040] In one embodiment, the second determining module is specifically used for:
[0041] Based on the size information of the first data block to be written to the target cache unit, the write strategy corresponding to the first data block is determined, and the amount of data to be written to the first data block is determined according to the write strategy and the number of times the first data block is written.
[0042] Based on the size information of the second data block to be read in the target cache unit, the reading strategy corresponding to the second data block is determined, and the amount of data to be read from the second data block is determined according to the reading strategy and the number of times the second data block is read;
[0043] Based on the amount of data written, the amount of data read, and the data read / write mode, the data empty space discrimination result of the target cache unit is determined.
[0044] In one embodiment, the target operation instruction is a write instruction, and the device further includes:
[0045] The configuration module is used to switch the data writing mode of the target cache unit and configure the current first data block to be valid when the current first data block is written. The data writing mode includes writing by row and writing by column.
[0046] In one embodiment, the target operation instruction is a read instruction, and the device further includes:
[0047] The switching module is used to switch the data reading mode of the target storage unit after the data reading is completed. The data reading mode includes reading by row and reading by column.
[0048] In one embodiment, the device further includes:
[0049] The acquisition module is used to obtain the size of the data block to be calculated;
[0050] The setting module is used to store the calculation results in the target area during the transformation calculation process if the size of the data block to be calculated is greater than a preset size threshold, and set the calculation results of other areas in the data block to be calculated, except the target area, to 0. The target area is a data area containing non-high frequency coefficients.
[0051] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method steps of the first aspect described above.
[0052] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method steps of the first aspect described above.
[0053] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the method steps of the first aspect described above.
[0054] The aforementioned data processing method, apparatus, computer equipment, readable storage medium, and program product can, for data blocks of different sizes, determine whether there are data vacancies in the target cache unit based on the current data read / write mode of the target cache unit, the size information of the first data block to be written to the target cache unit, and a preset vacancy discrimination strategy. Then, based on the data vacancy discrimination result, a target operation instruction is determined, which is a write instruction and / or a read instruction. Subsequently, data operations are performed on the target cache unit based on the target operation instruction, thereby improving the orderliness of reading and writing data blocks of different sizes in the same cache unit, avoiding data read / write errors, and realizing data read / write processing in scenarios where data is partitioned using multiple types of trees. Attached Figure Description
[0055] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0056] Figure 1 This is a flowchart illustrating a data processing method in one embodiment;
[0057] Figure 2a This is a schematic diagram of the data read / write process in one embodiment;
[0058] Figure 2b This is a schematic diagram of the data read / write process in another embodiment;
[0059] Figure 2c This is a schematic diagram of the data read / write process in another embodiment;
[0060] Figure 3 This is a flowchart illustrating an example of a data processing method in one embodiment;
[0061] Figure 4 This is a structural block diagram of a data processing device in one embodiment;
[0062] Figure 5 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0063] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0064] This application provides a data processing method. This embodiment illustrates the method applied to a terminal, but it is understood that the method can also be applied to a server, or to a system including both a terminal and a server, and implemented through interaction between the terminal and the server. It is understood that this method can be applied to any terminal with data processing capabilities, and this application is not limited to any particular type.
[0065] The data processing method provided in this application will be described in detail below with reference to specific implementation methods. For example... Figure 1 As shown, the method includes the following steps:
[0066] Step 102: Determine the current data read / write mode of the target cache unit.
[0067] In this embodiment, a reset initialization can be performed first, and then the terminal can determine the current data read / write mode of the target cache unit. The data read / write mode can include horizontal storage / vertical fetch mode and vertical storage / horizontal fetch mode; the data read / write mode can include a data read mode and a data write mode. In horizontal storage / vertical fetch mode, the data read mode is vertical (i.e., read by column) and the data write mode is horizontal (i.e., write by row). In vertical storage / horizontal fetch mode, the data read mode is horizontal (i.e., read by row) and the data write mode is vertical (i.e., write by column). The target cache unit can be a transposed buffer (buf).
[0068] Within the target cache unit, time-division multiplexing can be used to implement the function of "horizontal storage and vertical retrieval" or "vertical storage and horizontal retrieval" of data. Therefore, the data read / write mode can be switched according to the data block read / write process. The specific switching process will be explained in detail later.
[0069] Step 104: Based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and the preset empty space discrimination strategy, determine the data empty space discrimination result of the target cache unit.
[0070] In this embodiment, the terminal can determine the data space discrimination result of the target cache unit based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and a preset space discrimination strategy. The data space discrimination result can indicate whether there is a data space in the target cache unit.
[0071] Step 106: Determine the target operation instruction based on the data gap discrimination result. The target operation instruction is a write instruction and / or a read instruction.
[0072] In this embodiment of the application, if the data space determination result indicates that there is a data space in the target cache unit, the terminal determines that the target operation instruction includes a write instruction and a read instruction; if the data space determination result indicates that there is no data space in the target cache unit, the terminal determines that the target operation instruction is a read instruction.
[0073] Step 108: Perform data operations on the target cache unit based on the target operation instructions.
[0074] In this embodiment, the terminal can perform corresponding data write and / or data read operations on the target cache unit based on the target operation instruction. It is understood that if the data empty space determination result indicates that there is a data empty space in the target cache unit, the target operation instruction can include a write instruction and a read instruction; that is, the terminal can write a first data block into the target cache unit and simultaneously read data from the target cache unit. If the data empty space determination result indicates that there is no data empty space in the target cache unit, the terminal only performs a data read operation on the target cache unit and does not perform a data write operation.
[0075] The above scheme can be applied to data blocks of different sizes. For data blocks of different sizes, the scheme determines whether there are data vacancies in the target cache unit based on the current data read / write mode of the target cache unit, the size information of the data block, and the preset vacancy discrimination strategy. Then, the target operation instruction is determined based on the data vacancy discrimination result. The target operation instruction is a write instruction and / or a read instruction. Then, data operations are performed on the target cache unit based on the target operation instruction. This improves the orderliness of reading and writing data blocks of different sizes in the same cache unit and avoids data read / write errors. Therefore, it realizes the read and write processing of data (i.e., M*N data blocks) in the scenario of data partitioning by multiple types of trees.
[0076] Optionally, based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and a preset empty space discrimination strategy, the data empty space discrimination result of the target cache unit is determined, including: calculating the target write position identifier based on the data read / write mode, the current number of data writes, the size information of the first data block to be written to the target cache unit, and the number of pixels written in a single write corresponding to the first data block; calculating the target read position identifier based on the data read / write mode and the current number of data reads; and determining the data empty space discrimination result based on the target write position identifier and the target read position identifier.
[0077] In this embodiment, the terminal can calculate the target write position identifier based on the data read / write mode, the current number of data writes, the size information of the first data block to be written in the target cache unit, and the number of pixels written in a single write operation corresponding to the first data block. The target write position identifier is used to identify the current write position of the first data block in the target cache unit. Furthermore, the terminal can also calculate the target read position identifier based on the data read / write mode and the current number of data reads. The target read position identifier can represent the position of the currently read data in the target cache unit.
[0078] The terminal can determine whether there is a data gap between the write position and the read position based on the write position identified by the target write position identifier and the read position identified by the target read position identifier, thereby obtaining the data gap judgment result.
[0079] In one example, the target write position identifier includes the target write row and column index, and the target read position identifier includes the target read row and column index. The target write row and column index (waddr_line_idx) can be calculated as follows:
[0080] waddr_line_idx=din_hk_cnt* PIX_NUM / blk_width
[0081] Wherein, din_hk_cnt represents the current number of data writes, PIX_NUM represents the number of pixels written in a single write, and blk_width represents the width of the first data block.
[0082] It is understandable that when the current data write mode is horizontal, the calculated result is the target write row index, and when the current data write mode is vertical, the calculated result is the target write column index.
[0083] The target read row and column index (raddr_line_idx) can be calculated as follows:
[0084] raddr_line_idx= dout_hk_cnt
[0085] Here, `dout_hk_cnt` represents the current number of data reads. This means that each data read retrieves either a complete row or a complete column of data. Furthermore, when the current data read mode is horizontal, the calculated result is the target row index; when the current data read mode is vertical, the calculated result is the target column index.
[0086] The above method can accurately calculate the row or column index currently being written and the row or column index currently being read, thereby improving the accuracy of the target write position identifier and the target read position identifier, and thus improving the accuracy of data gap identification.
[0087] Optionally, when the target write position identifier includes the target write row and column index and the target read position identifier includes the target read row and column index, the data empty space discrimination result is determined based on the target write position identifier and the target read position identifier, including: determining the data empty space discrimination result based on the target write row and column index, the target read row and column index and the current data read and write status of the target cache unit.
[0088] In this embodiment, the terminal can determine the data gap determination result based on the target write row and column index, the target read row and column index, and the current data read / write status of the target cache unit. Specifically, if the first data block of the target cache unit is not fully written, and the target write row index is less than the height of the data block, or the target write column index is less than the width of the data block, then a data gap exists; otherwise, no data gap exists. When performing data read / write operations in the target cache unit, if reading of an already written data block begins, and the target write row and column index is less than the target read row and column index, and the first data block to be written is not fully written, then a data gap exists; otherwise, no data gap exists. If an already written data block is being read, and the first data block to be written has been fully written, then no data gap exists, and the terminal enters a waiting state.
[0089] The above scheme provides a way to identify data gaps. By comparing the target read row and column indices with the target write row and column indices, it is possible to accurately identify whether there are data gaps, thus improving the reliability of the data gap identification results.
[0090] Optionally, the target write location identifier may also include the target write row and column address, and the target read location identifier may also include the target read row and column address. The terminal can calculate the target write row and column address according to the address calculation strategy corresponding to the current data write mode, and can calculate the target read row and column address according to the address calculation strategy corresponding to the current data read mode.
[0091] Specifically, when the current data write mode is horizontal mode, the target write row address waddr = (din_hk_cnt * PIX_NUM / blk_width) + (din_hk_cnt * PIX_NUM % blk_width) * 16
[0092] When the current data write mode is vertical mode, the target write column address waddr = (din_hk_cnt * PIX_NUM / blk_width) * 16 + (din_hk_cnt * PIX_NUM % blk_width)
[0093] When the current data reading mode is horizontal mode, the target read row address raddr = dou_hk_cnt * 16;
[0094] When the current data reading mode is vertical flat mode, the target reading column address is raddr=dout_hk_cnt.
[0095] Wherein, din_hk_cnt represents the current number of data writes, PIX_NUM represents the number of pixels written in a single write, blk_width represents the width of the first data block, dout_hk_cnt represents the current number of data reads, and % represents the modulo operation.
[0096] In the above scheme, based on the calculated target write row / column address and target read row / column address, the read / write position in the register can be determined during data read / write operations, thereby controlling data read / write. Furthermore, the current data read / write mode (row mode or column mode) can be determined based on the changes in the read / write address.
[0097] Optionally, based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and a preset empty space discrimination strategy, the data empty space discrimination result of the target cache unit is determined, including: based on the size information of the first data block to be written to the target cache unit, determining the write strategy corresponding to the first data block, and determining the write data volume of the first data block according to the write strategy and the number of writes of the first data block; based on the size information of the second data block to be read in the target cache unit, determining the read strategy corresponding to the second data block, and determining the read data volume of the second data block according to the read strategy and the number of reads of the second data block; and based on the write data volume, the read data volume, and the data read / write mode, the data empty space discrimination result of the target cache unit is determined.
[0098] In this embodiment, different read / write strategies can be adopted for data blocks of different sizes. The specific read / write strategies will be described in detail later. It can be understood that the read / write strategy for each data block can be determined based on the size of the data block, under the condition of satisfying the preset chip processing performance. The data read / write strategy can be pre-configured in the terminal. During the read / write process, the corresponding data read / write strategy can be called according to the size of the current data block to read and write the data block.
[0099] The terminal can determine the writing strategy corresponding to the first data block based on the size information of the first data block to be written in the target cache unit. Then, according to the writing strategy, it can determine the number of pixels to be written in a single operation. Finally, it can multiply the number of pixels by the number of times the first data block is written to obtain the amount of data written in the first data block, which is the amount of data that has been written.
[0100] The terminal can also determine the reading strategy corresponding to the second data block based on the size information of the second data block to be read in the target cache unit. Then, according to the reading strategy, it determines the number of pixels to be read in a single operation, and calculates the product of this number of pixels and the number of reads of the second data block to obtain the amount of data read from the second data block. The terminal can identify data gaps in the target cache unit based on the amount of data written, the amount of data read, and the data read / write pattern, obtaining a data gap determination result. In one example, if the first data block of the target cache unit is not fully written, and the amount of data written is less than the amount of data in the currently written first data block, then there is a data gap; otherwise, there is no data gap. When performing data read / write operations in the target cache unit, if reading an already written data block begins, and the amount of data written is less than the amount of data read, and the first data block to be written is not fully written, then there is a data gap; otherwise, there is no data gap. If an already written data block is being read, and the first data block to be written has been fully written, then there is no data gap, and the terminal enters a waiting state.
[0101] The above solution provides another way to identify data gaps. By calculating the amount of data written, the amount of data read, and the data read / write pattern, it can identify data gaps in the target cache unit, thereby improving the accuracy of identifying data gaps in the target cache unit.
[0102] Optionally, when the target operation instruction is a write instruction, the method further includes: after the current first data block is written, switching the data write mode of the target cache unit and configuring the current first data block to be valid; the data write mode includes row-by-row writing and column-by-column writing.
[0103] In this embodiment, during the data block writing process, the terminal can determine whether the current data block writing is complete. Specifically, when blk_wr_done=1, it indicates that the current first data block has been written completely. The value of wr_hor_flag is inverted to switch the data writing mode of the target cache unit. For example, if the current data writing mode is horizontal mode, it switches to vertical mode. The terminal can also pull the read data valid signal dou_vld high to configure the current first data block as valid. When Blk_wr_done=0, it indicates that the data block has not yet been written completely, so the terminal can set dou_vld to 0 and wait for data to be written. Here, wr_hor_flag is used to identify the data writing mode.
[0104] Optionally, when the target operation instruction is a read instruction, the method further includes: after the data reading is completed, switching the data reading mode of the target storage unit, whereby the data reading mode includes reading by row and reading by column.
[0105] In this embodiment, when `dout_vld=1`, it indicates that data is currently being read. The terminal can determine whether the current block has been read completely. If it has, the value of `rd_hor_flag` is inverted, and the data read mode of the target storage unit is switched. Then, it checks whether all `blk` blocks have been read completely. If all `blk` blocks have been read completely, the process ends; otherwise, it continues to wait for data to be read. If the current block has not been read completely, it waits for data to be read. `rd_hor_flag` is used to identify the data read mode.
[0106] Optionally, the method further includes: obtaining the size of the data block to be calculated; if the size of the data block to be calculated is greater than a preset size threshold, then during the transformation calculation process, storing the calculation results in the target area, and setting the calculation results of other areas in the data block to be calculated, except for the target area, to 0, wherein the target area is a data area containing non-high frequency coefficients.
[0107] In this embodiment of the application, during the video encoding and decoding process, the video image can first be divided into MTT segments, and then transformation and transpose calculations can be performed based on the segmented image blocks. For example, a 2D transformation calculation is usually converted into two 1D calculations, that is, it is converted into two identical 1D calculations. However, a transpose calculation is required for the result of the first transformation calculation. For example, for a 32*32 data block X, the formula for the first step transformation can be: X*(H^T)=Y, where H is a 32*16 coefficient matrix, and Y is the result of the first step transformation, which is a 16*32 matrix; the formula for the second step transformation can be: H*Y=Z, where Y is the result of the first step transformation, and Z is the second step transformation, which is a 16*16 matrix.
[0108] During the transformation process, the terminal can obtain the size of the data block to be calculated. If the size of the data block to be calculated is greater than a preset size threshold, then during the transformation calculation, only the calculation results in the target area (i.e., partial calculation results) are stored, and the calculation results in other areas of the data block to be calculated, excluding the target area, are set to 0. The target area is the data area containing non-high-frequency coefficients. For example, during the transformation process, for large data blocks such as CU32 and CU64, only the calculation results of the top left 16*16 area are retained, i.e., the high-frequency coefficients are set to 0.
[0109] In the above scheme, since the transformation process often only retains the top-left 1 / 4 of the calculation results for large data blocks such as CU32 and CU64, i.e., the high-frequency coefficients are set to 0, the size of the data block stored in the transpose buffer and the corresponding data read / write strategy include:
[0110] For a 16*32 luminance block, if the original residual data block is 32*32, then 2 pixels are written every 1clk and 32 pixels are read every 8clk; if the original residual data block is 16*32, then 4 pixels are written every 1clk and 32 pixels are read every 8clk.
[0111] A 16*16 luminance block, writes 4 pixels every 1clk, and reads 16 pixels every 4clk;
[0112] A 16*8 luminance block, writes 4 pixels every 1 clk and reads 8 pixels every 2 clk;
[0113] An 8*32 luminance block is used, with 4 pixels written every 1 clk and 32 pixels read every 8 clk.
[0114] A 16*16 chroma block, 4 pixels are written every 1 clk, and 16 pixels are read every 4 clk;
[0115] A 16*8 chroma block, 4 pixels are written every 1 clk, and 8 pixels are read every 2 clk;
[0116] An 8*16 chroma block, 4 pixels are written every 1 clk, and 16 pixels are read every 4 clk;
[0117] A 16*4 chroma block, 4 pixels are written every 1clk, and 4 pixels are read every 1clk;
[0118] A 4*16 chroma block, 4 pixels are written every 1 clk, and 16 pixels are read every 4 clk.
[0119] The above solution supports M*N type transposes, minimizing computational area while meeting requirements. Taking a 32*32 block as an example, traditional techniques use two 32*32 blocks for computation. Assuming processor performance limits, one clock cycle requires writing four pixels. This solution uses a 32*16 block for computation. In the same timeframe (e.g., one clock cycle), each clock cycle only needs to perform 2 pixels, effectively reducing the computational area.
[0120] This application also provides an example of the data read / write process in the target storage unit, as detailed below:
[0121] Assuming the size of a single stored pixel is 16 bits, the size of the transposed buffer used for the CU32 can be set to 16*32*16 bits. Then, for a data block of size a*b followed by a data block of size c*d, a and c can be less than or equal to 16. First, consider the case where b and d are both less than or equal to 16. For example, the data read / write process for a 16*16 data block followed by an 8*16 data block transposed buffer is as follows... Figure 2a As shown in the diagram, the green blocks are 16x16 data blocks, and the 8x16 blocks are red data blocks. Data reading can begin after the first group of data in the bottom row of the green data block is written. Once the first column of data in the green block is read, the red data block can be written. In this case, the reading of the red block can begin after all the data in the green block has been read. Similarly, after the first row of data in the red block is read, the next data block (such as the first row of green data blocks in the diagram) can be written. It can be understood that one square in the diagram represents one pixel. The data read / write mode for the green data block is horizontal storage and vertical retrieval, while the data read / write mode for the red block is the opposite: vertical storage and horizontal retrieval.
[0122] For cases where either b or d is greater than 16, such as an 8*32 data block followed by a 16*16 data block, the transposed buf data read / write diagram is as follows: Figure 2b As shown in the diagram, the green data block is an 8x32 data block, and the red data block is a 16x16 data block. Data reading can begin after the first group of data in the bottom row of the green data block is written. Once the first column of data in the green block is read, the red data block can be written. In this case, the right half of the red data block is written only after the entire green data block has been read to avoid data conflicts. Similarly, after the first row of the red data block is read, the next data block can be written.
[0123] In cases where two numbers in b and d are greater than 16, such as a 16*32 data block followed by an 8*32 data block, the transpose buf data read / write process is as follows: Figure 2cAs shown in the diagram. The green data block is a 16*32 data block, and the red data block is an 8*32 data block. Data reading can begin after the first group of data in the bottom row of the green data block is written. Once the first column of data in the green block is read, the red data block can be written. Because the buf size is not rectangular, the vertical storage and horizontal retrieval order of the 16*32 and 8*32 data blocks is somewhat special. Specifically, when reading data from a 16*32 data block, the first and 17th rows are read first, followed by the other rows; for an 8*32 data block, the first, 9th, 17th, and 25th rows are read first, followed by the other rows.
[0124] This application also provides examples of data processing methods, such as... Figure 3 As shown, it includes the following steps:
[0125] Step 301: Reset and initialize.
[0126] Step 302: Determine the data writing mode based on wr_hor_flag.
[0127] Here, wr_hor_flag being 1 indicates that the data writing mode is horizontal, otherwise it is vertical.
[0128] Step 303: Calculate the data write address waddr according to the address calculation strategy corresponding to the data write mode.
[0129] Different write modes require different address calculation methods.
[0130] Step 304: Calculate the target data and write it into the row and column indexes.
[0131] Step 305: Determine the data reading mode based on Rd_hor_flag.
[0132] Step 306: Calculate the data read address according to the address calculation strategy corresponding to the data read mode.
[0133] Step 307: Calculate the target row and column index of the data.
[0134] Step 308: Determine if the current buf is empty.
[0135] If buf is empty, then the data can be loaded and step 309 is executed; otherwise, step 310 is executed.
[0136] Step 309: Pull the writable signal din_rdy of buf high.
[0137] Step 310: Determine whether there are any empty data slots based on the target write row and column index, the target read row and column index, and the current data read / write status of the target cache unit.
[0138] If there are empty data slots, proceed to step 311; otherwise, proceed to step 312.
[0139] Step 311: Pull din_rdy high and write the data.
[0140] Step 312: Pull din_rdy low and wait for the data to be read.
[0141] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0142] Based on the same inventive concept, this application also provides a data processing apparatus for implementing the data processing method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more data processing apparatus embodiments provided below can be found in the limitations of the data processing method described above, and will not be repeated here.
[0143] In one exemplary embodiment, such as Figure 4 As shown, a data processing device is provided, the device comprising: a first determining module 410, a second determining module 420, a third determining module 430, and an operation module 440.
[0144] The first determining module 410 is used to determine the current data read / write mode of the target cache unit;
[0145] The second determining module 420 is used to determine the data empty space discrimination result of the target cache unit based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and the preset empty space discrimination strategy.
[0146] The third determining module 430 is used to determine the target operation instruction based on the data gap discrimination result, wherein the target operation instruction is a write instruction and / or a read instruction.
[0147] The operation module 440 is used to perform data operations on the target cache unit based on the target operation instruction.
[0148] In one embodiment, the second determining module 420 is specifically used for:
[0149] Based on the data read / write mode, the current number of data writes, the size information of the first data block to be written in the target cache unit, and the number of pixels written in a single write corresponding to the first data block, the target write position identifier is calculated.
[0150] Calculate the target read location identifier based on the data read / write mode and the current number of data reads;
[0151] Based on the target write location identifier and the target read location identifier, the data gap identification result is determined.
[0152] In one embodiment, the target write location identifier includes a target write row and column index; the target read location identifier includes a target read row and column index;
[0153] The second determining module 420 is specifically used for:
[0154] Based on the target write row and column index, the target read row and column index, and the current data read / write status of the target cache unit, determine whether there are any empty data slots.
[0155] In one embodiment, the second determining module 420 is specifically used for:
[0156] Based on the size information of the first data block to be written to the target cache unit, the write strategy corresponding to the first data block is determined, and the amount of data to be written to the first data block is determined according to the write strategy and the number of times the first data block is written.
[0157] Based on the size information of the second data block to be read in the target cache unit, the reading strategy corresponding to the second data block is determined, and the amount of data to be read from the second data block is determined according to the reading strategy and the number of times the second data block is read;
[0158] Based on the amount of data written, the amount of data read, and the data read / write mode, the data empty space discrimination result of the target cache unit is determined.
[0159] In one embodiment, the target operation instruction is a write instruction, and the device further includes:
[0160] The configuration module is used to switch the data writing mode of the target cache unit and configure the current first data block to be valid when the current first data block is written. The data writing mode includes writing by row and writing by column.
[0161] In one embodiment, the target operation instruction is a read instruction, and the device further includes:
[0162] The switching module is used to switch the data reading mode of the target storage unit after the data reading is completed. The data reading mode includes reading by row and reading by column.
[0163] In one embodiment, the device further includes:
[0164] The acquisition module is used to obtain the size of the data block to be calculated;
[0165] The setting module is used to store the calculation results in the target area during the transformation calculation process if the size of the data block to be calculated is greater than a preset size threshold, and set the calculation results of other areas in the data block to be calculated, except the target area, to 0. The target area is a data area containing non-high frequency coefficients.
[0166] Each module in the aforementioned data processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the operations corresponding to each module.
[0167] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 5As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a data processing method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.
[0168] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0169] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the above-described method steps.
[0170] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the above-described method steps.
[0171] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the above-described method steps.
[0172] It should be noted that the user information (including but not limited to user device identifiers, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.
[0173] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.
[0174] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0175] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A data processing method, characterized in that, The method includes: Determine the current data read / write mode of the target cache unit; Based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and the preset empty space discrimination strategy, the data empty space discrimination result of the target cache unit is determined; Based on the data gap discrimination result, a target operation instruction is determined, wherein the target operation instruction is a write instruction and / or a read instruction; Data operations are performed on the target cache unit based on the target operation instructions.
2. The method according to claim 1, characterized in that, The step of determining the data empty space discrimination result of the target cache unit based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and the preset empty space discrimination strategy includes: Based on the data read / write mode, the current number of data writes, the size information of the first data block to be written in the target cache unit, and the number of pixels written in a single write corresponding to the first data block, the target write position identifier is calculated. Calculate the target read location identifier based on the data read / write mode and the current number of data reads; Based on the target write location identifier and the target read location identifier, the data gap identification result is determined.
3. The method according to claim 2, characterized in that, The target write location identifier includes the target write row and column index; the target read location identifier includes the target read row and column index; The step of determining the data gap identification result based on the target write position identifier and the target read position identifier includes: The data empty space discrimination result is determined based on the target write row and column index, the target read row and column index, and the current data read and write status of the target cache unit.
4. The method according to claim 1, characterized in that, The step of determining the data empty space discrimination result of the target cache unit based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and the preset empty space discrimination strategy includes: Based on the size information of the first data block to be written to the target cache unit, the write strategy corresponding to the first data block is determined, and the amount of data to be written to the first data block is determined according to the write strategy and the number of times the first data block is written. Based on the size information of the second data block to be read in the target cache unit, the reading strategy corresponding to the second data block is determined, and the amount of data to be read from the second data block is determined according to the reading strategy and the number of times the second data block is read; Based on the amount of data written, the amount of data read, and the data read / write mode, the data empty space discrimination result of the target cache unit is determined.
5. The method according to claim 1, characterized in that, The target operation instruction is a write instruction, and the method further includes: When the current first data block is written, the data write mode of the target cache unit is switched, and the current first data block is configured to be valid; the data write mode includes row-by-row writing and column-by-column writing.
6. The method according to claim 1, characterized in that, The target operation instruction is a read instruction, and the method further includes: Once the data reading is complete, the data reading mode of the target storage unit is switched, and the data reading mode includes reading by row and reading by column.
7. The method according to claim 1, characterized in that, The method further includes: Get the size of the data block to be calculated; If the size of the data block to be calculated is greater than a preset size threshold, then during the transformation calculation process, the calculation results in the target region are stored, and the calculation results of other regions in the data block to be calculated, excluding the target region, are set to 0. The target region is a data region containing non-high-frequency coefficients.
8. A data processing apparatus, characterized in that, The device includes: The first determining module is used to determine the current data read / write mode of the target cache unit; The second determining module is used to determine the data empty space discrimination result of the target cache unit based on the data read / write mode, the size information of the first data block to be written to the target cache unit, and the preset empty space discrimination strategy. The third determining module is used to determine the target operation instruction based on the data gap discrimination result, wherein the target operation instruction is a write instruction and / or a read instruction; An operation module is used to perform data operations on the target cache unit based on the target operation instruction.
9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.