Semiconductor structure, preparation method and electronic equipment

Abstract

The invention discloses a semiconductor structure, a preparation method and electronic equipment. The preparation method comprises the following steps: providing a substrate on which an MOS (Metal Oxide Semiconductor) tube region is formed; the MOS tube region comprises a fin type structure; forming a groove structure on the fin structure, wherein at least one wall body is formed in the groove structure; the groove structure is divided into at least two groove areas by the at least one wall body; and epitaxially growing a channel material in the groove structure with the at least one wall body to form a channel layer. The at least one wall body is formed in the groove structure, the groove structure is divided into the at least two groove areas, in the subsequent channel layer forming process, the channel material can react with at least part of the wall body, the growth rate of the channel layer on the peripheral side of the wall body is increased, and the yield of the channel layer is improved. The growth rate difference between the channel layer on the peripheral side of the wall body and the channel layer on the side wall of the groove structure is reduced, the uniformity and flatness of the surface of the channel layer are improved, and the problem of electric leakage caused by penetration of the channel layer in the subsequent process is prevented.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure, fabrication method, and electronic device. Background Technology

[0002] During the formation of the channel layer in a trench structure, the growth rate of the channel material varies in different lattice directions. When the trench structure is wide, the growth rate of the channel layer in the middle of the trench structure is much lower than that at the sidewalls of the trench structure. This causes the long channel region of semiconductor devices, especially long-channel devices, to easily form a V-shaped channel layer, which is prone to underfilling. In the subsequent contact process, the bottom of the V-shaped channel layer is easily penetrated, resulting in leakage current in the semiconductor device and low fabrication yield. Summary of the Invention

[0003] To address the problems of the prior art, this application provides a semiconductor structure, a fabrication method, and an electronic device. The technical solution is as follows:

[0004] On one hand, this application provides a method for fabricating a semiconductor structure, comprising:

[0005] A substrate is provided in which a MOS transistor region is formed; the MOS transistor region includes a fin structure.

[0006] A groove structure is formed on the fin structure, and at least one wall is formed in the groove structure; the at least one wall divides the groove structure into at least two groove regions;

[0007] A channel material is epitaxially grown in the trench structure having at least one wall to form a channel layer; the channel material is different from the material of the sidewall of the trench structure.

[0008] In some exemplary embodiments, the length of the trench structure is greater than or equal to a preset length, wherein the preset length is 20 nm to 200 nm.

[0009] In some exemplary embodiments, the at least one wall divides the trench structure into equal parts along its length.

[0010] Furthermore, the formation of a groove structure on the fin structure, and the formation of at least one wall in the groove structure, includes:

[0011] A photoresist layer is formed on the fin structure;

[0012] The photoresist layer is patterned to form at least one dam on the fin structure;

[0013] The fin structure on which at least one dam body is formed is etched to form the groove structure, and the wall body is formed on the area corresponding to the dam body.

[0014] Furthermore, the critical dimensions of the wall are determined based on the growth rate of the channel layer, and the critical dimensions of the wall are positively correlated with the growth rate of the channel layer.

[0015] In some exemplary embodiments, the height of the wall is less than or equal to the thickness of the trench layer.

[0016] Furthermore, after the trench layer is formed, the ratio between the height of the remaining wall portion in the trench layer and the thickness of the trench layer is less than or equal to a target ratio, which is 1 / 3 to 1 / 2.

[0017] Furthermore, before forming a groove structure on the fin structure, and before forming at least one wall in the groove structure, the method further includes:

[0018] At least two gates are formed on the fin structure; the channel layer is located between two adjacent gates.

[0019] Furthermore, the channel layer includes at least one of silicon-germanium channel and silicon-phosphorus channel.

[0020] On the other hand, this application also provides a semiconductor structure prepared by the preparation method described in any of the preceding claims.

[0021] Furthermore, the trench layer includes a residual portion of the wall, and the ratio between the height of the residual portion of the wall and the thickness of the trench layer is less than or equal to a target ratio, wherein the target ratio is 1 / 3 to 1 / 2.

[0022] On the other hand, this application also provides an electronic device including the semiconductor structure described above.

[0023] In the process of forming a trench structure on a fin structure, this application forms at least one wall in the trench structure, which can divide the trench structure into at least two trench regions. During the subsequent epitaxial growth of the trench material to form the trench layer, the trench material can react with at least a portion of the wall, accelerating the growth rate of the trench layer around the wall, reducing the difference between the growth rate of the trench layer around the wall and the growth rate of the trench layer at the edge of the trench structure, improving the uniformity and smoothness of the trench layer surface, preventing the trench layer from being penetrated in subsequent processes and causing leakage problems, greatly improving the preparation yield of the semiconductor structure, and improving the operational stability, operational reliability and lifespan of the device with the semiconductor structure. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart of a method for preparing a channel layer in the prior art;

[0026] Figure 2 A flowchart of a method for fabricating a semiconductor structure provided in this application;

[0027] Figure 3 A structural cross-sectional view of a wall formed in a trench structure, provided in an embodiment of this application;

[0028] Figure 4 A cross-sectional view of a channel layer provided in an embodiment of this application;

[0029] Figure 5 A flowchart of a method for preparing a wall structure provided in this application;

[0030] Figure 6 This is a cross-sectional view of the semiconductor structure in an exemplary embodiment of this application;

[0031] Figure 7 For example Figure 6 The flowchart shows the method for fabricating the semiconductor structure.

[0032] The attached figures are labeled as follows:

[0033] 100 - MOS transistor region, 110 - fin structure, 200 - trench structure, 300 - wall, 310 - residual wall, 400 - channel layer, 500 - photoresist layer, 510 - dam, 600 - gate, 700 - shallow trench isolation structure. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe specific objects or a sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0037] In semiconductor devices, a channel layer is formed between the source and drain of a field-effect transistor (FET) to enable the semiconductor device to conduct through the channel layer during operation; for example... Figure 1 As shown, in the process of manufacturing the channel layer, trench structures are often formed on the semiconductor structure, and then channel materials are epitaxially grown in the trench structure to form the channel layer. However, the growth rate of the channel material is different in different lattice directions, and the channel material is mostly grown along the crystal phase of silicon. Among them, for the short channel region (SC) of semiconductor devices, the trench structure length is very small, that is, the distance between the silicon sidewalls on both sides of the trench structure is extremely small. Therefore, during the formation of the channel layer, the difference in the growth rate of the channel material along the crystal phase of silicon is extremely small, and the formed channel layer is relatively uniform, with good flatness and less prone to leakage. The short channel region can be prepared according to conventional processes.

[0038] However, when the trench structure is long, especially in the long channel (LC) region of semiconductor devices, such as Figure 1 As shown, in the trench structure of the long trench region, the crystal phase at the bottom of the trench structure is almost horizontal, which results in a slow growth rate of the trench material. However, in the region near the sidewall of the trench structure, the trench material can grow along the silicon crystal phase on the sidewall, and the growth rate is faster. This eventually leads to the formation of a V-shaped trench layer with a central depression in the long trench region. In subsequent processing, the central depression of the V-shaped trench layer is extremely easy to be corroded or etched through, resulting in exposed silicon at the bottom and leakage problems.

[0039] To address the issue that the epitaxially grown channel layer in the aforementioned trench structure is prone to V-shaped formation, which can easily corrode and penetrate during subsequent processes, leading to leakage, this application provides a semiconductor structure, a fabrication method, and an electronic device. The fabrication method for the semiconductor structure includes providing a substrate with a MOS transistor region, the MOS transistor region including a fin structure; forming a trench structure on the fin structure, and forming at least one wall in the trench structure, the at least one wall dividing the trench structure into at least two trench regions; and then epitaxially growing a channel material in the trench structure with the at least one wall to form a channel layer, the channel material being different from the material of the trench structure sidewalls. During the formation of the trench structure, at least one wall is formed within the trench structure. This wall is made of the same material as the sidewall of the trench structure, i.e., the fin structure (or substrate). This increases the growth rate of the channel material around the wall during subsequent epitaxial growth of the channel material, reducing the difference between the growth rate of the channel material along the wall material and the growth rate along the sidewall material of the trench structure. This results in a more uniform and flat channel layer in the relatively long trench structure, preventing the center of the channel layer from being recessed. Consequently, it avoids local penetration of the channel layer and leakage in subsequent processes, greatly improving the yield of semiconductor structure fabrication and enhancing the structural performance, stability, and reliability of the semiconductor structure.

[0040] The following combination Figure 2-5 The method for fabricating the semiconductor structure according to the embodiments of this application will be described in detail.

[0041] See Figure 2 A substrate is provided in which a MOS transistor region is formed; the MOS transistor region includes a fin structure 110.

[0042] The MOS transistor region 100 is used to form the source / drain region, and the MOS transistor region 100 includes a fin structure 110, such as... Figure 2As shown, the substrate surface where the MOS transistor region 100 is formed is in an open state, that is, the surface of the fin structure 110 is exposed, so as to facilitate the trenching operation of the fin structure 110 in subsequent processes; in some exemplary embodiments, the material of the fin structure 110 is silicon, that is, the material of the substrate 100 and the sidewall of the trench structure 200 is silicon. The fin structure 110 can be formed by a series of photolithography processes such as hard mask epitaxial growth, exposure, etching, and cleaning removal, and multiple fin structures 110 are formed on the MOS transistor region 100, such as Figure 2 The diagram shows the fabrication process for forming a channel layer 400 on a single fin structure 110. Multiple channel layers 400 can be formed simultaneously or sequentially on multiple fin structures 110 using the same fabrication process.

[0043] Next, refer to Figure 2 A groove structure is formed on the fin structure, and at least one wall is formed in the groove structure.

[0044] Specifically, in some exemplary embodiments, the length of the trench structure 200 is greater than or equal to a preset length, which is 20nm to 200nm. Understandably, the preset length can be any value between 60nm and 150nm. Exemplarily, the preset length can be 20nm, 30nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 120nm, 130nm, 140nm, 150nm, 170nm, 200nm, etc. Thus, this fabrication method can be applied to various long-channel devices, or to long-channel regions in various semiconductor devices, eliminating the need for long-channel devices. This invention addresses the bottom filling issue during the formation of the trench layer 400 in a long trench region, preventing leakage in long trench devices. The fabrication process is simple and widely applicable. In some preferred embodiments, the preset length is 80nm to 150nm. For example, in one specific embodiment, the preset length is 80nm. If the length of the trench structure 200 is greater than or equal to 80nm, the semiconductor structure fabrication method provided in this application can be used for fabrication. In another specific embodiment, the preset length is 120nm. If the length of the trench structure 200 is greater than or equal to 120nm, the semiconductor structure fabrication method provided in this application can be used for fabrication.

[0045] Furthermore, it should be noted that the preset length is determined based on the performance of the processing equipment. Under other preset lengths, if the performance of the processing equipment is insufficient, the bottom filling problem may still easily occur even under a smaller preset length. Alternatively, the semiconductor structure preparation method provided in this application can be used to form a channel layer 400 in a relatively short trench structure 200 to solve the bottom filling problem during the formation of the channel layer 400, avoid leakage, and provide good flexibility and versatility.

[0046] In this configuration, at least one wall 300 divides the trench structure 200 into at least two trench regions. That is, the wall 300 is formed inside the trench structure 200, rather than on the sidewall of the trench structure 200, and there is a certain distance between the wall 300 and the sidewall of the trench structure 200. This allows the growth rate of the trench material away from the sidewall of the trench structure 200 to be increased during the subsequent epitaxial growth of the trench material, effectively preventing the trench layer 400 from sinking in the middle.

[0047] Wall 300 is a portion of the fin structure 110 retained during the formation of the trench structure 200. That is, the material of wall 300 is the same as the material of the sidewall of the trench structure 200, i.e., the fin structure 110, both being silicon material. Figure 3 As shown, the shape of the wall 300 is close to a sharp angle. This wall 300 is used to allow the subsequent epitaxial growth of the channel material to grow along the crystal phase direction of the wall 300 material, thereby accelerating the growth rate of the channel material around the wall 300. Compared to the case where the silicon crystal phase at the bottom of a conventional trench structure is horizontal, the presence of the wall 300 makes the growth rate of the channel material around the wall 300 along the silicon crystal phase relatively faster, consistent with the growth rate of the channel material in the sidewall region of the trench structure 200, thus greatly improving the uniformity of the subsequently formed trench layer 400. The introduction of the wall 300 shortens the spacing between two adjacent silicon materials, that is, the length of each trench region is shortened relative to the overall length of the trench structure 200. Each trench region can be used as a short channel region. The overall growth rate of the channel material in each trench region (i.e., the channel material between one side wall of the trench structure 200 and an adjacent wall 300 or the channel material between two adjacent walls 300) can also be improved to a certain extent, thereby improving the preparation efficiency and saving preparation time.

[0048] Specifically, in some exemplary embodiments, at least one wall 300 divides the trench structure 200 equally along its length to improve the consistency of the growth rate of the channel material at various locations within the trench structure 200 during subsequent epitaxial growth, thereby improving the uniformity and smoothness of the channel layer 400. In some exemplary embodiments, multiple wall structures 300 are formed within the trench structure 200, meaning that multiple walls 300 divide the trench structure 200 equally along its length, which is beneficial for improving the consistency of the growth rate of the channel material and accelerating the overall growth of the channel layer 400. Growth rate; In some exemplary embodiments, a wall 300 is formed within the trench structure 200, which is located in the central region of the trench structure 200 to bisecte the trench structure 200 along its length, thereby accelerating the growth rate of the channel material in the central region away from the sidewall of the trench structure 200. The growth rate of the channel material on both sides of the wall 300 is consistent, so that the channel layer 400 grown epitaxially in the trench structure 200 has a relatively flat surface in both the central region and the sidewall region, with good uniformity, effectively avoiding the formation of V-shaped channel layers and the occurrence of leakage problems.

[0049] Specifically, in some exemplary embodiments, the critical dimensions of the wall 300 are determined based on the length of the trench structure 200, and these critical dimensions are positively correlated with the length of the trench structure 200. The critical dimensions may include the line width of the wall 300, or the distance between the wall 300 and the sidewalls of adjacent trench structures 200 (i.e., the location where the wall 300 is formed). The number of walls 300 may also be included.

[0050] For example, the relatively long trench structure 200 indicates a significant difference in the growth rate of the channel material in the central region and the sidewall region of the trench structure 200. Correspondingly, the line width of the wall 300 can be increased, or the number of walls 300 can be increased, so that the growth rate of the channel material around the wall 300 is relatively fast during subsequent epitaxial growth, and is consistent with the growth rate of the channel material in the sidewall region of the trench structure 200. This prevents uneven growth rates or the wall 300 from being consumed in the early stages of epitaxial growth, which could lead to V-shaped depressions in the channel layer 400. This improves the overall growth rate of the trench structure 200. The uniformity, accuracy, and reliability of the formation of the channel layer 400 are ensured. Conversely, a shorter trench structure 200 indicates a smaller difference in the growth rate of the channel material in the central region and the sidewall region of the trench structure 200. Correspondingly, the line width of the wall 300 can be narrowed, or the number of walls 300 can be reduced. This is to prevent excessive residual wall 300 after epitaxial growth and excessively thin channel layer 400 area above the wall 300, which could lead to exposed tips of the wall 300 and leakage during subsequent processing. It also helps to reduce process difficulty and save preparation costs.

[0051] Specifically, in some exemplary embodiments, the critical dimensions of the wall 300 are determined based on the growth rate of the channel layer 400, and the critical dimensions of the wall 300 are positively correlated with the growth rate of the channel layer 400. For example, if the growth rate of the channel layer 400 is faster in subsequent steps, it indicates that the wall 300 is consumed quickly during the epitaxial growth process. Correspondingly, the critical dimensions of the wall 300 formed in the previous step can be selected as relatively large values. For example, the line width of the wall 300 can be increased accordingly, so that the growth rate of the channel material around the wall 300 is faster during the epitaxial growth process, preventing the wall 300 from being consumed in the early stage of epitaxial growth and causing the growth rate of the central area to be lower. A fast-to-slow growth rate can still easily lead to V-shaped depressions, thus improving the accuracy and reliability of the trench layer 400 formation. Conversely, a slower growth rate in subsequent steps indicates that the wall 300 is consumed more slowly during epitaxial growth. Correspondingly, the key dimensions of the wall 300 formed in the previous step can be selected to be relatively small values. For example, the line width of the wall 300 can be narrowed accordingly to prevent excessive residual wall 300 after epitaxial growth and excessively thin trench layer 400 area above the wall 300, which could lead to exposed tips of the wall 300 and leakage in subsequent processing. This also helps to improve the accuracy and reliability of the trench layer 400 formation.

[0052] In some preferred embodiments, the critical dimensions of the wall 300 are determined based on the growth rate of the trench layer 400 and the length of the trench structure 200. The critical dimensions of the wall 300 are positively correlated with the length of the trench structure 200 and the growth rate of the trench layer 400.

[0053] Specifically, in some exemplary embodiments, the height of the wall 300 is less than or equal to the thickness of the trench layer 400, so as to prevent the formation of a V-shaped trench layer 400 and ensure that the residual wall 300 in the final trench layer 400 is not easily exposed and leaks electricity, thus doubly improving the effectiveness and reliability of preventing leakage. In some preferred embodiments, the height of the wall 300 is equal to the thickness of the trench layer 400, that is, the height of the wall 300 is flush with the height of the trench layer 400, which can greatly improve the uniformity and flatness of the trench layer 400 obtained by subsequent epitaxial growth, and can also effectively prevent the residual wall 300 from being exposed and leaking electricity after the subsequent epitaxial growth step.

[0054] In addition, in some alternative embodiments, the height of the wall 300 can also be selected to be slightly higher than the height of the trench layer 400. During the subsequent extensional growth of the trench layer 400, the material of the wall 300 is consumed, resulting in a reduction in the height of the wall 300. As long as the height of the remaining part of the wall 310 in the final trench layer 400 is less than the thickness of the trench layer 400, this application does not make specific limitations in this regard.

[0055] Next, refer to Figure 2 In a groove structure having at least one wall, channel material is grown epitaxially to form a channel layer 400.

[0056] The channel material and the sidewall (i.e., substrate 100) of the trench structure 200 are made of different materials. During the formation of the channel layer 400, the channel material reacts with at least part of the wall 300, consuming the wall 300 and gradually reducing its volume. On the periphery of the wall 300, the channel material can grow epitaxially along the crystal phase of the wall 300 material, accelerating the growth rate of the channel material on the periphery of the wall 300 and reducing the difference in growth rate between the channel material on the periphery of the wall 300 and the channel material in the sidewall region of the trench structure 200. This ultimately forms a relatively flat and uniform channel layer 400, preventing leakage caused by the middle of the channel layer 400 being too thin and being penetrated in subsequent processes.

[0057] like Figure 4 As shown, the formed channel layer 400 is relatively uniform and flat, and its thickness in the length direction is also relatively uniform. It is not easy for the channel layer 400 to have a thin local thickness, thus avoiding the phenomenon that the channel layer 400 is easily etched through in subsequent processes and leakage occurs. Furthermore, in this embodiment, the channel layer 400 has a certain thickness to prevent it from being etched through in subsequent steps and causing leakage. The desired morphology, such as the epitaxial growth thickness of the channel layer 400, can be achieved by controlling the parameters during the epitaxial growth process, such as epitaxial growth temperature, epitaxial growth time, epitaxial growth pressure, radio frequency power, and epitaxial growth rate. Depending on different processing equipment, corresponding parameter conditions can be set according to different processing equipment to improve the fabrication accuracy and the structural performance of the semiconductor structure. This embodiment does not specifically limit this.

[0058] Specifically, the channel layer 400 includes at least one of silicon-germanium channel (SIGE) and silicon-phosphorus channel (SIP). That is, the method for fabricating this semiconductor structure can be used to form silicon-germanium channels in long channel regions or silicon-phosphorus channels in long channel regions to form the final NMOS and PMOS transistors, respectively. The silicon-germanium alloy and silicon-phosphorus alloy have different growth rates in different lattice directions. The epitaxial growth raw materials of silicon-germanium alloy and silicon-phosphorus alloy can both grow along the crystal phase of silicon material, thereby accelerating the epitaxial growth rate of silicon-germanium alloy and silicon-phosphorus alloy around the silicon wall 300, improving the surface flatness of silicon-germanium channel and silicon-phosphorus channel, and has a wide range of applications.

[0059] Specifically, during the formation of the channel layer 400, the channel material is epitaxially grown within the trench structure 200 through at least one of physical vapor deposition, atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), and plasma-enhanced chemical vapor deposition (PECVD). For example, a silicon-germanium channel is formed in the trench structure 200, and the channel material includes a silicon source and a germanium source. A silicon-germanium alloy can be formed through chemical vapor deposition. During the epitaxial growth process, the silicon material of the wall 300 can participate in the epitaxial growth reaction as part of the silicon source and be consumed, thus avoiding excessive protrusion of the residual wall 300 and local thinning of the channel layer 400, thereby improving the overall structure's anti-leakage performance.

[0060] Specifically, after the channel layer 400 is finally formed, the ratio between the flatness of the surface of the channel layer 400 and the overall thickness of the channel layer 400 is less than or equal to a preset ratio. The flatness refers to the height difference between the surface of the channel layer and the surface of the fin structure 110 at the sidewall of the trench structure 200. The preset ratio is -10% to +10%. It can be understood that the preset ratio can be any value from -10% to +10%. For example, the preset ratio can be -10%, -10%, -8%, -5%, -3%, 0%, +2%, +6%, +10%, etc. In this way, the flatness of the surface of the channel layer 400 is relatively uniform, and the channel layer 400 as a whole has a certain thickness, which can effectively prevent the channel layer 400 from being partially etched through in subsequent processes and causing leakage. The process difficulty requirements are also relatively low, and the fault tolerance rate is high. For example, in some preferred embodiments, the final surface of the channel layer 400 after filling is flush with the interface of the fin structure 110.

[0061] Specifically, after the trench layer 400 is formed, the ratio between the height of the remaining wall portion 310 in the trench layer 400 and the thickness of the trench layer 400 is less than or equal to a target ratio, which is 1 / 3 to 1 / 2. Understandably, this target ratio can be any value between 1 / 3 and 1 / 2. For example, this target ratio can be 1 / 3, 1 / 2.9, 1 / 2.7, 1 / 2.5, 1 / 2, etc. Thus, the height and volume of the remaining wall portion 310 in the trench layer 400 are relatively small, resembling the size of a burr in subsequent contact holes. It is also less prone to localized etching and leakage during the process, greatly improving the uniformity and flatness of the channel layer 400, thereby improving the structural accuracy and performance of the semiconductor structure and ensuring high reliability. For example, in one specific embodiment, the target ratio is 1 / 2, that is, the height of the remaining wall 310 in the channel layer 400 is less than or equal to 1 / 2 of the thickness of the channel layer 400; in another specific embodiment, the target ratio is 1 / 3, that is, the height of the remaining wall 310 in the channel layer 400 is less than or equal to 1 / 3 of the thickness of the channel layer 400.

[0062] Furthermore, after forming the trench structure 200 and before forming the channel layer 400, a strip process can be performed on the trench structure 200 and the fin structure 110 with at least one wall 300 to cooperate with the channel layer 400 in subsequent processing steps such as contact hole processes to form the desired morphology and desired structure of the final semiconductor structure, for example, to finally obtain a shaped MOS transistor. However, the strip process and the like are not very relevant to the steps of forming the uniform channel layer 400 in the embodiments of this application, and will not be described in detail here.

[0063] Specifically, in some exemplary implementations, such as Figure 5 As shown, forming a groove structure on the fin structure, and having at least one wall in the groove structure, includes:

[0064] A photoresist layer is formed on the fin structure;

[0065] The photoresist layer is patterned to form at least one dam on the fin structure;

[0066] The fin structure on which at least one dam body is formed is etched to form the groove structure, and the wall body is formed on the area corresponding to the dam body.

[0067] During the formation of the trench structure 200, the patterning process includes patterning exposure of the photoresist layer 500 and etching after exposure to form a dam 510 in the desired area or desired location of the fin structure 110. The material of the dam 510 is also photoresist, which may include at least one of cyclic rubber-type photoresist and cinnamic acid ester-type photoresist. In one specific embodiment, the cyclic rubber-type photoresist includes SU-8 photoresist, which has high viscosity and is beneficial to increasing the depth of the dam 510, so as to control the key dimensions of the wall 300 formed after subsequent etching steps.

[0068] Etching can be performed using methods such as dry etching or wet etching. Dry etching processes can include reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method or more than one etching method can also be used. In some exemplary embodiments, the trench structure 200 can be obtained through all-in-one etching (AIO), which refers to a process that completes the via etching, photoresist removal, and trench etching in the same step. This reduces pattern defects generated during the formation of the trench structure 200 and significantly accelerates the fabrication efficiency of the semiconductor structure.

[0069] The wall 300 is formed simultaneously in the area corresponding to the dam 510 during the etching process of the fin structure 110 to form the trench structure 200. That is, the positions of the dam 510 and the wall 300 correspond one-to-one. This patterning and etching process ensures accurate positioning of the dam 510 and the wall 300, resulting in high forming precision. This improves the effectiveness and reliability of enhancing the flatness of the channel layer 400, and also improves the structural precision of the channel layer 400 and the semiconductor structure. In other words, this embodiment adds a patterned dam 510 to the long channel area to... During the subsequent etching process, the area outside the dam 510 is etched, while the area below the dam 510 leaves a wall 300 within the trench structure 200. This allows the channel material to grow along the crystal phase of the wall 300 material in subsequent steps, accelerating the growth rate of the channel material around the wall 300 and preventing the formation of depressions around the wall 300. This results in a uniform channel layer 400 within the trench structure 200, effectively improving the surface flatness of the channel layer 400. Consequently, it prevents the channel layer 400 from being etched through in subsequent processes, thus avoiding leakage and greatly improving the overall structural precision and reliability of the semiconductor structure.

[0070] Specifically, in some exemplary embodiments, before forming a groove structure on the fin structure and forming at least one wall in the groove structure, the method further includes:

[0071] At least two gates are formed on the fin structure; the channel layer is located between two adjacent gates.

[0072] In some embodiments, the gate 600 can be formed before the trench structure 200 is formed by etching the fin structure 110. When initially determining the position of the trench structure 200 to be etched and whether a wall 300 needs to be formed within the trench structure 200 to be etched, the distance between two adjacent gates 600 can be used. The area corresponding to the trench structure 200 to be etched is located between two adjacent gates 600. The length of the trench structure 200 is less than or equal to the distance between two adjacent gates 600. After determining the distance between two adjacent upper gates, the position of the trench structure 200 and the channel layer 400 can be initially located, and the length of the trench structure 200 to be etched can be roughly obtained. This allows for a determination of whether to perform the above semiconductor structure fabrication method in this area to form a more uniform and flat channel layer 400, simplifying the processing flow and saving processing time.

[0073] Specifically, in some exemplary embodiments, after forming the gate 600, an isolation material is deposited on the fin structure 110 on which the gate 600 is formed to form an isolation structure on the gate 600. This isolation structure isolates the gate 600 from the external environment, preventing the gate 600 from being corroded in subsequent etching processes. Moreover, the isolation structure can be removed in subsequent processes, thereby greatly improving the overall structural accuracy of the final semiconductor structure. In some exemplary embodiments, the isolation material may include at least one of silicon nitride (SiN), silicon nitride, and silicon carbide, preferably silicon nitride, which has good isolation effect, good stability, and is not easily etched through.

[0074] The following describes a semiconductor structure and its fabrication method in a specific embodiment.

[0075] Taking the N-type metal-oxide-semiconductor field-effect transistor silicon reverse structure (NMOS Silicon Reverse, NSR) as an example, a silicon-germanium channel (SiGE) is formed on the open region of the NMOS region; such as Figure 6 As shown, on a substrate having MOS transistor regions 100, the substrate includes multiple MOS transistor regions 100, each including at least one NMOS transistor region and at least one PMOS transistor region. Each MOS transistor region 100 includes a fin structure 110, and the fin structures 110 of adjacent MOS transistor regions 100 are isolated from each other by a shallow trench isolation structure 700 (STI). In this embodiment, on the fin structure 110 of one of the NMOS transistor regions, this region is a long channel region of the NMOS transistor region. The channel (LC) has a large spacing between two adjacent gates 600, meaning the length of the trench structure 200 to be etched is relatively long, for example, greater than 80 nm. Since the silicon-germanium alloy grows rapidly along the silicon crystal phase, the epitaxial growth rate of the silicon-germanium alloy at the sidewalls of the trench structure 200 is greater than its epitaxial growth rate in the central region of the trench structure 200. Ultimately, the silicon-germanium channel epitaxially grown inside and outside the trench structure 200 easily forms a V-shaped depression, which is easily locally etched through in subsequent processes, causing leakage problems. To form such... Figure 6 The relatively flat and uniform silicon-germanium channel shown in this embodiment is as follows: Figure 7 The semiconductor structure is prepared by the method shown, and the semiconductor structure is specifically prepared through the following steps:

[0076] A substrate is provided in which a MOS transistor region 100 is formed; the MOS transistor region 100 is an NMOS transistor region, and the NMOS transistor region is a long channel region, the NMOS transistor region including a fin structure 110;

[0077] Multiple gates 600 are formed on the fin structure 110; wherein two gates 600 are on the long channel region corresponding to the NMOS transistor region.

[0078] A photoresist layer 500 is formed on the fin structure 110;

[0079] The photoresist layer 500 is patterned to form a dam 510 on the fin structure 110; the dam 510 is located between two adjacent gates 600 in the long channel region;

[0080] The fin structure 110 with the dam 510 formed on its surface is etched to form a trench structure 200 on the fin structure 110. At the same time, a silicon wall 300 is formed on the area corresponding to the dam 510. The silicon wall 300 divides the trench structure 200 into two trench areas in the length direction, and the height of the wall 300 is flush with the height of the desired silicon-germanium trench.

[0081] Silicon-germanium raw materials are epitaxially grown in a trench structure 200 in which silicon walls 300 are formed to form a silicon-germanium channel; the silicon-germanium channel is located between two adjacent gates 600; the height of the remaining portion of the silicon walls 310 in the silicon-germanium channel is 1 / 10 of the thickness of the silicon-germanium channel.

[0082] Based on the substrate with the silicon-germanium channel, the source / drain is formed in the NMOS region.

[0083] Furthermore, NMOS / PMOS is only used to distinguish between N-type and P-type transistors, and they are collectively referred to as MOS transistors. Forming a Si wall in the NMOS transistor region is equivalent to adding a photoresist strip in the NMOS transistor region. Conversely, in other embodiments, a Si wall can also be formed in the PMOS transistor region.

[0084] This application also provides a semiconductor structure prepared by the above-described semiconductor structure preparation method. The semiconductor structure has a relatively uniform channel layer 400 with a relatively flat surface, making it less likely to be penetrated and cause leakage. The structural strength and structural stability are greatly improved.

[0085] Specifically, the channel layer 400 of the semiconductor structure has a residual partial wall 310, the ratio between the height of the residual partial wall 310 and the thickness of the channel layer 400 is less than or equal to a target ratio of 1 / 3 to 1 / 2.

[0086] This application also provides a semiconductor device, including any of the semiconductor structures described in this application.

[0087] This application also provides an electronic device, which includes any of the semiconductor structures described in this application, or any of the semiconductor devices described in this application. The electronic device can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigator, camera, camcorder, voice recorder, MP3, MP4, PSP, etc., or it can be an intermediate product with the semiconductor device, such as a device motherboard with the semiconductor device. The use of the semiconductor device in this electronic device improves the working performance of the electronic device accordingly.

[0088] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided in which a MOS transistor region is formed; the MOS transistor region includes a fin structure. A groove structure is formed on the fin structure, and at least one wall is formed in the groove structure; the at least one wall divides the groove structure into at least two groove regions; A channel material is epitaxially grown in the trench structure having at least one wall to form a channel layer; the channel material is different from the material of the sidewall of the trench structure.

2. The preparation method according to claim 1, characterized in that, The length of the trench structure is greater than or equal to a preset length, which is 20nm to 200nm.

3. The preparation method according to claim 1, characterized in that, The at least one wall divides the trench structure into equal parts along its length.

4. The preparation method according to any one of claims 1-3, characterized in that, The formation of a groove structure on the fin structure, wherein at least one wall is formed in the groove structure, includes: A photoresist layer is formed on the fin structure; The photoresist layer is patterned to form at least one dam on the fin structure; The fin structure on which at least one dam body is formed is etched to form the groove structure, and the wall body is formed on the area corresponding to the dam body.

5. The preparation method according to any one of claims 1-3, characterized in that, The critical dimensions of the wall are determined based on the growth rate of the channel layer, and the critical dimensions of the wall are positively correlated with the growth rate of the channel layer.

6. The preparation method according to any one of claims 1-3, characterized in that, The height of the wall is less than or equal to the thickness of the trench layer.

7. The preparation method according to any one of claims 1-3, characterized in that, After the trench layer is formed, the ratio between the height of the remaining wall in the trench layer and the thickness of the trench layer is less than or equal to the target ratio, which is 1 / 3 to 1 / 2.

8. The preparation method according to any one of claims 1-3, characterized in that, Before forming a groove structure on the fin structure, and before forming at least one wall in the groove structure, the method further includes: At least two gates are formed on the fin structure; the channel layer is located between two adjacent gates.

9. A semiconductor structure, characterized in that, It is prepared by the preparation method according to any one of claims 1-8.

10. The semiconductor structure according to claim 9, characterized in that, The trench layer includes a remaining portion of the wall, and the ratio between the height of the remaining portion of the wall and the thickness of the trench layer is less than or equal to a target ratio, which is 1 / 3 to 1 / 2.

11. An electronic device, characterized in that, Including the semiconductor structure as described in any one of claims 9-10.

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