Vertical diffusion metal oxide semiconductor transistor structure and manufacturing method thereof
By employing a composite structure of low-doped and high-doped epitaxial layers in vertically diffused metal-oxide-semiconductor transistors, the problems of long manufacturing time and high cost in traditional manufacturing processes are solved, the transistor's breakdown voltage is improved and the on-resistance is reduced, and the voltage operating range of the device is improved.
Patent Information
- Application Number
- CN202411068494.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-05-10
- Filing Date
- 2024-08-06
- Publication Date
- 2025-11-14
AI Technical Summary
In the traditional vertically diffused metal-oxide-semiconductor field-effect transistor manufacturing process, the ion implantation and diffusion processes are time-consuming and costly, resulting in a decrease in the quality of the epitaxial layer surface film, an increase in leakage current, and a limitation on the device's breakdown voltage and on-resistance.
A composite structure of low-doped and high-doped epitaxial layers is adopted. Ion implantation and diffusion are performed on the high-doped epitaxial layer to replace the traditional surface treatment of the low-doped epitaxial layer, forming a high-doped epitaxial film to improve the quality of the gate oxide layer. The high-doped epitaxial layer restricts the breakdown of the depletion region between the main regions, thereby increasing the breakdown voltage and reducing the on-resistance.
It reduces process time and cost, improves the thin film quality of the gate oxide layer, enhances the device's breakdown voltage and reduces on-resistance, and improves the device's voltage operating range.
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Figure CN120957463A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a transistor structure and a method for manufacturing the same, and more particularly to a vertically diffused metal-oxide-semiconductor transistor structure and a method for manufacturing the same. Background Technology
[0002] Figure 1 This figure shows a cross-sectional schematic diagram of a typical vertically diffused metal oxide semiconductor (VDMOS) field-effect transistor (FET) cell structure. As shown, the VDMOS FET cell structure has an N-type heavily doped substrate 10 electrically connected to a drain region 11. An N-type lightly doped epitaxial layer 12 is formed on the substrate 10, and a field oxide layer 13 is formed on the surface of the epitaxial layer 12 to space the VDMOS FET cell structures from each other. Next, two P-type body regions 14 are formed on the surface region of the N-type lightly doped epitaxial layer 12. Each body region 14 has two source doped regions 15 and a P-type heavily doped region 16, wherein the P-type heavily doped region 16 is sandwiched between the two source doped regions 15 to reduce contact resistance and prevent the conduction of parasitic bipolar transistors. A gate structure 17 is formed above the body region 14 and adjacent to the source doped regions 15. This gate structure 17 is used to control whether the channel formed within the main body region 14 is open or closed. Figure 1 On the opposite sides of the source doped region 15 and the gate structure 17 of the VDMOS FET cell structure shown, the conduction current flows in a roughly vertical direction.
[0003] The breakdown voltage of conventional vertically diffused metal-oxide-semiconductor (VDMOS) field-effect transistors (FETs) is primarily determined by the thickness and N-type doping concentration of the lightly doped N-type epitaxial layer 12. To increase the breakdown voltage and reduce the on-resistance, conventional VDMOS FET manufacturing processes involve, after forming the aforementioned field oxide layer 13, using the field oxide layer 13 as a mask for blanket ion implantation and furnace-heated ion diffusion processes to improve on-resistance and breakdown voltage. However, these ion implantation and diffusion processes are time-consuming, increasing both process time and cost. Furthermore, ion implantation degrades the film quality on the surface of the epitaxial layer 12, leading to a decrease in the quality of the subsequently formed gate oxide film and consequently, higher leakage current. To overcome these problems, the industry urgently needs an innovative vertically diffused metal-oxide-semiconductor (MOSFET) structure and its manufacturing method to effectively improve the on-resistance and breakdown voltage of the device. Summary of the Invention
[0004] The main objective of this invention is to provide an innovative vertically diffused metal-oxide-semiconductor field-effect transistor structure and its manufacturing method, which can not only reduce process time and cost, but also increase the voltage operating range of the device and reduce the on-resistance of the device by increasing the gate breakdown voltage.
[0005] To achieve the above objectives, the present invention provides a vertically diffused metal-oxide-semiconductor (MOSFET) transistor structure, comprising a substrate, an epitaxial composite layer of a first conductivity type, a gate structure, and two main regions of a second conductivity type. The main regions are disposed within the epitaxial composite layer, and each main region is spaced apart by a predetermined distance. The epitaxial composite layer comprises a lightly doped epitaxial layer and a heavily doped epitaxial layer, with the lightly doped epitaxial layer disposed above the substrate and the heavily doped epitaxial layer disposed above the lightly doped epitaxial layer, such that the gate structure partially covers the heavily doped epitaxial layer and each main region.
[0006] In one embodiment of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the thickness of the lightly doped epitaxial layer is 10–200 micrometers (μm), and the doping concentration of the lightly doped epitaxial layer is 10. 13 ~10 16 cm -3 .
[0007] In one embodiment of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the thickness of the highly doped epitaxial layer is 1 to 10 micrometers (μm), and the doping concentration of the highly doped epitaxial layer is 10. 16 ~10 18 cm -3 .
[0008] In one embodiment of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the epitaxial composite layer is doped with phosphorus, arsenic or antimony.
[0009] In one embodiment of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, each main region includes two first conductivity type source regions and a second conductivity type highly doped region, with the second conductivity type highly doped region sandwiched between the two first conductivity type source regions.
[0010] To achieve the above objectives, the present invention provides a method for manufacturing a vertically diffused metal-oxide-semiconductor (MOSFET) transistor structure, comprising the following steps: providing a substrate, providing an epitaxial composite layer of a first conductivity type, providing a gate structure, and providing two body regions of a second conductivity type disposed within the epitaxial composite layer, wherein each body region is separated by a predetermined distance. The epitaxial composite layer comprises a lightly doped epitaxial layer and a heavily doped epitaxial layer, the lightly doped epitaxial layer being disposed above the substrate, and the heavily doped epitaxial layer being disposed above the lightly doped epitaxial layer, such that the gate structure partially covers the heavily doped epitaxial layer and each body region.
[0011] In one embodiment of the method for manufacturing a vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the epitaxial composite layer includes providing a thickness of 10 to 200 micrometers (μm) and a doping concentration of 10. 13 ~10 16 cm -3 The low-doped epitaxial layer.
[0012] In one embodiment of the method for manufacturing a vertically diffused metal-oxide-semiconductor transistor structure of the present invention, the epitaxial composite layer includes providing a layer with a thickness of 1 to 10 micrometers (μm) and a doping concentration of 10. 16 ~10 18 cm -3 Highly doped epitaxial layer.
[0013] In one embodiment of the method for manufacturing a vertically diffused metal-oxide-semiconductor transistor structure of the present invention, an epitaxial composite layer is provided comprising phosphorus, arsenic, or antimony doping.
[0014] In one embodiment of the manufacturing method of the vertically diffused metal-oxide-semiconductor transistor structure of the present invention, each main region includes two first conductivity source regions and a second conductivity highly doped region, such that the second conductivity highly doped region is sandwiched between the two first conductivity source regions.
[0015] Other objects of the present invention, as well as the technical means and embodiments of the present invention, will be understood by those skilled in the art upon referring to the accompanying drawings and the embodiments described below. Attached Figure Description
[0016] Figure 1 This is a cross-sectional schematic diagram of a unit structure in a traditional vertically diffused metal-oxide-semiconductor field-effect transistor.
[0017] Figures 2 to 4 This is a cross-sectional schematic diagram of fabricating a vertically diffused metal-oxide-semiconductor field-effect transistor according to an embodiment of the present invention; and
[0018] Figure 5 This is a schematic diagram of the process steps for manufacturing a vertically diffused metal-oxide-semiconductor field-effect transistor according to one embodiment of the present invention.
[0019] Explanation of reference numerals in the attached figures
[0020] 10 base
[0021] 11 Drain region
[0022] 12 Epitaxial Layers
[0023] 13 Field Oxide Layer
[0024] 14 Main Area
[0025] 15 Source Doped Region
[0026] 16 P-type highly doped regions
[0027] 17 Gate Structure
[0028] 100 base
[0029] 110 Epitaxial Composite Layer
[0030] 112 Low-doped epitaxial layer
[0031] 114 Highly Doped Epitaxial Layer
[0032] 116 Field Oxide Layer
[0033] 118 gate structure
[0034] 120 Main Area
[0035] 122 First conductivity type source region
[0036] 124 Second conductivity type highly doped region. Detailed Implementation
[0037] The following embodiments will explain the content of this invention. These embodiments are not intended to limit the implementation of this invention to any specific environment, application, or special method described in the embodiments. Therefore, the descriptions of the embodiments are merely illustrative of the invention and not intended to limit it. It should be noted that in the following embodiments and drawings, elements not directly related to this invention have been omitted and are not shown, and the dimensional relationships between the elements in the drawings are for ease of understanding only and are not intended to limit the actual scale.
[0038] This invention discloses a semiconductor structure and its manufacturing method, particularly a vertically diffused metal-oxide-semiconductor transistor and its manufacturing method. Please refer to... Figure 2 An epitaxial composite layer 110 of a first conductivity type is formed on a substrate 100. The substrate 100 may be an N-type heavily doped semiconductor substrate. The material of the substrate 100 may be, for example, but not limited to, silicon, silicon carbide, or gallium nitride. The epitaxial composite layer 110 may be an N-type epitaxial composite layer, and may be formed by metal-organic chemical vapor deposition epitaxy.
[0039] Specifically, unlike traditional techniques, the epitaxial composite layer 110 in the vertically diffused metal-oxide-semiconductor transistor structure of the present invention has an N-type low-doped epitaxial layer 112 and an N-type high-doped epitaxial layer 114. The low-doped epitaxial layer 112 is formed above the substrate 100, and then an epitaxial process is performed above the low-doped epitaxial layer 112 to form the high-doped epitaxial layer 114. The thickness of the low-doped epitaxial layer 112 is 10–200 micrometers (μm), and the doping concentration of the low-doped epitaxial layer 112 is 10. 13 ~10 16 cm -3 Furthermore, the thickness of the highly doped epitaxial layer 114 is 1–10 micrometers (μm), and the doping concentration of the highly doped epitaxial layer 114 is 10. 16 ~10 18 cm -3 The low-doped epitaxial layer 112 and the high-doped epitaxial layer 114 can be doped with phosphorus, arsenic or antimony.
[0040] Next, a bulk isolation structure is formed above the highly doped epitaxial layer 114, for example, a field oxide layer 116 is formed by oxidation, which serves as a spacer between unit structures in the semiconductor device, such as... Figure 3 As shown. After the internal unit structures of the device are separated, as in conventional technology, a gate structure 118 is sequentially formed on the epitaxial composite layer 110. Using the gate structure 118 as a mask, ion implantation and diffusion processes are performed on the epitaxial composite layer 110 to form two second conductivity type main regions 120 within the epitaxial composite layer 110, wherein each main region 120 is separated by a predetermined distance. The gate structure 118 includes a gate oxide layer and a polysilicon layer, wherein the gate oxide layer is formed on the surface of the epitaxial composite layer, and the polysilicon layer is formed on the gate oxide layer.
[0041] It should be noted that, unlike conventional techniques, the VDMOS transistor device disclosed in this invention uses a highly doped epitaxial film instead of the traditional ion implantation and diffusion process performed on the surface of a low-doped epitaxial layer. Therefore, the surface of the epitaxial composite layer in the VDMOS transistor device disclosed in this invention has better film quality than the epitaxial film bombarded by ions in conventional devices. Consequently, when forming the gate oxide layer in the gate structure 118 in the process of this invention, the quality of this gate oxide layer film is also better than that of the gate oxide layer in conventional devices, which can effectively reduce gate leakage current.
[0042] Furthermore, the main region 120 of each second conductivity type can be a P-type well region, and its doping concentration can be, for example, 10. 14 ~10 16 cm -3 However, this is not the only applicable provision. For further information, please refer to [link / reference needed]. Figure 4The VDMOS transistor device of the present invention further includes two first conductivity source regions 122 and a second conductivity highly doped region 124 in each main region 120, wherein the second conductivity highly doped region 124 is sandwiched between the two first conductivity source regions 122. Specifically, the first conductivity source region 122 is an N-type highly doped region with a doping concentration of approximately 10. 16 ~10 18 cm -3 On the other hand, the second conductivity type highly doped region 124 is a p-type highly doped region with a doping concentration of approximately 10⁻⁶. 16 ~10 18 cm -3 .
[0043] Please see Figure 5 This invention illustrates a method for manufacturing a vertically diffused metal-oxide-semiconductor transistor structure. In step S01, a substrate is provided. Next, in step S02, an epitaxial composite layer of a first conductivity type is provided on the substrate. Then, in step S03, a gate structure is provided on the epitaxial composite layer. Finally, in step S04, two main regions of a second conductivity type are provided within the epitaxial composite layer, with a predetermined distance between each main region. The epitaxial composite layer formed in step S02 comprises a lightly doped epitaxial layer and a heavily doped epitaxial layer. The structural relationship between the lightly and heavily doped epitaxial layers and the properties of each epitaxial layer are as described above and will not be repeated here. Furthermore, the source doped region and the P-type heavily doped region within the main region should also be referred to the foregoing description.
[0044] As described above, the vertically diffused metal-oxide-semiconductor transistor structure disclosed in this invention replaces the traditional ion implantation and diffusion process performed on the surface of a low-doped epitaxial layer with a highly doped epitaxial thin film, thus saving the time and cost required by the traditional ion implantation and diffusion process. Furthermore, the highly doped epitaxial layer 114 between the two main regions 120 in the transistor will prevent breakdown due to excessive depletion region between the two main regions 120 when the VDMOS transistor device is on, thus avoiding device failure and effectively improving the device's breakdown voltage. Moreover, the highly doped epitaxial layer also helps to reduce the on-resistance.
[0045] The above embodiments are merely illustrative of the implementation methods of the present invention and to explain the technical features of the present invention, and are not intended to limit the scope of protection of the present invention. Any changes or equivalent arrangements that can be easily made by those skilled in the art are within the scope of the present invention, and the scope of protection of the present invention should be determined by the claims.
Claims
1. A vertically diffused gold-oxide-semiconductor transistor structure, comprising: One base; An epitaxial composite layer of the first conductivity type; A gate structure; and Two main regions of the second conductivity type are disposed within the epitaxial composite layer, and each main region is separated by a predetermined distance. in, The epitaxial composite layer includes a low-doped epitaxial layer and a high-doped epitaxial layer. The low-doped epitaxial layer is disposed above the substrate, and the high-doped epitaxial layer is disposed above the low-doped epitaxial layer, such that the gate structure partially covers the high-doped epitaxial layer and each of the main regions.
2. The vertically diffused metal-oxide-semiconductor transistor structure as described in claim 1, wherein the thickness of the low-doped epitaxial layer is 10–200 micrometers, and the doping concentration of the low-doped epitaxial layer is 10. 13 ~10 16 cm -3 .
3. The vertically diffused metal-oxide-semiconductor transistor structure as described in claim 1, wherein the thickness of the highly doped epitaxial layer is 1 to 10 micrometers, and the doping concentration of the highly doped epitaxial layer is 10. 16 ~10 18 cm -3 .
4. The vertically diffused metal-oxide-semiconductor transistor structure as claimed in claim 1, wherein the epitaxial composite layer is doped with phosphorus, arsenic or antimony.
5. The vertically diffused metal-oxide-semiconductor transistor structure as claimed in claim 1, wherein each of the main regions comprises two first conductivity type source regions and a second conductivity type highly doped region, the second conductivity type highly doped region being sandwiched between the two first conductivity type source regions.
6. A method for manufacturing a vertically diffused gold-oxide-semiconductor transistor structure, comprising: Provide a base; Provide an epitaxial composite layer of a first conductivity type; Provide a gate structure; and Two main bodies of a second conductivity type are provided and disposed within the epitaxial composite layer, with each main body region separated by a predetermined distance. in, The epitaxial composite layer includes a low-doped epitaxial layer and a high-doped epitaxial layer. The low-doped epitaxial layer is disposed above the substrate, and the high-doped epitaxial layer is disposed above the low-doped epitaxial layer, such that the gate structure partially covers the high-doped epitaxial layer and each of the main regions.
7. The manufacturing method of claim 6, wherein providing the epitaxial composite layer comprises providing a layer with a thickness of 10-200 micrometers and a doping concentration of 10. 13 ~10 16 cm -3 The low-doped epitaxial layer.
8. The manufacturing method of claim 6, wherein providing the epitaxial composite layer comprises providing a layer with a thickness of 1 to 10 micrometers and a doping concentration of 10. 16 ~10 18 cm -3 The highly doped epitaxial layer.
9. The manufacturing method of claim 6, wherein the provided epitaxial composite layer comprises doped phosphorus, arsenic or antimony.
10. The manufacturing method of claim 6, wherein each of the main body regions comprises providing two first conductivity source regions and a second conductivity highly doped region, such that the second conductivity highly doped region is sandwiched between the two first conductivity source regions.