High maintenance voltage bidirectional high voltage ESD structure

Abstract

The application discloses a kind of high maintenance voltage bidirectional high-voltage ESD structures, including first N type deep well doped type well region injected in substrate, first N type well doped type well region and two first P type high-voltage doped type well region, two first P type well doped type well region corresponding injected in first P type high-voltage doped type well region;The top of each first P type well doped type well region is formed with first N type heavy doped active region and first P type heavy doped active region isolated from each other, and first N type heavy doped active region and first P type heavy doped active region are led out by metal line;It also includes N type buried layer, N type buried layer is injected in substrate, and is located below first N type deep well doped type well region, two first P type high-voltage doped type well region, and the bottom of first N type deep well doped type well region and the top of N type buried layer contact.The application changes the current path of parasitic NPN by cutting off the region, at least improves the maintenance voltage, effectively avoids latch-up effect.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a high-maintenance-voltage bidirectional high-voltage ESD structure. BACKGROUND

[0002] Electrostatic discharge (ESD) is a common cause of failure of high-voltage integrated circuits (such as power management and automotive electronics). The SCR structure is an important choice for on-chip ESD protection due to its high current discharge efficiency. There are three ways to improve the SCR holding voltage: one is to reduce the emitter injection efficiency to weaken the positive feedback of the parasitic transistor; two is to introduce a device shunt path in the SCR to weaken the positive feedback of the parasitic NPN and PNP transistors; three is to use ESD device stacking technology to stack the holding voltage by connecting multiple devices in series. The holding voltage of the traditional bidirectional SCR is limited by the current gain of the vertical NPN transistor. The N-type buried layer (NBL) doping concentration directly affects the conductivity and current gain of the vertical NPN, and the existing single high-maintenance-voltage scheme is mostly only applicable to the medium-low voltage window, making it difficult to meet the needs of high-voltage scenarios.

[0003] The traditional SCR has a deep hysteresis characteristic, and the trigger voltage is much higher than the breakdown voltage of the process gate oxide layer. The low holding voltage is easy to cause the latch-up effect. Reducing the emitter injection efficiency will sacrifice the device robustness and may increase the process level and layout area, and increase the manufacturing cost. Introducing a shunt path cannot meet the ESD design window requirements of high-voltage integrated circuits. The stacking technology has a slow opening speed and is difficult to respond to fast ESD events, and will increase the layout area. The current gain of the vertical NPN limits the traditional bidirectional SCR, and the holding voltage has limited space for improvement, which cannot adapt to the protection needs of high-voltage integrated circuits.

[0004] Therefore, a new technical solution is needed. SUMMARY

[0005] Therefore, the embodiments of the present application provide a high-maintenance-voltage bidirectional high-voltage ESD structure to at least solve the problem of low SCR holding voltage.

[0006] The embodiments of the present application provide the following technical solutions:

[0007] The embodiment of the present application provides a high-maintenance-voltage bidirectional high-voltage ESD structure, which comprises a first N-type deep well doped type well region implanted in a substrate, a first N-type well doped type well region located above the first N-type deep well doped type well region, and two first P-type high-voltage doped type well regions and two first P-type well doped type well regions implanted in the first P-type high-voltage doped type well regions on both sides of the first N-type well doped type well region; the top end of each first P-type well doped type well region is formed with a first N-type heavily doped active region and a first P-type heavily doped active region which are isolated from each other, and the first N-type heavily doped active region and the first P-type heavily doped active region are led out by metal lines;

[0008] The high-maintenance-voltage bidirectional high-voltage ESD structure further comprises an N-type buried layer implanted in the substrate and located below the first N-type deep well doped type well region and the two first P-type high-voltage doped type well regions, and the bottom end of the first N-type deep well doped type well region and the top end of the N-type buried layer are in contact;

[0009] The middle part of the N-type buried layer is formed with a cut-off region below the first N-type deep well doped type well region, which is used for turning the current path in the high-maintenance-voltage bidirectional high-voltage ESD structure to a lateral parasitic NPN and inhibiting the conduction of a vertical parasitic NPN.

[0010] Preferably, the middle part of the N-type buried layer forms the cut-off region by means of well cutting.

[0011] Preferably, the lateral sides of the cut-off region are located inside the lateral sides of the first N-type deep well doped type well region and in contact with the bottom end of the first N-type deep well doped type well region.

[0012] Preferably, the first N-type heavily doped active region and the first P-type heavily doped active region are isolated by a first STI region which is implanted downward into the corresponding first P-type well doped type well region.

[0013] Preferably, the high-maintenance-voltage bidirectional high-voltage ESD structure further comprises a second STI region located above the first N-type well doped type well region and between the first N-type heavily doped active regions or the first P-type heavily doped active regions of the two first P-type well doped type well regions.

[0014] Preferably, the high-maintenance-voltage bidirectional high-voltage ESD structure further comprises:

[0015] Two second N-type deep well doped type well regions are implanted into the substrate and located on the side of the corresponding first P-type high-voltage doped type well region away from the first N-type deep well doped type well region. The two second N-type deep well doped type well regions are located on both sides of the N-type buried layer and are in contact with both sides of the N-type buried layer.

[0016] Two second N-type well-doped well regions are implanted into the substrate and located above the corresponding second N-type deep well-doped well regions.

[0017] Preferably, it further includes a third STI region, which is located above the corresponding second N-type well-doped type well region, and one side of which extends above the corresponding first P-type well-doped type well region.

[0018] Preferably, the metal lines leading out from the first N-type heavily doped active region and the first P-type heavily doped active region above each of the first P-type well doped type well regions are interconnected and then led out.

[0019] Preferably, the first N-type heavily doped active region, the first P-type well doped well region, the first P-type high voltage doped well region, the P-type epitaxial layer, the first N-type deep well doped well region, and the first N-type well doped well region located on the same side as the first N-type deep well doped well region form a transistor.

[0020] Preferably, the first N-type deep well-doped type well region, the first N-type well-doped type well region, and the two first P-type heavily doped active regions, the two first P-type well-doped type well regions, the two first P-type high voltage doped type well regions, the two P-type epitaxial layers, and the two first N-type heavily doped active regions located on both sides of the first N-type deep well-doped type well region and the first N-type well-doped type well region form a bidirectional PNP transistor.

[0021] Compared with the prior art, the beneficial effects that the at least one technical solution adopted in the embodiments of the present invention can achieve include at least:

[0022] The present invention discloses a high sustaining voltage bidirectional high voltage ESD structure. By performing a well cut-off treatment through N-type buried layer doping implantation, the original longitudinal current path is disrupted, and the current cannot flow through the low-resistance vertical path. This forces the current to turn to the lateral NPN path. Since the lateral NPN path is longer and has higher resistance, the sustaining voltage is improved. This also removes the limitation of widening the distance between the high voltage port Hi and the low voltage port Lo, which would otherwise restrict the sustaining voltage from being increased due to the low resistance path from the longitudinal path. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a cross-sectional view of a high sustaining voltage bidirectional high voltage ESD structure according to an embodiment of the present invention;

[0025] Figure 2 This is a plan view of a high sustaining voltage bidirectional high voltage ESD structure according to an embodiment of the present invention;

[0026] Figure 3 This is an equivalent circuit diagram of a high sustaining voltage bidirectional high voltage ESD structure according to an embodiment of the present invention;

[0027] Figure 4 This is an IV diagram of a high sustaining voltage bidirectional high voltage ESD structure according to an embodiment of the present invention. Detailed Implementation

[0028] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0029] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0031] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0033] Electrostatic discharge (ESD) is one of the most common causes of integrated circuit product failure. With the rapid development of power semiconductor technology, high-voltage integrated circuits have become an important part of the integrated circuit industry, widely used in power management, automotive electronics, and other fields. The harsh operating environment of high-voltage integrated circuits places higher design requirements on ESD protection devices. They need to withstand high voltage and high current, and also have a high holding voltage, higher than the normal operating voltage of the circuit, to fundamentally eliminate the risk of latch-up.

[0034] Among the many ESD protection devices available, the SCR structure is widely used in on-chip ESD protection due to its extremely high current discharge efficiency. However, the traditional SCR structure has deep hysteresis, and its trigger voltage is generally much higher than the breakdown voltage of the process gate oxide layer. It also has a very low sustaining voltage, which easily leads to latch-up effects. This greatly limits its application in the field of high-voltage ICs. At present, the most common way to improve the sustaining voltage is to reduce the emitter injection efficiency and weaken the positive feedback effect of parasitic transistors. However, these methods sacrifice the robustness of the device to obtain a high sustaining voltage, and often increase the process layers and sacrifice the layout area, resulting in increased manufacturing costs. A more effective way to improve the sustaining voltage is to introduce a device shunt path in the SCR structure to weaken the positive feedback effect of parasitic NPN and PNP transistors, thereby achieving the purpose of improving the sustaining voltage. In addition, the high sustaining voltage solutions proposed for individual devices are often only effective for medium and low voltage windows, and are far from meeting the ESD design window requirements in high-voltage integrated circuits.

[0035] Another relatively effective method is ESD device stacking technology. A stacked structure consists of multiple ESD protection devices connected in series, and its sustaining voltage is the sum of the sustaining voltages of all the ESD protection devices. This can effectively solve the problem of insufficient sustaining voltage in a single SCR structure. However, stacking technology also has drawbacks. As the number of stacked devices increases, the trigger voltage also increases, potentially exceeding the upper limit of the protection device's window. Furthermore, stacking multiple ESD devices reduces the turn-on speed, making it difficult to respond quickly and effectively to fast ESD events. Additionally, the increased number of stacked devices also leads to an increase in area. In traditional bidirectional SCR structures, the current gain of the vertical NPN transistor is one of the main factors limiting the bidirectional SCR Vh. The doping concentration of the N-type buried layer directly affects the conductivity and current gain of the vertical NPN.

[0036] Based on this, the embodiments of this specification propose a processing solution: such as Figure 1 As shown, the present invention provides a high sustaining voltage bidirectional high voltage ESD structure. By cutting off the N-type buried layer 100 in the traditional bidirectional SCR structure, the vertical NPN conduction is suppressed, thereby turning the current path to the lateral NPN and improving the sustaining voltage.

[0037] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0038] The present invention provides a high sustaining voltage bidirectional high voltage ESD structure that enables the production of high sustaining voltage SCR devices for ESD protection of high voltage integrated circuits under conventional process dimensions (such as based on 180nm MBCD process), thereby meeting the design requirements of high sustaining voltage in ESD protection and having extremely high current discharge efficiency.

[0039] like Figures 1-4 As shown, an embodiment of the present invention provides a high sustaining voltage bidirectional high voltage ESD structure, including a first N-type deep well-doped well region 301 implanted in a substrate, a first N-type well-doped well region 302 located above the first N-type deep well-doped well region 301, two first P-type high voltage-doped well regions (106, 206) located on both sides of the first N-type well-doped well region 302, and two corresponding first P-type well-doped well regions (109, 209) implanted in the first P-type high voltage-doped well regions (106, 206); each first P-type well-doped well region (109, 209) has a first N-type heavily doped active region (108, 208) and a first P-type heavily doped active region (107, 207) formed at its top, and both the first N-type heavily doped active region (108, 208) and the first P-type heavily doped active region (107, 207) are led out by metal lines.

[0040] The high sustaining voltage bidirectional high voltage ESD structure further includes an N-type buried layer 100, which is injected into the substrate and located below the first N-type deep well doped type well region 301 and the two first P-type high voltage doped type well regions (106, 206). The bottom end of the first N-type deep well doped type well region 301 is in contact with the top end of the N-type buried layer 100. A cut-off region 401 is formed in the middle of the N-type buried layer 100. The cut-off region 401 is located below the first N-type deep well doped type well region 301 and is used to redirect the current path in the high sustaining voltage bidirectional high voltage ESD structure to the lateral parasitic NPN and suppress the conduction of the vertical parasitic NPN.

[0041] Among them, two P-type epitaxial layers (103, 203) are formed on both sides of the first N-type deep well-doped well region 301.

[0042] Among them, the two first P-type high-voltage doped type well regions (106, 206) are located on both sides of the first N-type deep well doped type well region 301 and are symmetrically arranged. The first N-type heavily doped active region (108, 208) and the first P-type heavily doped active region (107, 207) at their top are led out by metal lines to form a high-voltage port and a low-voltage port.

[0043] The N-type buried layer 100 is injected at the bottom of the substrate and is located below the first N-type deep well-doped type well region 301 and the two first P-type high-voltage doped type well regions (106, 206), with the N-type buried layer 100 and the two first P-type high-voltage doped type well regions spaced apart.

[0044] After the cutting area 401 is set in the middle of the N-type buried layer 100, the side cross-sectional view of the N-type buried layer 100 is a two-sub-N-type buried layer 100 structure in a separated state.

[0045] Preferably, the middle of the N-type buried layer 100 is cut off by a trap to form a cut-off region 401, thereby disrupting the longitudinal low-resistance current path and forcing the ESD current to turn to the lateral path, so as to improve the sustaining voltage and eliminate the risk of latch-up.

[0046] Specifically, the transverse sides of the cut-off region 401 are located inside the transverse sides of the first N-type deep well doped type well region 301 and are in contact with the bottom end of the first N-type deep well doped type well region 301, so as to precisely cut off the longitudinal path while retaining the effective conduction path of the transverse current.

[0047] By placing the cut-off region 401 directly below the first N-type deep well-doped well region 301 and ensuring that its lateral extent does not exceed the lateral boundary of the first N-type deep well-doped well region 301, the N-type buried layer 100 and the first N-type deep well-doped well region 301 can be made to fully contact each other, ensuring that the only path for longitudinal current is completely blocked and preventing longitudinal conduction due to residual residue.

[0048] In this method, by limiting the cut-off region 401 to the inside of the first N-type deep well doped type well region 301, the overall layout of the N-type buried layer 100 does not need to be changed. Only a local area directly below the first N-type deep well doped type well region 301 needs to be masked to block the doping implantation of the N-type buried layer 100, thus eliminating the need for additional complex processes.

[0049] Furthermore, the first N-type heavily doped active region (108, 208) and the first P-type heavily doped active region (107, 207) are isolated by a first STI region, which is injected downward into the corresponding first P-type well doped type well region (109, 209) to completely isolate the first P-type well doped type well region (109, 209) and the first N-type well doped type well region 302.

[0050] The first STI region can precisely define the boundaries of the first N-type heavily doped active region, the first P-type heavily doped active region, and the corresponding first P-row well-doped well region, ensuring the correct formation of parasitic transistors.

[0051] Furthermore, the high sustaining voltage bidirectional high voltage ESD structure also includes a second STI region, which is located above the first N-type well-doped type well region 302, and between the first N-type heavily doped active region (108, 208) or the first P-type heavily doped active region (107, 207) corresponding to the first P-type well-doped type well region (109, 209).

[0052] The second STI area is used to isolate critical areas, ensure the stability of the ESD discharge path, and meet the needs of two-way protection.

[0053] Furthermore, the high sustaining voltage bidirectional high-voltage ESD structure also includes two second N-type deep well-doped well regions (101, 201) and two second N-type well-doped well regions (102, 202). The two second N-type deep well-doped well regions (101, 201) are implanted into the substrate and located on the side away from the corresponding first P-type high-voltage doped well region (106, 206). The two second N-type deep well-doped well regions (101, 201) are located on both sides of the N-type buried layer 100 and are in contact with both sides of the N-type buried layer 100. The two second N-type well-doped well regions (102, 202) are implanted into the substrate and located above the corresponding second N-type deep well-doped well regions (101, 201).

[0054] Furthermore, the high sustaining voltage bidirectional high voltage ESD structure also includes a third STI region, which is located above the corresponding second N-type well-doped type well region 102, and one side of it extends above the corresponding first P-type well-doped type well region (109, 209).

[0055] Among them, the first STI region, the second STI region and the third STI region are all shallow trench isolation STI regions 303.

[0056] In some of these embodiments, such as Figure 3 As shown, the metal lines leading out from the first N-type heavily doped active region (108, 208) and the first P-type heavily doped active region (107, 207) above each first P-type well doped type well region (109, 209) are interconnected and then led out to facilitate the connection of high-voltage and low-voltage ports.

[0057] In some of these embodiments, a first N-type heavily doped active region (108, 208), a first P-type well-doped type well region (109, 209), a first P-type high-voltage doped type well region (106, 206), a P-type epitaxial layer (103, 203), and a first N-type deep well-doped type well region 301 and a first N-type well-doped type well region 302 located on the same side form a transistor (Q1, Q2).

[0058] The first N-type deep well-doped well region 301, the first N-type well-doped well region 302, and the first P-type heavily doped active regions (107, 207), the first P-type well-doped well region (109, 209), the first P-type high-voltage doped well region (106, 206), the P-type epitaxial layer (103, 203), and the two first N-type heavily doped active regions (108, 208) located on both sides form a bidirectional PNP transistor.

[0059] The working principle of this invention is as follows:

[0060] When a positive ESD pulse enters from the left port T1, the diode formed by the first P-type high-voltage doped well region 206 and the P-type epitaxial layer 203 first undergoes avalanche breakdown, forming an avalanche current. As the avalanche current flows to the right port T2, it reduces the potential of the first N-type deep well doped well region 301, causing the emitter junction of transistor Q3 to conduct forward, thus turning on transistor Q3. As the current increases, when a voltage drop of 0.7V is generated across R2, the emitter junction of transistor Q2 is forward biased and conducts, at which point transistor Q2 turns on. Subsequently, transistors Q2 and Q3 form a positive current feedback, thereby constructing a low-resistance SCR discharge path. Similarly, when a negative ESD pulse enters from the left port T1, transistors Q1 and Q3 will form a low-resistance SCR path with positive current feedback.

[0061] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions in the system embodiments.

[0062] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A high sustaining voltage bidirectional high voltage ESD structure, comprising a first N-type deep well-doped well region implanted into a substrate, a first N-type well-doped well region located above the first N-type deep well-doped well region, two first P-type high voltage-doped well regions located on both sides of the first N-type well-doped well region, and two first P-type well-doped well regions correspondingly implanted into the first P-type high voltage-doped well region; each of the first P-type well-doped well regions has a first N-type heavily doped active region and a first P-type heavily doped active region formed at its top, which are mutually isolated, and both the first N-type heavily doped active region and the first P-type heavily doped active region are led out by metal lines; Its features are, It also includes an N-type buried layer, which is injected into the substrate and located below the first N-type deep well doped type well region and the two first P-type high voltage doped type well regions, and the bottom end of the first N-type deep well doped type well region is in contact with the top end of the N-type buried layer. The N-type buried layer has a cut-off region in the middle, which is located below the first N-type deep well-doped type well region. This cut-off region is used to redirect the current path in the high sustaining voltage bidirectional high voltage ESD structure to the lateral parasitic NPN and suppress the conduction of the vertical parasitic NPN.

2. The high sustaining voltage bidirectional high voltage ESD structure according to claim 1, characterized in that, The cut-off region is formed in the middle of the N-type buried layer by a trap cutting method.

3. The high sustaining voltage bidirectional high voltage ESD structure according to claim 2, characterized in that, Both sides of the cut-off region are located inside the lateral sides of the first N-type deep well-doped type well region and are in contact with the bottom end of the first N-type deep well-doped type well region.

4. The high sustaining voltage bidirectional high voltage ESD structure according to any one of claims 1-3, characterized in that, The first N-type heavily doped active region and the first P-type heavily doped active region are isolated by a first STI region, which is injected downward into the corresponding first P-type well doped type well region.

5. The high sustaining voltage bidirectional high voltage ESD structure according to claim 4, characterized in that, It also includes a second STI region, which is located above the first N-type well-doped type well region and between the first N-type heavily doped active region or the first P-type heavily doped active region corresponding to the first P-type well-doped type well region.

6. The high sustaining voltage bidirectional high voltage ESD structure according to claim 4, characterized in that, Also includes: Two second N-type deep well doped type well regions are implanted into the substrate and located on the side of the corresponding first P-type high-voltage doped type well region away from the first N-type deep well doped type well region. The two second N-type deep well doped type well regions are located on both sides of the N-type buried layer and are in contact with both sides of the N-type buried layer. Two second N-type well-doped well regions are implanted into the substrate and located above the corresponding second N-type deep well-doped well regions.

7. The high sustaining voltage bidirectional high voltage ESD structure according to claim 6, characterized in that, It also includes a third STI region, which is located above the corresponding second N-type well-doped type well region, and one side of which extends above the corresponding first P-type well-doped type well region.

8. The high sustaining voltage bidirectional high voltage ESD structure according to any one of claims 1-3, characterized in that, The metal lines leading out from the first N-type heavily doped active region and the first P-type heavily doped active region above each of the first P-type well doped regions are interconnected and then led out.

9. The high sustaining voltage bidirectional high voltage ESD structure according to any one of claims 1-3, characterized in that, A transistor is formed by the first N-type heavily doped active region, the first P-type well doped well region, the first P-type high voltage doped well region, the P-type epitaxial layer, the first N-type deep well doped well region, and the first N-type well doped well region located on the same side as the first N-type deep well doped well region.

10. The high sustaining voltage bidirectional high voltage ESD structure according to claim 9, characterized in that, The first N-type deep well-doped type well region, the first N-type well-doped type well region, and the two first P-type heavily doped active regions, the two first P-type well-doped type well regions, the two first P-type high voltage doped type well regions, the two P-type epitaxial layers, and the two first N-type heavily doped active regions located on both sides of the first N-type deep well-doped type well region and the first N-type well-doped type well region form a bidirectional PNP transistor.

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