Photovoltaic module, laminated cell, back contact cell and method for manufacturing the same

Abstract

The present disclosure relates to the technical field of solar cell, and provides a photovoltaic module, a laminated cell, a back contact cell and a manufacturing method thereof. The manufacturing method comprises: providing a substrate, a second surface of the substrate comprising a first region and a second region; forming a tunneling layer on the second surface; forming a first polysilicon layer on the surface of the tunneling layer by using a first deposition process; forming a second polysilicon layer on the surface of the first polysilicon layer by using a second deposition process; the temperature and pressure of the first deposition process are higher than those of the second deposition process; performing a doping treatment to convert the first polysilicon layer and the second polysilicon layer into a first semiconductor doped layer; forming a second semiconductor doped layer on the second region; forming a first electrode and a second electrode, the first electrode being in electrical contact with the first semiconductor doped layer, and the second electrode being in electrical contact with the second semiconductor doped layer. The present disclosure is at least beneficial to realizing low-resistance ohmic contact between the first semiconductor doped layer and the first electrode while ensuring good surface passivation effect.

Description

Technical Field

[0001] This disclosure relates to the field of solar cell technology, and in particular to a photovoltaic module, a tandem cell, a back contact cell, and a method for manufacturing the same. Background Technology

[0002] With the continuous advancement of photovoltaic technology, improving the efficiency of solar cells has become a core objective for the industry. Among various high-efficiency crystalline silicon solar cell structures, back-contact (BC) cells have gradually attracted widespread attention due to their advantages such as no metal grid lines obstructing the front side, high light utilization, and short current transmission path.

[0003] Among them, the interdigitated back contact (IBC) battery, as a typical back contact platform technology, can be integrated with a variety of high-efficiency battery structures to further improve performance. The fusion of IBC and tunneling passivated contact (TOPCon) technology constitutes the tunneling passivated contact back contact (TBC) battery, which shows excellent efficiency potential.

[0004] However, in high-efficiency back-contact solar cells, there is a fundamental contradiction between surface passivation performance and ohmic contact performance of metal electrodes, which seriously restricts further improvement of cell performance. Summary of the Invention

[0005] This disclosure provides a photovoltaic module, a tandem cell, a back contact cell, and a method for manufacturing the same, which at least helps to achieve a low-resistance ohmic contact between the semiconductor layer and the metal electrode while ensuring a good surface passivation effect.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for manufacturing a back contact battery, comprising: providing a substrate having opposing first and second surfaces, the second surface including alternating first and second regions; forming a tunneling layer on the second surface; forming a first polycrystalline silicon layer on the surface of the tunneling layer using a first deposition process; forming a second polycrystalline silicon layer on the surface of the first polycrystalline silicon layer using a second deposition process; wherein a first deposition temperature of the first deposition process is higher than a second deposition temperature of the second deposition process, and a first deposition pressure of the first deposition process is higher than a second deposition pressure of the second deposition process; performing a doping process to convert the first polycrystalline silicon layer and the second polycrystalline silicon layer into a first semiconductor doped film; removing the first semiconductor doped film from the second region, the remaining first semiconductor doped film serving as the first semiconductor doped layer; forming a second semiconductor doped layer on the second region; forming a first electrode and a second electrode, the first electrode being in electrical contact with the first semiconductor doped layer, and the second electrode being in electrical contact with the second semiconductor doped layer.

[0007] In some embodiments, the difference between the first deposition temperature and the second deposition temperature is in the range of 20°C to 50°C; and / or, the difference between the first deposition pressure and the second deposition pressure is in the range of 150 mBar to 300 mBar.

[0008] In some embodiments, the process parameters of the first deposition process include: the first deposition pressure is 350 mBar to 500 mBar, the first deposition temperature is 570°C to 600°C, and the deposition time is 1000 s to 2000 s.

[0009] In some embodiments, the process parameters of the second deposition process include: the second deposition pressure is 200 mBar to 350 mBar, the second deposition temperature is 550℃ to 570℃, and the deposition time is 3000 s to 5000 s.

[0010] In some embodiments, the thickness of the first polysilicon layer is less than the thickness of the second polysilicon layer.

[0011] In some embodiments, the thickness ratio of the first polysilicon layer to the second polysilicon layer is 1:3 to 1:2.

[0012] In some embodiments, converting the first polysilicon layer and the second polysilicon layer into a first semiconductor doped film includes: converting the first polysilicon layer into a first doped portion; converting the second polysilicon layer into a second doped portion; after removing the first semiconductor doped film in the second region, the remaining first doped portion serves as a first semiconductor doped portion, and the remaining second doped portion serves as a second semiconductor doped portion, wherein the first semiconductor doped portion and the second semiconductor doped portion constitute the first semiconductor doped layer; wherein the first electrode is in electrical contact with the second semiconductor doped portion.

[0013] In some embodiments, the doping concentration of the first semiconductor doped portion is greater than the doping concentration of the second semiconductor doped portion.

[0014] According to some embodiments of this disclosure, another aspect of this disclosure provides a back contact battery, comprising: a substrate having opposing first and second surfaces, the second surface including alternating first and second regions; a tunneling layer located on the second surface; a first semiconductor doped layer located on the tunneling layer corresponding to the first region, the first semiconductor doped layer including a first semiconductor doped portion located on the surface of the tunneling layer and a second semiconductor doped portion located on the surface of the first semiconductor doped portion, the density of the first semiconductor doped portion being greater than the density of the second semiconductor doped portion; a second semiconductor doped layer located on the tunneling layer corresponding to the second region; a first electrode and a second electrode, the first electrode being in electrical contact with the second semiconductor doped portion and the second electrode being in electrical contact with the second semiconductor doped layer.

[0015] In some embodiments, the thickness of the first semiconductor doped portion is less than the thickness of the second semiconductor doped portion.

[0016] In some embodiments, the thickness ratio of the first semiconductor doped portion to the thickness of the second semiconductor doped portion is 1:3 to 1:2.

[0017] In some embodiments, the doping concentration of the first semiconductor doped portion is greater than the doping concentration of the second semiconductor doped portion.

[0018] In some embodiments, the dopant ions of the first semiconductor doped layer are P-type ions, and the dopant ions of the second semiconductor doped layer are N-type ions.

[0019] According to some embodiments of this disclosure, another aspect of this disclosure also provides a stacked battery, including: a bottom battery, which is a back contact battery as described in the above embodiments; and a perovskite battery, which is located on one side of the bottom battery.

[0020] According to some embodiments of this disclosure, another aspect of this disclosure provides a photovoltaic module, including: a battery string, which is formed by connecting multiple back-contact batteries formed by the manufacturing method of back-contact batteries as described in the above embodiments, or by connecting multiple back-contact batteries as described in the above embodiments, or by connecting multiple stacked batteries as described above; an encapsulating film for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulating film away from the battery string.

[0021] The technical solutions provided in this disclosure have at least the following advantages:

[0022] The method for manufacturing a back contact battery provided in this disclosure constructs a functionally layered polycrystalline silicon structure by stepwise control of deposition process parameters. Specifically, a first deposition process is used to form a first polycrystalline silicon layer on the surface of the tunneling layer. Since the first deposition process has a relatively high deposition temperature and relatively high deposition pressure, it is beneficial to form a dense first polycrystalline silicon layer. This facilitates the formation of a high-quality tunneling layer / polycrystalline silicon interface, effectively reducing the interface state density, improving surface passivation, and reducing carrier recombination. A second deposition process is used to form a second polycrystalline silicon layer on the first polycrystalline silicon layer. The second deposition process has a relatively low deposition temperature and relatively low deposition pressure, resulting in a less dense second polycrystalline silicon layer compared to the first polycrystalline silicon layer. Furthermore, the first semiconductor doped layer formed by doping also exhibits good interface performance with the tunneling layer, and the portion of the first semiconductor doped layer far from the substrate is relatively porous. During the formation of the first electrode, which is in electrical contact with the first semiconductor doped layer, the portion of the first semiconductor doped layer in contact with the first electrode has poor density. Therefore, the electrode material can more easily penetrate into the first semiconductor doped layer during the formation of the first electrode, and the contact area between the first electrode and the first semiconductor doped layer increases. This helps to reduce the contact resistance between the first electrode and the first semiconductor doped layer and improve the carrier collection efficiency. As can be seen from the foregoing analysis, the embodiments of this disclosure, while ensuring the passivation effect of the first semiconductor doped layer, can improve the ohmic contact characteristics between the first electrode and the first semiconductor doped layer, thereby helping to improve the open-circuit voltage and photoelectric conversion efficiency of the back contact battery. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 A schematic flowchart illustrating a method for manufacturing a back contact battery according to an embodiment of this disclosure;

[0025] Figure 2 A schematic diagram of the substrate structure corresponding to the substrate step in the manufacturing method of the back contact battery provided in this embodiment of the present disclosure is provided.

[0026] Figure 3 In order to be in Figure 2 A schematic diagram of the structure after the tunneling layer is formed on the structure shown;

[0027] Figure 4 In order to be in Figure 3 A schematic diagram of the structure after the first polycrystalline silicon layer is formed on the structure shown;

[0028] Figure 5 In order to be in Figure 4 A schematic diagram of the structure after the second polysilicon layer is formed on the structure shown;

[0029] Figure 6 To Figure 5 A schematic diagram of the structure after doping treatment;

[0030] Figure 7 In order to be in Figure 6 A schematic diagram of the structure after the first semiconductor doped layer is formed on the structure shown;

[0031] Figure 8 In order to be in Figure 7 A schematic diagram of the structure after the third polycrystalline silicon layer is formed on the structure shown;

[0032] Figure 9 In order to be in Figure 8 A schematic diagram of the structure after doping treatment is shown;

[0033] Figure 10 A schematic diagram of a back contact battery provided in an embodiment of this disclosure;

[0034] Figure 11 This is a schematic diagram of another structure of the back contact battery provided in an embodiment of this disclosure;

[0035] Figure 12 This is another schematic diagram of the structure of a back contact battery provided in an embodiment of this disclosure;

[0036] Figure 13 This is a partial cross-sectional structural diagram of a back-contact stacked battery provided in an embodiment of this disclosure;

[0037] Figure 14 This is a partial three-dimensional structural diagram of a photovoltaic module provided in an embodiment of the present disclosure;

[0038] Figure 15 for Figure 14 A partial cross-sectional schematic diagram along the cross-sectional direction AA1.

[0039] Explanation of reference numerals in the attached figures:

[0040] Substrate 100, first surface 101, second surface 102, first region I, second region II, tunneling layer 112, first polysilicon layer 113, second polysilicon layer 114, first semiconductor doped film 115, first semiconductor doped layer 116, third polysilicon layer 107, second semiconductor doped layer 117, first electrode 118, second electrode 119, functional layer 120, passivation layer 121, antireflection layer 122, spacer region III, first semiconductor doped portion 1161, second semiconductor doped portion 1162, back contact stacked cell 10, bottom cell 20, perovskite cell 30, back contact cell 40, encapsulating film 41, cover plate 42, solder ribbon 43. Detailed Implementation

[0041] In high-efficiency back-contact solar cell structures, alternating P-type and N-type semiconductor doped layers are typically placed on the back of a silicon substrate to collect holes and electrons, respectively, and are electrically connected through a first electrode and a second electrode. However, during actual process development, it was found that the contact resistance between the first electrode and the P-type semiconductor doped layer is significantly higher than the contact resistance between the second electrode and the N-type semiconductor doped layer. This leads to an increase in the overall series resistance of the cell, a decrease in conversion efficiency, and severely restricts further improvements in cell performance.

[0042] Analysis revealed that the difference in contact performance primarily stems from the fundamental differences in material properties and interfacial behavior between P-type and N-type doped layers. P-type dopant ions, with their generally smaller atomic radii than silicon atoms, are prone to lattice distortion, uneven doping distribution, and insufficient activation, resulting in poor crystal quality and high interfacial state density in the formed P-type polycrystalline silicon layer, which is detrimental to efficient carrier transport. In contrast, N-type dopant ions have a more closely matched atomic size to silicon, resulting in less lattice disturbance during doping and higher crystal integrity in the formed N-type polycrystalline silicon layer, with excellent interfacial characteristics. This makes it more conducive to forming a low-resistance ohmic contact between the metal electrode and silicon. For example, when the P-type dopant ion is boron (B), the covalent radius of boron atoms is significantly smaller than that of silicon atoms, easily causing localized lattice stress during doping, leading to boron atom segregation or clustering, making uniform activation difficult. Furthermore, in the subsequent co-sintering process, the first electrode struggles to effectively penetrate the P-type polycrystalline silicon layer to form a good metallurgical bond, further exacerbating the contact barrier and resulting in higher contact resistance.

[0043] To alleviate the aforementioned problems, the art typically attempts to improve contact performance by optimizing the deposition process of the P-type polysilicon layer. For example, reducing the deposition temperature and pressure during the deposition of the P-type polysilicon layer can decrease its density, forming a more porous microstructure. This allows the first electrode to penetrate the P-type semiconductor doped layer more easily during sintering, increasing the effective contact area between the first electrode and the silicon substrate, thereby reducing contact resistance. However, further research has found that while this method can improve electrode penetration to some extent, the porous structure not only leads to a decrease in the uniformity of the P-type semiconductor doped layer, disrupting the surface passivation effect, but also reduces the crystallization quality of the P-type semiconductor doped layer, resulting in insufficient activation of doped atoms and thus weakening the lateral transport capability of charge carriers. Therefore, simply reducing the deposition density to improve contact performance is insufficient to achieve a synergistic optimization between surface passivation and ohmic contact, and cannot achieve an effective balance between the two.

[0044] Based on an in-depth analysis of the aforementioned technical problems, this disclosure creatively proposes a method for manufacturing a back-contact battery. First, a dense first polycrystalline silicon layer is deposited under relatively high first deposition temperature and high first deposition pressure to optimize the interface quality between the tunneling layer and the polycrystalline silicon, thereby improving surface passivation performance. Then, a loosely structured second polycrystalline silicon layer is deposited under lower second deposition temperature and lower second deposition pressure. On this basis, a first semiconductor doped layer is formed through doping. The loose surface structure of the first semiconductor doped layer allows the electrode material to penetrate more easily into the first semiconductor doped layer during the subsequent formation of the first electrode, while also increasing the effective contact area between the first electrode and the first semiconductor doped layer. This helps to reduce contact resistance and improve carrier collection efficiency. This method significantly improves the ohmic contact characteristics between the first semiconductor doped layer and the first electrode while ensuring the overall passivation effect of the first semiconductor doped layer, thus contributing to improved open-circuit voltage and photoelectric conversion efficiency of the back-contact battery.

[0045] In the description of the embodiments of this disclosure, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary or secondary relationship of the indicated technical features. In the description of the embodiments of this disclosure, "multiple" means two or more, unless otherwise explicitly defined. Similarly, "multiple sets" refers to two or more sets (including two sets), and "multiple pieces" refers to two or more pieces (including two pieces).

[0046] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0047] In the description of the embodiments of this disclosure, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0048] In the description of the embodiments of this disclosure, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the embodiments of this disclosure and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of this disclosure. For example, if the device or element in the illustration is inverted, then the element described as "below," "under," "below," or "bottom" of other elements or features will be oriented "above" or "top" of said other elements or features. Therefore, the term "below" may, depending on the context in which the term is used, encompass both above and below orientations, which will be obvious to those skilled in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0049] In the description of the embodiments of this disclosure, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical contact; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0050] In the accompanying drawings corresponding to the embodiments of this disclosure, the thickness and area of ​​the layers are enlarged for better understanding and ease of description. Furthermore, when describing a component as "generally" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor on a portion of the edge of the entire surface.

[0051] In the description of the embodiments of this disclosure, when a component "includes" another component, other components are not excluded unless otherwise stated, and may be further included. The formation or placement of a second component above or on a first component, or on the surface of a first component, or on one side of a first component, may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be placed between the first and second components, thereby preventing direct contact between the first and second components. For simplicity and clarity, various components may be drawn at different scales. In the drawings, some layers / components may be omitted for simplicity. Unless otherwise specified, the formation or placement of a second component on the surface of a first component refers to direct contact between the first and second components. The term "component" can refer to a layer, film, region, portion, structure, etc.

[0052] The terminology used in the description of the various embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various embodiments and the appended claims, the term "component" is also intended to include the plural form unless the context clearly indicates otherwise. Components include layers, films, regions, or plates, etc.

[0053] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0054] Figure 1 This is a schematic flowchart illustrating a method for manufacturing a back contact battery according to an embodiment of this disclosure. (See reference...) Figure 1 The manufacturing method of the back contact battery includes:

[0055] S1. Provide a substrate having opposing first and second surfaces, the second surface comprising alternating first and second regions.

[0056] S2, a tunneling layer is formed on the second surface.

[0057] S3. Using the first deposition process, a first polycrystalline silicon layer is formed on the surface of the tunneling layer.

[0058] S4. A second polysilicon layer is formed on the surface of the first polysilicon layer using a second deposition process; wherein the first deposition temperature of the first deposition process is higher than the second deposition temperature of the second deposition process, and the first deposition pressure of the first deposition process is higher than the second deposition pressure of the second deposition process.

[0059] S5. Perform doping treatment to convert the first polysilicon layer and the second polysilicon layer into a first semiconductor doped film.

[0060] S6. Remove the first semiconductor doped film from the second region, and the remaining first semiconductor doped film serves as the first semiconductor doped layer.

[0061] S7. A second semiconductor doped layer is formed on the second region.

[0062] S8. A first electrode and a second electrode are formed, wherein the first electrode is in electrical contact with the first semiconductor doped layer and the second electrode is in electrical contact with the second semiconductor doped layer.

[0063] It is worth noting that the embodiments of this disclosure construct a polycrystalline silicon structure with functional layering characteristics by stepwise controlling the deposition process parameters, achieving a synergistic improvement in surface passivation and ohmic contact performance. Specifically, firstly, a first polycrystalline silicon layer is formed on the surface of the tunneling layer using a first deposition process. The first deposition process is carried out at relatively high temperature and pressure, which is conducive to the full migration and orderly arrangement of silicon atoms, thereby obtaining a dense film with high crystal quality. A high-quality interface is formed between this dense layer and the tunneling layer, significantly reducing the interface state density and effectively suppressing carrier recombination at the interface, providing a solid foundation for achieving excellent surface passivation. On this basis, a second polycrystalline silicon layer is deposited on the first polycrystalline silicon layer using a second deposition process. The second deposition process is carried out at lower temperature and lower pressure, which limits the migration ability of atoms, thus forming a more porous second polycrystalline silicon layer with higher porosity. The first semiconductor doped layer formed after subsequent doping treatment thus exhibits good interface performance with the tunneling layer and a relatively porous portion of the first semiconductor doped layer away from the substrate.

[0064] Furthermore, during the screen printing and sintering process, the paste of the first electrode can more easily penetrate the loose surface region of the first semiconductor doped layer, significantly increasing the effective contact area between the first electrode and the first semiconductor doped layer. The lower penetration barrier helps to significantly reduce the contact resistance and improve the lateral transport and vertical collection efficiency of charge carriers.

[0065] Therefore, this disclosure can improve the ohmic contact characteristics between the first electrode and the first semiconductor doped layer while ensuring the passivation effect of the first semiconductor doped layer, thereby helping to improve the open circuit voltage and photoelectric conversion efficiency of the back contact battery.

[0066] It should be noted that the density of the first and second polycrystalline silicon layers can be detected and evaluated by cross-sectional observation using a scanning electron microscope (SEM). Specifically, the dense first polycrystalline silicon layer, in the SEM cross-sectional image, exhibits a uniform and continuous film structure, clearly distinguishable grain outlines, relatively large and uniformly distributed grain sizes, and no obvious pores, gaps, or microcracks, displaying a highly dense microscopic morphological characteristic. The porous second polycrystalline silicon layer, on the other hand, exhibits a "sponge-like" or "flocculent" cross-sectional structure, with fine grains and blurred grain boundaries, numerous nanoscale pores and discontinuous regions, resulting in a loose and porous overall structure with lower density. Through the above SEM morphology comparison, the structural differences between the two polycrystalline silicon layers under the deposition process can be intuitively distinguished, thereby relating their impact on carrier transport, contact resistance, and interface passivation performance, providing a microscopic basis for optimizing the structural design of the back contact battery. To further illustrate the technical content of the embodiments of this disclosure, the following will describe each step in more detail with reference to the accompanying drawings.

[0067] Figures 2 to 12 This is a cross-sectional structural diagram of each step in the manufacturing method of the back contact battery provided in the embodiments of this disclosure.

[0068] refer to Figure 2 A substrate 100 is provided, the substrate 100 having a first surface 101 and a second surface 102 opposite to each other, the second surface 102 including an alternating first region I and a second region II.

[0069] In some embodiments, the height of the base 100 located in the first region I in the second surface 102 is less than the height of the base 100 located in the second region II compared to the first surface 101.

[0070] The substrate 100 is used to receive incident light and generate photogenerated carriers. In some embodiments, the substrate 100 may be a semiconductor substrate 100, such as silicon, germanium, germanium-silicon, or silicon on an insulator.

[0071] In some embodiments, the material of the substrate 100 may be an elemental semiconductor material. Specifically, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material may be monocrystalline, polycrystalline, amorphous, or microcrystalline (a state simultaneously possessing both monocrystalline and amorphous states is called microcrystalline). For example, silicon may be at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. If the material of the substrate 100 is silicon, then the material of the substrate 100 may include at least one of monocrystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0072] In some embodiments, the substrate 100 may also be a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanide, silicon carbide, gallium arsenide, indium gallium arsenide, perovskite, cadmium telluride, copper indium selenide, etc. Materials may also be silicon carbide, organic materials, or multi-component compounds. Multi-component compounds may include, but are not limited to, perovskite, gallium arsenide, cadmium telluride, copper indium selenide, etc.

[0073] The substrate 100 can also be a sapphire substrate 100, a silicon substrate on an insulator 100, or a germanium substrate on an insulator 100.

[0074] The substrate 100 can be an N-type semiconductor substrate 100 or a P-type semiconductor substrate 100. The N-type semiconductor substrate 100 is doped with an N-type dopant element, which can be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The P-type semiconductor substrate 100 is doped with a P-type dopant element, which can be at least one of group III elements such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0075] In some embodiments, the back-contact battery is a single-sided battery, in which case the first surface 101 of the substrate 100 serves as the light-receiving surface for receiving incident light, and the second surface 102 of the substrate 100 serves as the back-lighting surface. It should be noted that the light-receiving surface and the back-lighting surface are relative terms; the luminous flux of the light received by the light-receiving surface is greater than that received by the back-lighting surface. The "back-lighting surface" described in this embodiment can also receive light.

[0076] For those skilled in the art, the second surface 102 can be divided into a first region I and a second region II, wherein the first region I is generally used to refer to the relative region in which the first semiconductor doped layer is formed in a subsequent doping process, and the second region II is generally used to refer to the relative region in which the second semiconductor doped layer is formed in a subsequent doping process.

[0077] refer to Figure 3 A tunnel layer 112 is formed on the second surface 102.

[0078] Tunnel layer 112 is located in the first region I and the second region II.

[0079] In some embodiments, a tunneling layer 112 may be formed on the second surface 102 using low-pressure chemical vapor deposition (LPCVD).

[0080] In some embodiments, the material of the tunneling layer 112 may include at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polycrystalline silicon.

[0081] In some embodiments, the process parameters for forming the tunnel layer 112 include: a process duration of 2000s to 2500s and a process temperature of 500℃ to 600℃.

[0082] In some embodiments, the thickness of the tunneling layer 112 is 1nm to 2nm, for example, it can be 1nm, 1.1nm, 1.2nm, 1.3nm, 1.4nm, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 1.9nm or 2nm.

[0083] refer to Figure 4 A first polycrystalline silicon layer 113 is formed on the surface of the tunneling layer 112 using a first deposition process.

[0084] In some embodiments, the first deposition process can be low-pressure chemical vapor deposition (LPCVD).

[0085] Among them, LPCVD is carried out in a low-pressure environment, with a large diffusion coefficient of the reactant gas and uniform gas distribution, which enables the formation of high-quality, high-density and high-uniformity polycrystalline silicon thin films.

[0086] It should be noted that, in other embodiments, the first deposition process can also be plasma-enhanced chemical vapor deposition (PECVD) or atmospheric-pressure chemical vapor deposition (APCVD), etc.

[0087] In some embodiments, the process parameters of the first deposition process include: a first deposition pressure of 350 mBar to 500 mBar, for example, 350 mBar, 360 mBar, 370 mBar, 380 mBar, 390 mBar, 400 mBar, 410 mBar, 420 mBar, 430 mBar, 440 mBar, 450 mBar, 460 mBar, 470 mBar, 480 mBar, 490 mBar, or 500 mBar; and a first deposition temperature of 570℃ to 600℃, for example, 570℃, 571℃, 572℃, 573℃, 570 ... 4℃, 575℃, 576℃, 577℃, 578℃, 579℃, 580℃, 581℃, 582℃, 583℃, 584℃, 585℃, 586℃, 587℃, 588℃, 589℃, 590℃, 591℃, 592℃, 593℃, 594℃, 595℃, 596℃, 597℃, 598℃, 599℃, or 600℃; deposition time is 1000s~2000s, for example, it can be 1000s, 1100s, 1200s, 1300s, 1400s, 1500s, 1600s, 1700s, 1800s, 1900s, or 2000s.

[0088] It should be noted that a higher deposition temperature is beneficial for improving the surface migration ability of silicon atoms, promoting their orderly arrangement, and forming a polycrystalline silicon structure with good crystallinity. A higher deposition pressure increases the concentration of reactive gases, enhances the mass transport capacity during the deposition process, and is conducive to the formation of a dense and continuous first polycrystalline silicon layer 113. The synergistic effect of these two factors not only improves the density and crystal integrity of the first polycrystalline silicon layer 113, but also significantly improves the interface quality between the first polycrystalline silicon layer 113 and the underlying tunneling layer 112, effectively reducing the interface state density and suppressing carrier recombination at the interface, thereby ensuring excellent surface passivation performance.

[0089] In some embodiments, by employing zoned temperature control in the first deposition process, with each heating zone independently adjusting its temperature, precise control of the thermal field within the reaction chamber can be achieved. For example, referring to Table 1, the deposition apparatus has six heating zones, and in the first deposition process, the deposition temperatures of each heating zone are set to 580°C, 580°C, 575°C, 575°C, 580°C, and 580°C, respectively. This temperature distribution can moderately suppress the deposition rate in the gas inlet region and enhance the reaction activity in the outlet region, thereby compensating for the non-uniformity caused by gas consumption along the process. By optimizing the thermal field distribution, not only is the thickness uniformity of the first polycrystalline silicon layer 113 improved, but surface migration and grain merging of silicon atoms are also promoted, which is beneficial for forming a dense first polycrystalline silicon layer 113 with excellent crystal quality, meeting the performance requirements of efficient passivation contacts.

[0090] Table 1

[0091]

[0092] refer to Figure 5 A second deposition process is used to form a second polysilicon layer 114 on the surface of the first polysilicon layer 113.

[0093] In some embodiments, the second deposition process can be LPCVD technology.

[0094] The second polycrystalline silicon layer 114 is formed using LPCVD technology, which can effectively reduce its defect density, improve material quality, and also has excellent thickness uniformity.

[0095] It should be noted that in other embodiments, the second deposition process can also be a method such as PECVD technology and APCVD technology.

[0096] In this process, the first deposition temperature of the first deposition process is higher than the second deposition temperature of the second deposition process, and the first deposition pressure of the first deposition process is higher than the second deposition pressure of the second deposition process.

[0097] In some embodiments, the process parameters of the second deposition process include: a second deposition pressure of 200 mBar to 350 mBar, for example, 200 mBar, 210 mBar, 220 mBar, 230 mBar, 240 mBar, 250 mBar, 260 mBar, 270 mBar, 280 mBar, 290 mBar, 300 mBar, 310 mBar, 320 mBar, 330 mBar, 340 mBar, or 350 mBar; and a second deposition temperature of 550℃ to 570℃, for example, 550℃, 551℃, 552℃, 553℃, 554℃, or 570℃. 55℃, 556℃, 557℃, 558℃, 559℃, 560℃, 561℃, 562℃, 563℃, 564℃, 565℃, 566℃, 567℃, 568℃, 569℃, or 570℃; deposition time is 3000s~5000s, for example, it can be 3000s, 3100s, 3200s, 3300s, 3400s, 3500s, 3600s, 3700s, 3800s, 3900s, 4000s, 4100s, 4200s, 4300s, 4400s, 4500s, 4600s, 4700s, 4800s, 4900s, or 5000s.

[0098] The lower deposition temperature limits the surface migration ability of silicon atoms, resulting in small grain size and disordered arrangement; the lower deposition pressure reduces the concentration of reactive gases, slowing down the deposition rate of the second polycrystalline silicon layer 114 and facilitating the formation of a porous structure with high porosity. The synergistic effect of these two factors is beneficial for constructing a porous, loosely structured second polycrystalline silicon layer 114. This porous structure significantly reduces the penetration barrier of the first electrode paste during the metallization sintering stage, promoting the penetration of the first electrode into the polycrystalline silicon layer, significantly increasing the contact area between the polycrystalline silicon layer and the metal electrode, promoting metal penetration and uniform contact, thereby effectively reducing contact resistance and improving carrier collection efficiency. Combined with a longer deposition time, precise control of the microstructure can be achieved while ensuring the thickness and uniformity of the second polycrystalline silicon layer 114, further optimizing the electrical contact performance of the back contact battery.

[0099] In some embodiments, by employing zoned temperature control in the second deposition process, with each heating zone independently adjusting its temperature, precise control of the thermal field within the reaction chamber can be achieved. For example, referring to Table 1, the deposition equipment has six heating zones, and in the second deposition process, the deposition temperatures of each heating zone are set to 565°C, 565°C, 560°C, 565°C, 560°C, and 565°C, respectively. This temperature distribution effectively compensates for the concentration gradient caused by gas consumption along the process by appropriately lowering the temperature in the middle region to suppress local deposition rates and maintaining a higher temperature in the outlet region to enhance reaction activity, thereby improving the axial uniformity of the thickness of the second polycrystalline silicon layer 114. Simultaneously, the overall lower deposition temperature combined with localized thermal field control is beneficial for forming a second polycrystalline silicon layer 114 with a loose structure and high porosity.

[0100] In some embodiments, the difference between the first deposition temperature and the second deposition temperature is in the range of 20°C to 50°C, for example, it can be 20°C, 21°C, 22°C, 23°C, 24°C, 25°C, 26°C, 27°C, 28°C, 29°C, 30°C, 31°C, 32°C, 33°C, 34°C, 35°C, 36°C, 37°C, 38°C, 39°C, 40°C, 41°C, 42°C, 43°C, 44°C, 45°C, 46°C, 47°C, 48°C, 49°C, or 50°C; and / or, The difference between the first and second deposition pressures is in the range of 150 mBar to 300 mBar, for example, it can be 150 mBar, 160 mBar, 170 mBar, 180 mBar, 190 mBar, 200 mBar, 210 mBar, 220 mBar, 230 mBar, 240 mBar, 250 mBar, 260 mBar, 270 mBar, 280 mBar, 290 mBar or 300 mBar.

[0101] In some embodiments, the density of the polycrystalline silicon layer can be controlled by adjusting the temperature and pressure differences between the first and second deposition processes.

[0102] It is worth noting that temperature and pressure are the easiest process parameters to precisely control and maintain stably in LPCVD technology, and batch-to-batch consistency can be achieved through automated control systems. Compared with methods that rely on post-processing techniques such as etching and laser treatment to regulate film density, controlling density by adjusting deposition temperature and pressure has significant advantages such as strong process controllability, high result stability, and good repeatability.

[0103] In some embodiments, the source gas flow rates provided in the first deposition process and the second deposition process are equal.

[0104] It should be noted that in some embodiments, the source gas can be provided through multiple independent inlet pipes, and the gas flow rate of each pipe can be adjusted independently. For example, referring to Table 1, in the first and second deposition processes, silane gas is simultaneously introduced into the reaction chamber through three independent inlet pipes to achieve uniform gas distribution at multiple points. The gas flow rates of the three independent inlet pipes are 400 sccm, 430 sccm, and 900 sccm, respectively. This design helps to improve the diffusion distribution of the reactive gas among densely packed silicon wafers, reduce the concentration gradient caused by gas consumption, and thus improve the thickness uniformity and batch stability of the deposited film.

[0105] In other embodiments, the source gas flow rates provided in the first deposition process and the second deposition process may be different.

[0106] Optionally, the source gas flow rate of the first deposition process is greater than the source gas flow rate of the second deposition process.

[0107] A higher gas flow rate increases the reactive gas concentration, thereby improving the deposition rate. This facilitates rapid and uniform dense deposition under higher temperature and pressure conditions, forming a first polycrystalline silicon layer 113 with a complete structure and excellent interface quality, effectively improving surface passivation performance. Conversely, a lower gas flow rate reduces the reactive gas concentration and slows down the adsorption rate. Combined with lower temperature and pressure, this helps to generate a second polycrystalline silicon layer 114 with a looser structure and higher porosity. This provides a favorable channel for the penetration of the first electrode during the subsequent sintering process, reducing contact resistance and improving electrical contact performance. In some embodiments, the deposition temperature and deposition pressure of the second deposition process remain constant throughout the deposition process.

[0108] In other embodiments, in the second deposition process, the deposition temperature and deposition pressure decrease gradually throughout the deposition process, including step-wise or linear decreases.

[0109] Understandably, by gradually reducing the deposition temperature and pressure, a higher nucleation density can be formed in the early stages of the second deposition process, ensuring the continuity of the film between the first polycrystalline silicon layer 113 and the second polycrystalline silicon layer 114. As the deposition temperature and pressure decrease, the surface migration ability of silicon atoms weakens, grain growth is limited, and a tendency is formed to create small, isolated island structures, thus constructing a gradient loose structure with gradually increasing porosity. This loose structure is beneficial for promoting the penetration of the first electrode material during subsequent sintering, increasing the effective contact area, and reducing contact resistance.

[0110] In some embodiments, the thickness of the first polysilicon layer 113 is less than the thickness of the second polysilicon layer 114.

[0111] The first polysilicon layer 113, as the bottom polysilicon layer, has the core function of forming a high-quality interface with the tunneling layer 112 to achieve excellent surface passivation and suppress carrier recombination. Since the passivation effect mainly depends on the interface quality rather than the film thickness, a moderate thickness is sufficient to meet the performance requirements. At the same time, a thinner first polysilicon layer 113 helps to shorten the deposition time, reduce the overall thermal budget, and reduce stress accumulation caused by thermal expansion differences, thereby improving process stability and device reliability.

[0112] The second polysilicon layer 114, as the surface polysilicon layer, adopts a loose structure to form abundant micropores and a high specific surface area, enabling the subsequent first electrode to effectively penetrate and establish three-dimensional contact, significantly reducing contact resistance. By increasing the thickness of the second polysilicon layer 114, the conductive network can be further expanded, enhancing the lateral collection capability of charge carriers and improving its function as a conductive channel, thereby optimizing the overall electrical performance.

[0113] It should be noted that in other embodiments, the thickness of the first polysilicon layer 113 and the thickness of the second polysilicon layer 114 may also be the same.

[0114] In some embodiments, the thickness ratio of the first polysilicon layer 113 to the thickness ratio of the second polysilicon layer 114 is 1:3 to 1:2, for example, it can be 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, 0.41, 0.42, 0.43, 0.44, 0.45, 0.46, 0.47, 0.48 or 0.49, etc.

[0115] It is worth noting that the first semiconductor doped layer 116, composed of the first polysilicon layer 113 and the second polysilicon layer 114, with this thickness ratio, can balance passivation performance, electrical contact characteristics, and process stability. The first polysilicon layer 113, as the bottom polysilicon layer, although relatively thin, forms a dense structure through a high-temperature, high-pressure deposition process, effectively ensuring the interface quality with the tunneling layer 112, achieving excellent surface passivation, and suppressing carrier recombination. The second polysilicon layer 114, as the top polysilicon layer, is 2 to 3 times thicker than the first polysilicon layer 113. Combined with its loose porous structure, it significantly increases the contact area and conductive channel depth between the polysilicon layer and the first electrode, facilitating the penetration of the first electrode paste and the formation of three-dimensional contact, improving the lateral collection capability of carriers, and reducing contact resistance and series resistance. This thickness ratio, while achieving a balance and improvement in passivation and electrical contact performance, avoids increased thermal budget and internal stress accumulation caused by an excessively thick first polysilicon layer 113, which is beneficial for controlling process costs, improving yield, and ensuring mass production stability.

[0116] In some embodiments, the thickness of the first polysilicon layer 113 is 100nm to 150nm, for example, it can be 100nm, 110nm, 120nm, 130nm, 140nm or 150nm; the thickness of the second polysilicon layer 114 is 200nm to 450nm, for example, it can be 200nm, 210nm, 220nm, 230nm, 240nm, 250nm, 260nm, 270nm, 280nm, 290nm, 300nm, 310nm, 320nm, 330nm, 340nm, 350nm, 360nm, 370nm, 380nm, 390nm, 400nm, 410nm, 420nm, 430nm, 440nm or 450nm.

[0117] For example, if the thickness of the first polysilicon layer 113 is 100 nm, then the thickness of the second polysilicon layer 114 is 200 nm to 300 nm.

[0118] refer to Figure 6 The first polysilicon layer 113 and the second polysilicon layer 114 are subjected to doping treatment to transform them into a first semiconductor doped film 115.

[0119] In some embodiments, a first doped source layer is formed on the surface of the second polysilicon layer 114, and the first doped source layer contains a first doping element.

[0120] In some embodiments, the first dopant element may be a p-type dopant element, such as boron (B), aluminum (Al), or gallium (Ga). In some embodiments, the p-type dopant source may be a trivalent element or compound, such as boron or a boron-containing compound, such as boron tribromide or diborane.

[0121] In some embodiments, the first doped source layer may be boron-silicate glass (BSG).

[0122] For example, oxygen is introduced and the temperature is raised while depositing the first doping source on the surface of the second polysilicon layer 114, so that the first doping element in the first doping source is pushed into the first polysilicon layer 113 and the second polysilicon layer 114 to obtain the first semiconductor doped film 115.

[0123] In some embodiments, the thickness of the first doped source layer is 10nm to 100nm, such as 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm or 100nm.

[0124] In some embodiments, the first polysilicon layer 113 and the second polysilicon layer 114 need to be annealed before the doping process.

[0125] Because LPCVD deposition occurs at relatively low temperatures, the resulting first polycrystalline silicon layer 113 and second polycrystalline silicon layer 114 may contain amorphous or microcrystalline components, resulting in limited crystallinity, poor conductivity, and hindering the activation of subsequent doping elements. High-temperature annealing promotes solid-state crystallization of amorphous silicon, transforming it into a polycrystalline silicon structure with high crystallinity. This effectively improves the crystallinity of the first polycrystalline silicon layer 113 and second polycrystalline silicon layer 114, enhancing their conductivity and doping activity.

[0126] refer to Figure 7 Remove the first semiconductor doped film 115 from the second region II, and the remaining first semiconductor doped film 115 serves as the first semiconductor doped layer 116.

[0127] In some embodiments, a laser etching process is used to remove the first semiconductor doped film 115 in the second region II, while retaining the first semiconductor doped film 115 in the first region I as the first semiconductor doped layer 116.

[0128] In other embodiments, the first semiconductor doped film 115 of the second region II can also be removed by photolithography combined with dry or wet etching, inkjet printing etching solution, mechanical mask-assisted plasma etching, or other methods.

[0129] The first semiconductor doped layer 116 is used to form an electrical contact with the first electrode to achieve selective collection of charge carriers. Since the portion of the first semiconductor doped layer 116 near the substrate 100 is composed of a first polysilicon layer 113, which has high density, the interface performance between the first semiconductor doped layer and the tunneling layer is good, which is beneficial to improving surface passivation performance and effectively suppressing carrier recombination. The portion of the first semiconductor doped layer 116 away from the substrate 100 is composed of a second polysilicon layer 114, which has poor density. Therefore, the portion of the first semiconductor doped layer away from the substrate 100 is relatively loose, making it easier for the electrode material to penetrate into the first semiconductor doped layer 116 when forming the first electrode. This increases the contact area between the first electrode and the first semiconductor doped layer 116, effectively reducing the contact resistance between the first electrode and the first semiconductor doped layer 116 and improving the carrier collection efficiency.

[0130] like Figure 7 As shown, the first semiconductor doped layer 116 includes a first semiconductor doped portion 1161 and a second semiconductor doped portion 1162 arranged sequentially from bottom to top. The density of the first semiconductor doped portion 1161 is greater than the density of the second semiconductor doped portion 1162.

[0131] The first semiconductor doped portion 1161 is formed by doping the first polycrystalline silicon layer 113. The first semiconductor doped portion 1161 has a dense structure and good crystal quality, and can form a high-quality interface with the underlying tunneling layer 112, effectively reducing the interface state density and suppressing the recombination of charge carriers at the interface, thereby achieving excellent surface passivation effect.

[0132] The second semiconductor doped portion 1162 is formed by doping the second polysilicon layer 114. The structure of the second semiconductor doped portion 1162 is relatively loose and has a high porosity. When the first electrode is formed subsequently, it is beneficial for the electrode material to penetrate the second semiconductor doped portion 1162 and enter the interior of the first semiconductor doped layer 116 during the sintering process, which significantly increases the effective contact area between the first electrode and the first semiconductor doped layer 116, thereby helping to reduce the contact resistance and improve the carrier collection efficiency.

[0133] In some embodiments, the doping concentration of the first semiconductor doped portion 1161 is greater than the doping concentration of the second semiconductor doped portion 1162.

[0134] Since the first semiconductor doped portion 1161 is located near the tunneling layer 112, its high doping characteristics can, on the one hand, enhance field-effect passivation, effectively repel minority carriers, reduce interface recombination, and improve surface passivation performance; on the other hand, the dense structure formed by high doping has stronger corrosion resistance, which can resist the erosion of glass frit during the subsequent sintering of the first electrode, preventing the "burn-through" phenomenon caused by the first electrode penetrating the first semiconductor doped layer 116, and ensuring the integrity of the passivation structure. While the second semiconductor doped portion 1162 serves as a contact layer, its loose structure, although relatively low in doping concentration, can still effectively promote the penetration of the first electrode slurry, achieving good ohmic contact. This doping gradient design can balance passivation reliability and contact stability, which is beneficial to improving the overall performance and yield of the back contact battery.

[0135] It should be noted that in other embodiments, the first electrode can also make electrical contact with the first semiconductor doped portion 1161. Specifically, during sintering, the first electrode penetrates the loosely structured second semiconductor doped portion 1162 and forms an ohmic contact with the underlying highly doped and densely structured first semiconductor doped portion 1161. This design guides metal penetration through the loosely structured second semiconductor doped portion 1162, increasing the effective contact area, while utilizing the high doping characteristics of the first semiconductor doped portion 1161 to reduce the contact barrier, which helps to achieve a low-resistance electrical connection. During this process, it is necessary to precisely control the sintering process parameters (such as temperature and time) and the thickness of each layer to prevent excessive corrosion of the first electrode from penetrating the first semiconductor doped portion 1161 and destroying the tunneling layer 112 below it, i.e., to avoid the "burn-through" phenomenon, so as to ensure that the surface passivation performance is not affected, and to balance electrical contact performance and device reliability.

[0136] refer to Figures 8 to 9 A second semiconductor doped layer 117 is formed on the second region II, and the second semiconductor doped layer 117 is insulated from the first semiconductor doped layer 116.

[0137] Specifically, refer to Figure 8 A third polycrystalline silicon layer 107 is formed on the surface of the tunneling layer 112 located in the second region II using a third deposition process.

[0138] refer to Figure 9 The third polysilicon layer 107 is doped to transform it into a second semiconductor doped layer 117.

[0139] In some embodiments, the third deposition process can be LPCVD technology.

[0140] The deposition parameters of the third deposition process can be the same as those of the first deposition process. For example, the deposition temperature and deposition pressure of the third deposition process can be the same as those of the first deposition process. This design facilitates the formation of a dense, high-quality third polycrystalline silicon layer 107 on the surface of the tunneling layer in the second region II, ensuring excellent interface passivation performance between it and the tunneling layer. Following N-type doping, the resulting second semiconductor doped layer 117 exhibits high doping concentration and high activation rate, which not only promotes efficient electron transport but also provides a uniform and stable reaction interface for the subsequent sintering of the second electrode. Combined with the corrosion effect of the second electrode paste during high-temperature sintering, reliable ohmic contacts can be formed in the dense second semiconductor doped layer 117, effectively reducing contact resistance and improving carrier collection efficiency.

[0141] It should be noted that in other embodiments, the second deposition process can also be a method such as PECVD technology and APCVD technology.

[0142] In some embodiments, the third polysilicon layer 107 is doped to transform the third polysilicon layer 107 into a second semiconductor doped layer 117, including: forming a second doping source layer on the surface of the third polysilicon layer 107, the second doping source layer containing a second doping element.

[0143] In some embodiments, the second dopant element may be an N-type dopant element. In some embodiments, the N-type dopant source may be a pentavalent element or a compound, such as phosphorus or a phosphorus-containing compound, such as phosphorus trichloride.

[0144] In some embodiments, the second doped source layer may be phospho-silicate glass (PSG).

[0145] It should be noted that after the doping process, the second doping source layer and the first doping source layer need to be removed to ensure that the subsequently formed electrode can directly contact the first semiconductor doped layer and the second semiconductor doped layer, thereby forming a good ohmic contact.

[0146] refer to Figure 10In some embodiments, the first doped source layer located on the surface of the first semiconductor doped layer 116 and the second doped source layer located on the second semiconductor doped layer 117 can be removed by laser irradiation. During the removal of the second and first doped source layers, the scanning path of the laser beam partially overlaps between the first region I and the second region II, thus forming an isolation structure, namely, a spacer region III, in the overlapping irradiation area. This spacer region III physically separates the first semiconductor doped layer 116 and the second semiconductor doped layer 117, effectively preventing leakage caused by conductive connection between the two, thereby improving the insulation reliability and overall conversion efficiency of the battery.

[0147] In some embodiments, the width of the spacer region III is 10 μm to 100 μm.

[0148] If the first semiconductor doped film 115 of the second region II is removed at the same time as the tunneling layer 112 of the second region II, a tunneling layer needs to be formed on the second region II before the second semiconductor doped layer 117 is formed on the second region II.

[0149] refer to Figure 10 A first electrode 118 and a second electrode 119 are formed. The first electrode 118 is in electrical contact with the first semiconductor doped layer 116, and the second electrode 119 is in electrical contact with the second semiconductor doped layer 117.

[0150] The conductivity type of the first semiconductor doped layer 116 is opposite to that of the second semiconductor doped layer 117.

[0151] In some embodiments, the method of forming the first electrode 118 and the second electrode 119 may include: printing a metal paste onto the surfaces of the first semiconductor doped layer 116 and the second semiconductor doped layer 117 using a screen printing process. In some embodiments, the metal paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel.

[0152] In some embodiments, the metal paste is sintered using a sintering process. The metal paste contains highly corrosive components such as glass. During sintering, these corrosive components will erode a portion of the first semiconductor doped layer 116, allowing the metal paste to penetrate into that portion. This allows the metal paste to burn through the first semiconductor doped layer 116 from the side away from the substrate 100 into a portion of the first semiconductor doped layer 116, forming the first electrode 118.

[0153] In some embodiments, the process for forming the second electrode 119 may be the same as the process for forming the first electrode 118, as described above in the method for forming the first electrode 118.

[0154] In some embodiments, converting the first polysilicon layer 113 and the second polysilicon layer 114 into a first semiconductor doped film 115 includes: converting the first polysilicon layer 113 into a first doped portion; converting the second polysilicon layer 114 into a second doped portion; after removing the first semiconductor doped film 115 in the second region, the remaining first doped portion serves as a first semiconductor doped portion 1161, and the remaining second doped portion serves as a second semiconductor doped portion 1162, wherein the first semiconductor doped portion 1161 and the second semiconductor doped portion 1162 constitute a first semiconductor doped layer 116; wherein the first electrode 118 is in electrical contact with the second semiconductor doped portion 1162.

[0155] In some embodiments, the first polysilicon layer 113 and the second polysilicon layer 114 can be doped as a whole by a doping process to form a first doped portion and a second doped portion, respectively. The first doped portion and the second doped portion together constitute a first semiconductor doped film 115, and the first semiconductor doped film 115 continuously covers the surface of the tunneling layer 112.

[0156] The first semiconductor doped layer 116 is located only in the first region, including a first semiconductor doped portion 1161 located on the surface of the tunneling layer and a second semiconductor doped portion 1162 located on the surface of the first semiconductor doped portion 1161. The density of the first semiconductor doped portion 1161 is greater than the density of the second semiconductor doped portion 1162.

[0157] The second semiconductor doped portion 1162 has a loose porous structure, which is beneficial for the penetration of the metal electrode and the formation of three-dimensional contact. When the first electrode 118 is subsequently formed, the first electrode 118 mainly makes electrical contact with the second semiconductor doped portion 1162, which helps to reduce contact resistance and improve carrier collection efficiency.

[0158] In some embodiments, the doping concentration of the first semiconductor doped portion 1161 is different from the doping concentration of the second semiconductor doped layer 117, and the doping concentration of the second semiconductor doped portion 1162 is different from the doping concentration of the second semiconductor doped layer 117.

[0159] refer to Figure 11 In some embodiments, before forming the first electrode 118 and the second electrode 119, the manufacturing method further includes forming a functional layer 120 on the surface of the first semiconductor doped layer 116 and the surface of the second semiconductor doped layer 117.

[0160] In some embodiments, the method of forming the functional layer 120 may include forming the functional layer 120 on the surfaces of the first semiconductor doped layer 116 and the second semiconductor doped layer 117 using the PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

[0161] In some embodiments, a functional layer 120 is formed on the first surface 101 in the same process step.

[0162] In some embodiments, the functional layer 120 includes a passivation layer 121 and an antireflection layer 122, wherein the antireflection layer 122 is located on the surface of the passivation layer 121.

[0163] Optionally, an aluminum oxide layer is deposited on the surfaces of the first semiconductor doped layer, the second semiconductor doped layer, and the second surface using atomic layer deposition (ALD) technology, serving as a passivation layer 121. Passivation layer 121 significantly reduces the surface recombination rate and improves the open-circuit voltage of the back contact cell. Furthermore, a silicon nitride or silicon oxynitride layer is deposited on passivation layer 121 using PECVD technology, serving as an antireflection layer 122. Antireflection layer 122 reduces light reflection loss and increases light absorption efficiency by optimizing its thickness and refractive index. In addition, passivation layer 121 and antireflection layer 122 provide further surface passivation effects, further improving the overall performance of the back contact cell.

[0164] refer to Figure 12 In some embodiments, before forming the functional layer 120, the manufacturing method further includes texturing the substrate 100 to form a textured structure on the first surface 101 and the spacer region III. In some embodiments, a solution texturing method can be used to manufacture the textured structure. The textured structure can increase the number of refractions of light on the surface of the solar cell, which is beneficial to the absorption of light by the solar cell, so as to maximize the utilization rate of solar energy by the cell. For example, if the substrate 100 is monocrystalline silicon, a mixed solution of alkaline solution and alcohol solution can be used to texturize the surface of the substrate 100; if the substrate 100 is polycrystalline silicon, an acid solution can be used to texturize the surface of the substrate 100.

[0165] In some embodiments, the textured surface structure can be manufactured using laser texturing or reactive ion etching (RIE) texturing processes.

[0166] It is worth noting that the back contact battery prepared by the manufacturing method provided in this disclosure exhibits superior electrical characteristics compared to traditional single-layer polycrystalline silicon battery: the series resistance (Rs) is significantly reduced and the open-circuit voltage (Uoc) is improved, indicating that the structure has significant advantages in passivation performance and electrical contact performance.

[0167] This disclosure discloses a multilayered polycrystalline silicon structure by controlling deposition process parameters in stages. First, a dense first polycrystalline silicon layer is deposited under relatively high deposition temperature and pressure to optimize the interface quality between the tunneling layer and the polycrystalline silicon, effectively reducing the interface state density and improving surface passivation performance. Subsequently, a porous second polycrystalline silicon layer is deposited under lower deposition temperature and pressure. Based on this, a first semiconductor doped layer is formed through doping. The upper region of this first semiconductor doped layer is derived from the porous second polycrystalline silicon layer, exhibiting a porous structure and high porosity. During the subsequent formation of the first electrode, the first electrode material can more easily penetrate this region during sintering, reaching deep into the first semiconductor doped layer. This significantly increases the effective contact area between the first electrode and the first semiconductor doped layer, thereby effectively reducing contact resistance and improving carrier collection efficiency. Meanwhile, by rationally controlling the temperature, pressure, and other parameters of the first and second deposition processes, it is not only beneficial to form a dense, high-quality first polysilicon layer that meets the stringent requirements of efficient passivation contacts for interface performance, but also to construct a porous, loosely structured second polysilicon layer, achieving an electrical contact structure with low contact resistance. Furthermore, by optimizing the thickness ratio of the first and second polysilicon layers, while simultaneously and synergistically improving passivation and electrical contact performance, it avoids the increased thermal budget and internal stress accumulation problems caused by an excessively thick first polysilicon layer. This helps reduce process costs and improve device reliability, production yield, and mass production stability.

[0168] Accordingly, another embodiment of this disclosure also provides a back contact battery, which can be manufactured by the manufacturing method of the back contact battery provided in the above embodiments. The back contact battery provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions of the foregoing embodiments; detailed descriptions will not be repeated below.

[0169] refer to Figure 10 The back contact battery provided in this embodiment includes: a substrate 100, a tunneling layer 112, a first semiconductor doped layer 116, a second semiconductor doped layer 117, a first electrode 118, and a second electrode 119.

[0170] The substrate 100 has a first surface 101 and a second surface 102 opposite to each other, the second surface 102 including an alternating first region I and a second region II.

[0171] In some embodiments, if the back contact battery is a single-sided battery, then the first surface 101 of the substrate 100 serves as the light-receiving surface for receiving incident light, and the second surface 102 of the substrate 100 serves as the back-lighting surface.

[0172] For those skilled in the art, the second surface 102 can be divided into a first region I and a second region II, wherein the first region I is generally used to refer to the relative region in which the first semiconductor doped layer is formed in a subsequent doping process, and the second region II is generally used to refer to the relative region in which the second semiconductor doped layer is formed in a subsequent doping process.

[0173] The tunnel layer 112 is located on the second surface 102.

[0174] In some embodiments, the material of the tunneling layer 112 may include at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polycrystalline silicon.

[0175] The first semiconductor doped layer 116 is located on the tunneling layer 112 corresponding to the first region I, and the first semiconductor doped layer 116 includes a first semiconductor doped portion 1161 located on the surface of the tunneling layer 112 and a second semiconductor doped portion 1162 located on the surface of the first semiconductor doped portion 1161. The density of the first semiconductor doped portion 1161 is greater than the density of the second semiconductor doped portion 1162.

[0176] For example, the first semiconductor doped portion 1161 is a dense structure located on the tunneling layer 112 corresponding to the first region I, which is beneficial to forming a high-quality tunneling layer / polysilicon interface, effectively reducing the interface state density, improving the surface passivation performance, and suppressing carrier recombination.

[0177] The second semiconductor doped portion 1162 has a loose structure and is used for electrical contact with the metal electrode. It can significantly increase the contact area between the polysilicon layer and the metal electrode, promote metal penetration and uniform contact, thereby effectively reducing contact resistance and improving carrier collection efficiency.

[0178] The second semiconductor doped layer 117 is located on the tunneling layer 112 corresponding to the second region II, and the second semiconductor doped layer 117 is insulated from the first semiconductor doped layer 116.

[0179] The conductivity type of the first semiconductor doped layer 116 is opposite to that of the second semiconductor doped layer 117.

[0180] The first electrode 118 is in electrical contact with the second semiconductor doped portion 1162, and the second electrode 119 is in electrical contact with the second semiconductor doped layer 117.

[0181] It should be noted that in some embodiments, a spacer region III is provided between the first region I and the second region II, and the width of the spacer region III is 10μm to 100μm. The spacer region III can isolate the first semiconductor doped layer 116 and the second semiconductor doped layer 117, avoiding leakage current and affecting battery efficiency.

[0182] The second semiconductor doped portion 1162 has a loose porous structure, which is beneficial for the penetration of the metal electrode and the formation of three-dimensional contacts. The first electrode 118 is in electrical contact with the second semiconductor doped portion 1162, which helps to reduce contact resistance and improve carrier collection efficiency.

[0183] In some embodiments, the thickness of the first semiconductor doped portion 1161 is less than the thickness of the second semiconductor doped portion 1162.

[0184] The first semiconductor doped portion 1161 is located on the surface of the tunneling layer 112. Its core function is to form a high-quality interface with the tunneling layer 112, thereby achieving excellent surface passivation and suppressing carrier recombination. Since the passivation effect mainly depends on the interface quality rather than the film thickness, a moderate thickness is sufficient to meet the performance requirements.

[0185] The second semiconductor doped part 1162 serves as a conductive channel. By employing a thicker film layer, it can enhance the lateral collection capability of charge carriers, thereby optimizing the overall electrical performance.

[0186] It should be noted that in other embodiments, the thickness of the first semiconductor doped portion 1161 and the thickness of the second semiconductor doped portion 1162 may also be the same.

[0187] In some embodiments, the thickness ratio of the first semiconductor doped portion 1161 to the thickness ratio of the second semiconductor doped portion 1162 is 1:3 to 1:2, for example, it can be 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, 0.41, 0.42, 0.43, 0.44, 0.45, 0.46, 0.47, 0.48 or 0.49, etc.

[0188] It is worth noting that the first semiconductor doped layer 116, which is composed of the first semiconductor doped portion 1161 and the second semiconductor doped portion 1162 with this thickness ratio, can take into account passivation performance, electrical contact characteristics and process stability.

[0189] For example, if the thickness of the first semiconductor doped portion 1161 is 100 nm, then the thickness of the second semiconductor doped portion 1162 is 200 nm to 300 nm.

[0190] In some embodiments, the doping concentration of the first semiconductor doped portion 1161 is greater than the doping concentration of the second semiconductor doped portion 1162. This doping gradient design can balance passivation reliability and contact stability, which is beneficial to improving the overall performance and yield of the back contact battery.

[0191] In some embodiments, the dopant ions of the first semiconductor doped layer are P-type ions, such as boron (B), aluminum (Al) or gallium (Ga), and the dopant ions of the second semiconductor doped layer are N-type ions.

[0192] refer to Figure 11 In some embodiments, the back contact battery further includes a functional layer 120. The functional layer 120 is located on the surface of the first semiconductor doped layer 116 and the surface of the second semiconductor doped layer 117.

[0193] In some embodiments, the functional layer 120 includes a passivation layer 121 and an antireflection layer 122, wherein the antireflection layer 122 is located on the surface of the passivation layer 121.

[0194] The passivation layer 121 can significantly reduce the surface recombination rate and improve the open-circuit voltage of the back contact battery. The passivation layer 121 may include a single-layer film structure or a stacked film structure, and the material of the passivation layer 121 may be any one or more of the following materials: silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, titanium oxide, hafnium oxide, or aluminum oxide.

[0195] The antireflection layer 122, by optimizing its thickness and refractive index, can reduce light reflection loss and increase light absorption efficiency. The material of the antireflection layer 122 can be any one or more of silicon nitride or silicon oxynitride.

[0196] In some embodiments, the functional layer 120 is also located on the first surface 101 and the spacer region III.

[0197] refer to Figure 12 In some embodiments, the first surface 101 and the substrate located in the interval region III can be a velvety structure.

[0198] According to some embodiments of this disclosure, another aspect of this disclosure provides a stacked battery, including the back contact battery as described in the above embodiments. The stacked battery provided in yet another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions of the foregoing embodiments; detailed descriptions will not be repeated below.

[0199] Figure 13 This is a partial cross-sectional structural diagram of a stacked battery provided in an embodiment of this disclosure.

[0200] refer to Figure 13 The tandem solar cell 10 includes a bottom cell 20 and a perovskite cell 30.

[0201] The bottom battery 20 is a back contact battery as described in the above embodiment.

[0202] The perovskite solar cell 30 is located on one side of the bottom cell 20.

[0203] In some embodiments, an intermediate layer may be included between the bottom cell 20 and the perovskite cell 30, and the charge carriers in the bottom cell 20 and the perovskite cell 30 are connected in series through recombination in the intermediate layer. The intermediate layer may be a transparent conductive layer.

[0204] According to some embodiments of this disclosure, another aspect of this disclosure also provides a photovoltaic module, which is formed by connecting multiple back contact cells provided in the foregoing embodiments, or by connecting multiple back contact cells formed by the manufacturing method of the foregoing embodiments, or by connecting multiple stacked cells provided in the foregoing embodiments. The following will describe in detail another embodiment of the photovoltaic module provided by this disclosure with reference to the accompanying drawings. For parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding descriptions of the foregoing embodiments, which will not be repeated in detail below.

[0205] Figure 14 This is a partial three-dimensional structural diagram of a photovoltaic module provided in an embodiment of the present disclosure; Figure 15 for Figure 14 A partial cross-sectional schematic diagram along the cross-sectional direction AA1.

[0206] refer to Figure 14 and Figure 15 The photovoltaic module provided in this embodiment includes: a battery string, an encapsulating film 41, and a cover plate 42.

[0207] The battery string is formed by connecting multiple back contact batteries 40 provided in the foregoing embodiments, or by connecting multiple back contact batteries 40 formed by the manufacturing method of the back contact batteries provided in the foregoing embodiments, or by connecting multiple stacked batteries provided in the foregoing embodiments.

[0208] The encapsulating film 41 is used to cover the surface of the battery string.

[0209] Cover plate 42 is used to cover the surface of the encapsulating film away from the battery string.

[0210] The photovoltaic module also includes a solder ribbon 43, which is electrically connected to at least two back contact cells 40 to connect adjacent back contact cells 40 in series.

[0211] In some embodiments, the encapsulating film 41 includes a first encapsulating layer and a second encapsulating layer. The first encapsulating layer covers one of the front or back sides of the solar cell, and the second encapsulating layer covers the other of the front or back sides of the solar cell. Specifically, at least one of the first or second encapsulating layer can be an organic encapsulating film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyvinyl octene elastomer (POE) film, or polyethylene terephthalate (PET) film. Alternatively, at least one of the first or second encapsulating layer can also be an EP film, an EPE film, or a PVP film. Here, EP film refers to a co-extruded film composed of stacked EVA film and POE film; EPE film refers to a co-extruded film formed by sequentially stacking EVA film + POE film + EVA film; and PVP film refers to a co-extruded film formed by stacking POE film + EVA film + POE film. Co-extruded films can be manufactured by sequentially extruding one or more raw materials onto another pre-made film during the film processing, or by bonding different types of pre-made films together.

[0212] In some cases, the first encapsulation layer and the second encapsulation layer still have a boundary line before lamination. After lamination, the photovoltaic module will no longer have the concept of a first encapsulation layer and a second encapsulation layer. That is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0213] In some embodiments, the cover plate 42 can be a glass cover plate, a plastic cover plate, or other cover plate with light-transmitting function. Specifically, the surface of the cover plate 42 facing the encapsulating film 41 can be an uneven surface or a textured surface containing multiple raised structures, thereby increasing the utilization rate of incident light. The cover plate 42 includes a first cover plate and a second cover plate, the first cover plate being opposite to the first encapsulation layer, and the second cover plate being opposite to the second encapsulation layer.

[0214] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for manufacturing a back-contact battery, characterized in that, include: A substrate is provided, the substrate having opposing first and second surfaces, the second surface comprising alternating first and second regions; A tunneling layer is formed on the second surface; A first polycrystalline silicon layer is formed on the surface of the tunneling layer using a first deposition process. A second polycrystalline silicon layer is formed on the surface of the first polycrystalline silicon layer using a second deposition process; wherein, the first deposition temperature of the first deposition process is higher than the second deposition temperature of the second deposition process, and the first deposition pressure of the first deposition process is higher than the second deposition pressure of the second deposition process. Doping is performed to convert the first polysilicon layer and the second polysilicon layer into a first semiconductor doped film; Remove the first semiconductor doped film from the second region, and the remaining first semiconductor doped film serves as the first semiconductor doped layer; A second semiconductor doped layer is formed on the second region; A first electrode and a second electrode are formed, wherein the first electrode is in electrical contact with the first semiconductor doped layer, and the second electrode is in electrical contact with the second semiconductor doped layer.

2. The method for manufacturing a back contact battery according to claim 1, characterized in that, The difference between the first deposition temperature and the second deposition temperature is in the range of 20°C to 50°C; and / or, the difference between the first deposition pressure and the second deposition pressure is in the range of 150 mBar to 300 mBar.

3. The method for manufacturing a back contact battery according to claim 1 or 2, characterized in that, The process parameters for the first deposition process include: The first deposition pressure is 350 mBar to 500 mBar, the first deposition temperature is 570℃ to 600℃, and the deposition time is 1000 s to 2000 s.

4. The method for manufacturing a back contact battery according to claim 3, characterized in that, The process parameters for the second deposition process include: The second deposition pressure is 200 mBar to 350 mBar, the second deposition temperature is 550℃ to 570℃, and the deposition time is 3000 s to 5000 s.

5. The method for manufacturing a back contact battery according to claim 1, characterized in that, The thickness of the first polycrystalline silicon layer is less than the thickness of the second polycrystalline silicon layer.

6. The method for manufacturing a back contact battery according to claim 5, characterized in that, The ratio of the thickness of the first polycrystalline silicon layer to the thickness of the second polycrystalline silicon layer is 1:3 to 1:

2.

7. The method for manufacturing a back contact battery according to claim 1, characterized in that, Converting the first polysilicon layer and the second polysilicon layer into a first semiconductor doped film includes: The first polycrystalline silicon layer is converted into a first doped portion; The second polycrystalline silicon layer is converted into a second doped portion; After removing the first semiconductor doped film in the second region, the remaining first doped portion serves as the first semiconductor doped portion, and the remaining second doped portion serves as the second semiconductor doped portion. The first semiconductor doped portion and the second semiconductor doped portion constitute the first semiconductor doped layer. The first electrode is in electrical contact with the second semiconductor doped portion.

8. The method for manufacturing a back contact battery according to claim 7, characterized in that, The doping concentration of the first semiconductor doped portion is greater than the doping concentration of the second semiconductor doped portion.

9. A back-contact battery, characterized in that, include: A substrate having opposing first and second surfaces, the second surface comprising alternating first and second regions; A tunneling layer located on the second surface; A first semiconductor doped layer is located on the tunneling layer corresponding to the first region, and the first semiconductor doped layer includes a first semiconductor doped portion located on the surface of the tunneling layer and a second semiconductor doped portion located on the surface of the first semiconductor doped portion, wherein the density of the first semiconductor doped portion is greater than the density of the second semiconductor doped portion. A second semiconductor doped layer is located on the tunneling layer corresponding to the second region; A first electrode and a second electrode, wherein the first electrode is in electrical contact with the second semiconductor doped portion and the second electrode is in electrical contact with the second semiconductor doped layer.

10. The back contact battery according to claim 9, characterized in that, The thickness of the first semiconductor doped portion is less than the thickness of the second semiconductor doped portion.

11. The back contact battery according to claim 10, characterized in that, The thickness ratio of the first semiconductor doped portion to the thickness of the second semiconductor doped portion is 1:3 to 1:

2.

12. The back contact battery according to claim 9, characterized in that, The doping concentration of the first semiconductor doped portion is greater than the doping concentration of the second semiconductor doped portion.

13. The back contact battery according to claim 9, characterized in that, The doped ions of the first semiconductor doped layer are P-type ions, and the doped ions of the second semiconductor doped layer are N-type ions.

14. A stacked battery, characterized in that, include: The bottom battery is a back contact battery as described in any one of claims 9 to 13; A perovskite solar cell, wherein the perovskite solar cell is located on one side of the bottom solar cell.

15. A photovoltaic module, characterized in that, include: The battery string is formed by connecting multiple back contact batteries formed by the manufacturing method of the back contact battery as described in any one of claims 1 to 8, or by connecting multiple back contact batteries as described in any one of claims 9 to 13, or by connecting multiple stacked batteries as described in claim 14. An encapsulating film is used to cover the surface of the battery string; A cover plate is used to cover the surface of the encapsulating film that faces away from the battery string.

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