Perovskite crystalline silicon tandem cell and manufacturing method thereof, photovoltaic module and photovoltaic system

Abstract

The application relates to the technical field of batteries, and discloses a perovskite crystalline silicon laminated battery, a manufacturing method thereof, a photovoltaic module and a photovoltaic system. The manufacturing method of the perovskite crystalline silicon laminated battery comprises the following steps: providing a silicon substrate, wherein the silicon substrate comprises a first surface and a second surface arranged oppositely; manufacturing a P-type doped layer and a first electrode layer which are arranged in sequence and stacked on the first surface of the silicon substrate; and manufacturing an N-type doped layer, a tunneling layer, a hole transport layer, a perovskite layer, an electron transport layer, a buffer layer, a second electrode layer and an anti-reflection layer which are arranged in sequence and stacked on the second surface of the silicon substrate; wherein the buffer layer is manufactured by adopting a plasma enhanced atomic layer deposition method to form the buffer layer on the side of the electron transport layer away from the perovskite layer. The technical scheme provided by the application can improve the long-term stability of the perovskite crystalline silicon laminated battery.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of batteries, in particular to a perovskite crystalline silicon tandem battery, a manufacturing method thereof, a photovoltaic module and a photovoltaic system. BACKGROUND

[0002] The perovskite crystalline silicon tandem battery is a new type of photovoltaic device composed of a perovskite battery and a crystalline silicon battery. This battery can utilize the complementary absorption characteristics of perovskite materials and crystalline silicon materials for different wavelengths of sunlight to achieve efficient segmented utilization of the solar spectrum, thereby breaking through the theoretical efficiency limit of traditional single-crystal silicon batteries and achieving higher photoelectric conversion efficiency.

[0003] However, the long-term stability of the battery is not as good as that of mature crystalline silicon batteries. Insufficient stability can cause the photoelectric conversion efficiency of the battery to decay rapidly over time, seriously affecting the performance and actual service life of the battery. SUMMARY

[0004] The purpose of the present application is to provide a perovskite crystalline silicon tandem battery, a manufacturing method thereof, a photovoltaic module and a photovoltaic system for improving the long-term stability of the perovskite crystalline silicon tandem battery.

[0005] An embodiment of the first aspect of the present application provides a manufacturing method of a perovskite crystalline silicon tandem battery, comprising: providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged oppositely; manufacturing a P-type doped layer, a first electrode layer arranged in sequence and stacked on the first surface of the silicon substrate; manufacturing an N-type doped layer, a tunneling layer, a hole transport layer, a perovskite layer, an electron transport layer, a buffer layer, a second electrode layer and an anti-reflection layer arranged in sequence and stacked on the second surface of the silicon substrate; wherein the manufacturing of the buffer layer comprises: forming the buffer layer on the side of the electron transport layer away from the perovskite layer by using a plasma-enhanced atomic layer deposition method.

[0006] The manufacturing method provided by the embodiment of the present application uses the plasma-enhanced atomic layer deposition method to manufacture the buffer layer. This process can achieve high-density growth of the buffer layer under low-temperature conditions and significantly reduce the defect density of the buffer layer. The buffer layer prepared in this way can meet the design requirements of the perovskite crystalline silicon tandem battery in terms of low-temperature compatibility, interface stability and efficient transmission, thereby the scheme can significantly improve the long-term stability and reliability of the perovskite crystalline silicon tandem battery.

[0007] In some embodiments, the buffer layer is formed on the side of the electron transport layer away from the perovskite layer by using the plasma-enhanced atomic layer deposition method, comprising: depositing a SnO2 film on the side of the electron transport layer away from the perovskite layer by using an atomic layer deposition device; and performing surface modification on the SnO2 film by using a plasma generation device, wherein the working gas in the plasma generation device comprises argon and oxygen.

[0008] In some embodiments, the plasma generation device comprises a magnetron sputtering device.

[0009] In some embodiments, the power of the magnetron sputtering device is 30W-300W, and / or the flow rate of the working gas in the magnetron sputtering device is 5sccm-50sccm, and / or the flow rate ratio of argon and oxygen is 280:1-1:1, and / or the chamber substrate heating temperature of the magnetron sputtering device is 25℃-80℃, and / or the working time of the magnetron sputtering device is 1min-30min.

[0010] In some embodiments, the deposition vacuum degree of the atomic layer deposition device is 0-1x10 4 Pa, and / or the deposition pipe temperature of the atomic layer deposition device is 50℃-150℃, and / or the deposition chamber temperature of the atomic layer deposition device is 40℃-150℃.

[0011] In some embodiments, the thickness of the SnO2 thin film is 10nm-20nm.

[0012] In some embodiments, before the P-type doped layer is made, the manufacturing method comprises: making a first passivation layer on the first side of the silicon substrate; and / or, before the N-type doped layer is made, the manufacturing method comprises: making a second passivation layer on the second side of the silicon substrate; and / or, before the electron transport layer is made, the manufacturing method comprises: making a third passivation layer on the side of the perovskite layer away from the silicon substrate.

[0013] Embodiments of the second aspect of the application provide a perovskite crystalline silicon tandem cell, which is made by the manufacturing method of the first aspect.

[0014] The perovskite crystalline silicon tandem cell provided by the embodiments of the application improves the long-term stability and reliability of the cell by using the manufacturing method of the first aspect.

[0015] Embodiments of the third aspect of the application provide a photovoltaic module, comprising a perovskite crystalline silicon tandem cell, which is made by the manufacturing method of the first aspect.

[0016] The photovoltaic module provided by the embodiments of the application improves the long-term stability and reliability of the perovskite crystalline silicon tandem cell and the photovoltaic module comprising the perovskite crystalline silicon tandem cell by using the manufacturing method of the first aspect.

[0017] Embodiments of the fourth aspect of the application provide a photovoltaic system, comprising the photovoltaic module of the third aspect.

[0018] The photovoltaic system provided by the embodiments of the application improves the long-term stability and reliability of the photovoltaic module by using the photovoltaic module of the third aspect. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative effort based on these drawings.

[0020] Figure 1 A structure schematic diagram of a perovskite crystalline silicon tandem cell provided by the embodiments of the present application;

[0021] Figure 2 A flowchart of a manufacturing method of a perovskite crystalline silicon tandem cell provided by the embodiments of the present application;

[0022] Figure 3 A flowchart of a manufacturing method of a perovskite crystalline silicon tandem cell provided by the embodiments of the present application;

[0023] Main element symbol explanation:

[0024] 1000, perovskite crystalline silicon tandem cell;

[0025] 11, first electrode layer; 111, first transparent electrode layer; 112, first metal electrode layer; 12, P-type doped layer; 13, first passivation layer; 14, silicon substrate; 15, second passivation layer; 16, N-type doped layer;

[0026] 21, tunneling layer;

[0027] 31, hole transport layer; 32, perovskite layer; 33, third passivation layer; 34, adhesion layer; 35, electron transport layer; 36, buffer layer; 37, second electrode layer; 371, second transparent electrode layer; 372, second metal electrode layer; 38, anti-reflection layer. DETAILED DESCRIPTION

[0028] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0029] It is to be noted that when a component is referred to as being "fixed" or "set" on another component, it can be directly or indirectly on the other component. When a component is referred to as being "connected" to another component, it can be directly or indirectly connected to the other component. The terms "upper", "lower", "left", "right", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of description, and cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the patent. The terms "first", "second" are only for the convenience of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0030] Reference to "one embodiment", "some embodiments" or "an embodiment" in the present application description means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Therefore, the phrases "in one embodiment", "in some embodiments", "in other some embodiments", "in other some embodiments" and the like appearing in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. In addition, in one or more embodiments, specific features, structures or characteristics can be combined in any suitable manner.

[0031] The instability of perovskite crystalline silicon tandem cells is caused by multiple factors, such as intrinsic defects of perovskite materials, interface compatibility problems between film layers in the device, environmental sensitivity of materials, and the like.

[0032] In a typical tandem cell structure, the perovskite top cell has a buffer layer, and due to the thermal stability limitation of the crystalline silicon bottom cell, the buffer layer must be prepared at low temperature. This temperature window constraint makes the buffer layer unable to form an ordered crystal structure, and can only exist in an amorphous state. The amorphous structure naturally has problems such as high defect density, high surface roughness, and weak chemical stability, which will have a great impact on the long-term stability of the perovskite crystalline silicon tandem cell.

[0033] Based on the above problems, the embodiments of the present application provide a perovskite crystalline silicon tandem cell and a manufacturing method thereof, a photovoltaic module and a photovoltaic system. By optimizing the preparation process of the perovskite crystalline silicon tandem cell, the long-term stability and reliability of the perovskite crystalline silicon tandem cell can be effectively improved.

[0034] In a first aspect, the embodiments of the present application provide a manufacturing method of a perovskite crystalline silicon tandem cell.

[0035] Please refer to Figure 1and Figure 2 The manufacturing method provided by the embodiments of the present application comprises the following steps.

[0036] S100, providing a silicon substrate 14, the silicon substrate 14 comprising a first surface and a second surface arranged oppositely.

[0037] The silicon substrate 14 can be a high-purity single crystal silicon wafer, which is not limited to be P-type doped or N-type doped; the first surface and the second surface of the silicon substrate 14 can be a textured surface.

[0038] The silicon substrate 14 has a certain thickness, which can be used as a support substrate of the perovskite-silicon tandem cell 1000 to provide reliable mechanical support for other functional layers.

[0039] S200, manufacturing a P-type doped layer 12 and a first electrode layer 11 which are arranged in sequence on the first surface of the silicon substrate 14.

[0040] Specifically, the P-type doped layer 12 is manufactured on the first surface of the silicon substrate 14, and the first electrode layer 11 is manufactured on the side of the P-type doped layer 12 away from the silicon substrate 14.

[0041] S300, manufacturing an N-type doped layer 16, a tunneling layer 21, a hole transport layer 31, a perovskite layer 32, an electron transport layer 35, a buffer layer 36, a second electrode layer 37 and an anti-reflection layer 38 which are arranged in sequence on the second surface of the silicon substrate 14. The manufacturing of the buffer layer 36 comprises: forming the buffer layer 36 on the side of the electron transport layer 35 away from the perovskite layer 32 by using a plasma enhanced atomic layer deposition method.

[0042] Specifically, the N-type doped layer 16 is manufactured on the second surface of the silicon substrate 14, the tunneling layer 21 is manufactured on the side of the N-type doped layer 16 away from the silicon substrate 14, the hole transport layer 31 is manufactured on the side of the tunneling layer 21 away from the N-type doped layer 16, the perovskite layer 32 is manufactured on the side of the hole transport layer 31 away from the tunneling layer 21, the electron transport layer 35 is manufactured on the side of the perovskite layer 32 away from the hole transport layer 31, the buffer layer 36 is manufactured on the side of the electron transport layer 35 away from the perovskite layer 32, the second electrode layer 37 is manufactured on the side of the buffer layer 36 away from the electron transport layer 35, and the anti-reflection layer 38 is manufactured on the side of the second electrode layer 37 away from the buffer layer 36.

[0043] The buffer layer 36 is an ultra-thin functional layer arranged between the electron transport layer 35 and the second electrode layer 37, and is mainly used for improving the energy level matching between the upper and lower film layers, reducing the contact barrier, and blocking the diffusion of metal ions of the external electrode layer, etc. The material of the buffer layer 36 can be an organic small molecule, an inorganic compound, etc. The buffer layer 36 is prepared by using a plasma enhanced atomic layer deposition method. Specifically, an ultra-thin film is deposited on the surface of a substrate to be made into the buffer layer 36, and then plasma is introduced to modify the surface, thereby forming the required buffer layer 36.

[0044] On the one hand, the plasma has directionality and high kinetic energy, can bombard the surface of the film, promote the migration and rearrangement of atoms on the surface of the film, and can fill the microporous structure on the surface of the film, thereby effectively improving the density of the buffer layer 36. The improved density of the buffer layer 36 can improve the contact effect between the upper and lower film layers, reduce the risk of film peeling, and effectively block the diffusion of metal ions of the electrode layer to the perovskite layer 32, thereby enhancing the stability of the battery. On the other hand, the high-activity oxide in the plasma can fill the oxygen vacancies on the surface of the film, thereby reducing the defect density of the buffer layer 36. The reduced defect density of the buffer layer 36 can reduce the interface recombination and the contact resistance between the film layers, thereby enhancing the electrical performance of the battery. In addition, the energy of the plasma can promote the transformation of the amorphous film to a nanocrystalline or microcrystalline structure at low temperature, forming nanoscale microcrystalline grains, which can further optimize the optical and electrical performance of the buffer layer 36, thereby improving the photoelectric conversion efficiency of the battery.

[0045] The manufacturing method provided in the embodiments of the present application uses the plasma enhanced atomic layer deposition method to manufacture the buffer layer 36. This process can realize the high-density growth of the buffer layer 36 at low temperature, and significantly reduce the defect density of the buffer layer 36. The buffer layer 36 prepared in this way can meet the design requirements of the perovskite crystalline silicon stacked battery 1000 in terms of low-temperature compatibility, interface stability, and high-efficiency transmission, thereby significantly improving the long-term stability and reliability of the perovskite crystalline silicon stacked battery 1000.

[0046] In some embodiments, referring to Figure 1 , Figure 2 and Figure 3 , in step S300, the buffer layer 36 is formed on the side of the electron transport layer 35 away from the perovskite layer 32 by using the plasma enhanced atomic layer deposition method, including:

[0047] S310, depositing a SnO2 film on the side of the electron transport layer 35 away from the perovskite layer 32 by using an atomic layer deposition device.

[0048] SnO2 is an inorganic oxide material with high electron mobility, high light transmittance and good chemical stability. The buffer layer 36 is designed to be SnO2 material, which can achieve excellent energy level matching and is beneficial to optimize the electron transport performance.

[0049] In S320, the SnO2 thin film is surface-modified by using a plasma generating device. The working gas in the plasma generating device includes argon and oxygen.

[0050] Argon is an inert gas. The Ar⁺ ions generated by ionization have a physical sputtering effect, which can bombard the surface of the SnO2 thin film, promote the displacement and rearrangement of the SnO2 thin film surface atoms and lattices, and thus improve the compactness of the SnO2 thin film.

[0051] Oxygen is used to provide high-activity oxygen free radicals and O⁺ ions to oxidize oxygen vacancies in the SnO2 thin film, thereby reducing n-type doping and defect states of the SnO2 thin film, and improving the insulation (blocking holes) and stability of the SnO2 thin film.

[0052] In the above embodiment, on the one hand, SnO2 is selected as the material of the buffer layer 36, and a mixed gas of argon and oxygen is used for plasma surface modification, which can obtain a buffer layer 36 with high quality, low defects and high stability; on the other hand, the deposition and surface modification of the buffer layer 36 are carried out in two steps, which can independently optimize the deposition parameters and plasma treatment parameters, reduce the mutual interference in the deposition and plasma treatment process, and thus is beneficial to further improve the film quality of the buffer layer 36.

[0053] In some embodiments, the plasma generating device includes a magnetron sputtering device.

[0054] The magnetron sputtering device can generate low-temperature plasma by using electric field, and realize physical and chemical modification of the film surface by bombarding the film surface with charged particles.

[0055] On the one hand, the magnetron sputtering device can generate a relatively high-density plasma with high modification efficiency; on the other hand, the magnetron sputtering device uses electric energy rather than heat energy to treat the plasma, which can realize efficient modification at low temperature and meet the low-temperature process requirements of the perovskite crystalline silicon tandem battery 1000.

[0056] In some embodiments, the power of the magnetron sputtering device is 30W-300W, and / or the flow rate of the working gas in the magnetron sputtering device is 5sccm-50sccm, and / or the flow rate ratio of argon and oxygen is 280:1-1:1, and / or the chamber base heating temperature of the magnetron sputtering device is 25℃-80℃, and / or the working time of the magnetron sputtering device is 1min-30min.

[0057] The power of the magnetron sputtering device directly affects the density and ion energy of the plasma. If the power of the magnetron sputtering device is too low, it may result in insufficient plasma density and weak ion bombardment energy, and the modification effect is not obvious. If the power of the magnetron sputtering device is too high, it may result in too high plasma density and too strong ion bombardment energy, which is easy to cause damage to the film surface. Limiting the power of the magnetron sputtering device to 30W-300W is conducive to improving the surface modification effect of the film and reducing the risk of film damage.

[0058] The flow rate of the working gas refers to the total flow rate of argon and oxygen into the chamber of the magnetron sputtering device. The gas flow rate affects the working gas pressure and the stability of the plasma in the device. If the working gas flow rate is too low, the number of gas molecules is insufficient, which may result in difficulty in maintaining stable discharge of the plasma. If the working gas flow rate is too high, it may result in too high gas pressure in the chamber, shortening the mean free path of ions and reducing the bombardment energy, which affects the modification effect. Limiting the flow rate of the working gas to 5sccm-50sccm is conducive to maintaining a stable working gas pressure and improving the stability and efficiency of surface modification.

[0059] The flow ratio of argon and oxygen refers to the ratio of the volume flow rates of the two. Argon is used to provide physical bombardment, and oxygen is used to provide chemical oxidation. By adjusting the ratio of argon and oxygen, different modification effects can be achieved. Setting the flow ratio of argon and oxygen in a wide range of 280:1-1:1 can cover various modification modes, with high applicability.

[0060] The heating temperature of the chamber substrate is used to control the actual temperature of the substrate on which the buffer layer 36 is to be made. In this embodiment, the substrate includes various functional layers made before the buffer layer 36. If the heating temperature of the chamber substrate is too low, it may result in insufficient reaction dynamics on the film surface, affecting the surface modification efficiency. If the heating temperature of the chamber substrate is too high, it may cause decomposition of some functional layers in the substrate, affecting the product quality of the perovskite / silicon tandem cell 1000. Limiting the heating temperature of the chamber substrate to 25℃-80℃ can meet the low-temperature process requirements of the perovskite / silicon tandem cell 1000, and is also conducive to promoting chemical reactions on the film surface and effectively improving the surface modification efficiency.

[0061] The working time of the magnetron sputtering device determines the time during which the plasma acts on the film. Limiting the working time of the magnetron sputtering device to 1min-30min is conducive to balancing the surface modification effect and production efficiency.

[0062] It should be noted that the setting of each of the above process parameters is related. In actual application, they can be adjusted cooperatively according to the initial state of the SnO2 film to be treated.

[0063] In some embodiments, the deposition vacuum degree of the atomic layer deposition device is 0-1x104 Pa, and / or the deposition pipe temperature of the atomic layer deposition device is 50-150°C, and / or the deposition chamber temperature of the atomic layer deposition device is 40-150°C.

[0064] The deposition vacuum degree of the atomic layer deposition device refers to the working pressure of the reaction chamber. The deposition vacuum degree affects the effect of thin film deposition. Specifically, if the deposition vacuum degree is too large, it may cause uneven thin film deposition or generate particles during the deposition process. The deposition vacuum degree is limited to 0-1x10 4 Pa, the requirements of thin film deposition efficiency and thin film deposition quality can be balanced.

[0065] The deposition pipe of the atomic layer deposition device is used to transport gaseous precursors, and the temperature of the deposition pipe directly affects the transmission state of the precursors. If the deposition pipe temperature is too low, it may cause the precursors to liquefy or crystallize in the pipe, causing pipe blockage; if the deposition pipe temperature is too high, it may cause thermal decomposition of the precursors in the pipe, generating impurity gas and affecting the reliability of subsequent thin film deposition. Limiting the deposition pipe temperature to 50-150°C meets the transportation requirements of various types of precursors, so that the precursors can remain in a stable gaseous state, thereby helping to achieve stable and continuous supply.

[0066] The deposition chamber temperature of the atomic layer deposition device refers to the ambient temperature of the substrate to be made into the buffer layer 36. If the deposition chamber temperature is too low, it may cause slow thin film deposition rate and poor thin film deposition quality; if the chamber temperature is too high, it may cause decomposition of the functional layer inside the substrate, which does not meet the requirements of low-temperature process. Limiting the deposition chamber temperature to 40-150°C can balance the SnO2 thin film deposition rate, deposition effect, and low-temperature process requirements of the perovskite crystalline silicon tandem battery 1000.

[0067] It should be noted that the setting of the above-mentioned process parameters has relevance, and in actual application, they can be adjusted in coordination according to the design requirements of the SnO2 thin film to be processed.

[0068] In some embodiments, the thickness of the SnO2 thin film is 10-20 nm.

[0069] For example, the thickness of the SnO2 thin film can be 10 nm, 15 nm, or 20 nm.

[0070] The buffer layer 36 is mainly used to improve the energy level matching between the upper and lower film layers, reduce the contact barrier, and block the diffusion of metal ions from the outside electrode layer. The thickness of the buffer layer 36 directly affects the film layer quality, metal ion blocking effect, light transmittance, electron transport effect, etc. In the above embodiments, by limiting the thickness of the SnO2 thin film within a reasonable range, the performance requirements of film layer quality, metal blocking, light transmittance, electron transport, etc. can be balanced, thereby facilitating the improvement of the structural reliability of the buffer layer 36.

[0071] In some embodiments, referring to Figure 1 , the first electrode layer 11 includes a first transparent electrode layer 111 and a first metal electrode layer 112, and the first metal electrode layer 112 is arranged on the side of the first transparent electrode layer 111 away from the P-type doped layer 12; the second electrode layer 37 includes a second transparent electrode layer 371 and a second metal electrode layer 372, and the second metal electrode layer 372 is arranged on the side of the second transparent electrode layer 371 away from the buffer layer 36.

[0072] The first transparent electrode layer 111 and the second transparent electrode layer 371 are arranged on the inner side and have good transparency, which can be used to guide the incident light into the battery and transport the photo-generated carriers to the outer metal electrode layer. The materials of the first transparent electrode layer 111 and the second transparent electrode layer 371 can be the same or different, and can be at least one of indium tin oxide, indium zinc oxide, and zinc aluminum oxide, for example. In a specific embodiment, the materials of the first transparent electrode layer 111 and the second transparent electrode layer 371 are both indium tin oxide.

[0073] The first metal electrode layer 112 and the second metal electrode layer 372 are arranged on the outer side and are used to collect and export photo-generated carriers, so that the battery forms a complete closed circuit and generates current. The materials of the first metal electrode layer 112 and the second metal electrode layer 372 can be the same or different, and can be at least one of silver, gold, copper, aluminum, and carbon, for example. In a specific embodiment, the materials of the first metal electrode layer 112 and the second metal electrode layer 372 are both silver.

[0074] In some embodiments, before the P-type doped layer 12 is made, the manufacturing method includes: making a first passivation layer 13 on the first side of the silicon substrate 14; and / or, before the N-type doped layer 16 is made, the manufacturing method includes: making a second passivation layer 15 on the second side of the silicon substrate 14; and / or, before the electron transport layer 35 is made, the manufacturing method includes: making a third passivation layer 33 on the side of the perovskite layer 32 away from the silicon substrate 14.

[0075] The first passivation layer 13 is directly deposited on the first side of the silicon substrate 14, which can passivate the surface defects of the first side of the silicon substrate 14 and provide a good contact interface for the P-type doped layer 12, thereby improving the stability and photoelectric performance of the battery.

[0076] The second passivation layer 15 is directly deposited on the second surface of the silicon substrate 14, which can passivate the surface defects of the second surface of the silicon substrate 14 and provide a good contact interface for the N-type doped layer 16, thereby improving the stability and photoelectric performance of the battery.

[0077] The third passivation layer 33 is directly deposited on the upper surface of the perovskite layer 32, which can passivate the surface defects of the perovskite layer 32 and optimize the energy level matching between the perovskite layer 32 and the electron transport layer 35, thereby improving the stability and photoelectric performance of the battery.

[0078] The manufacturing method provided in the embodiments of the present application mainly improves the preparation process of the buffer layer 36. Specifically, the surface of the buffer layer 36 is modified by introducing plasma, thereby improving the film quality of the buffer layer 36 and further improving the long-term stability and reliability of the battery. The specific preparation process of the buffer layer 36 and the setting of various working parameters in the preparation process are particularly important. The following provides several specific embodiments for explanation and description.

[0079] Embodiment one: The buffer layer 36 is prepared by atomic layer deposition. Specifically, SnO2 film is deposited on the side of the electron transport layer 35 away from the perovskite layer 32 by using an atomic layer deposition device, the deposition vacuum degree is set to 0.5x10 4 Pa, the deposition pipeline temperature is 60℃, the deposition chamber temperature is 70℃, and the film thickness of the SnO2 film is 15nm.

[0080] Embodiment two: The buffer layer 36 is prepared by ion plasma enhanced atomic layer deposition. Specifically, SnO2 film is deposited on the side of the electron transport layer 35 away from the perovskite layer 32 by using an atomic layer deposition device, the deposition vacuum degree is set to 0.5x10 4 Pa, the deposition pipeline temperature is 60℃, the deposition chamber temperature is 70℃, and the film thickness of the SnO2 film is 15nm; the surface of the SnO2 film is modified by using a magnetron sputtering device, the device power is 100W, the working gas is a mixed gas of argon and oxygen, the flow rate of the working gas is 28.1sccm, the flow rate ratio of argon and oxygen is 28:0.1, the chamber base heating temperature is 25℃, and the working time is 10min.

[0081] Embodiment three: The buffer layer 36 is prepared by ion plasma enhanced atomic layer deposition. The difference between this embodiment and embodiment two is that the chamber base heating temperature of the magnetron sputtering device is set to 50℃.

[0082] Embodiment four: The buffer layer 36 is prepared by ion plasma enhanced atomic layer deposition. The difference between this embodiment and embodiment two is that the chamber base heating temperature of the magnetron sputtering device is set to 80℃.

[0083] The defect density, surface roughness and lattice diffraction relative peak intensity of the buffer layer 36 in each of the above embodiments are measured by means of X-ray photoelectron spectroscopy, atomic force microscopy, X-ray diffraction, etc. The test results are as follows:

[0084]

[0085] It can be seen from the comparative example one and the example two, the example three and the example four that the defect density and the surface roughness of the buffer layer 36 can be effectively reduced by using the ion plasm-enhanced atomic layer deposition method to manufacture the buffer layer 36. It can be seen from the comparative example two, the example three and the example four that the defect density and the surface roughness of the buffer layer 36 can be further reduced by increasing the chamber base heating temperature of the magnetron sputtering equipment.

[0086] The photoelectric conversion efficiency and the annual attenuation rate of the perovskite crystalline silicon stacked cell 1000 prepared in each of the above embodiments are measured by using a solar simulator. Specifically, a standard solar intensity calibration is performed, and a long period of IV test is performed on a test object with an area of 1.0 cm 2 The test results are rounded to two decimal places. The test results are as follows:

[0087]

[0088] It can be seen from the comparative example one and the example two, the example three and the example four that the photoelectric conversion efficiency of the perovskite crystalline silicon stacked cell 1000 can be effectively improved and the annual attenuation rate of the cell can be reduced by using the ion plasm-enhanced atomic layer deposition method to manufacture the buffer layer 36. It can be seen from the comparative example two, the example three and the example four that the improvement effect is better when the chamber base heating temperature is set to the intermediate value (for example, 50°C).

[0089] In one specific embodiment provided in the present application, the manufacturing method of the perovskite crystalline silicon stacked cell 1000 includes:

[0090] S1: providing a silicon substrate 14, the silicon substrate 14 including a first surface and a second surface arranged oppositely.

[0091] S2: manufacturing a first passivation layer 13 on the first surface of the silicon substrate 14.

[0092] Without limitation, the first passivation layer 13 can be manufactured by using an evaporation method, a spin coating method or a spraying method.

[0093] S3: manufacturing a P-type doped layer 12 on the side of the first passivation layer 13 away from the silicon substrate 14.

[0094] S4: manufacturing a first transparent electrode layer 111 on the side of the P-type doped layer 12 away from the first passivation layer 13.

[0095] The first transparent electrode layer 111 can be made by magnetron sputtering, with the equipment power limited to 50-200 W.

[0096] For example, the first transparent electrode layer 111 is made by magnetron sputtering: the sample is placed in a magnetron sputtering device, an ITO target is set, the power is controlled to 60 W, the running time is 1.5 h, and the film thickness is 100 nm.

[0097] S5: The first metal electrode layer 112 is made on the side of the first transparent electrode layer 111 away from the P-type doped layer 12.

[0098] The first metal electrode layer 112 can be made by evaporation, with the evaporation vacuum limited to 5×10 -5 Pa-2×10 -4 Pa, the evaporation temperature limited to 500-2000℃, and the evaporation rate limited to 0.1-5 Å / S.

[0099] For example, the first metal electrode layer 112 is made by evaporation: the sample is placed on a mask, put into an evaporation chamber, and evaporated when the evaporation vacuum is 2×10 -4 Pa, the evaporation voltage is adjusted to the evaporation temperature, the evaporation rate is controlled to 2.5 Å / S, silver is evaporated onto the first transparent electrode layer 111, and the silver layer has a thickness of 200 nm.

[0100] S6: The second passivation layer 15 is made on the second side of the silicon substrate 14.

[0101] The second passivation layer 15 can be made by evaporation, spin coating, or spraying.

[0102] S7: The N-type doped layer 16 is made on the side of the second passivation layer 15 away from the silicon substrate 14.

[0103] S8: The tunneling layer 21 is made on the side of the N-type doped layer 16 away from the second passivation layer 15.

[0104] The tunneling layer 21 can be made by atomic layer deposition, magnetron sputtering, or wet chemical method.

[0105] For example, the tunneling layer 21 is made by magnetron sputtering: the sample is placed in a magnetron sputtering device, the power is controlled to 60 W, the running time is 1 h, and the film thickness is 100 nm.

[0106] S9: The hole transport layer 31 is made on the side of the tunneling layer 21 away from the N-type doped layer 16.

[0107] The hole transport layer 31 can be made by magnetron sputtering, with the equipment power limited to 30-90 W.

[0108] For example, the hole transport layer 31 is prepared by a magnetron sputtering method: the sample is treated by an ultraviolet-ozone machine for 15 min, and then placed in a magnetron sputtering device, with a power of 60 W and a running time of 1 h, to prepare a nickel oxide film on the surface of the substrate, with a thickness of 40 nm.

[0109] S10: preparing a perovskite layer 32 on the side of the hole transport layer 31 away from the tunneling layer 21.

[0110] Without limitation, the perovskite layer 32 can be prepared by a flash method or a solution wet method; when the perovskite layer 32 is prepared by the flash method, the perovskite precursor solution is uniformly coated on the surface of the hole transport layer 31, with a spin speed of 1000 rpm-6000 rpm and a spin time of 20 s-120 s, followed by flash operation, with a flash time of 10 s-60 s and a flash temperature of 0-100°C, and then annealing treatment, with an annealing temperature of 50°C-150°C and an annealing time of 5 min-40 min.

[0111] For example, the perovskite layer 32 is prepared by the flash method: the perovskite precursor solution is prepared by weighing perovskite raw material powder dissolved in 1 ml of DMF and DMSO solvents, with a magnetic stirring for 30 min, wherein the solvent ratio is 8:2; the sample is placed on a spin coater base, with a spin speed of 3500 rpm and a spin time of 30 s, and 120 ul of the perovskite precursor solution is coated on the surface of the sample, followed by placing the sample on a flash platform, with a flash time of 30 s and a flash temperature of 30°C, to form a film with a thickness of about 500 nm, and then annealing treatment, with an annealing temperature of 100°C and an annealing time of 15 min.

[0112] S11: preparing a third passivation layer 33 on the side of the perovskite layer 32 away from the hole transport layer 31.

[0113] Without limitation, the third passivation layer 33 can be prepared by an evaporation method, a spin coating method or a spraying method; when the third passivation layer 33 is prepared by the evaporation method, the evaporation vacuum degree is limited to 1 Pa-5x10 -4Pa, the evaporation rate is limited to 0.05 Å / S-1 Å / S, after the evaporation is finished, annealing operation is carried out, the annealing temperature is limited to 0-150℃, and the annealing time is limited to 0-30 min; when the third passivation layer 33 is made by using the spin coating method, the dispersion liquid is uniformly coated on the surface of the substrate, propylene diamine iodine is dissolved in organic solvents such as methanol, ethanol or isopropanol, ultrasonic dissolution and spin coating are carried out, the propylene diamine iodine concentration is limited to 0.1 mg / ml-6 mg / ml, the ultrasonic time is limited to 0-30 min, the spin coating rotation speed is limited to 1000 rpm-7000 rpm, the spin coating time is limited to 20 s-120 s, after the spin coating is finished, annealing operation is carried out, the annealing temperature is limited to 40℃-160℃, and the annealing time is limited to 5 min-40 min; when the third passivation layer 33 is made by using the spraying method, the dispersion liquid is sprayed on the surface of the substrate, the spraying rate is limited to 0-100 cm / s, after the spraying is finished, annealing operation is carried out, the annealing temperature is limited to 20℃-170℃, and the annealing time is limited to 0-30 min.

[0114] For example, the third passivation layer 33 is made by using the evaporation method: 3 mg of propylene diamine iodine is placed in a crucible, a sample is placed on a mask plate, and then the sample is placed in an evaporation chamber of an evaporation machine. When the evaporation vacuum degree is 2×10 -4 Pa, the evaporation temperature is adjusted by adjusting the evaporation voltage, the evaporation rate is controlled to be 0.1 Å / S, the propylene diamine iodine is evaporated on the perovskite absorption layer, the film thickness is 4 nm, after the evaporation is finished, annealing treatment is carried out, the annealing temperature is set to be 100℃, and the annealing time is 8 min.

[0115] S12: An adhesion layer 34 is made on the side of the third passivation layer 33 away from the perovskite layer 32.

[0116] Not limited, the adhesion layer 34 can be made by using the evaporation method, the adhesion layer 34 material is evaporated on the surface of the substrate, the evaporation vacuum degree is limited to 1 Pa-5×10 -4 Pa, the evaporation temperature is limited to 50℃-400℃, the evaporation rate is limited to 0.05 Å / S-1 Å / S, and the film thickness is limited to 1 nm-5 nm.

[0117] S12: An electron transport layer 35 is made on the side of the third passivation layer 33 away from the perovskite layer 32.

[0118] Not limited, the electron transport layer 35 can be made by using the spin coating method, the inkjet method or the evaporation method; when the electron transport layer 35 is made by using the spin coating method, the dispersion liquid is uniformly coated on the surface of the substrate, the spin coating rotation speed is limited to 500 rpm-4000 rpm, and the spin coating time is limited to 10 s-80 s; when the electron transport layer 35 is made by using the evaporation method, the material is evaporated on the surface of the substrate, the evaporation vacuum degree is limited to 5×10 -5 Pa-5×10-4 Pa, the evaporation rate is limited to 0.05 Å / S-1 Å / S.

[0119] For example, the electron transport layer 35 is made by using the evaporation method: the sample is placed on a mask plate and put into the evaporation chamber, and the evaporation is carried out when the evaporation vacuum degree is 1×10 -4 Pa, the evaporation temperature is adjusted to the evaporation voltage, and the evaporation rate is controlled to 0.1 Å / S-0.15 Å / S. C 60 The evaporation is carried out on the third passivation layer 33, and the film thickness is 20 nm.

[0120] S13: A buffer layer 36 is made on the side of the electron transport layer 35 away from the third passivation layer 33.

[0121] For example, the SnO2 film is deposited by using the atomic layer deposition device, the deposition vacuum degree is set to 0.5×10 4 Pa, the deposition pipe temperature is 60℃, the deposition chamber temperature is 70℃, and the SnO2 film thickness is 15 nm; the SnO2 film is surface-modified by using the magnetron sputtering device, the device power is 100W, the working gas is argon and oxygen, the working gas flow is 28.1sccm, the argon and oxygen ratio is 28:0.1, the chamber base temperature is 50℃, and the device working time is 10min.

[0122] S14: A second transparent electrode layer 371 is made on the side of the buffer layer 36 away from the electron transport layer 35.

[0123] Not limited, the second transparent electrode layer 371 can be made by using the magnetron sputtering method and the evaporation method; when the second transparent electrode layer 371 is made by using the magnetron sputtering method, the material is sputtered to the surface of the above-mentioned substrate, and the power is controlled to be limited to 30W-200W; when the second transparent electrode layer 371 is made by using the evaporation method, the material is evaporated to the surface of the substrate, and the evaporation vacuum degree is limited to 1×10 - 5 Pa-5×10 -4 Pa, the evaporation temperature is limited to 1000℃-2000℃, and the evaporation rate is limited to 0.05 Å / S-3 Å / S.

[0124] For example, the second transparent electrode layer 371 is made by using the magnetron sputtering method: the sample is placed in the magnetron sputtering device, the ITO target material is set, the power is controlled to be 50W, the running time is 1h, and the film thickness is 100nm.

[0125] S15: A second metal electrode layer 372 is made on the side of the second transparent electrode layer 371 away from the buffer layer 36.

[0126] For example, the second metal electrode layer 372 is made by an evaporation method: the sample is placed on a mask, and is put into an evaporation chamber, and evaporation is performed when the evaporation vacuum degree is 2x10 -4 Pa, the evaporation voltage is adjusted to the evaporation temperature, the evaporation rate is controlled to be 2.5 Å / S, silver is evaporated on the second transparent electrode layer 371, and the evaporation thickness of the silver layer is 100 nm.

[0127] S16: a reflection reduction layer 38 is made on the side of the second metal electrode layer 372 away from the second transparent electrode layer 371.

[0128] Not limited, the reflection reduction layer 38 can be made by a magnetron sputtering method or an evaporation method; when the reflection reduction layer 38 is made by the evaporation method, the evaporation rate is limited to 0-5 Å / S.

[0129] For example, the reflection reduction layer 38 is made by an evaporation method: the sample is placed on a mask, and is put into an evaporation chamber, and evaporation is performed when the evaporation vacuum degree is 2x10 -4 Pa, the evaporation voltage is adjusted to the evaporation temperature, the evaporation rate is controlled to be 2 Å / S, magnesium fluoride is evaporated on the second metal electrode layer 372, the film thickness is 100 nm, and after the end, the annealing table temperature is set to 100℃, and an annealing operation is performed for 8 min.

[0130] In summary, the manufacturing method of the perovskite crystalline silicon stacked cell provided in the embodiments of the present application can improve the compactness of the buffer layer 36 and reduce the defect density of the buffer layer 36 by using the plasma enhanced atomic layer deposition method to make the buffer layer 36, so that the buffer layer 36 can meet the design requirements of the perovskite crystalline silicon stacked cell 1000 in terms of low-temperature compatibility, interface stability, and efficient transmission, thereby effectively improving the long-term stability and reliability of the perovskite crystalline silicon stacked cell 1000.

[0131] In a second aspect, the embodiments of the present application provide a perovskite crystalline silicon stacked cell 1000 made by the manufacturing method of the first aspect.

[0132] In a specific embodiment, please refer to Figure 1The perovskite crystalline silicon tandem battery 1000 comprises, from bottom to top, a first metal electrode layer 112, a first transparent electrode layer 111, a P-type doped layer 12, a first passivation layer 13, a silicon substrate 14, a second passivation layer 15, an N-type doped layer 16, a tunneling layer 21, a hole transport layer 31, a perovskite layer 32, a third passivation layer 33, an adhesion layer 34, an electron transport layer 35, a buffer layer 36, a second transparent electrode layer 371, a second metal electrode layer 372, and an anti-reflection layer 38, which are sequentially stacked. The first metal electrode layer 112, the first transparent electrode layer 111, the P-type doped layer 12, the first passivation layer 13, the silicon substrate 14, the second passivation layer 15, and the N-type doped layer 16 together form a crystalline silicon bottom cell, and the hole transport layer 31, the perovskite layer 32, the third passivation layer 33, the adhesion layer 34, the electron transport layer 35, the buffer layer 36, the second transparent electrode layer 371, the second metal electrode layer 372, and the anti-reflection layer 38 together form a perovskite top cell, and the tunneling layer 21 serves as a connecting layer connecting the crystalline silicon bottom cell and the perovskite top cell.

[0133] The first passivation layer 13, the second passivation layer 15, and the third passivation layer 33 can be propylene diamine iodine, including but not limited to at least one of propylene diamine bromine, butyl chloride amine, butyl bromide amine, butyl iodine amine, N,N-dimethyl-1,3-propylene diamine hydrochloride, and decabutyl amine bromine; the first passivation layer 13, the second passivation layer 15, and the third passivation layer 33 can also be magnesium fluoride, including but not limited to at least one of lithium fluoride and sodium fluoride.

[0134] The hole transport layer 31 can be at least one of poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine], poly-3-hexylthiophene, nickel oxide, molybdenum trioxide, cuprous iodide, and cuprous thiocyanate. The thickness of the hole transport layer 31 is 1 nm-600 nm.

[0135] The perovskite layer 32 has a general structure of ABX3; wherein A is an organic cation, including at least one of CH3NH3 + , NH2CH=NH2 + , CH3CH2NH3 + , Cs + ; B is a metal cation, including at least one of Pb 2+ , Sn 2+ ; and X is a halide anion, including at least one of F - , Cl - , Br - , I - . The thickness of the perovskite layer 32 is 1 nm-600 nm.

[0136] The electron transport layer 35 can be zinc oxide, tin dioxide, titanium dioxide, [6,6]-phenyl C 61at least one of methyl butyrate, carbon 60, 2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline. The thickness of the electron transport layer 35 is 1 nm-600 nm.

[0137] The buffer layer 36 can be at least one of zinc oxide, tin dioxide, titanium dioxide. The thickness of the buffer layer 36 is 0-30 nm.

[0138] The adhesion layer 34 can be N,N,N',N'-tetraepoxypropyl-4,4'-diaminodiphenyl methane.

[0139] The first metal electrode layer 112, the second metal electrode layer 372 can be at least one of silver, gold, copper, aluminum, carbon.

[0140] The anti-reflection layer 38 is used to reduce the reflection loss of incident light on the surface of the cell, increase the absorption of light, and improve the short-circuit current. The anti-reflection layer 38 can be a single layer or a multi-layer dielectric film. The thickness of the anti-reflection layer 38 is 1 nm-600 nm.

[0141] The perovskite crystalline silicon tandem cell 1000 provided by the embodiments of the present application improves the long-term stability and reliability of the cell by using the manufacturing method of the first aspect.

[0142] In a third aspect, the embodiments of the present application provide a photovoltaic module, comprising the perovskite crystalline silicon tandem cell 1000 manufactured by the manufacturing method in the embodiments of the first aspect.

[0143] The photovoltaic module can comprise a plurality of perovskite crystalline silicon tandem cells 1000, which can be connected in series or parallel, and can form an independent power generation module after packaging.

[0144] The photovoltaic module provided by the embodiments of the present application improves the long-term stability and reliability of the perovskite crystalline silicon tandem cell 1000 and the photovoltaic module comprising the perovskite crystalline silicon tandem cell 1000 by using the manufacturing method of the first aspect.

[0145] In a fourth aspect, the embodiments of the present application provide a photovoltaic system, comprising the photovoltaic module in the third aspect.

[0146] The photovoltaic system can comprise a plurality of photovoltaic modules, and the plurality of photovoltaic modules and the supporting equipment form a complete power generation system, which can convert solar energy into usable alternating current energy and be connected to the power grid or used for local load.

[0147] The photovoltaic system provided by the embodiments of the present application improves the long-term stability and reliability of the photovoltaic module by using the photovoltaic module of the third aspect.

[0148] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit them; although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method for manufacturing a perovskite crystalline silicon tandem cell, characterized by, The method comprises: providing a silicon substrate comprising a first surface and a second surface arranged oppositely; forming a P-type doped layer, a first electrode layer arranged successively on the first surface of the silicon substrate; forming an N-type doped layer, a tunneling layer, a hole transport layer, a perovskite layer, an electron transport layer, a buffer layer, a second electrode layer, and an anti-reflection layer arranged successively on the second surface of the silicon substrate; wherein forming the buffer layer comprises: forming the buffer layer on a side of the electron transport layer away from the perovskite layer by using a plasma enhanced atomic layer deposition method; forming the buffer layer on a side of the electron transport layer away from the perovskite layer by using a plasma enhanced atomic layer deposition method comprises: depositing a SnO2 thin film on a side of the electron transport layer away from the perovskite layer by using an atomic layer deposition device; performing surface modification on the SnO2 thin film by using a plasma generation device, wherein a working gas in the plasma generation device comprises argon and oxygen.

2. The method of claim 1, wherein The plasma generation device comprises a magnetron sputtering device.

3. The method of claim 2, wherein The power of the magnetron sputtering device is 30W-300W, and / or the flow rate of the working gas in the magnetron sputtering device is 5sccm-50sccm, and / or the flow rate ratio of the argon and oxygen is 280:1-1:1, and / or the chamber base heating temperature of the magnetron sputtering device is 25℃-80℃, and / or the working time of the magnetron sputtering device is 1min-30min.

4. The method of claim 1, wherein The deposition vacuum of the atomic layer deposition apparatus is 0-1x10 4 Pa, and / or the deposition pipe temperature of the atomic layer deposition apparatus is 50-150°C, and / or the deposition chamber temperature of the atomic layer deposition apparatus is 40-150°C.

5. The method of claim 1, wherein The thickness of the SnO2 thin film is 10nm-20nm.

6. The production method according to any one of claims 1 to 5, wherein Before forming the P-type doped layer, the method comprises: forming a first passivation layer on the first surface of the silicon substrate; and / or, before forming the N-type doped layer, the method comprises: forming a second passivation layer on the second surface of the silicon substrate; and / or, before forming the electron transport layer, the method comprises: forming a third passivation layer on a side of the perovskite layer away from the silicon substrate.

7. A perovskite crystalline silicon tandem cell, characterized by, The perovskite crystalline silicon tandem cell is formed by using the method according to any one of claims 1-6.

8. A photovoltaic module, characterized by, The photovoltaic module comprises the perovskite crystalline silicon tandem cell according to claim 8.

9. A photovoltaic system characterized by, The photovoltaic module comprises the perovskite crystalline silicon tandem cell according to claim 8.

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