Display panel

Abstract

In an embodiment of the present disclosure, a display panel is provided, the display panel comprising: a substrate; a pixel structure layer on the substrate and including a plurality of sub-pixels; and an optical path conversion unit on the pixel structure layer and converting a path of light generated from the pixel structure layer.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0062877, filed on May 14, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The embodiments of this disclosure relate to a display panel and a display system including the display panel. Background Technology

[0003] With the development of information technology, the importance of display devices as the connection medium between users and information is becoming increasingly apparent. As a result, the use of display devices (such as liquid crystal displays and organic light-emitting diode displays) is increasing.

[0004] The display system may include at least one display device. An image output from a display panel included in the display device may be displayed to the user via a lens.

[0005] The information disclosed in this background section is intended to enhance the understanding of the background technology of this disclosure, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0006] Embodiments of this disclosure may relate to display panels capable of reducing the size and weight of display systems, and display systems including such display panels.

[0007] According to one or more embodiments of the present disclosure, a display panel includes: a substrate; a pixel structure layer on the substrate and including a plurality of sub-pixels; and a light path conversion unit on the pixel structure layer and configured to convert the path of light generated from the pixel structure layer.

[0008] In an embodiment, the optical path conversion unit can be configured to converge light generated from the pixel structure layer.

[0009] In one embodiment, the optical path conversion unit may include a Fresnel lens on the pixel structure layer.

[0010] In some embodiments, the Fresnel lens may include epoxy resin.

[0011] In an embodiment, the optical path conversion unit may include a spherical lens or an aspherical lens on the pixel structure layer.

[0012] In an embodiment, the optical path conversion unit can be configured to change the direction of travel of light generated from the pixel structure layer.

[0013] In one embodiment, the optical path conversion unit may include a reflective layer.

[0014] In one embodiment, the reflective layer may have a flat surface.

[0015] In one embodiment, the reflective layer may have a curved surface.

[0016] In this embodiment, the display panel may also include a protective layer on the optical path conversion unit.

[0017] In one embodiment, the display panel may further include a cover window between the pixel structure layer and the optical path conversion unit.

[0018] In one embodiment, the display panel may further include a polarizing film layer between the cover window and the optical path conversion unit.

[0019] In this embodiment, the display panel may further include a wire grid polarization layer between the pixel structure layer and the optical path conversion unit.

[0020] In one embodiment, the display panel may further include a dam surrounding the pixel structure layer.

[0021] In an embodiment, the pixel structure layer may include: a pixel circuit layer on a substrate; a light-emitting element layer on the pixel circuit layer; and an optical functional layer on the light-emitting element layer.

[0022] In an embodiment, the pixel circuit layer may include at least one transistor; the light-emitting element layer may include a positive electrode, a light-emitting structure, and a negative electrode; and the optical function layer may include a color filter layer and a lens array.

[0023] According to one or more embodiments of the present disclosure, a display system includes a housing and at least one display panel in the housing, the at least one display panel including: a substrate; a pixel structure layer on the substrate and including a plurality of sub-pixels; and a light path conversion unit on the pixel structure layer and configured to convert the path of light generated from the pixel structure layer.

[0024] In an embodiment, the display system may further include at least one lens in the housing to receive light whose path has been altered by the light path conversion unit.

[0025] In an embodiment, the optical path conversion unit can be configured to converge light generated from the pixel structure layer.

[0026] In one embodiment, the optical path conversion unit may include a Fresnel lens on the pixel structure layer.

[0027] In an embodiment, the optical path conversion unit may include a spherical lens or an aspherical lens on the pixel structure layer.

[0028] In an embodiment, the optical path conversion unit can be configured to change the direction of travel of light generated from the pixel structure layer.

[0029] In one embodiment, the optical path conversion unit may include a reflective layer.

[0030] In one embodiment, the reflective layer may have a flat surface.

[0031] In one embodiment, the reflective layer may have a curved surface.

[0032] According to some embodiments of this disclosure, the size and weight of a display system including a display panel can be reduced.

[0033] However, this disclosure is not limited to the foregoing aspects and features, and the foregoing and additional aspects and features will be set forth in part in the detailed description below with reference to the accompanying drawings, and in part will be apparent from them or may be learned by practicing one or more of the embodiments presented in this disclosure. Attached Figure Description

[0034] The above and other aspects and features of this disclosure will be more clearly understood from the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which: Figure 1 This is a block diagram illustrating a display device according to an embodiment; Figure 2 This illustrates an embodiment. Figure 1 A bounding box of a subpixel; Figure 3 This illustrates an embodiment. Figure 1 A floor plan of the display panel; Figure 4 It is shown Figure 3 An exploded perspective view of a portion of the display panel; Figure 5 This illustrates an embodiment. Figure 4 A planar image of one pixel; Figure 6 It is along Figure 5 A sectional view taken by line I-I'; Figure 7 Included according to the embodiments Figure 6 A cross-sectional view of the light-emitting structure in a light-emitting element; Figure 8 Included according to the embodiments Figure 6 A cross-sectional view of the light-emitting structure in a light-emitting element; Figure 9 This illustrates an embodiment. Figure 4 A planar image of one pixel; Figure 10 This illustrates an embodiment. Figure 4 A planar image of one pixel; Figure 11This is a block diagram illustrating a display system according to an embodiment; Figure 12 It is shown Figure 11 A perspective view of an application example of a display system; Figure 13 It shows what the user is wearing. Figure 12 A diagram of a head-mounted display device; Figure 14 It is shown Figure 13 A diagram showing the distance between the display panel and the user's eyes; Figure 15 This is a cross-sectional view showing the display panel of the display device according to an embodiment; Figure 16 This illustrates an embodiment. Figure 15 A diagram of the optical path conversion unit; Figures 17A to 17E It shows the manufacturing process. Figure 16 A diagram showing the method of displaying the panel; Figures 18A to 18C This illustrates one or more embodiments. Figure 15 A diagram of the optical path conversion unit; Figure 19 This illustrates an embodiment. Figure 15 A diagram of the optical path conversion unit; Figure 20A and Figure 20B This is a cross-sectional view showing the display panel of a display device according to one or more embodiments; Figure 21 This is a cross-sectional view showing the display panel of the display device according to an embodiment; Figure 22 This is a cross-sectional view showing the display panel of the display device according to an embodiment; Figure 23 This is a cross-sectional view showing the display panel of a display device according to an embodiment; and Figures 24A to 24F This illustrates the manufacturing process according to an embodiment. Figure 16 A diagram showing the method of displaying the panel. Detailed Implementation

[0035] In the following description, embodiments will be illustrated in more detail with reference to the accompanying drawings, in which the same reference numerals refer to the same elements throughout. However, this disclosure may be implemented in a variety of different forms and should not be construed as being limited to the embodiments shown herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey to those skilled in the art the aspects and features of this disclosure. Therefore, processes, elements, and techniques not necessary for those skilled in the art to fully understand the aspects and features of this disclosure may not be described. Unless otherwise stated, the same reference numerals denote the same elements throughout the drawings and written description, and therefore redundant descriptions may not be repeated.

[0036] When a particular embodiment can be implemented in various ways, the specific process sequence may differ from the described sequence. For example, two consecutively described processes may be performed simultaneously or substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0037] Furthermore, as those skilled in the art will understand, in view of the whole of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole, or combined with each other, and may be technically interlocked and operated in a variety of suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable way, unless otherwise stated or implied.

[0038] In the accompanying drawings, for clarity, the relative dimensions, thicknesses, and proportions of elements, layers, and regions may be exaggerated and / or simplified. For ease of interpretation, spatial relative terms such as “below,” “under,” “lower,” “below,” “above,” “upper,” etc., may be used herein to describe the relationship of one element or feature as shown in the drawings to another element or feature (or other elements or features). It will be understood that, in addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the drawings is flipped, an element described as “below” or “under” or “below” other elements or features will subsequently be oriented “above” said other elements or features. Thus, the example terms “below” and “below” can cover both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein should be interpreted accordingly.

[0039] Furthermore, it should be anticipated that the shapes shown in the accompanying drawings may vary in practice depending on, for example, tolerances and / or manufacturing techniques. Therefore, the embodiments of this disclosure should not be construed as limited to the specific shapes shown in the drawings, and should be interpreted to account for possible shape variations, for example, due to manufacturing processes. Thus, the shapes shown in the drawings may not depict the actual shape of an area of ​​the device, and this disclosure is not limited thereto.

[0040] In the accompanying figures, the DR1, DR2, and DR3 axes are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the DR1, DR2, and DR3 axes can be perpendicular or substantially perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0041] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or portion described below may be referred to as the second element, component, region, layer, or portion.

[0042] It will be understood that when an element or layer is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be one or more intermediary elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it may be directly electrically connected to the other layer, region, or element, or it may be indirectly electrically connected, with one or more intermediary layers, regions, or elements situated therebetween. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or there may be one or more intermediary elements or layers.

[0043] The terminology used herein is for the purpose of describing particular embodiments and is not intended to limit the disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a” and “an” are also intended to include the plural forms. It will also be understood that when the terms “comprising,” “including,” “having,” and variations thereof are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, the expression “A and / or B” means A, B, or A and B. Expressions such as “at least one of…” modify the entire list of elements when following a list of elements, rather than individual elements within that list. For example, the expressions “at least one of a, b and c” and “at least one of the groups consisting of a, b and c” mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b and c, or variations thereof.

[0044] As used herein, the terms “substantially,” “about,” and similar terms are used as approximate terms rather than terms of degree and are intended to account for inherent biases in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, the use of “may” in describing embodiments of this disclosure refers to “one or more embodiments of this disclosure.” As used herein, the term “use” and variations thereof may be considered synonymous with the term “utilize” and variations thereof, respectively.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0046] Figure 1 This is a block diagram illustrating a display device according to an embodiment.

[0047] Reference Figure 1 The display device 100 may include a display panel 110, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0048] The display panel 110 includes sub-pixels SP. The sub-pixels SP can be connected to the gate driver 120 via first gate line GL1 to the m-th gate line GLm (where m is a positive integer). The sub-pixels SP can be connected to the data driver 130 via first data line DL1 to the n-th data line DLn (where n is a positive integer).

[0049] Each subpixel SP can include at least one light-emitting element to generate light. Therefore, each subpixel SP can generate light of a desired color (e.g., a specific or predetermined color) (such as red, green, blue, cyan, magenta, or yellow). Two or more subpixels in a subpixel SP can constitute a pixel PXL. For example, as... Figure 1 As shown, three sub-pixels SP can form a pixel PXL.

[0050] Gate driver 120 is connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 may output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In some embodiments, gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for timing-synchronizing the output of gate signals with applied data signals, etc.

[0051] In some embodiments, a first emission control line EL1 to an m-th emission control line ELm connected to the sub-pixel SP in the row direction may be further provided. In this case, the gate driver 120 may include an emission control driver to control the first emission control line EL1 to the m-th emission control line ELm, and the emission control driver may operate under the control of the controller 150.

[0052] The gate driver 120 may be disposed on one side of the display panel 110. However, this disclosure is not limited thereto. For example, the gate driver 120 may be divided into two or more physically and / or logically partitioned drivers, and the drivers may be disposed on one side of the display panel 110 and on the opposite side of the display panel 110. As described above, the gate driver 120 may be disposed around the display panel 110 in various suitable shapes as needed or desired.

[0053] Data driver 130 is connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 receives image data DATA and data control signal DCS from controller 150. Data driver 130 operates in response to data control signal DCS. In some embodiments, data control signal DCS may include source start pulse, source shift clock, source output enable signal, etc.

[0054] The data driver 130 can use a voltage from the voltage generator 140 to apply a data signal having a grayscale voltage (e.g., grayscale level or grayscale value) corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Therefore, the selected sub-pixel SP can generate light corresponding to the data signal. Thus, an image can be displayed on the display panel 110.

[0055] In some embodiments, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0056] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 can generate multiple voltages and can provide the generated voltages to components of display device 100. For example, voltage generator 140 can generate multiple voltages by receiving an input voltage from outside display device 100, adjusting the received voltage, and modulating the adjusted voltage.

[0057] Voltage generator 140 can generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first power supply voltage VDD and second power supply voltage VSS can be provided to sub-pixels SP. The first power supply voltage VDD can have a relatively high voltage level, and the second power supply voltage VSS can have a lower voltage level than the first power supply voltage VDD. In other embodiments, the first power supply voltage VDD or the second power supply voltage VSS can be provided by an external device of display device 100.

[0058] Additionally, voltage generator 140 can generate various suitable voltages. For example, voltage generator 140 can generate an initialization voltage applied to the sub-pixel SP. For example, during sensing operation for sensing the electrical characteristics of the transistors and / or light-emitting elements of the sub-pixel SP, a reference voltage (e.g., a predetermined reference voltage) can be applied to the first data lines DL1 to the nth data lines DLn, and voltage generator 140 can generate the reference voltage.

[0059] The controller 150 controls the overall operation of the display device 100. The controller 150 receives input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from an external source. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0060] The controller 150 can convert the input image data IMG to fit the display device 100 or display panel 110, and can output image data DATA. In some embodiments, the controller 150 can output image data DATA by aligning the input image data IMG to fit subpixels SP in rows (e.g., row units).

[0061] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In this case, the data driver 130, voltage generator 140, and controller 150 may be functionally separated components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be configured as a component distinct from the driver integrated circuit (DIC) (e.g., configured as a component separate from the driver integrated circuit (DIC)).

[0062] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 can sense the temperature around itself and can generate temperature data TEP representing the sensed temperature. In some embodiments, the temperature sensor 160 may be configured to be adjacent to the display panel 110 and / or adjacent to the driver integrated circuit DIC.

[0063] The controller 150 can control various operations of the display device 100 in response to temperature data TEP. In some embodiments, the controller 150 can adjust the brightness of the image output from the display panel 110 in response to temperature data TEP. For example, the controller 150 can control data signals and a first power supply voltage VDD and a second power supply voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0064] Figure 2 This illustrates an embodiment. Figure 1 A bounding box of a subpixel. In Figure 2 In the middle, refer to the above. Figure 1 Among the described subpixels SP, a representative example is shown: a subpixel SPij arranged in the i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (where j is an integer greater than or equal to 1 and less than or equal to n).

[0065] Reference Figure 2Subpixel SPij may include subpixel circuit SPC and light-emitting element LD.

[0066] The light-emitting element (LD) can be connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. The first power supply voltage node VDDN can be the reference mentioned above. Figure 1 The node described is for the first power supply voltage VDD, and the node for the second power supply voltage VSSN can be the node for transmitting the second power supply voltage VSS.

[0067] The anode AE ​​of the light-emitting element LD can be connected to the first power supply voltage node VDDN via the sub-pixel circuit SPC, and the cathode CE of the light-emitting element LD can be connected to the second power supply voltage node VSSN. For example, the anode AE ​​of the light-emitting element LD can be connected to the first power supply voltage node VDDN via one or more transistors included in the sub-pixel circuit SPC.

[0068] The sub-pixel circuit SPC can be connected to the reference above. Figure 1 The description includes the i-th gate line GL1 to the m-th gate line GLm, the i-th emission control line ELi among the first emission control lines EL1 to the m-th emission control lines ELm, and the j-th data line DLj among the first data lines DL1 to the n-th data lines DLn. The sub-pixel circuit SPC can control the light-emitting element LD based on the signal received through the signal lines.

[0069] The sub-pixel circuit (SPC) can operate in response to a gate signal received via the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In some embodiments, such as Figure 2 As shown, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. As described above, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to gate signals received through the corresponding two or more sub-gate lines.

[0070] The sub-pixel circuit SPC can operate in response to a transmission control signal received via the i-th transmission control line ELi. In some embodiments, the i-th transmission control line ELi may include one or more sub-transmission control lines. When the i-th transmission control line ELi includes two or more sub-transmission control lines, the sub-pixel circuit SPC can operate in response to a transmission control signal received via the corresponding two or more sub-transmission control lines.

[0071] The sub-pixel circuit SPC can receive a data signal via the j-th data line DLj. The sub-pixel circuit SPC can store a voltage corresponding to the data signal in response to at least one of the gate signals received via the first sub-gate line SGL1 or the second sub-gate line SGL2. The sub-pixel circuit SPC can adjust the current flowing from the first power supply voltage node VDDN through the light-emitting element LD to the second power supply voltage node VSSN according to the stored voltage, in response to the emission control signal received via the i-th emission control line ELi. Therefore, the light-emitting element LD can generate light with a brightness corresponding to the data signal.

[0072] Figure 3 This illustrates an embodiment. Figure 1 A floor plan of the display panel.

[0073] Reference Figure 3 ,and Figure 1 The display panel DP corresponding to the display panel 110 may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA is disposed around the display area DA.

[0074] Display panel DP can include substrate SUB, subpixels SP, and pad (also known as "solder pad") PD.

[0075] When the display panel DP is used as a display for a head-mounted display (HMD), virtual reality (VR) device, mixed reality (MR) device, augmented reality (AR) device, etc., the display panel DP can be positioned close to (e.g., very close to) the user's eyes. In this case, the sub-pixels SP can have a relatively high integration density. To increase the integration density of the sub-pixels SP, the substrate SUB can be set as a silicon substrate. The sub-pixels SP and / or other components of the display panel DP can be formed on the substrate SUB, which may be a silicon substrate. A display device 100 including other components of the display panel DP formed on a substrate SUB that is a silicon substrate (e.g., see reference 100). Figure 1 This can be referred to as an OLED on silicon (OLEDoS) display device.

[0076] Subpixels SP are disposed on the substrate SUB in the display area DA. The subpixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, this disclosure is not limited thereto. For example, the subpixels SP can be arranged in a zigzag shape along the first direction DR1 and the second direction DR2. For example, the subpixels SP can be arranged in a rhombus shape (e.g., pentiole). ® Shape, Pentile ®(This is a formally registered trademark of Samsung Display Co., Ltd.) The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction.

[0077] Two or more sub-pixels from a plurality of sub-pixels SP can form a pixel PXL.

[0078] Components for controlling subpixels SP can be set on the base SUB in the non-display area NDA. For example, lines connected to subpixels SP (such as those referenced above) Figure 1 The first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn described can be set in the non-display area NDA.

[0079] The above reference Figure 1 At least one of the described gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 may be integrated into the non-display area NDA of the display panel DP. In some embodiments, the above references Figure 1 The described gate driver 120 can be mounted on the display panel DP and can be located in the non-display area NDA. In other embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. In some embodiments, a temperature sensor 160 can be located in the non-display area NDA to sense the temperature of the display panel DP.

[0080] The pad PD is positioned on the substrate SUB within the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via wirelines. For example, the pad PD can be connected to the sub-pixel SP via first data lines DL1 to nth data lines DLn.

[0081] The pad PD can connect the display panel DP to the display device 100 (e.g., refer to...). Figure 1 Other components of ). In some embodiments, reference can be made to the above. Figure 1 The described driver integrated circuit (DIC) provides voltages and signals for the operation of components included in the display panel (DP) via a pad (PD). For example, first data lines DL1 to nth data lines DLn can be connected to the driver integrated circuit (DIC) via the pad (PD). For example, a first power supply voltage VDD and a second power supply voltage VSS can be received from the driver integrated circuit (DIC) via the pad (PD). For example, when the gate driver 120 is mounted on the display panel (DP), the gate control signal GCS can be transmitted from the driver integrated circuit (DIC) to the gate driver 120 via the pad (PD).

[0082] In some embodiments, the circuit board may be electrically connected to the pad PD using conductive adhesive members, such as anisotropic conductive films. The circuit board may be a flexible printed circuit board (FPCB) or a flexible film made of flexible material. The driver integrated circuit (DIC) may be mounted on the circuit board to be electrically connected to the pad PD.

[0083] In some embodiments, the display area DA can have various suitable shapes. The display area DA can have a closed-loop shape including straight edges and / or curved edges. For example, the display area DA can have various suitable shapes (such as polygons, circles, semicircles, and ellipses).

[0084] In some embodiments, the display panel DP may have a flat or substantially flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially rounded. In some embodiments, the display panel DP may be flexible, foldable, or rollable. In this case, the display panel DP including the substrate SUB may include a suitable material with flexible properties.

[0085] Figure 4 It is shown Figure 3 An exploded perspective view of a portion of the display panel. Figure 4 For ease of explanation, the display panel DP is schematically shown in the reference above. Figure 3 The portion corresponding to pixels PXL1 and PXL2 within the described pixel PXL. The portion of the display panel DP corresponding to the other remaining pixels PXL can be constructed as follows: Figure 4 The parts shown are the same or substantially the same (or similar).

[0086] Reference Figure 3 and Figure 4 Each of the first pixel PXL1 and the second pixel PXL2 may include first sub-pixels to third sub-pixels SP1, SP2, and SP3. However, this disclosure is not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels SP, or may include two sub-pixels SP.

[0087] exist Figure 4 In the diagram, when viewed from a third direction intersecting the first direction DR1 and the second direction DR2 towards DR3 (e.g., in a planar view), the first to third sub-pixels SP1, SP2, and SP3 have a quadrilateral shape and have dimensions that are equal to or substantially equal to each other. However, this disclosure is not limited thereto. In other embodiments, the first to third sub-pixels SP1, SP2, and SP3 may have various suitable shapes.

[0088] The display panel (DP) may include a substrate (SUB), a pixel circuit layer (PCL), a light-emitting element layer (LDL), a packaging layer (TFE), an optical functional layer (OFL), an outer coating layer (OC), and a cover window (CW).

[0089] In some embodiments, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a glass substrate. In other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0090] A pixel circuit layer (PCL) is disposed on a substrate (SUB). The substrate (SUB) and / or the pixel circuit layer (PCL) may include an insulating layer and conductive patterns disposed between the insulating layers. The conductive patterns of the pixel circuit layer (PCL) may be used as at least a portion of circuit elements, lines, etc. The conductive patterns may include copper, but this disclosure is not limited thereto.

[0091] The circuit elements may include a sub-pixel circuit SPC for each of the first to third sub-pixels SP1, SP2 and SP3 (e.g., see reference). Figure 2 The sub-pixel circuit (SPC) may include transistors and one or more capacitors. Each transistor may include a semiconductor portion comprising a source region, a drain region, and a channel region, and a gate electrode stacked with the semiconductor portion. In some embodiments, when the substrate SUB is a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In some embodiments, when the substrate SUB is a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other on a third direction DR3, with an insulating layer disposed therebetween.

[0092] The lines of the pixel circuit layer (PCL) may include signal lines (such as gate lines, emit control lines, data lines, etc.) connected to each of the first to third sub-pixels SP1, SP2, and SP3. The lines may also include connections to the referenced above. Figure 2 The described first power supply voltage node VDDN line. Additionally, the line may also include connections to the referenced above. Figure 2 The line describing the second power supply voltage node VSSN.

[0093] The light-emitting element layer (LDL) may include an anode (AE), a pixel-defining layer (PDL), a light-emitting structure (EMS), and a cathode (CE).

[0094] The anode AE ​​can be disposed on the pixel circuit layer PCL. The anode AE ​​can contact the circuit elements of the pixel circuit layer PCL. The anode AE ​​may include an opaque conductive material capable of reflecting light, but this disclosure is not limited thereto.

[0095] A pixel-defining layer (PDL) is disposed on the anode electrode (AE). The PDL may include an opening (OP) that exposes a portion of each of the anode electrodes (AE). The opening (OP) of the PDL can be understood as an emission region corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively.

[0096] In some embodiments, the pixel-defining layer (PDL) may comprise an inorganic material. In this case, the pixel-defining layer (PDL) may comprise multiple stacked inorganic layers. For example, the pixel-defining layer (PDL) may comprise silicon oxide (SiO2). x ) and silicon nitride (SiN) x In other embodiments, the pixel defining layer (PDL) may include an organic material. However, the material of the pixel defining layer (PDL) is not limited thereto.

[0097] The light-emitting structure (EMS) can be disposed on the anode (AE) exposed by the opening (OP) of the pixel-defining layer (PDL). The EMS may include a light-emitting layer for generating light, an electron transport layer for transporting electrons, a hole transport layer for transporting holes, etc.

[0098] In some embodiments, the light-emitting structure EMS can fill the opening OP of the pixel-defining layer PDL and can be disposed entirely on the pixel-defining layer PDL. In other words, the light-emitting structure EMS can extend across the first sub-pixel SP1 to the third sub-pixel SP3. In this case, at least a portion of the layer in the light-emitting structure EMS can be broken or bent at the boundary between the first sub-pixel SP1 and the third sub-pixel SP3. However, this disclosure is not limited thereto. For example, the portions of the light-emitting structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 can be spaced apart from each other (e.g., can be separated from each other), and each of said portions can be disposed in the corresponding opening OP of the pixel-defining layer PDL.

[0099] The cathode CE can be disposed on the light-emitting structure EMS. The cathode CE can extend across the first sub-pixel SP1 to the third sub-pixel SP3. As described above, the cathode CE can be configured as a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3.

[0100] The cathode CE can be a thin metal layer with a thickness sufficient to transmit light emitted from the light-emitting structure EMS. The cathode CE can be formed of a metallic material or a transparent conductive material to have a relatively thin thickness. In some embodiments, the cathode CE may include at least one of a variety of suitable transparent conductive materials comprising indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In other embodiments, the cathode CE may include at least one of silver (Ag), magnesium (Mg), and suitable mixtures thereof. However, the material of the cathode CE is not limited to these.

[0101] One of the anodes AE, the portion of the light-emitting structure EMS superimposed thereon, and the portion of the cathode CE superimposed thereon can constitute a light-emitting element LD (e.g., see reference). Figure 2 In other words, each of the light-emitting elements (LDs) in the first sub-pixel SP1 to the third sub-pixel SP3 may include an anode AE, a portion of the light-emitting structure EMS superimposed on the anode AE, and a portion of the cathode CE superimposed on the anode AE. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the corresponding anode AE ​​and electrons injected from the cathode CE can be transferred to the light-emitting layer of the light-emitting structure EMS to form excitons, and light can be generated when the excitons transition from the excited state to the ground state. The brightness of the light can be determined based on the amount of current flowing through the light-emitting layer. The wavelength range of the generated light can be determined based on the structure of the light-emitting layer.

[0102] The encapsulation layer TFE is disposed on the cathode CE. The encapsulation layer TFE may cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can prevent or substantially prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL. In some embodiments, the encapsulation layer TFE may comprise a structure in which one or more inorganic layers and one or more organic layers are alternately stacked. For example, the inorganic layers may include silicon nitride, silicon oxide, silicon oxynitride (SiO2), etc. x N y For example, the organic layer may include organic insulating materials such as acrylic resin (polyacrylate), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB) resin. However, the materials of the organic and inorganic layers of the encapsulation layer TFE are not limited to these.

[0103] To improve the packaging efficiency of the TFE encapsulation layer, the TFE encapsulation layer may also include aluminum oxide (AlO2). x The thin film containing aluminum oxide can be located on the upper surface of the encapsulation layer TFE facing the optical functional layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0104] Thin films containing alumina can be formed using atomic layer deposition (ALD). However, this disclosure is not limited thereto. The encapsulation layer TFE may also comprise a thin film formed from at least one of a variety of materials suitable for improving encapsulation efficiency.

[0105] The optical functional layer (OFL) is disposed on the encapsulation layer (TFE). The optical functional layer (OFL) may include a color filter layer (CFL) and a lens array (LA).

[0106] A color filter layer (CFL) is disposed between the encapsulation layer (TFE) and the lens array (LA). The CFL filters light emitted from the light-emitting structure (EMS) and selectively outputs light of a wavelength range or color corresponding to each sub-pixel (SP). The CFL may include color filters (CF) corresponding to the first sub-pixels SP1 through SP3, respectively, and each of the CFs allows light of a wavelength range corresponding to the corresponding sub-pixel SP to pass through. For example, the color filter corresponding to the first sub-pixel SP1 allows red light to pass through, the color filter corresponding to the second sub-pixel SP2 allows green light to pass through, and the color filter corresponding to the third sub-pixel SP3 allows blue light to pass through. Depending on the light emitted from the light-emitting structure (EMS) of each sub-pixel SP, at least a portion of the color filter CF may be omitted.

[0107] A lens array LA is disposed on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixels SP1 through SP3, respectively. Each of the lenses LS can improve light output efficiency by directing light emitted from the light-emitting structure EMS to a desired path. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a higher refractive index than the outer coating OC. In some embodiments, the lenses LS may include organic materials. In some embodiments, the lenses LS may include acrylic resin (polyacrylate) materials. However, the materials of the lenses LS are not limited to these.

[0108] In some embodiments, at least a portion of the color filter CF of the color filter layer CFL and at least a portion of the lens LS of the lens array LA may be shifted in a direction parallel to or substantially parallel to the plane defined by the first direction DR1 and the second direction DR2, compared to the opening OP of the pixel-defining layer PDL. More specifically, in the central region of the display area DA, when viewed in the third direction DR3 (e.g., in a planar view), the center of the color filter CF and the center of the lens LS may be aligned with the center of the corresponding opening OP of the pixel-defining layer PDL, or may be superimposed on the center of the corresponding opening OP of the pixel-defining layer PDL. For example, in the central region of the display area DA, the opening OP of the pixel-defining layer PDL may be completely superimposed on the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be shifted in a planar direction from the center of the opening OP of the corresponding pixel-defining layer PDL. For example, in the region of the display area DA adjacent to the non-display area NDA, the opening OP of the pixel limiting layer PDL can be partially superimposed with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, at the center of the display area DA, light emitted from the light-emitting structure EMS can be efficiently output in the normal direction of the display surface. At the periphery of the display area DA, light emitted from the light-emitting structure EMS can be efficiently output in a direction tilted at a certain angle (e.g., a predetermined angle) relative to the normal direction of the display surface.

[0109] An outer coating OC can be disposed on the lens array LA. The outer coating OC can cover the optical functional layer OFL, the encapsulation layer TFE, the light-emitting structure EMS, and / or the pixel circuit layer PCL. The outer coating OC can include various materials suitable for protecting the underlying layers from foreign matter such as dust or moisture. For example, the outer coating OC can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC can include epoxy resin, but this disclosure is not limited thereto. The outer coating OC can have a refractive index lower than that of the lens array LA.

[0110] A cover window (CW) may be disposed on the outer coating (OC). The cover window (CW) may protect the layer beneath it. The cover window (CW) may have a higher refractive index than the outer coating (OC). The cover window (CW) may include glass, but this disclosure is not limited thereto. For example, the cover window (CW) may be encapsulating glass to protect components disposed beneath it. In other embodiments, the cover window (CW) may be omitted as needed or desired.

[0111] Figure 5 This illustrates an embodiment. Figure 4 A planar image of a single pixel. In Figure 5 For ease of explanation, the above reference is shown schematically. Figure 4 The first pixel PXL1 is described in the first pixel PXL1 and the second pixel PXL2. The other remaining pixels can be constructed to be the same as or substantially the same as (or similar to) the first pixel PXL1.

[0112] Reference Figure 4 and Figure 5 The first pixel PXL1 may include a first sub-pixel SP1 to a third sub-pixel SP3 arranged along the first direction DR1.

[0113] The first sub-pixel SP1 may include a first emission region EMA1 and a non-emission region NEA surrounding the first emission region EMA1. The second sub-pixel SP2 may include a second emission region EMA2 and a non-emission region NEA surrounding the second emission region EMA2. The third sub-pixel SP3 may include a third emission region EMA3 and a non-emission region NEA surrounding the third emission region EMA3.

[0114] The first emission region EMA1 can be light emitted from the light-emitting structure EMS (e.g., reference). Figure 4 The second emission region EMA2 can be the region where light is emitted from the portion of the light-emitting structure EMS corresponding to the second sub-pixel SP1. The third emission region EMA3 can be the region where light is emitted from the portion of the light-emitting structure EMS corresponding to the third sub-pixel SP3. (Refer to the above.) Figure 4 As described, each emission region can be understood as a corresponding opening OP of each of the first sub-pixels SP1 to the third sub-pixels SP3 in the pixel-defined layer PDL.

[0115] Figure 6 It is along Figure 5 A sectional view taken by line I-I'.

[0116] Reference Figure 6 The pixel circuit layer PCL can be set on the substrate SUB.

[0117] The substrate SUB may include a silicon wafer substrate formed using semiconductor processes. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0118] A pixel circuit layer (PCL) is disposed on a substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include transistor T_SP1 for the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3. Transistor T_SP1 for the first sub-pixel SP1 may be a sub-pixel circuit (SPC) included in the first sub-pixel SP1 (e.g., see reference 1). Figure 2 One of the transistors in the second sub-pixel SP2, transistor T_SP2 can be one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and transistor T_SP3 of the third sub-pixel SP3 can be one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 6 For ease of illustration, only one transistor of each sub-pixel is shown, and the other remaining circuit elements are not shown.

[0119] The transistor T_SP1 of the first sub-pixel SP1 may include the source region SRA, the drain region DRA, and the gate electrode GE.

[0120] The source region (SRA) and drain region (DRA) can be located within the substrate (SUB). A well (WL) formed by ion implantation can also be located within the substrate (SUB), and the source region (SRA) and drain region (DRA) can be spaced apart from each other within the well (WL). The region between the source region (SRA) and drain region (DRA) within the well (WL) can be defined as the channel region.

[0121] The gate electrode GE can be stacked with the channel region between the source region SRA and the drain region DRA, and can be disposed in the pixel circuit layer PCL. The gate electrode GE can be separated from the well region WL or the channel region by an insulating material (such as the gate insulating layer GI). The gate electrode GE may include a conductive material.

[0122] Multiple layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers. The conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via a drain connection portion DRC that passes through (e.g., penetrates) one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via a source connection portion SRC that passes through (e.g., penetrates) one or more insulating layers.

[0123] Since the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 are connected to different circuit elements and / or lines, the transistor T_SP1 of the first sub-pixel SP1 can be set as one of the transistors of the first sub-pixel SP1.

[0124] Each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be constructed to be the same as or substantially the same as (or similar to) the transistor T_SP1 of the first sub-pixel SP1.

[0125] As described above, the substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0126] A via layer (VIAL) is disposed on the pixel circuit layer (PCL). The via layer (VIAL) can cover the pixel circuit layer (PCL) and can have a generally flat or substantially flat surface. The via layer (VIAL) can planarize or substantially planarize the steps on the pixel circuit layer (PCL). The via layer (VIAL) can include silicon oxide (SiO2). x Silicon nitride (SiN) x The present disclosure is not limited thereto.

[0127] The light-emitting element layer (LDL) is disposed on the via layer (VIAL). The light-emitting element layer (LDL) may include a first reflective electrode (RE1) to a third reflective electrode (RE3), a planarization layer (PLNL), a first anode electrode (AE1) to a third anode electrode (AE3), a pixel definition layer (PDL), a light-emitting structure (EMS), and a cathode electrode (CE).

[0128] On the via layer VIAL, the first reflective electrode RE1 to the third reflective electrode RE3 are respectively disposed in the first sub-pixel SP1 to the third sub-pixel SP3. Each of the first reflective electrode RE1 to the third reflective electrode RE3 can be disposed in the corresponding circuit element in the pixel circuit layer PCL through a via through the via layer VIAL.

[0129] The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can be used as total reflection mirrors for reflecting light emitted from the light-emitting structure EMS toward the display surface (e.g., toward the cover window CW). The first reflecting electrodes RE1 to the third reflecting electrodes RE3 may include metallic materials suitable for reflecting light. The first reflecting electrodes RE1 to the third reflecting electrodes RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and suitable alloys selected from two or more of these materials.

[0130] In some embodiments, the connecting electrode may be disposed below each of the first to third reflective electrodes RE1 to RE3. The connecting electrode can improve the electrical connection characteristics between the reflective electrode and the corresponding circuit elements of the pixel circuit layer PCL. The connecting electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but this disclosure is not limited thereto. In some embodiments, the corresponding reflective electrode may be located between multiple layers of the connecting electrode.

[0131] A buffer pattern BFP may be disposed below at least one of the reflective electrodes RE1 to RE3. The buffer pattern BFP may include inorganic materials (such as silicon carbonitride), but this disclosure is not limited thereto. By providing the buffer pattern BFP, the height of the corresponding reflective electrode on the third-direction DR3 can be adjusted. For example, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0132] The first reflecting electrodes RE1 to the third reflecting electrodes RE3 can be used as total reflection mirrors, and the cathode CE can be used as a half-reflection mirror. Light emitted from the light-emitting layer of the light-emitting structure EMS can be amplified by at least partially reciprocating between the corresponding reflecting electrode and the cathode CE, and the amplified light can be output through the cathode CE. As described above, the distance between each reflecting electrode and the cathode CE can be understood as the resonant distance of the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0133] The first sub-pixel SP1 can have a shorter resonant distance than the other sub-pixels, which is the resonant distance of the buffer pattern BFP. The resonant distance adjusted as described above allows light within a specific wavelength range (e.g., red) to be effectively and efficiently amplified. Therefore, the first sub-pixel SP1 can effectively and efficiently output light within the corresponding wavelength range.

[0134] exist Figure 6 In this embodiment, the buffer pattern BFP is set to the first sub-pixel SP1, but not to the second sub-pixel SP2 and the third sub-pixel SP3; however, this disclosure is not limited thereto. The buffer pattern BFP may also be set in at least one of the second sub-pixel SP2 and the third sub-pixel SP3 to adjust the resonant distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue, respectively; the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE; and the distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0135] To planarize or substantially planarize the step between the first reflective electrode RE1 and the third reflective electrode RE3, a planarization layer PLNL can be disposed on the via layer VIAL and the first reflective electrode RE1 to the third reflective electrode RE3. The planarization layer PLNL can generally cover the first reflective electrode RE1 to the third reflective electrode RE3 and the via layer VIAL, and can have a flat or substantially flat surface. In some embodiments, the planarization layer PLNL can be omitted as needed or desired.

[0136] On the planarization layer PLNL, first anodes AE1 to third anodes AE3 are respectively stacked with first reflective electrodes RE1 to third reflective electrodes RE3. When viewed on a third-direction DR3 (e.g., in a planar view), the first anodes AE1 to third anodes AE3 may have the same shape as referenced above. Figure 5 The first emission regions EMA1 to the third emission regions EMA3 are described as having similar shapes. The first anode AE1 to the third anode AE3 are respectively connected to the first reflective electrodes RE1 to the third reflective electrodes RE3. The first anode AE1 can be connected to the first reflective electrode RE1 through a first via VIA1 passing through (e.g., penetrating) the planarization layer PLNL. The second anode AE2 can be connected to the second reflective electrode RE2 through a second via VIA2 passing through (e.g., penetrating) the planarization layer PLNL. The third anode AE3 can be connected to the third reflective electrode RE3 through a third via VIA3 passing through (e.g., penetrating) the planarization layer PLNL.

[0137] In some embodiments, the first anode AE1 to the third anode AE3 may include suitable transparent conductive materials (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO)). x The materials are at least one of indium gallium zinc oxide (IGZO) and / or indium tin zinc oxide (ITZO). However, the materials of the first anode AE1 to the third anode AE3 are not limited thereto. For example, the first anode AE1 to the third anode AE3 may include titanium nitride.

[0138] In some embodiments, an insulating layer may be further provided for adjusting the height of one or more of the first anodes AE1 to the third anodes AE3. The insulating layer may be provided between one or more of the first anodes AE1 to the third anodes AE3 and their corresponding reflective electrodes. In this case, the planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first sub-pixels SP1 to the third sub-pixels SP3 may correspond to red, green, and blue, respectively, and the distance between the first anode AE1 and the cathode CE may be shorter than the distance between the second anode AE2 and the cathode CE, and the distance between the second anode AE2 and the cathode CE may be shorter than the distance between the third anode AE3 and the cathode CE. A pixel defining layer PDL is provided on portions of the first anodes AE1 to the third anodes AE3 and the planarization layer PLNL. The pixel defining layer PDL may include an opening OP that exposes a portion of each of the first anodes AE1 to the third anodes AE3. The opening OP of the pixel defining layer PDL may define the emission region of each of the first sub-pixels SP1 to the third sub-pixels SP3. The pixel defining layer PDL may be provided as shown above. Figure 5 The non-emission area NEA is described, and the first emission area EMA1 to the third emission area EMA3 can be defined.

[0139] In some embodiments, the pixel defining layer (PDL) may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO2). x ) and silicon nitride (SiN) x At least one of the following. For example, the pixel defining layer PDL may include a first inorganic insulating layer to a third inorganic insulating layer stacked sequentially, and each of the first inorganic insulating layer to the third inorganic insulating layer may include silicon nitride and / or silicon oxide. However, this disclosure is not limited thereto. The first inorganic insulating layer to the third inorganic insulating layer may have a stepped profile in the region adjacent to the opening OP.

[0140] The separator SPR can be set in the boundary region BDA between subpixels that are adjacent to each other (e.g., side-by-side). In other words, the separator SPR can be set as shown above. Figure 3 The boundary region BDA between each of the sub-pixels SP is described.

[0141] The spacer PR can cause discontinuities (e.g., discontinuous portions) in the light-emitting structure EMS within the boundary region BDA. For example, the light-emitting structure EMS may be broken or bent in the boundary region BDA due to the spacer PR.

[0142] The separator SPR can be disposed in or on the pixel defining layer PDL. The pixel defining layer PDL can include one or more trenches TRCH1 and TRCH2 as separator SPRs in the boundary region BDA. In some embodiments, such as Figure 6 As shown, one or more trenches TRCH1 and TRCH2 may pass through the pixel defining layer PDL and may partially pass through the planarization layer PLNL. In other embodiments, one or more trenches TRCH1 and TRCH2 may pass through the pixel defining layer PDL and the planarization layer PLNL, and may partially pass through the via layer VIAL. In other embodiments, one or more trenches TRCH1 and TRCH2 may at least partially pass through the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining layer PDL may be disposed in one or more trenches TRCH1 and TRCH2.

[0143] exist Figure 6 In the diagram, two trenches TRCH1 and TRCH2 are shown in the boundary region BDA. However, this disclosure is not limited thereto. For example, the pixel-limiting layer PDL may include one trench in the boundary region BDA. As another example, the pixel-limiting layer PDL may include three or more trenches in the boundary region BDA.

[0144] Due to the first trench TRCH1 and the second trench TRCH2 in the boundary region BDA, discontinuous portions (such as the first gap VD1 and the second gap VD2) can be formed in the light-emitting structure EMS. A portion of the multiple layers stacked in the light-emitting structure EMS can be broken or bent through the first gap VD1 and the second gap VD2. For example, at least one charge-generating layer included in the light-emitting structure EMS can be broken in the first gap VD1 and the second gap VD2. As described above, portions of the light-emitting structure EMS included in the first sub-pixel SP1 to the third sub-pixel SP3 can be at least partially separated due to the first trench TRCH1 and the second trench TRCH2.

[0145] exist Figure 6 In the boundary region BDA, a first gap VD1 and a second gap VD2 are formed in the light-emitting structure EMS, but this disclosure is not limited thereto. For example, concave valleys can be formed in the light-emitting structure EMS in the boundary region BDA. Depending on the shape of the first trench TRCH1 and the second trench TRCH2, the discontinuous portions formed in the light-emitting structure EMS can be modified in various ways.

[0146] In some embodiments, the light-emitting structure EMS can be formed by processes such as vacuum deposition or inkjet printing. In this case, the same material as the light-emitting structure EMS can be located on the bottom surface of the first trench TRCH1 and the second trench TRCH2 adjacent to the via layer VIAL.

[0147] The separator SPR can be modified and configured in various ways, allowing the light-emitting structure EMS to have discontinuous portions in the boundary region BDA. In some embodiments, in the absence of the first trench TRCH1 and the second trench TRCH2, additional inorganic insulating patterns stacked on the pixel defining layer PDL can be provided in the boundary region BDA. Among the additionally stacked inorganic insulating patterns, the width of the uppermost inorganic insulating pattern can be greater than the width of the inorganic insulating pattern immediately below it. For example, in the boundary region BDA, the first to third inorganic insulating patterns can be stacked sequentially from the pixel defining layer PDL, and the uppermost third inorganic insulating pattern can have a width greater than the width of the second inorganic insulating pattern. For example, the pixel defining layer PDL can have a "T"-shaped or "I"-shaped cross-section in the boundary region BDA. Depending on the shape of the pixel defining layer PDL, multiple layers included in the light-emitting structure EMS can be at least partially broken or bent in the boundary region BDA.

[0148] The light-emitting structure EMS can be disposed on the anodes AE1 to AE3 exposed by the opening OP of the pixel-defining layer PDL. The light-emitting structure EMS can fill the opening OP of the pixel-defining layer PDL and can be configured to span the entire length of the first sub-pixels SP1 to the third sub-pixels SP3. As described above, the light-emitting structure EMS can be at least partially disconnected or bent in the boundary region BDA by the separator SPR. Therefore, when operating the display panel DP, the current flowing from each of the first sub-pixels SP1 to the third sub-pixels SP3 through the laminar flow included in the light-emitting structure EMS to its adjacent sub-pixels can be reduced. Therefore, the first light-emitting elements LD1 to the third light-emitting elements LD3 can operate with relatively high reliability.

[0149] The cathode CE can be disposed on the light-emitting structure EMS. The cathode CE can be commonly disposed on the first sub-pixel SP1 to the third sub-pixel SP3. The cathode CE can be used as a semi-reflective mirror that allows light emitted from the light-emitting structure EMS to be partially transmitted and partially reflected.

[0150] The first anode AE1, the portion of the light-emitting structure EMS superimposed on the first anode AE1, and the portion of the cathode CE superimposed on the first anode AE1 can constitute the first light-emitting element LD1. The second anode AE2, the portion of the light-emitting structure EMS superimposed on the second anode AE2, and the portion of the cathode CE superimposed on the second anode AE2 can constitute the second light-emitting element LD2. The third anode AE3, the portion of the light-emitting structure EMS superimposed on the third anode AE3, and the portion of the cathode CE superimposed on the third anode AE3 can constitute the third light-emitting element LD3.

[0151] The encapsulation layer TFE is disposed on the cathode CE. The encapsulation layer TFE can prevent or substantially prevent oxygen and / or moisture from penetrating into the light-emitting element layer LDL.

[0152] An optical functional layer (OFL) is disposed on the encapsulation layer TFE. In some embodiments, the optical functional layer OFL can be attached to the encapsulation layer TFE via an adhesive layer (APL). For example, the optical functional layer OFL can be manufactured separately and attached to the encapsulation layer TFE via the adhesive layer APL. The adhesive layer APL can further perform the function of protecting the underlying layer including the encapsulation layer TFE.

[0153] The optical functional layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include a first color filter CF1 to a third color filter CF3 corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively. The first color filters CF1 to the third color filters CF3 can allow light of different wavelength ranges to pass through. For example, the first color filters CF1 to the third color filters CF3 can allow red, green, and blue light to pass through, respectively.

[0154] In some embodiments, the first color filter CF1 to the third color filter CF3 may be partially superimposed on each other in the boundary region BDA. In other embodiments, the first color filter CF1 to the third color filter CF3 may be spaced apart from each other, and a black matrix may be disposed between the first color filter CF1 to the third color filter CF3.

[0155] The lens array LA is disposed on the color filter layer CFL. The lens array LA may include first lenses LS1 to third lenses LS3, respectively, corresponding to first sub-pixels SP1 to third sub-pixels SP3. Each of the first lenses LS1 to third lenses LS3 can improve light output efficiency by outputting light emitted from first light-emitting elements LD1 to third light-emitting elements LD3 to a desired path.

[0156] Figure 7 Included according to the embodiments Figure 6 A cross-sectional view of the light-emitting structure in a light-emitting element.

[0157] Reference Figure 7 The light-emitting structure EMS can have a series structure in which a first light-emitting unit or a first light-emitting stack EU1 is stacked with a second light-emitting unit or a second light-emitting stack EU2. The light-emitting structure EMS can be constructed as described above. Figure 6 The light-emitting structures of each of the first light-emitting elements LD1 to the third light-emitting element LD3 described are the same or substantially the same.

[0158] Each of the first light-emitting unit EU1 and the second light-emitting unit EU2 may include at least one light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit or a first electron transport layer ETU1, and a first hole transport unit or a first hole transport layer HTU1. The first light-emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit or a second electron transport layer ETU2, and a second hole transport unit or a second hole transport layer HTU2. The second light-emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0159] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and may also include a hole buffer layer, an electron blocking layer, etc., if needed or desired. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same or substantially the same structure as each other, or may be different from each other.

[0160] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may also include an electron buffer layer, a hole blocking layer, etc., if desired or required. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same or substantially the same structure as each other, or may be different from each other.

[0161] A connecting layer, which can be configured in the form of a charge generation layer CGL, can be disposed between the first light-emitting unit EU1 and the second light-emitting unit EU2 to connect the first light-emitting unit EU1 and the second light-emitting unit EU2 to each other. In some embodiments, the charge generation layer CGL can have a stacked structure of a p-doped layer and an n-doped layer. For example, the p-doped layer can include a p-type dopant (such as HAT-CN, TCNQ and / or NDP-9), and the n-doped layer can include an alkali metal, an alkaline earth metal, a lanthanide metal, or a suitable combination thereof. However, this disclosure is not limited thereto.

[0162] In some embodiments, the first emissive layer EML1 and the second emissive layer EML2 can produce light of different colors from each other. Light emitted from each of the first emissive layer EML1 and the second emissive layer EML2 can be mixed together and considered as white light. For example, the first emissive layer EML1 can produce blue light, and the second emissive layer EML2 can produce yellow light. In some embodiments, the second emissive layer EML2 can include a stacked structure of a first sub-emissive layer for producing red light and a second sub-emissive layer for producing green light. Red and green light can be mixed together, and thus yellow light can be provided. In this case, an intermediate layer that performs the function of transporting holes and / or blocking the transport of electrons can be further disposed between the first sub-emissive layer and the second sub-emissive layer.

[0163] In other embodiments, the first light-emitting layer EML1 and the second light-emitting layer EML2 can produce light of the same color as each other.

[0164] The light-emitting structure EMS can be formed by suitable methods such as vacuum deposition and / or inkjet printing, but this disclosure is not limited thereto.

[0165] Figure 8 Included according to the embodiments Figure 6 A cross-sectional view of the light-emitting structure in a light-emitting element.

[0166] Reference Figure 8 The light-emitting structure EMS' can have a series structure of first light-emitting units or first light-emitting stack EU1' to third light-emitting units or third light-emitting stack EU3' stacked together. The light-emitting structure EMS' can be constructed as described above. Figure 6 The light-emitting structures of each of the first light-emitting elements LD1 to the third light-emitting element LD3 described are the same or substantially the same.

[0167] Each of the first light-emitting units EU1' to the third light-emitting units EU3' may include a light-emitting layer that generates light according to an applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit or a first electron transport layer ETU1', and a first hole transport unit or a first hole transport layer HTU1'. The first light-emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit or a second electron transport layer ETU2', and a second hole transport unit or a second hole transport layer HTU2'. The second light-emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit or a third electron transport layer ETU3', and a third hole transport unit or a third hole transport layer HTU3'. The third light-emitting layer EML3' can be disposed between the third electron transmission unit ETU3' and the third hole transmission unit HTU3'.

[0168] Each of the first hole transport units HTU1' to the third hole transport units HTU3' may include at least one of a hole injection layer and a hole transport layer, and may also include a hole buffer layer, an electron blocking layer, etc., if needed or desired. The first hole transport units HTU1' to the third hole transport units HTU3' may have the same or substantially the same structure as each other, or may be different from each other.

[0169] Each of the first electron transport units ETU1' to the third electron transport units ETU3' may include at least one of an electron injection layer and an electron transport layer, and may also include an electron buffer layer, a hole blocking layer, etc., if needed or desired. The first electron transport units ETU1' to the third electron transport units ETU3' may have the same or substantially the same structure as each other, or may be different from each other.

[0170] The first charge generation layer CGL1' is disposed between the first light-emitting unit EU1' and the second light-emitting unit EU2'. The second charge generation layer CGL2' is disposed between the second light-emitting unit EU2' and the third light-emitting unit EU3'.

[0171] In some embodiments, the first light-emitting layers EML1' to the third light-emitting layers EML3' can produce light of different colors from each other. The light emitted by each of the first light-emitting layers EML1' to the third light-emitting layers EML3' can be mixed together and can be considered as white light. For example, the first light-emitting layer EML1' can produce blue light, the second light-emitting layer EML2' can produce green light, and the third light-emitting layer EML3' can produce red light.

[0172] In other embodiments, two or more of the first light-emitting layers EML1' to the third light-emitting layers EML3' can produce light of the same color as each other.

[0173] Reference above Figure 7 and Figure 8 The descriptions differ, see above for reference. Figure 6 The described light-emitting structure EMS may include a light-emitting unit or a light-emitting stack in each of the first light-emitting element LD1 to the third light-emitting element LD3. In this case, the light-emitting units included in each of the first light-emitting element LD1 to the third light-emitting element LD3 may emit light of different colors from each other. For example, the light-emitting unit of the first light-emitting element LD1 may emit red light, the light-emitting unit of the second light-emitting element LD2 may emit green light, and the light-emitting unit of the third light-emitting element LD3 may emit blue light. In this case, as referenced above... Figure 6 Depending on the description, the light-emitting units of the first sub-pixel SP1 to the third sub-pixel SP3 can be spaced apart from each other (e.g., they can be separated from each other), and each of them can be set in the corresponding opening OP of the pixel-defining layer PDL. In this case, at least some of the color filters CF1 to CF3 can be omitted as needed or desired.

[0174] Figure 9 This illustrates an embodiment. Figure 4 A planar image of a single pixel.

[0175] Reference Figure 9 The first pixel PXL1' may include the first sub-pixel SP1' to the third sub-pixel SP3'.

[0176] The first sub-pixel SP1' may include a first emission region EMA1' and a non-emission region NEA' surrounding the first emission region EMA1'. The second sub-pixel SP2' may include a second emission region EMA2' and a non-emission region NEA' surrounding the second emission region EMA2'. The third sub-pixel SP3' may include a third emission region EMA3' and a non-emission region NEA' surrounding the third emission region EMA3'.

[0177] The first sub-pixel SP1' and the second sub-pixel SP2' can be arranged along the second direction DR2. The third sub-pixel SP3' can be arranged relative to each of the first sub-pixel SP1' and the second sub-pixel SP2' along the first direction DR1.

[0178] The second sub-pixel SP2' may have a larger area than the first sub-pixel SP1', and the third sub-pixel SP3' may have a larger area than the second sub-pixel SP2'. Therefore, the second emission region EMA2' may have a larger area than the first emission region EMA1', and the third emission region EMA3' may have a larger area than the second emission region EMA2'. However, this disclosure is not limited thereto. For example, the first sub-pixel SP1' and the second sub-pixel SP2' may have the same or substantially the same area as each other, and the third sub-pixel SP3' may have an area larger than each of the first sub-pixel SP1' and the second sub-pixel SP2'. As described above, the areas of the first sub-pixels SP1' to the third sub-pixels SP3' can be modified in various ways as needed or desired.

[0179] Figure 10 This illustrates an embodiment. Figure 4 A planar image of a single pixel.

[0180] Reference Figure 10 The first pixel PXL1'' may include first sub-pixels SP1'' to third sub-pixels SP3''. The first sub-pixel SP1'' may include a first emitting region EMA1'' and a non-emitting region NEA'' surrounding the first emitting region EMA1''. The second sub-pixel SP2'' may include a second emitting region EMA2'' and a non-emitting region NEA'' surrounding the second emitting region EMA2''. The third sub-pixel SP3'' may include a third emitting region EMA3'' and a non-emitting region NEA'' surrounding the third emitting region EMA3''.

[0181] When viewed on a third-party DR3 (e.g., in a planar view), the first sub-pixel SP1'' to the third sub-pixel SP3'' can have polygonal shapes. For example, the shapes of the first sub-pixel SP1'' to the third sub-pixel SP3'' can be as follows: Figure 10 The hexagonal shape shown.

[0182] When viewed on a third-party DR3 (e.g., in a plan view), the first emission region EMA1'' to the third emission region EMA3'' may have a circular shape. However, this disclosure is not limited thereto. For example, each of the first emission region EMA1'' to the third emission region EMA3'' may have a polygonal shape.

[0183] The first sub-pixel SP1'' and the third sub-pixel SP3'' can be arranged along the first direction DR1. The second sub-pixel SP2'' can be set in a direction that is tilted at an acute angle relative to the first sub-pixel SP1'' based on the second direction DR2 (e.g., a diagonal direction).

[0184] supply Figure 5 , Figure 9 and Figure 10 The arrangement of subpixels shown is an example, and this disclosure is not limited thereto. Each pixel may include two or more subpixels SP, the subpixels SP may be arranged in various suitable ways, the subpixels SP may have various suitable shapes, and their emission regions EMA1, EMA2, and EMA3 may also have various suitable shapes.

[0185] Figure 11 This is a block diagram illustrating a display system according to an embodiment.

[0186] Reference Figure 11 The display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220.

[0187] Processor 1100 can perform various suitable tasks and calculations. In some embodiments, processor 1100 may include an application processor, graphics processor, microprocessor, central processing unit (CPU), etc. Processor 1100 can be connected to other components of display system 1000 via a bus system and can control other components.

[0188] exist Figure 11 In the display system 1000, there are a first display device 1210 and a second display device 1220. The processor 1100 can be connected to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0189] Through the first channel CH1, the processor 1100 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 can be configured as described above. Figure 1 The described display device 100 is the same as or substantially the same as (or similar to). In this case, the first image data IMG1 and the first control signal CTRL1 can be provided respectively as referenced above. Figure 1 The input image data IMG and control signal CTRL are described.

[0190] Through the second channel CH2, the processor 1100 can transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 can be configured as described above. Figure 1The described display device 100 is the same as or substantially the same as (or similar to). In this case, the second image data IMG2 and the second control signal CTRL2 can be provided respectively as referenced above. Figure 1 The input image data IMG and control signal CTRL are described.

[0191] Display system 1000 may include a computing system (such as a portable computer, mobile phone, smartphone, tablet PC, smartwatch, watch phone, portable multimedia player (PMP), navigation device, and ultra-mobile personal computer (UMPC)) for providing image display functionality. Additionally, display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0192] Figure 12 It is shown Figure 11 A perspective view of an application example of the display system.

[0193] Reference Figure 12 The above reference Figure 11 The described display system 1000 can be applied to a head-mounted display device 2000. The head-mounted display device 2000 can be a wearable electronic device that can be worn on a user's head.

[0194] The head-mounted display device 2000 may include a headband 2100 and a display device housing 2200. The headband 2100 may be connected to the display device housing 2200. The headband 2100 may include a horizontal strap and / or a vertical strap for securing the head-mounted display device 2000 to a user's head. The horizontal strap may surround the side of the user's head (e.g., around the periphery of the side of the user's head), and the vertical strap may surround the upper part of the user's head (e.g., around the periphery of the upper part of the user's head). However, this disclosure is not limited thereto. For example, the headband 2100 may be implemented in the form of an eyeglass frame, a helmet, etc.

[0195] The display device housing 2200 can accommodate the above reference. Figure 11 The first display device 1210 and the second display device 1220 are described. The display device housing 2200 can also accommodate the above-mentioned reference. Figure 11 The processor 1100 is described.

[0196] Figure 13 It shows what the user is wearing. Figure 12 A diagram of a head-mounted display device.

[0197] Reference Figure 13In the head-mounted display device 2000, a first display panel DP1 of a first display device 1210 and a second display panel DP2 of a second display device 1220 are provided. The head-mounted display device 2000 may also include one or more lenses LLNS and RLNS.

[0198] Within the display device housing 2200, the right eye lens RLNS can be positioned between the first display panel DP1 and the user's right eye. Within the display device housing 2200, the left eye lens LLNS can be positioned between the second display panel DP2 and the user's left eye.

[0199] The image output from the first display panel DP1 can be displayed to the user's right eye via the right eye lens RLNS. The right eye lens RLNS can refract light from the first display panel DP1 to guide it toward the user's right eye. The right eye lens RLNS can perform optical functions to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0200] The image output from the second display panel DP2 can be displayed to the user's left eye via the left eye lens LLNS. The left eye lens LLNS can refract light from the second display panel DP2 to guide it towards the user's left eye. The left eye lens LLNS can perform optical functions to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0201] In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens with a pancake-shaped profile. In some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens comprising sub-regions with different optical properties. In this case, each display panel can output an image corresponding to a sub-region of the multi-channel lens, and the output image can pass through its respective sub-region and can be displayed to the user.

[0202] Figure 14 It is shown Figure 13 The diagram shows the distance between the display panel and the user's eyes. Figure 14 The display panel DP shown can be Figure 13 One of the first display panel DP1 and the second display panel DP2 shown in the figure. Figure 14 The lens LNS shown can be Figure 13 The image shows one of the right-eye lens RLNS and the left-eye lens LLNS. See the reference above. Figure 4 As described, Figure 14 The display panel DP is shown as including a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a packaging layer TFE, an optical functional layer OFL, an outer coating OC, and a cover window CW.

[0203] Reference Figure 14 Light from the display panel DP passes through the lens LNS and is directed to the user's left or right eye. Thus, the lens LNS can have a focal length (e.g., a specific or predetermined focal length) FL. In the head-mounted display device 2000, the display panel DP and the lens LNS can be set to be spaced apart from each other by a distance D1. In this case, the distance from the top of the display panel DP to the user's eye is "D1+FL".

[0204] like Figure 14 As shown, the lens LNS is positioned at an appropriate distance (e.g., a specific or predetermined distance) from the display panel DP, so that the image output from the display panel DP can be viewed by the user's eyes. Furthermore, it is desirable that the appropriate distance from the lens LNS to the user's eyes ensures that the image output from the display panel DP can be viewed by the user's eyes. Thus, the size of the display device housing 2200 may increase. Therefore, due to the increased overall size and weight of the head-mounted display device 2000, user convenience may decrease.

[0205] According to some embodiments of this disclosure, the display panel DP includes an optical path conversion unit or optical path conversion layer that converts the path of light generated from each sub-pixel SP. Therefore, the distance between the display panel DP and the user's eyes can be shortened, and the size and weight of the head-mounted display device can be reduced.

[0206] Figure 15 This is a cross-sectional view showing the display panel of a display device according to an embodiment.

[0207] Reference Figure 15 According to another embodiment of the present disclosure, the display panel DPa of the display device may include an optical path conversion unit or an optical path conversion layer OPC. For example... Figure 15 As shown, in some embodiments, the optical path conversion unit (OPC) can be formed at the topmost portion of the display panel (DPa). As used herein, the pixel circuit layer (PCL), light-emitting element layer (LDL), encapsulation layer (TFE), and optical functional layer (OFL) sequentially formed on the substrate (SUB) can be referred to as the "pixel structure layer." The pixel circuit layer (PCL), light-emitting element layer (LDL), encapsulation layer (TFE), and optical functional layer (OFL) included in the pixel structure layer constitute multiple sub-pixels (SPs). Figure 15 In this process, the optical path conversion unit (OPC) can be formed on the pixel structure layer.

[0208] For example, such as Figure 15 As shown, the optical path conversion unit (OPC) can be formed on the optical functional layer (OFL) of the display panel (DPa). See also... Figure 14 and Figure 15 The above reference Figure 14The described display panel DP includes an outer coating OC and a cover window CW on the optical functional layer OFL. However, in Figure 15 In the display panel DPa, the optical path conversion unit OPC can be formed on the optical functional layer OFL, and the outer coating OC and the cover window CW may not be included in the display panel DPa. However, this disclosure is not limited thereto, and the display panel DPa may include at least one of the outer coating OC and the cover window CW on or below the optical path conversion unit OPC.

[0209] The light path conversion unit (OPC) converts the path of light generated from each sub-pixel SP of the display panel DPa. In some embodiments, the OPC can converge the light generated from each sub-pixel SP of the display panel DPa to the user's eye. In other words, the OPC may include a lens with a focal length FL. Because the OPC converges light from the display panel DPa, the head-mounted display device 2000 may include only the display panel DPa and may not include the aforementioned reference. Figure 14 The lens LNS described above. As another example, a head-mounted display device may include lenses with a larger diameter than those described above. Figure 14 The lens LNS is described as a short focal length lens, and the display panel DPa is described as such.

[0210] Therefore, the distance between the display panel DPa of the head-mounted display device and the user's eyes can be shortened, and the size and weight of the head-mounted display device can be reduced.

[0211] exist Figure 15 In this embodiment, the light path conversion unit (OPC) is shown to converge light generated from the display panel DPa, but this disclosure is not limited thereto. For example, the OPC can emit light generated from the display panel DPa. In another example, instead of converging or emitting light generated from the display panel DPa, the OPC can simply change the direction of light travel. According to embodiments, the OPC can converge or emit light generated from the display panel DPa and can change the direction of light travel.

[0212] As used here, the optical path conversion unit (OPC) can be referenced above. Figure 4 The described lens array LA is distinct from, or distinguished from, the first lenses LS1 to the third lenses LS3 included in the lens array LA. Each of the first lenses LS1 to the third lenses LS3 included in the lens array LA outputs light emitted from the light-emitting element of the corresponding sub-pixel SP to the desired path. In contrast, the optical path conversion unit OPC changes the path of light emitted from the light-emitting elements included in the entire pixel structure layer of the display panel DPa.

[0213] Figure 16This illustrates an embodiment. Figure 15 A diagram of the optical path conversion unit.

[0214] Reference Figure 16 The illustration shows a display panel DPa1 implemented with a Fresnel lens for the optical path conversion unit or optical path conversion layer OPC1. Unlike the curved surface of an optical lens, a Fresnel lens can include multiple grooves with a concentric shape. Each groove of the Fresnel lens can act as an individual refractive surface and can refract light. When a Fresnel lens is used as the optical path conversion unit OPC1, the thickness and weight of the optical path conversion unit can be reduced. In an embodiment, the Fresnel lens can be formed on the upper layer of the display panel DPa1 to have a sheet shape.

[0215] Figures 17A to 17E It shows the manufacturing process. Figure 16 A diagram showing the method of displaying the panel.

[0216] Reference Figure 17A A pixel circuit layer (PCL), a light-emitting element layer (LDL), a packaging layer (TFE), and an optical functional layer (OFL) are sequentially formed on a substrate (SUB). In other words, a pixel structure layer is formed on the substrate (SUB). (See reference...) Figure 17B Subsequently, a resin layer EPX is formed on the optical functional layer (OFL) of the pixel structure layer. The resin layer EPX may include epoxy resin. However, the material of the resin layer is not limited to this.

[0217] Reference Figure 17C A mold MLD with a Fresnel lens pattern can be pressed onto the resin layer EPX. Therefore, the upper surface of the resin layer EPX can be transformed into the shape of a Fresnel lens. (See reference...) Figure 17D The EPX resin layer can be cured by irradiating it with ultraviolet light while the MLD mold is pressed onto the EPX resin layer. Afterwards, as... Figure 17E As shown, the mold MLD is separated from the resin layer. The separated resin layer can become an optical path conversion unit OPC1 implemented with a Fresnel lens having a pattern corresponding to the pattern of the mold MLD. Figures 17A to 17E As shown, when a Fresnel lens is formed by coating a resin layer EPX onto the optical functional layer OFL, the thickness of the optical path conversion unit OPC1 can be reduced, and therefore the thickness of the display panel DPa1 can also be reduced.

[0218] A Fresnel lens formed of epoxy resin on a pixel structure layer can be partially used as an outer coating OC. In other words, the cured resin layer EPX can protect the underlying layer from foreign matter such as dust or moisture.

[0219] Figures 18A to 18C This illustrates one or more embodiments. Figure 15A diagram of the optical path conversion unit.

[0220] Reference Figure 18A This illustrates a display panel DPa2 implemented using a convex lens for the optical path conversion unit or optical path conversion layer OPC2. (Refer to...) Figure 18B This illustrates a display panel DPa3 implemented using a concave lens for the optical path conversion unit or optical path conversion layer OPC3. (Refer to...) Figure 18C This illustrates a display panel DPa4 implemented using an aspherical lens for the optical path conversion unit or optical path conversion layer OPC4.

[0221] Although the above reference Figure 16 The described Fresnel lens may be desirable in terms of thickness and weight, but spherical or aspherical lenses may be desirable in terms of the quality of the image perceived by the user's eye. Therefore, in some embodiments, such as Figures 18A to 18C As shown, the optical path conversion units OPC2, OPC3 and OPC4 can be implemented using convex lenses, concave lenses or aspherical lenses.

[0222] Figure 19 This illustrates an embodiment. Figure 15 A diagram of the optical path conversion unit.

[0223] Reference Figure 19 The optical path conversion unit or optical path conversion layer OPC5 included in the display panel DPa5 may include a resin layer EPX and a reflective layer RFL. The reflective layer RFL can change the direction of light movement by reflecting light generated from each sub-pixel of the display panel DPa5. In an embodiment, the reflective layer RFL may be formed at a 45-degree angle relative to the direction of light travel emitted from the sub-pixel. In this case, the incident light entering the reflective layer RFL and the reflected light reflected from the reflective layer RFL may form a 90-degree angle with each other. When the optical path conversion unit OPC5 included in the display panel DPa5 includes the reflective layer RFL, the placement of the display panel DPa5 can be designed more freely in the head-mounted display device. The reflective layer RFL may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and suitable alloys selected from two or more of these materials, but this disclosure is not limited thereto.

[0224] exist Figure 19In this diagram, the optical path conversion unit OPC5 is shown as a planar shape with a reflective layer RFL, but this disclosure is not limited thereto. For example, the optical path conversion unit may include a reflective layer with a curved shape. In this case, the optical path conversion unit can change the direction of light generated from the sub-pixel and converge or emit the light generated from the sub-pixel. For example, when the reflective layer has the shape of a convex mirror, the optical path conversion unit can change the direction of light generated from the sub-pixel and emit the light. Additionally, when the reflective layer has the shape of a concave mirror, the optical path conversion unit can change the direction of light generated from the sub-pixel and converge the light. Furthermore, the reflective layer may have the shape of an aspherical mirror.

[0225] Figure 20A and Figure 20B This is a cross-sectional view showing the display panel of a display device according to one or more embodiments.

[0226] Reference Figure 20A The display panel DPb may also include a protective layer PL formed on the optical path conversion unit OPC. The protective layer PL may include various materials suitable for protecting the optical path conversion unit OPC, such that the optical path conversion unit OPC retains or substantially retains its optical properties. For example, the protective layer PL may include a polymer, but this disclosure is not limited thereto.

[0227] Reference Figure 20B When the display panel DPb1 includes a light path conversion unit or light path conversion layer OPC1 implemented with a Fresnel lens, a protective layer PL can be formed on the light path conversion unit OPC1. After the Fresnel lens is formed and cured, the protective layer PL can be formed on the Fresnel lens to protect the surface shape of the Fresnel lens.

[0228] In some embodiments, a cover window may be further formed on the protective layer PL.

[0229] In addition, Figure 20B The image shows an embodiment of the optical path conversion unit OPC1 implemented using a Fresnel lens, but this disclosure is not limited thereto. For example, Figure 20A The optical path conversion unit OPC shown may include at least one of the following: convex lens, concave lens, aspherical lens, plane mirror, convex mirror, concave mirror, and aspherical mirror.

[0230] Figure 21 This is a cross-sectional view showing the display panel of a display device according to an embodiment.

[0231] Reference Figure 21 An embodiment is shown where the optical path conversion unit (OPC) is mounted on the display panel (DPc) on the cover window (CW). Figures 15 to 20BIn the illustrated embodiment, the optical path conversion unit is formed on the optical functional layer OFL included in the pixel structure layer, and the outer coating OC and the cover window CW are not included in the display panel. However, according to Figure 21 In the embodiment shown, the outer coating OC and the cover window CW are formed on the optical functional layer OFL of the pixel structure layer, and the optical path conversion unit OPC is formed on the outer coating OC and the cover window CW.

[0232] Figure 22 This is a cross-sectional view showing the display panel of a display device according to an embodiment.

[0233] Reference Figure 22 The image shows a display panel DPd with a polarizing film layer (PFL) included between the optical path conversion unit (OPC) and the cover window (CW). By placing the polarizing film layer (PFL) below the OPC, the characteristics of the light transmitted to the OPC can be improved.

[0234] exist Figure 22 The illustration shows an embodiment in which a cover window (CW) is formed on an outer coating (OC), a polarizing film layer (PFL) is formed on the cover window (CW), and an optical path conversion unit (OPC) is formed on the polarizing film layer (PFL), but the disclosure is not limited thereto.

[0235] According to the embodiments, the above references can be omitted. Figure 22 The described overlay window (CW) is shown. In this case, the polarizing film layer (PFL) can be formed on the outer coating layer (OC), and the optical path conversion unit (OPC) can be formed on the polarizing film layer (PFL).

[0236] According to an embodiment, the polarizing film layer PFL can be disposed below the cover window CW. In this case, the polarizing film layer PFL can be formed on the outer coating OC, the cover window CW can be formed on the polarizing film layer PFL, and the optical path conversion unit OPC can be formed on the cover window CW.

[0237] According to an embodiment, the cover window CW can be disposed on the optical path conversion unit OPC. In this case, the polarizing film layer PFL can be formed on the outer coating layer OC, the optical path conversion unit OPC can be formed on the polarizing film layer PFL, and the cover window CW can be formed on the optical path conversion unit OPC.

[0238] Figure 23 This is a cross-sectional view showing the display panel of a display device according to an embodiment.

[0239] Reference Figure 23The diagram illustrates a display panel DPe comprising a wire-grid polarizing layer (e.g., a wire-grid polarizer) WGP between an optical path conversion unit (OPC) and an outer coating (OC). The wire-grid polarizing layer WGP is a polarizing layer with a metal pattern at a nanoscale. When light is incident on the wire-grid polarizing layer WGP, the polarization component parallel to the metal pattern (e.g., S-polarization) is reflected, and the polarization component perpendicular to the metal pattern (e.g., P-polarization) is transmitted. By placing the wire-grid polarizing layer WGP below the optical path conversion unit (OPC), the characteristics of the light transmitted to the OPC can be improved.

[0240] exist Figure 23 The illustration shows an embodiment in which a wire grating polarization layer (WGP) is formed on an outer coating layer (OC) and an optical path conversion unit (OPC) is formed on the wire grating polarization layer (WGP). However, this disclosure is not limited thereto.

[0241] According to one embodiment, the cover window CW can be placed between the outer coating OC and the wire grid polarization layer WGP. In another embodiment, the cover window CW can be placed between the wire grid polarization layer WGP and the optical path conversion unit OPC. In yet another embodiment, the cover window CW can be disposed on the optical path conversion unit OPC.

[0242] Figures 24A to 24F This illustrates the manufacturing process according to an embodiment. Figure 16 A diagram showing the method of displaying the panel.

[0243] Reference Figure 24A A pixel circuit layer (PCL), a light-emitting element layer (LDL), a packaging layer (TFE), and an optical functional layer (OFL) are sequentially formed on a substrate (SUB). In other words, a pixel structure layer is formed on the substrate (SUB). (See reference...) Figure 24B A dammed optical array (DAM) can be formed around the pixel structure layer, or in other words, around the display area that includes subpixels. The dammed DAM can be used to maintain the stacked form of the subpixels during the process of forming the optical path conversion unit (OPC1) on the pixel structure layer. The dammed DAM can be formed around the display area formed by the subpixels (e.g., around the periphery of the display area formed by the subpixels).

[0244] Reference Figure 24C Subsequently, a resin layer EPX can be formed on the dam DAM and pixel structure layers. The resin layer EPX may include epoxy resin. However, the materials used to form the resin layer are not limited to this.

[0245] Reference Figure 24D A mold MLD with a Fresnel lens pattern can be pressed onto the resin layer EPX. Therefore, the upper surface of the resin layer EPX is transformed into the shape of a Fresnel lens. At this time, a portion of the pressure transmitted from the mold MLD can be transmitted to the lower part of the resin layer EPX. For example... Figure 24DAs shown, the dam DAM formed around the display area formed by subpixels (e.g., around the periphery of the display area formed by subpixels) resists pressure transmitted from the resin layer EPX. Therefore, even if pressure is transmitted to the lower part of the resin layer EPX, the pixel structure layer surrounded by the dam DAM can maintain the stacked form of the subpixels.

[0246] Reference Figure 24E The EPX resin layer can be cured by irradiating it with ultraviolet light while the MLD mold is pressed onto the EPX resin layer. Afterwards, as... Figure 24F As shown, the mold MLD is separated from the resin layer. The separated resin layer becomes the optical path conversion unit OPC1, which is implemented using a Fresnel lens with a pattern corresponding to the pattern of the mold MLD.

[0247] Reference Figure 24A and Figure 24B After sequentially forming the pixel circuit layer PCL, the light-emitting element layer LDL, the encapsulation layer TFE, and the optical functional layer OFL on the substrate SUB, the dam DAM is formed, but this disclosure is not limited thereto. For example, the dam DAM can be formed on the substrate SUB, and then the pixel circuit layer PCL, the light-emitting element layer LDL, the encapsulation layer TFE, and the optical functional layer OFL can be formed sequentially.

[0248] The foregoing is a description of some embodiments of this disclosure and is not to be construed as limiting it. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications can be made to the embodiments without departing from the spirit and scope of this disclosure. It will be understood that, unless otherwise described, the description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Therefore, as will be apparent to those skilled in the art, unless specifically stated otherwise, features, characteristics, and / or elements described in connection with a particular embodiment can be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments. Therefore, it will be understood that the foregoing is a description of various exemplary embodiments and is not to be construed as limiting to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included within the spirit and scope of this disclosure as defined in the appended claims and their equivalents.

Claims

1. A display panel, the display panel comprising: Base; A pixel structure layer, on the substrate, includes multiple sub-pixels; as well as An optical path conversion unit is located on the pixel structure layer and is configured to convert the path of light generated from the pixel structure layer.

2. The display panel according to claim 1, wherein, The optical path conversion unit is configured to converge the light generated from the pixel structure layer.

3. The display panel according to claim 2, wherein, The optical path conversion unit includes a Fresnel lens on the pixel structure layer.

4. The display panel according to claim 2, wherein, The optical path conversion unit includes a spherical lens or an aspherical lens on the pixel structure layer.

5. The display panel according to claim 1, wherein, The optical path conversion unit includes a reflective layer configured to change the direction of travel of the light generated from the pixel structure layer.

6. The display panel according to claim 1, further comprising: A protective layer is provided on the optical path conversion unit.

7. The display panel according to claim 1, further comprising: A cover window is located between the pixel structure layer and the optical path conversion unit; as well as A polarizing film layer is located between the cover window and the optical path conversion unit.

8. The display panel according to claim 1, further comprising: A wire grid polarization layer is located between the pixel structure layer and the optical path conversion unit.

9. The display panel according to claim 1, further comprising: A dam surrounds the pixel structure layer.

10. The display panel according to claim 1, wherein, The pixel structure layer includes: A pixel circuit layer on the substrate; A light-emitting element layer is placed on the pixel circuit layer; and An optical functional layer is provided on the light-emitting element layer, wherein: The pixel circuit layer includes at least one transistor; The light-emitting element layer includes a positive electrode, a light-emitting structure, and a negative electrode; and The optical functional layer includes a color filter layer and a lens array.

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