Voltage range for training physical memory

Abstract

A voltage range for training a physical memory is described. An apparatus can be configured to include a PHY having an interface to support communication of command signals and data with a physical memory. The PHY implements: a training mode for training the interface within a training voltage range to transmit the command signal or data; and an operating mode for using the trained interface to communicate the command signal or data within an operating voltage range that is smaller than the training voltage range.

Description

[0001] Related applications This application claims priority to U.S. Patent Application Serial No. 18 / 305,080, filed April 21, 2023, entitled “Voltage Range for Training Physical Memory,” the entire disclosure of which is incorporated herein by reference in its entirety. Background Technology

[0002] The amount of data and the speed at which computing devices can access data from physical memory are driving factors in overall device operation. Due to this operational effect, technologies are continuously developed to improve the speed, accuracy, and storage capacity of physical memory, examples of which include dynamic random access memory (DRAM). However, this ongoing development has encountered additional challenges affecting when data can be accessed from physical memory, challenges arising from environmental conditions affecting the operation of physical memory (e.g., heat), and so on. Attached Figure Description

[0003] The specific implementation method is described with reference to the accompanying drawings.

[0004] Figure 1 This is a block diagram of a non-limiting example system configured to employ training and operation mode techniques as described herein.

[0005] Figure 2 To show in more detail Figure 1 A block diagram of a non-limiting example system of a PHY configuration, which is communicatively coupled via an interface to a physical memory implemented using multiple dynamic random access memory (DRAM) devices.

[0006] Figure 3 This is a block diagram of a non-limiting example system showing the training voltage range of the training mode and the operating voltage range of the operating mode.

[0007] Figure 4 This is a block diagram of a non-limiting example system illustrating the personalized programmability of a dynamic random access memory (DRAM) device that implements the training voltage range for the training mode and the operating voltage range for the operating mode.

[0008] Figure 5 The process in an example implementation of a training and operating mode voltage range for an interface that communicatively couples the PHY to the physical memory is described. Detailed Implementation

[0009] Overview The PHY (also known as the physical layer) is typically implemented as an integrated circuit to provide a physical interface in the hardware between processing units (e.g., central processing units) and physical memory (e.g., dynamic random access memory). The PHY is responsible for converting digital data from the processing unit into analog electrical signals, which are then transmitted to the physical memory via the physical interface. Similarly, the PHY is also responsible for converting analog electrical signals received through the physical interface into digital data for use by the processing unit.

[0010] As part of implementing the physical interface, the PHY performs training (e.g., at startup and adjustable during operation) to set the parameters of the physical interface for optimized communication. The PHY can use training to address design differences between the processing unit and physical memory, changes in operating conditions (e.g., temperature), and so on. Examples of parameters set as part of the training include impedance calibration, set by adjusting the terminating resistor values ​​in the PHY and physical memory. Impedance calibration is used to match the impedances of the transmitter and receiver utilized by the physical interface between the PHY and physical memory to reduce signal reflections and maintain signal integrity. As part of the training, voltage and timing reference parameters are also set by adjusting voltage levels and clock phase to establish a common voltage and timing reference for signals transmitted between the PHY and physical memory. As part of the training, read and write equalization is set by adjusting the relative timing of the clock and data signals on the physical interface to coordinate data sampling. For example, a data strobe signal (DQS) is aligned with the data signal (DQ) during a read operation to define "when" the data signal is sampled based on the data strobe signal.

[0011] However, conventional techniques for training performed by the PHY are inefficient, consuming a significant amount of time and leading to increased power consumption. Examples of conventional training techniques involve brute-force methods or rely on prior knowledge of the device. In conventional brute-force methods, the PHY tests a range of possible values ​​for each parameter (e.g., impedance, voltage and timing reference, equalization settings, clock phase, etc., as described above). Therefore, the PHY is delegated to compare and evaluate every combination of parameters to identify the optimal combination that produces the best results, such as the highest communication speed that also supports reliable communication. Consequently, conventional brute-force methods can consume significant resources when evaluating a potentially large number of parameter combinations.

[0012] A priori methods rely on careful measurement and characterization of components to establish parameters. For example, in a priori methods, impedance and data throughput are measured and characterized for the physical connection between the PHY and physical memory. However, such measurements and resulting characterizations are difficult to accurately achieve in real-world scenarios due to variations in component manufacturing processes and can vary due to changing environmental conditions encountered during typical component operation.

[0013] To address these technical challenges, the PHY implements a training mode to train parameters that form part of the physical interface supporting communication of data and command signals between the PHY and physical memory. Once the parameters of the physical interface are set by the training mode, an operating mode is used to support increased signal rates for data and command signals.

[0014] In training mode, the PHY uses a first voltage range to determine the values ​​of the parameters described above. For example, the voltage reference (Vref) parameter has values ​​learned as part of the training. The voltage reference parameter defines a stable reference voltage that can be used as a midpoint reference voltage as part of differential signaling to distinguish high logic levels from low logic levels, such as distinguishing one from zero, based on whether the detected voltage level is higher or lower than the reference voltage. Therefore, training the voltage reference parameter by the PHY involves determining a reference voltage at which the voltage reference parameter will be set.

[0015] To determine the value of the voltage reference (Vref) parameter, the PHY sets a first voltage range as part of the training mode. This first voltage range is set by the PHY by modifying the termination state (e.g., using a termination resistor to electrically terminate the transmission line) and the output impedance to allow for weak termination at physical memory to support rail-to-rail voltage swings (e.g., from 0.1 volts to 1.1 volts). The initial value of the voltage reference (Vref) parameter is then set within this "known good" first range and subsequently optimized along with other parameters of the training physical interface, as described above.

[0016] Once the voltage reference (Vref) parameter and other parameters are set during training mode, the PHY initiates an operating mode with a reduced signal range to support increased signal speed, for example, from 0.85 volts to 1.1 volts. For example, changes in voltage levels within the increased voltage range in training mode take longer to execute than changes within the reduced voltage range in operating mode. However, during training performed in training mode, the larger voltage range is used to improve the training efficiency of the physical interface (e.g., by using a known good Vref) because the signal speed at that point in time has a lower priority than achieving the overall trained interface. Once training is complete, the reduced voltage range is used in operating mode to increase the signal speed. Further discussion of these and other examples is included in the following sections and is illustrated in the corresponding figures.

[0017] In some aspects, the technology described herein relates to a device comprising: a physical layer (PHY) having an interface supporting command signals and data communication with physical memory, the PHY implementing: a training mode for training the interface to transmit the command signals or data within a training voltage range; and an operating mode for using the trained interface to transmit the command signals or data within an operating voltage range smaller than the training voltage range.

[0018] In some respects, the technology described herein relates to a device in which the interface implements an interface protocol that employs parameters for controlling the communication of command signals and data with the physical memory.

[0019] In some respects, the technology described herein relates to a device in which the training mode detects the value of the parameter of the interface protocol, and the operating mode uses the detected parameter.

[0020] In some respects, the technology described herein relates to a device in which the parameter relates to a signal or timing.

[0021] In some respects, the technology described herein relates to a device in which the parameter relates to voltage reference (Vref) training, command training, clock-to-gated equalization, write equalization training, or gated-to-DQ training of the interface protocol.

[0022] In some respects, the technology described herein relates to a device in which the parameter relates to how a signal propagates from one physical memory component of the physical memory to another physical memory component of the physical memory.

[0023] In some respects, the technology described herein relates to a device in which the training mode is configured to modify the termination state or output impedance of the PHY to achieve the training voltage range of the training mode.

[0024] In some respects, the technology described herein relates to a device in which the training mode is further configured to, as part of the training mode, modify the termination state or output impedance of the physical memory to achieve the training voltage range.

[0025] In some respects, the technology described herein relates to a device in which the training mode operates at a lower frequency than the operating mode.

[0026] In some respects, the technology described herein relates to a device in which the PHY includes another interface for transmitting command signals and data to a memory controller.

[0027] In some respects, the technology described herein relates to a device in which the PHY is implemented in hardware as part of an integrated circuit, the interface is bidirectional, and the physical memory is dynamic random access memory (DRAM).

[0028] In some aspects, the technology described herein relates to a system comprising: a memory controller; dynamic random access memory (DRAM); and a physical layer (PHY) providing communication coupling with the memory controller and the DRAM, the PHY implementing: a training mode, as part of training the interface between the PHY and the DRAM, the training mode for detecting values ​​of parameters, the training mode operating within a training voltage range; and an operating mode for implementing the interface between the PHY and the DRAM using the detected values ​​of the parameters, the operating mode operating within an operating voltage range smaller than the training voltage range.

[0029] In some respects, the technology described herein relates to a system in which the training mode is configured to modify the termination state and output impedance of the PHY to achieve the training voltage range of the training mode.

[0030] In some respects, the technology described herein relates to a system in which the training mode is further configured to, as part of the training mode, modify the termination state and output impedance of the dynamic random access memory (DRAM) to achieve the training voltage range.

[0031] In some respects, the techniques described herein relate to a system in which the parameter includes a signal or timing.

[0032] In some respects, the techniques described herein relate to a system in which the parameter includes voltage reference (Vref) training.

[0033] In some respects, the techniques described herein relate to a system in which the parameters include command training, clock-to-gated equalization, or gated-to-DQ training.

[0034] In some aspects, the technology described herein relates to a method comprising: setting a training mode to train an interface between a physical layer (PHY) and a physical memory to transmit command signals or data, the training mode employing a training voltage range; and setting an operating mode to operate the trained interface between the PHY and the physical memory to transmit command signals or data, the operating mode employing an operating voltage range smaller than the training voltage range.

[0035] In some respects, the techniques described herein relate to a method in which the training mode is configured to modify the termination state and output impedance of the PHY to achieve the training voltage range of the training mode.

[0036] In some respects, the techniques described herein relate to a method in which the training of the interface is voltage reference (Vref) training.

[0037] Figure 1 This is a block diagram of a non-limiting example system 100 configured to employ training and operational mode techniques described herein. These techniques can be used with a wide range of device configurations 102. By way of example and not limitation, examples of such devices include computing devices, servers, mobile devices (e.g., wearable devices, mobile phones, tablets, laptops), processors (e.g., graphics processing units, central processing units, and accelerators), digital signal processors, interference accelerators, disk array controllers, hard disk drive host adapters, memory cards, solid-state drives, wireless communication hardware connections, Ethernet hardware connections, switches, bridges, network interface controllers, and other device configurations. Other examples include artificial intelligence training accelerators, encryption and compression accelerators, network packet processors, and video encoders and decoders. It should be understood that in various specific implementations, without departing from the spirit or scope of the techniques described herein, the techniques described herein can be used with any one or more of the devices just listed above and / or a variety of other devices.

[0038] The illustrated device 102 example includes a processing unit 104 having a core 106 communicatively coupled (e.g., via a bus) to a memory controller 108, which in turn is communicatively coupled (e.g., via a bus) to physical memory 110. The processing unit 104 is configured in hardware to execute instructions as arithmetic and logical operations, to control input / output devices, and to manage data storage and retrieval. The processing unit can be configured as a central processing unit, a graphics processing unit, and other processing units, including digital signal processing, tensor processing units, and field-programmable gate arrays. The core 106, as part of the processing unit 104, can be configured in various ways to execute instructions as part of the processing unit 104 to perform operations, for example, executing an operating system 112, an application program 114, etc., as one or more integrated circuits in hardware. Other configurations are also contemplated, examples of which include parallel processors, graphics processing units, etc.

[0039] In one example, memory controller 108 is configured (e.g., as an integrated circuit in hardware, as a microcontroller configured to execute instructions, etc.) for use with I / O devices, such as as an input / output memory management unit (IOMMU). Memory controller 108 can be configured as part of the processing unit 104 itself (e.g., as an on-die memory controller) or as a separate component on the motherboard of device 102. Although a single instance of physical memory 110 is illustrated, physical memory 110 represents various types of physical memory (e.g., implemented in hardware) that can be implemented together as multiple physical memory components 116, such as volatile and non-volatile memory.

[0040] Memory controller 108 is configured to control access between core 106 and physical memory 110. Memory controller 108 can be configured in hardware, for example, using one or more integrated circuits, to support instruction execution, etc., by being configured as a microcontroller. In the illustrated example, memory controller 108 supports virtual memory address 118 used by core 106 in a virtual address space and physical memory address 120 in the physical address space of physical memory 110. Virtual memory is a technique for managing the use of shared physical memory 110 (e.g., via multiple cores). Virtual memory supports a variety of different functions. Examples of these functions include expanding the amount of memory available to an application beyond the actual amount of memory available in physical memory, offloading memory management from application 114 and operating system 112, using various types of memory without the application's knowledge, supporting memory optimization, addressing memory fragmentation, etc.

[0041] Processing unit 104 employs a physical layer (PHY) 122 to implement a physical interface 124 with physical memory 110. For example, PHY 122 can be configured as hardware (e.g., dedicated or included as part of processing unit 104) communicatively disposed between processing unit 104 and physical memory 110. PHY 122 is configured to support interoperability between processing unit 104 and physical memory 110, even when developed by different manufacturers. To this end, PHY 122 defines signals, timings, and other parameters that can be programmed as part of training to define how command signals and data are transmitted through physical interface 124.

[0042] Training is performed on PHY 122 (e.g., at startup and adjustable during operation) to set parameters of physical interface 124 for optimized communication. Examples of parameters set as part of the training include impedance calibration set by adjusting the terminating resistor values ​​in PHY 122 and physical memory 110. Impedance calibration is used to match the impedances of the transmitter and receiver utilized by physical interface 124 between PHY 122 and physical memory 110 to reduce signal reflections and maintain signal integrity. As part of the training, voltage and timing reference parameters are also set by adjusting voltage levels and clock phase to establish a common voltage and timing reference for signals transmitted between PHY 122 and physical memory 110. As part of the training, read and write equalization is set by adjusting the relative timing of the clock and data signals on physical interface 124 to coordinate data sampling. For example, a data strobe signal (DQS) is aligned with the data signal (DQ) during a read operation to define “when” the data signal is sampled based on the data strobe signal.

[0043] To maximize the speed of command signaling and data communication via physical interface 124, PHY 122 supports training mode 126 and operating mode 128. Training mode 126 operates as a handshake technique to determine the values ​​of programmable parameters to be used to implement the protocol.

[0044] The conventional techniques for performing training are carried out in one of the two ways described above. In the first brute-force example, a significant amount of trial and error is involved when setting and testing different values ​​for the parameters. Due to the large number of parameters being tested and the large number of values ​​available for these parameters, this example suffers from operational inefficiencies, latency, increased power consumption, and so on. In the second example, a priori approach is adopted, which relies on careful measurement and characterization of the processing unit, physical memory, and the interfaces therein, which is difficult to achieve in real-world scenarios. This challenge is further exacerbated when faced with changing environmental conditions.

[0045] To overcome these challenges, a training mode 126 is employed, which uses a training voltage range 130 larger than the operating voltage range 132 used as part of the operating mode 128. In this way, reduced training time and increased accuracy are achieved during training mode 126, while maintaining the faster communication speeds supported by operating mode 128, as further described below.

[0046] During the early stages of training performed by training mode 126, for example, the voltage reference (Vref) setting is not established. Therefore, an asynchronous technique is employed during the initial training phase, during which Vref is not used until its value is determined. To reduce the amount of time spent in training, as part of the training, PHY 122 initially employs a training voltage range 130 to support rail-to-rail voltage swings. These voltage swings define a minimum and a maximum voltage, with the minimum voltage defining logic one (VIH minimum) and the maximum voltage defining logic zero (VIL maximum). This is achieved by modifying the termination state and output impedance of the physical interface 124 between PHY 122 and physical memory 110 to support this increased range (e.g., weakly terminated at physical memory 110).

[0047] Once the asynchronous feedback portion of training mode 126 is complete and the value of Vref is determined, the termination state and output impedance are returned to the operating voltage range 132 by PHY 122. Therefore, once trained, physical interface 124 operates with increased signal speed and improved efficiency using the parameters learned during training mode 126. Thus, the amount of time spent performing the asynchronous portion of training to find the value of Vref is reduced, and the operating mode is implemented within this reduced time, thereby improving device operation.

[0048] Figure 2 This is a block diagram of a non-limiting example system 200 showing a more detailed configuration of PHY 122, which is communicatively coupled via physical interface 124 to a physical memory 110 implemented using multiple dynamic random access memory (DRAM) devices 202(1), ..., 202(N). The PHY 122 shown includes multiple bidirectional transceivers implementing DQ channel 204, DM channel 206, DQS channel 208, command / address channel 210, and clock 212. DQ channel 204 implements data signaling, for example, via corresponding wires illustrated using bidirectional arrows. DM channel 206 carries a data mask signal. The data mask signal is used to selectively enable or disable data writing from DQ channel 204 to memory. When the data mask signal is asserted (active), the corresponding data bit is masked or ignored during a write operation, thereby allowing the memory controller to selectively write data to a specific memory location without affecting adjacent locations. DQS channel 208 implements a data strobe that transmits clock signals for DQ channel 204 and DM channel 206. The data strobe is used, for example, to control the sampling of DQ channel 204 and DM channel 206 based on the rising and falling edges of the signals. For instance, the data strobe of DQS channel 208 is used to control when a data signal is sampled from DQ channel 206 to define a logic one or zero.

[0049] Command / address channel 210 supports the transmission of command signals to DRAM device 202(1) (e.g., to a corresponding transceiver). Various types of command signals and associated addresses are transmitted from PHY 122 using command / address channel 210, examples of which include maintenance, setup, and data-bearing command signals such as "read" and "write". For "read" and "write", command signals are transmitted via the command / address channel, and in a write operation, data is transferred from PHY 122 to DRAM device 202(1) via DQ channel 204, sampled based on a data strobe signal from DQS channel 208. Conversely, data is transferred from DRAM device 202(1) to PHY 122 via DQ channel 204 in a read command, also sampled based on a data strobe signal from DQS channel 208.

[0050] In some cases, multiple DRAM devices are communicatively coupled via physical interface 124 of PHY 122. In one example, this is achieved via a bidirectional multi-branch bus to support communication with DRAM devices 202(1), ..., DRAM devices 202(N). However, the use of a bidirectional multi-branch bus introduces challenges such as signal discontinuities and reflections caused by loads on opposite sides of DRAM device 202(1). For example, a write from PHY 122 to DRAM device 202(N) involves awareness of DRAM device 202(1) on the multi-branch bus between PHY 122 and DRAM device 202(N), for example, to terminate the bus to prevent unwanted signal reflections.

[0051] However, training the physical interface 124 involves a "chicken and egg" problem. For example, training one type of parameter may depend on another type of parameter. Therefore, in practice, training faces non-standardized feedback (i.e., data packets not formed as strobe and data bits) but rather asynchronous feedback constrained by levels with unknown timing relationships. Furthermore, training often depends on sequencing, such as training the command / address channel 210 before training the DQ channel 204.

[0052] Therefore, without knowing the correct timing of the command / address channel 210, and without a correct voltage or time reference for the transceiver implementing the physical interface 124, initial training is performed by the PHY 122. However, the training performed by the PHY 122 still depends on feedback received from the DRAM device and the interpretation of that feedback. As mentioned above, conventional techniques for solving this problem involve brute force, which involves multiple different input voltage levels, reference levels, etc., to determine "what works." On the other hand, prior knowledge involves careful measurement of the hardware, the accuracy of which is limited by manufacturing accuracy, variability, and environmental conditions (e.g., heat).

[0053] Therefore, in this example, PHY 122 utilizes the training voltage range 130 during training mode 126 to provide a larger voltage swing, and thus increased detectability. PHY 122 does this by modifying the physical memory 110 and the termination state and output impedance of PHY 122 itself. For example, the termination state and output impedance are set using the values ​​at the corresponding transistors. Setting the values ​​at the corresponding transistors forces the signal to have a wider swing (e.g., rail-to-rail) in the training voltage range 130. Once training is complete (e.g., the portion involving asynchronous feedback), PHY 122 returns to the operating voltage range 132 using parameters with a smaller voltage swing detected during training mode 126 to support higher data transfer rates.

[0054] Figure 3 This is a block diagram of a non-limiting example system 300 illustrating a training voltage range 130 for training mode 126 and an operating voltage range 132 for operating mode 128. In the illustrated example, a voltage range from zero volts to 1.1 volts is shown for the physical interface 124 between physical memory 110 and PHY 122.

[0055] In operating mode 128, the operating voltage range 132 is limited to between 0.85 volts and 1.1 volts. This is to support higher communication frequencies (in the gigahertz range) by minimizing detected voltage swings (e.g., defining a minimum voltage for logic one (VIH minimum) and a maximum voltage for logic zero (VIL maximum)). This is because shorter voltage swings can be executed in a shorter amount of time to change the voltage on the wires implementing the physical interface 124, and thus support the higher frequencies.

[0056] On the other hand, in training mode 126, communication speed is not a driving factor, and therefore it can be performed at a reduced frequency (e.g., in the megahertz range). Based on this insight, the training voltage range 130 is set between 0.1 volts and 1.1 volts by PHY 122. This is done by modifying the parameters of the termination strength and output impedance of DRAM devices 202(1) to 202(N) and PHY 122, for example, by setting them via the corresponding bits using the associated transistors.

[0057] For example, by utilizing the large swing of the training voltage range 130 of training mode 126, the "guaranteed working" value of the voltage reference (Vref) can be set as part of the training, regardless of process variations and environmental conditions, which is not possible in conventional techniques. These techniques also support the interleaving of training mode 126 with operating mode 128, for example, to address changing environmental conditions.

[0058] Figure 4 This is a block diagram of a non-limiting example system 400, illustrating the personalized programmability of DRAM devices 202(1) to 202(N) for implementing training voltage range 130 of training mode 126 and operating voltage range 132 of operating mode 128. Each of the PHY 122 and DRAM devices 202(1) to 202(N) can be configured to include terminals 402, 404(1), 404(N) and registers 406, 408(1) to 408(N) that can be independently programmed (e.g., for different voltage ranges). The independent programmability of PHY 122 supports personalized training.

[0059] DRAM devices 202(1) to 202(N) include, for example, registers 408(1) to 408(N) that can be programmed to different values. Examples of these registers and corresponding functions include a default mode register (e.g., RTT_Park), a register specifying the resistor terminating the signal sent to physical memory 110 (e.g., RTT_WR), and so on. Each DRAM device 202(1) to 202(N) sharing a communication coupling (e.g., via a wire) is typically referred to as a “rank”. Therefore, training a specific rank involves individually changing the termination between these various states to control “which” rank is being trained along that communication coupling. Several other examples are also considered.

[0060] Figure 5 The process 500 in an example implementation of a stepping algorithm is described, which provides a structure for training and an operating mode voltage range for a physical interface for communicatively coupling the physical layer (PHY) to the physical memory.

[0061] A training mode is set to train the interface between the PHY and physical memory to transmit command signals or data. The training mode employs a training voltage range (box 502). As an example, the PHY 122 sets the training voltage range 130 at PHY 122 and / or individual DRAM devices 202(1) to 202(N) by setting the termination state or output impedance using the corresponding transistor.

[0062] An operating mode is configured to operate the trained interface between the PHY and physical memory to transmit command signals or data. The operating mode employs an operating voltage range smaller than the training voltage range (block 504). As an example, operating mode 128 employs parameters trained as part of training mode 126. Operating mode 128 then uses these parameters at an operating voltage range 132 smaller than the training voltage range 130 of training mode 126, which is also set by the corresponding transistor. In this way, higher frequencies are supported as part of operating mode 128, which benefits from the reduced training time of training mode 126, which operates at lower frequencies. Several other examples are also considered.

[0063] It should be understood that many variations are possible based on the disclosed content of this article. Although features and elements are described above in specific combinations, each feature or element can be used alone without other features and elements, or in various combinations with or without other features or elements.

[0064] The various functional units illustrated in the accompanying drawings and / or described herein (including device 102 where appropriate) are implemented in any of a variety of different ways, such as hardware circuitry, software or firmware executing on a programmable processor, or any combination of two or more of hardware, software, and firmware. The provided methods are implemented in any of a variety of devices, such as general-purpose computers, processors, or processor cores. As examples, suitable processors include general-purpose processors, special-purpose processors, conventional processors, digital signal processors (DSPs), graphics processing units (GPUs), parallel accelerator processors, multiple microprocessors, one or more microprocessors associated with a DSP core, controllers, microcontrollers, application-specific integrated circuits (ASICs), field-programmable gate array (FPGA) circuitry, any other type of integrated circuit (IC), and / or state machines.

[0065] In one or more embodiments, the methods or processes provided herein are implemented in a computer program, software, or firmware incorporated in a non-transitory computer-readable storage medium for execution by a general-purpose computer or processor. Examples of non-transitory computer-readable storage media include read-only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media (such as internal hard disks and removable disks), magneto-optical media and optical media (such as CD-ROM disks), and digital versatile disks (DVDs).

[0066] Although the system and technology have been described in language specific to structural features and / or methodological actions, it should be understood that the system and technology defined in the appended claims are not necessarily limited to the specific features or actions described. Rather, these specific features and actions are disclosed as exemplary forms of implementing the claimed subject matter.

Claims

1. An apparatus, the apparatus comprising: The physical layer (PHY) has an interface that supports command signals and data communication with physical memory. The PHY implements: A training mode, wherein the training mode is used to train the interface to transmit the command signal or data within a training voltage range; and An operating mode for using a trained interface to transmit the command signals or data within an operating voltage range smaller than the training voltage range.

2. The device of claim 1, wherein the interface implements an interface protocol, the interface protocol employing parameters for controlling communication of the command signals and the data with the physical memory.

3. The device of claim 2, wherein the training mode detects the value of the parameter of the interface protocol, and the operation mode uses the detected parameter.

4. The device according to claim 2, wherein the parameter relates to a signal or timing.

5. The device according to claim 2, wherein the parameters relate to voltage reference (Vref) training, command training, clock-to-gated equalization, write equalization training, or gated-to-DQ training of the interface protocol.

6. The device of claim 2, wherein the parameter relates to how a signal propagates from one physical memory component of the physical memory to another physical memory component of the physical memory.

7. The device of claim 1, wherein the training mode is configured to: modify the termination state or output impedance of the PHY to achieve the training voltage range of the training mode.

8. The device of claim 1, wherein the training mode is further configured to: as part of the training mode, modify the termination state or output impedance of the physical memory to achieve the training voltage range.

9. The device of claim 1, wherein the training mode operates at a lower frequency than the operating mode.

10. The device of claim 1, wherein the PHY includes another interface for transmitting command signals and data to the memory controller.

11. The device of claim 1, wherein the PHY is implemented in hardware as part of an integrated circuit, the interface is bidirectional, and the physical memory is dynamic random access memory (DRAM).

12. A system comprising: Memory controller; Dynamic random access memory (DRAM); and The physical layer (PHY) provides communication coupling with the memory controller and the DRAM. The PHY implements: A training mode, as part of training the interface between the PHY and the DRAM, is used to detect parameter values, and the training mode operates within a training voltage range. and An operating mode for implementing the interface between the PHY and the DRAM using the detected values ​​of the parameters, the operating mode operating within an operating voltage range smaller than the training voltage range.

13. The system of claim 12, wherein the training mode is configured to: modify the termination state and output impedance of the PHY to achieve the training voltage range of the training mode.

14. The system of claim 13, wherein the training mode is further configured to: as part of the training mode, modify the termination state and output impedance of the dynamic random access memory (DRAM) to achieve the training voltage range.

15. The system of claim 12, wherein the parameters include signals or timing.

16. The system of claim 12, wherein the parameters include voltage reference (Vref) training.

17. The system of claim 12, wherein the parameters include command training, clock-to-gated equalization, or gated-to-DQ training.

18. A method, the method comprising: A training mode is set to train the interface between the physical layer (PHY) and physical memory to transmit command signals or data, wherein the training mode adopts a training voltage range; as well as An operating mode is set to operate the trained interface between the PHY and the physical memory to transmit command signals or data, wherein the operating mode uses an operating voltage range smaller than the trained voltage range.

19. The method of claim 18, wherein the training mode is configured to: modify the termination state and output impedance of the PHY to achieve the training voltage range of the training mode.

20. The method of claim 18, wherein the training of the interface is voltage reference (Vref) training.

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