Substrate support table and substrate processing apparatus

Abstract

The invention provides a substrate supporting table and a substrate processing apparatus which can improve cooling performance of a substrate. This substrate support table is provided with: a base having a lower surface, a circular first upper surface on the opposite side from the lower surface, and a circular second upper surface which is a surface on the opposite side from the lower surface, is formed closer to the lower surface than the first upper surface, and surrounds the periphery of the first upper surface; a first electrostatic chuck disposed on the first upper surface and including a first ceramic member and a first electrostatic electrode disposed in the first ceramic member; and a second electrostatic chuck formed separately from the first electrostatic chuck, disposed on the second upper surface, and including a second ceramic member and a second electrostatic electrode disposed in the second ceramic member.

Description

Technical Field

[0001] This invention relates to a substrate support platform and a substrate processing apparatus. Background Technology

[0002] Patent Document 1 discloses a mounting stage comprising an electrostatic chuck for supporting a substrate and an edge ring, and a base supporting the electrostatic chuck. The electrostatic chuck has: a first region having a first upper surface and configured to support a substrate placed on the first upper surface; a second region having a second upper surface integrally disposed around the first region and configured to support an edge ring placed on the second upper surface; a first electrode disposed in the first region for applying a DC voltage; a second electrode disposed in the second region for applying a DC voltage; and a third electrode for applying a bias power.

[0003] <Prior art documents>

[0004] <Patent Documents>

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-205379 Summary of the Invention

[0006] <Problem to be solved by this invention>

[0007] In one aspect, the present invention provides a substrate support stage and a substrate processing apparatus for improving the cooling performance of a substrate.

[0008] <Methods for solving problems>

[0009] To address the aforementioned issues, according to one approach, a substrate support stage is provided, comprising: a base having a lower surface, a first upper surface in a circular shape opposite to the lower surface, and a second upper surface in an annular shape formed on a side closer to the lower surface than the first upper surface and surrounding the first upper surface; a first electrostatic chuck comprising a first ceramic member and a first electrostatic electrode disposed within the first ceramic member, disposed on the first upper surface; and a second electrostatic chuck separately formed from the first electrostatic chuck, comprising a second ceramic member and a second electrostatic electrode disposed within the second ceramic member, disposed on the second upper surface.

[0010] <The Effects of the Invention>

[0011] According to one side, a substrate support stage and a substrate processing apparatus that improve the cooling performance of a substrate can be provided. Attached Figure Description

[0012] Figure 1This is an example of a diagram used to illustrate the structure of a capacitively coupled plasma processing device.

[0013] Figure 2 This is an example of a diagram illustrating the structure of the substrate support portion according to the first embodiment.

[0014] Figure 3 This is an example of a partially enlarged sectional view of the base.

[0015] Figure 4 This is an example of a diagram illustrating the structure of the substrate support portion according to the second embodiment.

[0016] Figure 5 This is an example of a diagram illustrating the structure of the substrate support portion according to the third embodiment.

[0017] Figure 6 This is an example of a diagram illustrating the structure of the substrate support portion according to the fourth embodiment.

[0018] Figure 7A This is an example of a diagram illustrating the structure of the substrate support portion according to the fourth embodiment.

[0019] Figure 7B This is an example of a diagram illustrating the structure of the substrate support portion according to the fourth embodiment.

[0020] Figure 7C This is an example of a diagram illustrating the structure of the substrate support portion according to the fourth embodiment.

[0021] Figure 7D This is an example of a diagram illustrating the structure of the substrate support portion according to the fourth embodiment.

[0022] Figure 7E This is an example of a diagram illustrating the structure of the substrate support portion according to the fourth embodiment.

[0023] Figure 7F This is an example of a diagram illustrating the structure of the substrate support portion according to the fourth embodiment.

[0024] Figure 8 This is an example of a diagram illustrating the structure of the substrate support portion according to the fifth embodiment.

[0025] Figure 9 This is an example of a diagram illustrating the structure of the substrate support portion according to the sixth embodiment.

[0026] Figure 10 This is an example of a diagram illustrating the structure of the substrate support portion according to the seventh embodiment.

[0027] Figure 11This is an example of a diagram illustrating the structure of the substrate support portion according to the eighth embodiment.

[0028] Figure 12 This is an example of a diagram illustrating the structure of the substrate support portion according to the ninth embodiment. Detailed Implementation

[0029] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the same reference numerals will be used to label the same or equivalent parts in each drawing.

[0030] [Plasma Processing System]

[0031] The following describes a structural example of a plasma processing system. Figure 1 This is an example of a diagram illustrating the structure of a capacitively coupled plasma processing apparatus (substrate processing apparatus) 1.

[0032] The plasma processing system includes a capacitively coupled plasma processing device 1 and a control unit 2. The capacitively coupled plasma processing device 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40. Furthermore, the plasma processing device 1 includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one processing gas into the plasma processing chamber 10. The gas inlet includes a spray head 13. The substrate support 11 is disposed within the plasma processing chamber 10. The spray head 13 is disposed above the substrate support 11. In one embodiment, the spray head 13 constitutes at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the spray head 13, the sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas into the plasma processing space 10s, and at least one gas outlet for discharging gas from the plasma processing space 10s. The plasma processing chamber 10 is grounded. The spray head 13 and the substrate support 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0033] The substrate support portion 11 includes a main body portion (substrate support stage) 111 and a ring assembly 112. The main body portion 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body portion 111 surrounds the central region 111a of the main body portion 111 when viewed from above. The substrate W is disposed on the central region 111a of the main body portion 111, and the ring assembly 112 is disposed on the annular region 111b of the main body portion 111 in such a way that it surrounds the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also referred to as a substrate support surface for supporting the substrate W, and the annular region 111b is also referred to as an annular support surface for supporting the ring assembly 112.

[0034] In one embodiment, the main body 111 is as described below. Figure 2 As shown, the device includes a base 1110, a first electrostatic chuck 1111, and a second electrostatic chuck 1112. The base 1110 includes a conductive member. The conductive member of the base 1110 functions as a lower electrode. The first electrostatic chuck 1111 is disposed on the base 1110. The first electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. The second electrostatic chuck 1112 is disposed on the base 1110. Furthermore, the second electrostatic chuck 1112 is formed in a ring shape and is configured to surround the first electrostatic chuck 1111 when viewed from above. The second electrostatic chuck 1112 includes a ceramic member 1112a and an electrostatic electrode 1112b disposed within the ceramic member 1112a. The ceramic member 1112a has an annular region 111b. Alternatively, other components surrounding the second electrostatic chuck 1112, such as the annular insulating member, may also have an annular region 111b. In this case, the ring assembly 112 may be disposed on the annular insulating member, or on both the second electrostatic chuck 1112 and the annular insulating member. Furthermore, at least one RF / DC electrode coupled to the RF (Radio Frequency) power supply 31 and / or DC (Direct Current) power supply 32, described later, may be disposed within the ceramic member 1111a. In this case, the at least one RF / DC electrode functions as a lower electrode. When the bias RF signal and / or DC signal, described later, are supplied to the at least one RF / DC electrode, the RF / DC electrode is also referred to as a bias electrode. Additionally, the conductive member of the base 1110 and the at least one RF / DC electrode may also function as multiple lower electrodes. Furthermore, the electrostatic electrode 1111b may also function as a lower electrode. Therefore, the substrate support portion 11 includes at least one lower electrode.

[0035] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover ring is formed of an insulating material.

[0036] Furthermore, the substrate support 11 may also include a temperature control module configured to adjust at least one of the first electrostatic chuck 1111, the second electrostatic chuck 1112, the ring assembly 112, and the substrate W to a target temperature. The temperature control module may also include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid such as brine or gas flows in the flow path 1110a. In one embodiment, the flow path 1110a is formed within the base 1110, and one or more heaters are disposed within the ceramic component 1111a of the first electrostatic chuck 1111 and / or the ceramic component 1112a of the second electrostatic chuck 1112. Additionally, the substrate support 11 may also include a heat transfer gas supply section configured to supply heat transfer gas to the gap between the back surface of the substrate W and the central region 111a.

[0037] The spray head 13 is configured to introduce at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The spray head 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas inlets 13c. The processing gas supplied to the gas supply port 13a is introduced into the plasma processing space 10s through the gas diffusion chamber 13b and the plurality of gas inlets 13c. Furthermore, the spray head 13 includes at least one upper electrode. In addition to the spray head 13, the gas inlet unit may also include one or more side gas injectors (SGIs) installed in one or more openings formed in the sidewall 10a.

[0038] The gas supply unit 20 may also include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one processing gas from its respective gas source 21 to the spray head 13 via its respective flow controller 22. Each flow controller 22 may also include, for example, a mass flow controller or a pressure-controlled flow controller. Furthermore, the gas supply unit 20 may also include one or more flow modulation devices for modulating or pulsedizing the flow rate of at least one processing gas.

[0039] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. This causes at least one processing gas supplied to the plasma processing space 10s to form plasma. Therefore, the RF power supply 31 can function as at least part of a plasma generation unit configured to generate plasma from one or more processing gases in the plasma processing chamber 10. Furthermore, by supplying a bias RF signal to at least one lower electrode, a bias potential is generated on the substrate W, enabling the introduction of ionic components from the formed plasma into the substrate W.

[0040] In one embodiment, the RF power supply 31 includes a first RF generation unit 31a and a second RF generation unit 31b. The first RF generation unit 31a is configured to be coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10MHz to 150MHz. In one embodiment, the first RF generation unit 31a may also be configured to generate multiple source RF signals with different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0041] The second RF generation unit 31b is configured to be coupled to at least one lower electrode via at least one impedance matching circuit to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than that of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generation unit 31b may also be configured to generate multiple bias RF signals with different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. Furthermore, in various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0042] Furthermore, if the main body 111 of the substrate support portion 11 has multiple lower electrodes and supplies the same or different bias RF signals to each electrode, the RF power supply 31 may also be configured to include multiple second RF generation units 31b, and supply bias RF signals to each lower electrode from the separate second RF generation units 31b.

[0043] Furthermore, the power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generating unit 32a and a second DC generating unit 32b. In one embodiment, the first DC generating unit 32a is configured to be connected to at least one lower electrode to generate a first DC signal. The generated first bias DC signal is applied to at least one lower electrode. In one embodiment, the second DC generating unit 32b is configured to be connected to at least one upper electrode to generate a second DC signal. The generated second DC signal is applied to at least one upper electrode.

[0044] In various embodiments, at least one of the first and second DC signals can also be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses can have rectangular, trapezoidal, triangular, or combinations thereof pulse waveforms. In one embodiment, a waveform generation unit for generating a sequence of voltage pulses based on the DC signals is connected between the first DC generation unit 32a and at least one lower electrode. Therefore, the first DC generation unit 32a and the waveform generation unit constitute a voltage pulse generation unit. When the second DC generation unit 32b and the waveform generation unit constitute a voltage pulse generation unit, the voltage pulse generation unit is connected to at least one upper electrode. The voltage pulses can have positive or negative polarity. Furthermore, the sequence of voltage pulses can include one or more positive voltage pulses and one or more negative voltage pulses within one cycle. Alternatively, the first and second DC generation units 32a and 32b can be provided in addition to the RF power supply 31, or the first DC generation unit 32a can be provided instead of the second RF generation unit 31b.

[0045] The exhaust system 40 can be connected, for example, to a gas outlet 10e located at the bottom of the plasma processing chamber 10. The exhaust system 40 may also include a pressure regulating valve and a vacuum pump. The pressure within the plasma processing space 10s is adjusted by the pressure regulating valve. The vacuum pump may also include a turbomolecular pump, a dry pump, or a combination thereof.

[0046] The controller 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform the various processes described herein. The controller 2 may be configured to control the various elements of the plasma processing apparatus 1 to perform the various processes described herein. In one embodiment, part or all of the control unit 2 may also be included in the plasma processing apparatus 1. The control unit 2 may also include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 is implemented, for example, by a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and perform various control actions by executing the read program. The program may be pre-stored in the storage unit 2a2 or retrieved via a medium when needed. The retrieved program is stored in the storage unit 2a2 and read from and executed by the processing unit 2a1. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 may also communicate with the plasma processing device 1 via a communication line such as LAN (Local Area Network).

[0047] [Substrate Support]

[0048] Next, regarding the structure of the main body 111 of the substrate support portion 11 according to the first embodiment, using Figure 2 as well as Figure 3 Let me explain. Figure 2 This is an example of a cross-sectional schematic diagram illustrating the structure of the main body 111 of the substrate support portion 11 according to the first embodiment. Figure 3 It is the outer periphery of base 1110 ( Figure 2 An example of a partially enlarged sectional view within the area indicated by the dashed line. Additionally, in Figure 2 The diagram shows a cross-sectional view of the substrate support 11 being cut off at a location where the heat transfer gas flow path 15 and the porous component 16 are arranged. Therefore, although Figure 2 The conductive layer 210 shown in the illustration is divided by the heat transfer gas flow path 15, the porous member 16, etc., but in reality, conductive layers 210 are also formed at locations that avoid the heat transfer gas flow path 15, the porous member 16, etc., and are interconnected. The same applies to conductive layer 230. Furthermore, the same applies in the other figures described later.

[0049] The main body 111 includes a base 1110, a first electrostatic chuck 1111, a second electrostatic chuck 1112, and a support member 1113.

[0050] The base 1110 is formed of an insulating material. Specifically, the base 1110 is formed of an insulating material with a lower thermal expansion ratio than Al. Specifically, an insulating material with a coefficient of thermal expansion (CTE) in the range of 4 to 10 ppm / °C can be used. Specifically, SiC, AlN, and Al2O3 can be used, for example. A flow path 1110a for the flow of heat transfer fluid is formed within the base 1110. The base 1110 has a lower surface 1110f, and a first upper surface 1110b and a second upper surface 1110c, which are the surfaces opposite to the lower surface 1110f. The first upper surface 1110b is formed in a circular shape and is formed at a position higher than the second upper surface 1110c. That is, the first upper surface 1110b is formed at a position farther from the lower surface 1110f than the second upper surface 1110c. The second upper surface 1110c, when viewed from above, is formed in an annular shape surrounding the first upper surface 1110b, and is located at a lower position than the first upper surface 1110b. That is, the second upper surface 1110c is formed closer to the lower surface 1110f than the first upper surface 1110b. The first electrostatic chuck 1111 is disposed and fixed on the first upper surface 1110b via adhesive layer 1114. The second electrostatic chuck 1112 is disposed and fixed on the second upper surface 1110c via adhesive layer 1115. Furthermore, adhesive layers 1114 and 1115 can be made of a material with a thermal conductivity of 1 W / mK or higher. Additionally, the thickness of adhesive layers 1114 and 1115 can be 200 μm or less.

[0051] Furthermore, the base 1110 has a first side surface 1110d and a second side surface 1110e. The first side surface 1110d is a cylindrical side surface formed between the outer peripheral end of the first upper surface 1110b and the inner peripheral end of the second upper surface 1110c. The second side surface 1110e is a cylindrical side surface formed between the outer peripheral end of the second upper surface 1110c and the outer peripheral end of the lower surface 1110f. The lower surface 1110f is a circular surface.

[0052] On the surface of the base 1110, a conductive layer (first conductive layer) 210, an insulating layer (first insulating layer) 220, a conductive layer (second conductive layer) 230, and an insulating layer (second insulating layer) 240 are formed in layers.

[0053] A conductive layer 210 is formed on the surface of a base 1110, including at least a first upper surface 1110b. The conductive layer 210 is formed, for example, of Al. The conductive layer 210 is formed over the first upper surface 1110b, the first side surface 1110d, the second upper surface 1110c, the second side surface 1110e, and the lower surface 1110f. The conductive layer 210 includes conductive layers 210a, 210b, and 210c. Conductive layer 210a is the portion of the conductive layer 210 formed on the first upper surface 1110b that is not covered by the insulating layer 220. Conductive layer 210b is the portion of the conductive layer 210 formed on the lower surface 1110f that is not covered by the insulating layer 220. The conductive layer 210c is the portion of the conductive layer 210 formed by electrically connecting conductive layers 210a and 210b, extending over the first side surface 1110d, the second upper surface 1110c, the second side surface 1110e, and the lower surface 1110f, and not covered by the insulating layer 220. The conductive layer 210a formed on the first upper surface 1110b is supplied with an RF signal for plasma generation and functions as a lower electrode. Furthermore, the conductive layer 210a is supplied with a first bias RF signal and functions as a substrate-side bias electrode. That is, the conductive layer 210a is supplied with at least one of an RF signal for plasma generation or a first bias signal. Furthermore, the conductive layers 210b and 210c formed on the lower surface 1110f, the second side surface 1110e, the second upper surface 1110c, and the first side surface 1110d of the conductive layer 210 function as wiring layers for the conductive layer 210a, which functions as a bias electrode to the lower electrode and / or the substrate side. The film thickness of the conductive layer 210 can be used, for example, in the range of 50 μm to 500 μm.

[0054] An insulating layer 220 is formed to cover at least a portion of the conductive layer 210. The insulating layer 220 electrically insulates the conductive layer 210 from the conductive layer 230. The insulating layer 220 is formed, for example, from Al2O3, Y2O3, AlN, or PI. The insulating layer 220 is formed outside the conductive layer 210, extending over the lower surface 1110f, the second side surface 1110e, the second upper surface 1110c, and the first side surface 1110d. That is, the insulating layer 220 is formed to cover the conductive layer 210c, and exposes the conductive layer 210b in a portion of the lower surface 1110f, and exposes the conductive layer 210a in the first upper surface 1110b. Furthermore, the conductive layer 210a formed on the first upper surface 1110b is covered by the adhesive layer 1114 and the first electrostatic chuck 1111. Alternatively, the insulating layer 220 may also be formed to cover the conductive layer 210 in the first upper surface 1110b. In addition, the insulating layer 220 is formed by thermal spraying or coating. The film thickness of the insulating layer 220 is, for example, in the range of 50 μm to 1000 μm, and in the case of forming a thinner film thickness, it can also be formed in the range of 50 μm to 600 μm.

[0055] A conductive layer 230 is formed on the surface of a base 1110, including at least a second upper surface 1110c. The conductive layer 230 is formed, for example, of an Al layer. The conductive layer 230 is formed outside the insulating layer 220, extending over the lower surface 1110f, the second side surface 1110e, and the second upper surface 1110c. The conductive layer 230 includes conductive layers 230a, 230b, and 230c. Conductive layer 230a is the portion of the conductive layer 230 formed on the second upper surface 1110c that is not covered by the insulating layer 240. Conductive layer 230b is the portion of the conductive layer 230 formed on the lower surface 1110f that is not covered by the insulating layer 240. Conductive layer 230c is the portion of the conductive layer 230 formed by electrically connecting conductive layers 230a and 230b, extending over the second side surface 1110e and the lower surface 1110f, and covered by the insulating layer 240. The conductive layer 230a formed on the second upper surface 1110c of the conductive layer 230 is supplied with a second bias RF signal and functions as an edge ring-side bias electrode. Furthermore, the conductive layers 230b and 230c formed on the lower surface 1110f and second side surface 1110e of the conductive layer 230 function as wiring layers to the conductive layer 230a, which functions as an edge ring-side bias electrode. The film thickness of the conductive layer 230 can, for example, be used in the range of 50 μm to 500 μm.

[0056] An insulating layer 240 is formed to cover at least a portion of the conductive layer 230. The insulating layer 240 is configured to prevent the conductive layer 230 from being exposed in the plasma processing space 10s. The insulating layer 240 is formed, for example, from Al2O3, Y2O3, AlN, PI, etc. The insulating layer 240 is formed outside the conductive layer 230, extending across the lower surface 1110f and the second side surface 1110e. That is, the insulating layer 240 is formed to cover the conductive layer 230c, exposing the conductive layer 230b in a portion of the lower surface 1110f, and exposing the conductive layer 230a in the second upper surface 1110c. Furthermore, the conductive layer 230a formed on the second upper surface 1110c is covered by the adhesive layer 1115 and the second electrostatic chuck 1112. Alternatively, the insulating layer 240 may also be formed to cover the conductive layer 230 in the second upper surface 1110c. Additionally, the insulating layer 240 may be formed by thermal spraying or coating. The thickness of the insulating layer 240 is, for example, in the range of 50 μm to 1000 μm, and in the case of forming a thinner film, it can also be formed in the range of 50 μm to 600 μm.

[0057] The first electrostatic chuck 1111 has a central region 111a supporting the substrate W. The first electrostatic chuck 1111 is disposed on the first upper surface 1110b of the base 1110 via an adhesive layer 1114. The outer periphery of the adhesive layer 1114 is sealed by a sealing member 1116 (e.g., an O-ring). This suppresses the consumption of the adhesive layer 1114 due to the handling of gases, plasmas, etc. The first electrostatic chuck 1111 includes a ceramic component (first ceramic component) 1111a and an electrostatic electrode (first electrostatic electrode) 1111b disposed within the ceramic component 1111a. Furthermore, the thickness of the ceramic component 1111a is 2 mm or less, and in the case of forming a thinner film thickness, it can also be formed to a thickness in the range of 0.3 mm to 1 mm.

[0058] The second electrostatic chuck 1112 is formed separately from the first electrostatic chuck 1111. The second electrostatic chuck 1112 has an annular region 111b of a support ring assembly 112 (e.g., an edge ring). The second electrostatic chuck 1112 is disposed on the second upper surface 1110c of the base 1110 via an adhesive layer 1115. The inner peripheral side of the adhesive layer 1115 is sealed by a sealing member 1116. The outer peripheral side of the adhesive layer 1115 is sealed by a sealing member 1117 (e.g., an O-ring). This suppresses the consumption of the adhesive layer 1115 due to the handling of gases, plasmas, etc. The second electrostatic chuck 1112 includes a ceramic component (second ceramic component) 1112a and an electrostatic electrode (second electrostatic electrode) 1112b disposed within the ceramic component 1112a. Furthermore, the thickness of the ceramic component 1112a is 2 mm or less, and in the case of forming a thinner film thickness, it can also be formed to a thickness in the range of 0.3 mm to 1 mm.

[0059] The support member 1113 is formed of, for example, an insulating material and is disposed under the base 1110. The support member 1113 is fixed to the back of the base 1110, for example, by fastening members (not shown) such as bolts.

[0060] The electrical connection member 1131 is formed of a conductive material and is electrically connected to the conductive layer 210b on the lower surface 1110f of the base 1110. The electrical connection member 1131 is supplied with a source RF signal for plasma generation from the first RF generation unit 31a. In addition, the electrical connection member 1131 is supplied with a first bias RF signal from the second RF generation unit 31b.

[0061] The electrical connection member 1132 is formed of a conductive material and is electrically connected to the conductive layer 230b on the lower surface 1110f of the base 1110. The electrical connection member 1132 is supplied with a second bias RF signal from the second RF generation unit 31b.

[0062] Alternatively, the RF power supply 31 may be configured to include a plurality of independent second RF generating units 31b, one of which supplies a first bias RF signal to the electrical connection member 1131, and another second RF generating unit 31b supplies a second bias RF signal to the electrical connection member 1132.

[0063] The power supply 30 supplies a source RF signal and a first bias RF signal for plasma generation from the electrical connection member 1131 to the conductive layer 210a, which functions as a lower electrode and a bias electrode.

[0064] Here, the contact point between the electrical connection member 1131 and the conductive layer 210 is formed on the lower surface 1110f of the base 1110. Therefore, the contact area between the electrical connection member 1131 and the conductive layer 210 can be made larger. This suppresses heat generation at the contact point between the electrical connection member 1131 and the conductive layer 210. Furthermore, by forming the contact point between the electrical connection member 1131 and the conductive layer 210, which will become a heat-generating element, on the lower surface 1110f of the base 1110, the temperature rise of the substrate W supported on the substrate support 11 can be suppressed.

[0065] Furthermore, the source RF signal and the first bias RF signal supplied from the lower surface 1110f of the base 1110 reach the conductive layer 210a through the conductive layer 210, which serves as a wiring layer, formed on the outer peripheral surface of the base 1110. Therefore, a larger cross-sectional area for current flow can be formed in the wiring layer. This suppresses heat generation in the conductive layer 210.

[0066] Similarly, it is possible to suppress heat generation at the junction between the electrical connection member 1132 and the conductive layer 230. In addition, it is possible to suppress heat generation in the conductive layer 230.

[0067] Furthermore, the electrostatic chuck is divided into a first electrostatic chuck 1111 and a second electrostatic chuck 1112, and formed separately. Additionally, the first upper surface 1110b is formed at a position higher than the second upper surface 1110c. Therefore, compared to the case where the electrostatic chuck is formed integrally, the thickness of the ceramic component 1111a in the first electrostatic chuck 1111 can be reduced.

[0068] Furthermore, by forming a conductive layer 210a, which serves as both a lower electrode and a bias electrode, on the surface of the base 1110, the thickness of the ceramic component 1111a of the first electrostatic chuck 1111 can be reduced. As a result, the thermal conductivity between the substrate W and the base 1110 is improved, enabling suitable cooling of the substrate W.

[0069] Furthermore, by reducing the thickness of the ceramic component 1111a, the temperature difference between the upper and lower surfaces of the ceramic component 1111a can be reduced. This also reduces the difference in thermal expansion caused by the temperature difference between the upper and lower surfaces of the ceramic component 1111a. Therefore, the warpage of the ceramic component 1111a can be reduced.

[0070] Furthermore, by reducing the thickness of the ceramic component 1111a, the distance between the substrate W and the conductive layer 210a, which functions as a lower electrode and a bias electrode, can be shortened. Therefore, abnormal discharge in the heat transfer gas flow path 15 formed in the ceramic component 1111a can be suppressed.

[0071] Similarly, the thickness of the ceramic component 1112a of the second electrostatic chuck 1112 can be reduced. As a result, the warpage of the ceramic component 1112a can be reduced.

[0072] Furthermore, the distribution path 15a of the heat transfer gas flow path 15 is formed within the base 1110. That is, the flow path of the heat transfer gas flow path 15 formed in the first electrostatic chuck 1111 can also be formed along the thickness direction (vertical direction), without providing a flow path in the surface direction (horizontal direction). As a result, compared with the structure in which the distribution path of the heat transfer gas flow path 15 is formed within the first electrostatic chuck 1111, the thickness of the ceramic component 1111a can be reduced.

[0073] Furthermore, the structure of the substrate support portion 11 is not limited to... Figure 2 as well as Figure 3 The structure shown.

[0074] Figure 4 This is an example illustrating the structure of the substrate support portion 11 according to the second embodiment. Similar to the aforementioned... Figure 2 Similarly, in the example shown, the lower electrode and the substrate-side bias electrode are formed on the base 1110 as conductive layer 210a, and the edge ring-side bias electrode is formed on the base 1110 as conductive layer 230a.

[0075] Furthermore, in the aforementioned Figure 2 In the example shown, the distribution flow path 15a of the heat transfer gas flow path 15 is formed on the base 1110 between the flow path 1110a and the lower surface 1110f. The location of the distribution flow path 15a is not limited to this. Figure 4 As shown, the distribution flow path 15a of the heat transfer gas flow path 15 can also be a structure of a base 1110 formed between the flow path 1110a and the upper surface (first upper surface 1110b). Other structures are the same as those described above, and repeated descriptions are omitted.

[0076] Figure 5 This is an example illustrating the structure of the substrate support portion 11 according to the third embodiment. (As described above...) Figure 2 Similarly, in the example shown, the lower electrode and the substrate-side bias electrode are formed on the base 1110 as a conductive layer 210a. Furthermore, in Figure 5 The diagram shows a cross-sectional view of the substrate support 11 cut off at the locations where wiring 1112d, power supply rod 1134, etc., are arranged. Therefore, Figure 5 The conductive layer 210 shown in the diagram is divided into an inner peripheral side and an outer peripheral side by wiring 1112d, power supply rod 1134, etc., but in reality, a conductive layer 210 is also formed at a position that avoids the positions where wiring 1112d, power supply rod 1134, etc. are arranged, and conduction is achieved.

[0077] The conductive layer 210 includes conductive layers 210a, 210b, 210c, and 210d. Here, the insulating layer 220 is formed to cover at least a portion of the conductive layer 210. Furthermore, the insulating layer 220 is configured to prevent the conductive layer 210 from being exposed to the plasma processing space 10s. Conductive layer 210a is the portion of the conductive layer 210 formed on the first upper surface 1110b that is not covered by the insulating layer 220. Conductive layer 210b is the portion of the conductive layer 210 formed on the lower surface 1110f that is not covered by the insulating layer 220 or the support member 1113. Conductive layer 210c is the portion of the conductive layer 210 formed across the first side surface 1110d, the second upper surface 1110c, and the second side surface 1110e that is covered by the insulating layer 220. Conductive layer 210d is the portion of the conductive layer 210 formed on the lower surface 1110f that is covered by the support member 1113. Conductive layers 210c and 210d electrically connect conductive layers 210a and 210b.

[0078] like Figure 5As shown, the lower electrode and the substrate-side bias electrode are formed as conductive layer 210a on the base 1110. On the other hand, the edge ring-side bias electrode is formed as bias electrode 1112c within the second electrostatic chuck 1112. On the back side of the second electrostatic chuck 1112, a wiring 1112d made of conductive material is formed, connecting the back side of the second electrostatic chuck 1112 to the bias electrode 1112c. The wiring 1112d is, for example, a via. On the base 1110, a power supply rod 1134 and a sleeve 1135 are provided. The upper end of the power supply rod 1134 is connected to the wiring 1112d. The lower end of the power supply rod 1134 is connected to the electrical connection member 1137 via a power supply line 1136. The electrical connection member 1137 is supplied with a second bias RF signal from the second RF generation unit 31b. Other structures are the same as described above, and repeated descriptions are omitted.

[0079] Figure 6 This is an example of a diagram illustrating the structure of the substrate support portion 11 according to the fourth embodiment. Figures 7A to 7F This is a diagram illustrating an example of the arrangement of conductive layers 210, 230 in the second upper surface 1110c of the base 1110 of the substrate support portion 11 according to the fourth embodiment. In other words, Figures 7A to 7F This is a diagram showing an example of the configuration of the conductive layer 210, insulating layer 220, and conductive layer 230 when viewed from above on the second upper surface 1110c.

[0080] exist Figure 2 In the example shown, on the second upper surface 1110c of the base 1110, three layers—a conductive layer 210, an insulating layer 220, and a conductive layer 230—are sequentially stacked along the thickness direction. In contrast, in… Figure 6 In the substrate support portion 11 shown, conductive layer 210, insulating layer 220, and conductive layer 230 are disposed on the second upper surface 1110c. That is, on the second upper surface 1110c, conductive layer 210, insulating layer 220, and conductive layer 230 may also be formed as a single layer in the thickness direction. Other structures are the same as described above, and repeated descriptions are omitted.

[0081] For example, such as Figure 7A As shown, conductive layer 210, insulating layer 220, and conductive layer 230 can be formed within one layer by alternating arrangements along the circumferential direction. Additionally, as... Figure 7B As shown, the corners 210e and 230e of conductive layers 210 and 230 can also be rounded. In this case, the concentration of electric field at the corners can be suppressed.

[0082] For example, such as Figure 7C As shown, the conductive layer 210, insulating layer 220, and conductive layer 230 can also be formed within a single layer by alternating nested configurations along the circumferential direction. Additionally, as... Figure 7DAs shown, the corners 210f and 230f of conductive layers 210 and 230 can also be rounded. In this case, the concentration of electric field at the corners can be suppressed.

[0083] For example, such as Figure 7E As shown, the conductive layer 210, insulating layer 220, and conductive layer 230 can also be formed within a single layer by alternating nested configurations along the circumferential direction. Additionally, as... Figure 7F As shown, the corners 210g and 230g of conductive layers 210 and 230 can also be rounded. In this case, the concentration of electric field at the corners can be suppressed.

[0084] This improves the thermal conductivity between the second electrostatic chuck 1112 and the base 1110.

[0085] Figure 8 This is an example of a diagram illustrating the structure of the substrate support portion 11 according to the fifth embodiment.

[0086] In the substrate support portion 11 according to the fifth embodiment, the base 1110 is formed of a conductive material, specifically, a material containing molybdenum (Mo) (Mo alloy). Here, ceramic components 1111a and 1112a are, for example, Al2O3. As the material of the base 1110, by using a material containing molybdenum (Mo), the difference in thermal expansion with Al2O3 can be reduced compared to SiC. As a result, deformation of adhesive layers 1114 and 1115 can be suppressed. Furthermore, by forming the base 1110 with a metallic material, the generation of cracks can be suppressed. Alternatively, the base 1110 may also be formed of a material containing tungsten (W) (W alloy). Furthermore, the base 1110 may also be formed of a material containing Si-Al (Si-Al alloy).

[0087] Furthermore, the base 1110 functions as both a lower electrode and a substrate-side bias electrode. Additionally, with Figure 5 Similarly, in the example shown, a bias electrode 1112c is formed within the second electrostatic chuck 1112 as an edge ring-side bias electrode.

[0088] Furthermore, an insulating layer 221 is laminated on the surface of the base 1110. The insulating layer 221 is formed to cover at least a portion of the base 1110. Furthermore, the insulating layer 221 is configured to prevent the base 1110 from being exposed to the plasma processing space 10s. The insulating layer 221 is formed, for example, from Al2O3, Y2O3, AlN, PI, etc. Alternatively, the insulating layer 221 can be formed by thermal spraying or coating. The film thickness of the insulating layer 221 is, for example, in the range of 50 μm to 1000 μm, and in the case of forming a thinner film thickness, it can also be formed in the range of 50 μm to 600 μm.

[0089] The other structures are the same as those described above, and repeated explanations are omitted.

[0090] Figure 9 This is an example of a diagram illustrating the structure of the substrate support portion 11 according to the sixth embodiment.

[0091] In the substrate support portion 11 according to the sixth embodiment, and with Figure 8 Similarly, in the example shown, the base 1110 functions as both the lower electrode and the substrate-side bias electrode. Furthermore, with... Figure 8 Similarly, in the example shown, a bias electrode 1112c is formed within the second electrostatic chuck 1112 as an edge ring-side bias electrode.

[0092] Here, the base 1110 is formed by joining a first base 310 and a second base 320. The first base 310 and the second base 320 are formed of different conductive materials. The second base 320 can, for example, be a metallic material having a coefficient of thermal expansion (CTE) in the range of 4 to 7 ppm / °C. Specifically, the second base 320 is formed of a material containing any one of molybdenum (Mo), tungsten (W), or Si-Al (Mo alloy, W alloy, Si-Al alloy). The first base 310 can be a non-magnetic metal. Specifically, the first base 310 is formed of a material containing aluminum (Al) or stainless steel (SUS).

[0093] The first base 310 and the second base 320 can be joined by friction stir bonding, aluminum brazing, etc.

[0094] Furthermore, a recess forming a flow path 1110a is formed on the upper surface side of the first base 310. The flow path 1110a is formed by joining the first base 310 with the recess to the second base 320. By forming the recess forming the flow path 1110a in the first base 310, which is formed of a material with good processability, the flow path 1110a is easily formed in the base 1110. Other structures are the same as described above, and repeated descriptions are omitted.

[0095] Figure 10 This is an example of a diagram illustrating the structure of the substrate support portion 11 according to the seventh embodiment.

[0096] In the substrate support portion 11 according to the seventh embodiment, and with Figure 8 Similarly, in the example shown, the base 1110 functions as both the lower electrode and the substrate-side bias electrode. Furthermore, with... Figure 8 Similarly, in the example shown, a bias electrode 1112c is formed within the second electrostatic chuck 1112 as an edge ring-side bias electrode.

[0097] In the substrate support portion 11 according to the seventh embodiment, the base 1110 is formed by fixing the first base 310 and the second base 320 with fastening members (not shown) such as bolts. Furthermore, a sealing member 340, such as an O-ring, is provided between the first base 310 and the second base 320 to seal the heat transfer gas flow path 15 and the heat transfer medium flow path 1110a. Other structures are the same as described above, and repeated descriptions are omitted.

[0098] Figure 11 This is an example of a diagram illustrating the structure of the substrate support portion 11 according to the eighth embodiment.

[0099] In the substrate support portion 11 according to the eighth embodiment, and with Figure 8 Similarly, in the example shown, the base 1110 functions as both a lower electrode and a substrate-side bias electrode. Furthermore, an insulating layer (first insulating layer) 222, a conductive layer 232, and an insulating layer (second insulating layer) 242 are stacked on the surface of the base 1110. An edge ring-side bias electrode is formed on the base 1110 as a conductive layer 232a.

[0100] An insulating layer 222 is formed to cover at least a portion of the base 1110. The insulating layer 222 electrically insulates the base 1110 from the conductive layer 232. The insulating layer 222 is formed, for example, from Al2O3, Y2O3, AlN, PI, etc. The insulating layer 222 is formed on the surface of the base 1110, including at least the second upper surface 1110c. Specifically, the insulating layer 222 is formed over the lower surface 1110f, the second side surface 1110e, the second upper surface 1110c, and the first side surface 1110d. Furthermore, the insulating layer 222 electrically insulates the base 1110 from the conductive layer 232. Additionally, the insulating layer 222 can be formed by thermal spraying or coating. The film thickness of the insulating layer 222 is, for example, in the range of 50 μm to 1000 μm, and in the case of forming a thinner film thickness, it can also be formed in the range of 50 μm to 600 μm.

[0101] A conductive layer 232 is formed on an insulating layer 222 formed at least on the second upper surface 1110c. The conductive layer 232 is formed, for example, of an Al layer. Specifically, the insulating layer 222 is formed covering the lower surface 1110f, the second side surface 1110e, and the second upper surface 1110c. The conductive layer 232 includes conductive layers 232a, 232b, and 232c. Conductive layer 232a is the portion of the conductive layer 232 formed on the second upper surface 1110c that is not covered by the insulating layer 242. Conductive layer 232b is the portion of the conductive layer 232 formed on the lower surface 1110f that is not covered by the insulating layer 242. Conductive layer 232c is the portion of the conductive layer 232 formed by electrically connecting conductive layers 232a and 232b, covering the second side surface 1110e and the lower surface 1110f, and covered by the insulating layer 242. The conductive layer 232a formed on the second upper surface 1110c of the conductive layer 232 is supplied with a second bias RF signal and functions as an edge ring-side bias electrode. Furthermore, portions of the conductive layer 232 formed on the lower surface 1110f and the second side surface 1110e function as wiring layers for the conductive layer 232a, which functions as the edge ring-side bias electrode. The film thickness of the conductive layer 232 can, for example, be in the range of 50 μm to 500 μm.

[0102] An insulating layer 242 is formed to cover at least a portion of the conductive layer 232. The insulating layer 242 is configured to prevent the conductive layer 232 from being exposed to the plasma processing space for 10 seconds. The insulating layer 242 is formed, for example, from Al2O3, Y2O3, AlN, PI, etc. Alternatively, the insulating layer 242 can be formed by thermal spraying or coating. The film thickness of the insulating layer 242 is, for example, in the range of 50 μm to 1000 μm, and in the case of forming a thinner film thickness, it can also be formed in the range of 50 μm to 600 μm.

[0103] The other structures are the same as those described above, and repeated explanations are omitted.

[0104] Figure 12 This is an example of a diagram illustrating the structure of the substrate support portion 11 according to the ninth embodiment.

[0105] In the substrate support portion 11 according to the eighth embodiment, and with Figure 9 Similarly, in the example shown, the base 1110 functions as both a lower electrode and a substrate-side bias electrode. Furthermore, the base 1110 is formed by joining a first base 310 and a second base 320. Alternatively, the base 1110 can be formed by fixing the first base 310 and the second base 320 with fastening members (not shown) such as bolts. Other structures are the same as described above, and repeated descriptions are omitted.

[0106] The above-disclosed implementation methods include, for example, the following methods.

[0107] (Postscript 1)

[0108] A substrate support platform, comprising:

[0109] The base has a lower surface, a first upper surface in a circular shape opposite to the lower surface, and a second upper surface in an annular shape formed on the side of the lower surface that is opposite to the lower surface and surrounds the first upper surface.

[0110] A first electrostatic chuck includes a first ceramic component and a first electrostatic electrode disposed within the first ceramic component and disposed on the first upper surface; and

[0111] The second electrostatic chuck is formed separately from the first electrostatic chuck, and includes a second ceramic component and a second electrostatic electrode disposed within the second ceramic component and disposed on the second upper surface.

[0112] (Postscript 2)

[0113] According to the substrate support stage described in Appendix 1, wherein...

[0114] The base is formed of insulating material.

[0115] The substrate support stage includes:

[0116] A first conductive layer, formed on the surface of the base including at least the first upper surface, is supplied with at least one of an RF signal for plasma generation or a first bias signal; and

[0117] A first insulating layer covers at least a portion of the first conductive layer.

[0118] (Note 3)

[0119] According to Appendix 2, the substrate support stage, wherein...

[0120] The first conductive layer is formed over the first upper surface, the first side surface between the first upper surface and the second upper surface, the second upper surface, the second side surface between the second upper surface and the lower surface, and the lower surface.

[0121] (Postscript 4)

[0122] The substrate support stage according to Appendix 3 includes:

[0123] A second conductive layer, formed on the surface of the base including at least the second upper surface, is supplied with a second bias signal; and

[0124] A second insulating layer covers at least a portion of the second conductive layer.

[0125] (Note 5)

[0126] According to the substrate support stage described in Appendix 4, wherein...

[0127] The second conductive layer is formed covering the second upper surface, the second side surface, and the lower surface.

[0128] (Note 6)

[0129] According to Appendix 2 or Appendix 3, the substrate support stage, wherein...

[0130] The second electrostatic chuck has a bias electrode disposed within the second ceramic component and supplied with a second bias signal.

[0131] (Note 7)

[0132] According to the substrate support stage described in Appendix 1, wherein...

[0133] The base is formed of a conductive material.

[0134] The base is supplied with at least one of an RF signal for plasma generation or a first bias signal.

[0135] (Postscript 8)

[0136] According to the substrate support stage described in Appendix 7, wherein...

[0137] The base has a first base including the lower surface of the base, and a second base formed of a different material from the first base and including the first upper surface and the second upper surface.

[0138] (Note 9)

[0139] According to the substrate support stage described in Appendix 8, wherein...

[0140] The first base and the second base are joined together.

[0141] (Postscript 10)

[0142] According to the substrate support stage described in Appendix 8, wherein...

[0143] The first base and the second base are fixed together by fastening members.

[0144] (Postscript 11)

[0145] The substrate support stage according to any one of Appendices 8 to 10, wherein...

[0146] The first base is formed of Al or SUS.

[0147] The second base is formed from any one of Mo alloy, W alloy, or Si-Al alloy.

[0148] (Postscript 12)

[0149] The substrate support stage according to any one of Appendices 7 to 11 comprises:

[0150] A first insulating layer is formed on the surface of the base, which includes at least the second upper surface;

[0151] A second conductive layer, formed on at least the first insulating layer formed on the second upper surface, is supplied with a second bias signal; and

[0152] A second insulating layer covers at least a portion of the second conductive layer.

[0153] (Postscript 13)

[0154] The substrate support stage according to any one of Appendices 7 to 11, wherein...

[0155] The second electrostatic chuck has a bias electrode disposed within the second ceramic component and supplied with a second bias signal.

[0156] (Postscript 14)

[0157] The substrate support stage according to any one of Annexes 1 to 13, wherein,

[0158] The thickness of the first electrostatic chuck is less than 1 mm.

[0159] (Postscript 15)

[0160] A substrate processing apparatus comprising:

[0161] The substrate support stage as described in any one of Appendix 1 to Appendix 14.

[0162] Furthermore, the present invention is not limited to the structures listed in the above embodiments, or the combinations thereof with other elements shown herein. Modifications can be made in these aspects without departing from the spirit of the invention, and can be appropriately determined depending on the application.

[0163] Furthermore, this application claims priority based on Japanese Patent Application No. 2023-61597, filed on April 5, 2023, and incorporates the entire contents of that Japanese Patent Application by reference.

[0164] Explanation of reference numerals in the attached figures

[0165] 1: Plasma processing device

[0166] 10: Plasma processing chamber

[0167] 11: Substrate support portion

[0168] 111: Main body (substrate support platform)

[0169] 111a: Central Area

[0170] 111b: Annular region

[0171] 1110: Base

[0172] 1110a: flow path

[0173] 1110b: First upper surface

[0174] 1110c: Second upper surface

[0175] 1110d: First side view

[0176] 1110e: Second side

[0177] 1110f: Lower surface

[0178] 1111: First electrostatic chuck

[0179] 1111a: Ceramic component (first ceramic component)

[0180] 1111b: Electrostatic electrode (first electrostatic electrode)

[0181] 1112: Second electrostatic chuck

[0182] 1112a: Ceramic component (second ceramic component)

[0183] 1112b: Electrostatic electrode (second electrostatic electrode)

[0184] 1112c: Bias electrode

[0185] 1112d: Wiring

[0186] 31: RF power supply

[0187] 31a: First RF Generation Unit

[0188] 31b: Second RF Generation Unit

[0189] 210: Conductive layer (first conductive layer)

[0190] 220: Insulation layer (first insulation layer)

[0191] 230: Conductive layer (second conductive layer)

[0192] 240: Insulation layer (second insulation layer)

[0193] 310: First Foundation

[0194] 320: Second base.

Claims

1. A substrate support platform, comprising: The base has a lower surface, a first upper surface in a circular shape opposite to the lower surface, and a second upper surface in an annular shape formed on the side of the lower surface that is opposite to the lower surface and surrounds the first upper surface. A first electrostatic chuck is disposed on the first upper surface and includes a first ceramic component and a first electrostatic electrode disposed within the first ceramic component. as well as The second electrostatic chuck is formed separately from the first electrostatic chuck, disposed on the second upper surface, and includes a second ceramic component and a second electrostatic electrode disposed within the second ceramic component.

2. The substrate support stage according to claim 1, wherein, The base is formed of insulating material. The substrate support stage includes: A first conductive layer, formed on the surface of the base including at least the first upper surface, and supplied with at least one of an RF signal for plasma generation or a first bias signal; and A first insulating layer covers at least a portion of the first conductive layer.

3. The substrate support stage according to claim 2, wherein, The first conductive layer is formed over the first upper surface, the first side surface between the first upper surface and the second upper surface, the second upper surface, the second side surface between the second upper surface and the lower surface, and the lower surface.

4. The substrate support stage according to claim 3, comprising: A second conductive layer is formed on the surface of the base, which includes at least the second upper surface, and is supplied with a second bias signal. as well as A second insulating layer covers at least a portion of the second conductive layer.

5. The substrate support stage according to claim 4, wherein, The second conductive layer is formed covering the second upper surface, the second side surface, and the lower surface.

6. The substrate support stage according to claim 2 or 3, wherein, The second electrostatic chuck has a bias electrode disposed within the second ceramic component and supplied with a second bias signal.

7. The substrate support stage according to claim 1, wherein, The base is formed of a conductive material. The base is supplied with at least one of an RF signal for plasma generation or a first bias signal.

8. The substrate support stage according to claim 7, wherein, The base has: A first base, which includes the lower surface of the base; The second base, which is formed of a different material from the first base, includes the first upper surface and the second upper surface.

9. The substrate support stage according to claim 8, wherein, The first base and the second base are joined together.

10. The substrate support stage according to claim 8, wherein, The first base and the second base are fixed together by fastening members.

11. The substrate support stage according to any one of claims 8 to 10, wherein, The first base is formed of Al or SUS. The second base is formed from any one of Mo alloy, W alloy, or Si-Al alloy.

12. The substrate support stage according to any one of claims 7 to 10, comprising: A first insulating layer is formed on the surface of the base, which includes at least the second upper surface; A second conductive layer is formed on at least the first insulating layer formed on the second upper surface and is supplied with a second bias signal. as well as A second insulating layer covers at least a portion of the second conductive layer.

13. The substrate support stage according to any one of claims 7 to 10, wherein, The second electrostatic chuck has a bias electrode disposed within the second ceramic component and supplied with a second bias signal.

14. The substrate support stage according to any one of claims 1 to 5, wherein, The thickness of the first electrostatic chuck is less than 1 mm.

15. A substrate processing apparatus comprising a substrate support stage according to any one of claims 1 to 5.

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