Dedicated hardware device for decoding non-binary polar codes

Abstract

Dedicated hardware devices and methods for decoding data are disclosed. The data comprises a plurality of encoded non-binary data symbols, a dedicated hardware device: receiving the plurality of encoded non-binary data symbols, each encoded non-binary data symbol being received over a corresponding channel; determining a log-likelihood ratio vector for each encoded non-binary data symbol; applying a contiguous cancellation decoding routine to the plurality of log-likelihood ratio vectors, the contiguous cancellation decoding routine comprising one or more groups of operations to be applied to a subset of the plurality of log-likelihood ratio vectors; and generating a plurality of decoded non-binary data symbols based on a result of the successive cancellation decoding routine.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to U.S. Patent Application No. 18 / 126,798, filed March 27, 2023, entitled “APPLICATION - SPECIFIC HARDWAREDEVICE FOR DECODING NON-BINARY POLAR CODES”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to data decoding, and more particularly to dedicated hardware devices for decoding non-binary polar codes. Background Technology

[0004] Binary polar codes have been shown to achieve symmetric capacity for binary-input discrete memoryless channels with low-complexity encoding and decoding. Non-binary polar codes (NBPCs) have also been shown to achieve capacity similar to their binary polar counterparts. NBPCs were investigated to improve the latency and error rate performance of binary polar codes (BPCs). Due to symbol-by-symbol decoding, the latency of the NBPC successive cancellation (SC) algorithm is generally lower than that of BPC SC decoding. Furthermore, due to its superior performance, NBPC can be used with SC decoding rather than with a list of SCs.

[0005] Recently, the latency of BPC has been extensively studied based on the concept of special nodes (or "supernodes") in simplified SC decoding, with the aim of reducing latency. However, fast decoding of NBPC has not yet been implemented, making NBPC impractical for real-world applications.

[0006] Therefore, fast SC decoding of NBPC is required, and more specifically, specific decoding routines are needed for decoding special nodes of a binary tree within the context of NBPC. Summary of the Invention

[0007] Therefore, one aspect of this technology is to provide a low-latency solution to the problem of decoding non-binary polar codes.

[0008] In a first broad aspect of this technology, a dedicated hardware device is provided for decoding data comprising a plurality of encoded non-binary data symbols. The dedicated hardware device: receives the plurality of encoded non-binary data symbols, each encoded non-binary data symbol being received via a corresponding channel; determines a log-likelihood ratio vector for each encoded non-binary data symbol; applies a successive elimination decoding routine to the plurality of log-likelihood ratio vectors, the successive elimination decoding routine comprising one or more sets of operations to be applied to a subset of the plurality of log-likelihood ratio vectors; and generates a plurality of decoded non-binary data symbols based on the result of the successive elimination decoding routine.

[0009] In some non-limiting implementations, the one or more operation groups comprise multiple operation groups, and subsets of the multiple operation groups are sequentially applied to subsets of the multiple log-likelihood ratio vectors, such that the output of a given operation group is used at least partially as the input of a successive operation group.

[0010] In some non-limiting implementations, the initial iteration of the successive elimination decoding routine includes applying a first set of operations to the subset of the plurality of log-likelihood ratio vectors. The execution of each operation in the first set of operations includes: performing a first permutation operation on the first log-likelihood ratio vector to define a first permutation log-likelihood ratio vector, the first permutation operation being defined based on the value of a first parameter; determining a first output based on the first permutation log-likelihood ratio vector and a second log-likelihood ratio vector; performing a second permutation operation on the first log-likelihood ratio vector to define a second permutation log-likelihood ratio vector, the second permutation operation being defined based on the value of the first parameter and the first output; and determining a second output based on the first permutation log-likelihood ratio vector and the second permutation log-likelihood ratio vector.

[0011] In some non-limiting implementations, the final iteration of the successive elimination decoding routine includes applying a final set of operations to the output of a previous set of operations. The execution of each operation in the final set of operations includes: performing a first permutation operation on a first output of the previous set of operations in the successive elimination decoding routine to define a first permutation vector, the first permutation operation being defined based on the value of a first parameter; determining a first primary output of the successive elimination decoding routine based on the first permutation vector and a second output of the previous set of operations; performing a second permutation operation on the first output of the previous set of operations to define a second permutation output, the second permutation operation being defined based on the value of the first parameter and the first primary output; and determining a second primary output based on the second permutation vector and the second output of the previous set of operations.

[0012] In some non-restrictive implementations, the log-likelihood ratio vector includes 2 qThe elements of the Galois field of q are integers corresponding to the number of bits mapped in each non-binary data symbol.

[0013] In some non-limiting implementations, at least one operation in the one or more operation groups includes performing an Extended Min-Sum (EMS) operation.

[0014] According to the dedicated hardware device of claim 1, for each given encoded non-binary data symbol, the length of the corresponding log-likelihood ratio vector is equal to the number of bits mapped in the given encoded non-binary data symbol.

[0015] In some non-limiting implementations, each of the one or more operation groups is mapped to a node of a binary tree, and each node has a corresponding node size N. s It receives a corresponding input matrix as input, the columns of which correspond to the log-likelihood ratio vector affected by the operations in the previous operation group, and each leaf node of the binary tree corresponds to one of the corresponding channels.

[0016] In some non-limiting implementations, the corresponding channel includes a predetermined set of information channels. The dedicated hardware device also identifies one or more predetermined decoding routines to be executed on the binary tree.

[0017] In some non-limiting implementations, the dedicated hardware device further identifies a given node of the binary tree, the leaf nodes of which can be represented as a vector d = [a,...,a], where each corresponding channel in the corresponding channel is represented as "b" for the information channel and "a" in other cases; and by setting the output of the given node to a size of N. s The all-zero vector is used to perform a predetermined decoding routine on the given node.

[0018] In some non-limiting implementations, the dedicated hardware device further identifies a given node of the binary tree, the leaf nodes of which can be represented as a vector d = [b,...,b], where each corresponding channel in the corresponding channel is represented as "b" for the information channel and as "a" in other cases; and outputs N s A vector of symbols is used to perform a predetermined decoding routine on the given node, wherein the corresponding correspondence likelihood ratio vector of the symbols in each column of the corresponding input matrix is ​​zero.

[0019] In some non-limiting implementations, the dedicated hardware device further identifies a given node of the binary tree, the leaf nodes of which can be represented as a vector d = [a,...,a,b], where each corresponding channel in the corresponding channel is represented as "b" for the information channel and "a" otherwise; and performs a predetermined decoding routine on the given node by summing the columns of the corresponding input matrix to obtain a sum vector; and selecting a non-binary data symbol corresponding to the smallest element of the sum vector, the output of the third special node being N of the selected non-binary data symbol. s Repeated 2 times.

[0020] In some non-limiting implementations, the dedicated hardware device further identifies a given node of the binary tree, the leaf nodes of which can be represented as a vector d = [a, b, ..., b], where each corresponding channel in the corresponding channel is represented as "b" for the information channel and as "a" in other cases; and performs a predetermined decoding routine on the given node by generating N s A vector of N non-binary data symbols s The corresponding correspondence likelihood ratio vector of each non-binary data symbol in each column of the corresponding input matrix is ​​zero; and in response to the N s A vector of non-binary data symbols satisfies the GF(2)-based algorithm. q The parity check equation for addition, which includes the N... s The vector of non-binary data symbols is set as the output of the node, and in other cases, starting from the first non-binary data symbol, each non-binary data symbol is replaced with a non-binary data symbol that satisfies the parity equation.

[0021] In some non-limiting implementations, the dedicated hardware device further identifies a given node of the binary tree, the leaf nodes of which can be represented as vectors d = [a,...,a,b,b], where each corresponding channel in the corresponding channel is represented as "b" for the information channel and as "a" in other cases; and performs a predetermined decoding routine on the given node by: summing the columns with even indices in the corresponding input matrix to obtain a first sum vector; selecting a first non-binary data symbol corresponding to the smallest element of the first sum vector; summing the columns with odd indices in the corresponding input matrix to obtain a second sum vector; selecting a second non-binary data symbol corresponding to the smallest element of the second sum vector; the output of the node is an N-fold concatenation of the first non-binary data symbol and the second non-binary data symbol. s Repeated 2 times.

[0022] In some non-limiting implementations, the dedicated hardware device further identifies a given node of the binary tree, the leaf nodes of which can be represented as a vector d = [a,...,a,b,b,b], where each corresponding channel in the corresponding channel is represented as "b" for the information channel and as "a" in other cases; and performs a predetermined decoding routine on the given node by: Determine the second matrix, where α k′,j These are the coefficients of the input matrix; generating N s A vector of N non-binary data symbols s The correspondence likelihood ratio vector for each non-binary data symbol in each column of the second matrix is ​​zero. In response to the N... s A vector of non-binary data symbols satisfies the GF(2)-based algorithm. q The parity check equation for addition, the dedicated hardware device will also include the N s The vector of non-binary data symbols is set as the output of the node, and in other cases, starting from the first non-binary data symbol, each non-binary data symbol is replaced with a non-binary data symbol that satisfies the parity check.

[0023] In some non-limiting implementations, the dedicated hardware device further identifies a given node of the binary tree, the leaf nodes of which can be represented as a vector d = [a, a, b, ..., b], where each corresponding channel in the corresponding channel is represented as "b" for the information channel and as "a" in other cases. The dedicated hardware device also performs a predetermined decoding routine on the given node by generating N... s The first vector consisting of / 2 non-binary data symbols, the N s The corresponding correspondence likelihood ratio vectors of the two non-binary data symbols in each column of the corresponding input matrix with even indices are zero; and in response to the first vector not satisfying the GF(2)-based ... q The parity equation for addition, starting from the first non-binary data symbol, replaces each non-binary data symbol with a non-binary data symbol that satisfies the parity check, generating N. s A second vector consisting of 2 non-binary data symbols, wherein the corresponding correspondence likelihood ratio vector in each column of the corresponding input matrix with an odd index is zero. In response to the second vector not satisfying the GF(2)-based... q The parity check equation for addition is used, and the dedicated hardware device also replaces each non-binary data symbol with a non-binary data symbol that satisfies the parity check. The output of the node is an alternating concatenation of the first vector and the second vector.

[0024] In some non-limiting implementations, the dedicated hardware device further identifies a given node of the binary tree, the leaf nodes of which can be represented as a vector d = [a, a, a, b, ..., b], where each corresponding channel in the corresponding channel is represented as "b" for the information channel and as "a" in other cases; and performs a predetermined decoding routine on the given node by: summing the columns of the corresponding input matrix to obtain a sum vector; selecting a first non-binary data symbol corresponding to the smallest element of the sum vector; generating N s A vector of -1 non-binary data symbols, wherein N s -1 non-binary data symbols have a corresponding correspondence likelihood ratio vector of zero in each column of the corresponding input matrix; and in response to the vector not satisfying GF(2 q The parity equation of addition replaces each non-binary data symbol with a non-binary data symbol that satisfies the parity check, and the output of the node is the concatenation of the vector and the first non-binary data symbol.

[0025] In some non-limiting implementations, the dedicated hardware device further identifies a given node of the binary tree, the leaf nodes of which can be represented as vectors d = [a,...,a,a,a,b,a,b,b,b], where each corresponding channel in the corresponding channel is represented as "b" for the information channel and as "a" in other cases; and performs a predetermined decoding routine on the given node by summing columns in the input matrix whose indices differ by multiples of 8 to define eight LLR output vectors, the output of the node being a repeated concatenation of the eight LLR output vectors.

[0026] In some non-limiting implementations, the dedicated hardware device further identifies a given node of the binary tree, the leaf nodes of which can be represented as a vector d = [a,...,a,b,...,b], where the vector includes n r Each "a", wherein the channel is represented as "b" for an information channel and as "a" in other cases; and a predetermined decoding routine is performed on the given node by: determining n r A set of n equations; for each equation, the n equations are solved in parallel by performing the following operations. r Equations: Generate N s / n r A vector of N non-binary data symbols s / n r The corresponding correspondence likelihood ratio vector of each non-binary data symbol in each column of the corresponding input matrix is ​​zero; and in response to the N s / n r A vector of non-binary data symbols satisfies the GF(2)-based algorithm. q The parity check equation for addition, which includes the N... s / n r The vector of non-binary data symbols is set as the output of the node, and in other cases, starting from the first non-binary data symbol, each non-binary data symbol is replaced with a non-binary data symbol that satisfies the parity equation.

[0027] In some unrestricted implementations, each node is associated with computational parameters used to perform operations in the corresponding set of operations.

[0028] In some non-limiting implementations, the dedicated hardware device also identifies that nodes at the same level of the binary tree have equal computational parameters.

[0029] In some non-limiting implementations, the dedicated hardware device further identifies that the binary tree includes at least three levels and the computational parameter of the leaf node is equal to 1.

[0030] The implementations of this technology each have at least one of the aforementioned objectives and / or aspects, but not necessarily all of them. It should be understood that some aspects of this technology that attempt to achieve the aforementioned objectives may not satisfy those objectives, and / or may satisfy other objectives not specifically described herein.

[0031] Additional and / or alternative features, aspects and advantages of the implementation of this technology will become apparent from the following description, the accompanying drawings and the appended claims. Attached Figure Description

[0032] Embodiments of this disclosure will be described by way of example only with reference to the accompanying drawings, in which:

[0033] Figure 1 is a graphical representation of a binary polarization nucleus in a radix-2 Galois field;

[0034] Figure 2 shows a base of 2. q The graphical representation of the binary polarization nucleus in the Galois field, where q is an integer;

[0035] Figure 3 is a schematic diagram of the polarization encoding / decoding pipeline 300;

[0036] Figure 4 shows a base of 2. q A graphical representation of the binary polarization kernel used to decode the first non-binary data symbol in the Galois field;

[0037] Figure 5 shows a base of 2. qA graphical representation of the binary polarization kernel in the Galois field used to decode the second non-binary data symbol using the first non-binary data symbol;

[0038] Figure 6 is a graphical representation of a binary tree;

[0039] Figure 7A and Figure 7B This includes representations of binary trees according to some non-limiting implementations of the present technology and pruned versions of the binary trees according to some non-limiting implementations of the present technology, with identifiers of their special nodes;

[0040] Figure 8 The graph shows simulation results of error rate performance of binary polar code (BPC) and non-binary polar code (NBPC) using fast successive cancellation (SC) and SC decoding routines in some non-limiting implementations of the present technology.

[0041] Figure 9 This is a graphical representation of a binary tree based on some non-limiting implementations of this technology;

[0042] Figure 10 This is based on some non-limiting implementations of the technology for use. Figure 9 A schematic diagram of a dedicated hardware device for decoding non-binary data symbols using a binary tree;

[0043] Figure 11 This is a graphical representation of a binary tree based on some non-limiting implementations of this technology;

[0044] Figure 12 This is based on some non-limiting implementations of the technology for use. Figure 11 A schematic diagram of a dedicated hardware device for decoding non-binary data symbols using a binary tree;

[0045] Figure 13 This is a block diagram of a system configured to decode data comprising multiple encoded non-binary data symbols according to some non-limiting embodiments of the present technology;

[0046] Figure 14 This is a block diagram of an electronic device according to some non-limiting embodiments of the present technology;

[0047] Figure 15 It is a graphical representation of a binary tree that includes type 5 special nodes;

[0048] Figure 16It is a graphical representation of a binary tree that includes special nodes for extended generalized parity checking. Detailed Implementation

[0049] Polar codes are a class of capacity-implementing linear block codes with a well-defined coding structure and low-complexity encoding / decoding algorithms. Polar codes can be constructed based on the concept of channel polarization, where recursive application of the polarization kernel generates a synthetic channel. Figure 1 shows a graphical representation of a binary polarization kernel 100. The circled "+" symbol represents modulo-2 addition.

[0050] For binary codes (i.e., from left to right in Figure 1), the input vector with bits [u1, u2] is multiplied by kernel 100 to generate an output vector with bits [u1 + u2, u2]. Bits u1 and u2 are elements of a radix-2 Galois field. The use of polarization kernels in the context of binary polarized codes is described in more detail in E. Arikan’s “Channel polarization: A method for constructing capacity achieving codes for symmetric binary-input memoryless channels” (IEEE Transactions on Information Theory, Vol. 55, pp. 3051–3073, July 2009), the entire contents of which are incorporated herein by reference.

[0051] For non-binary codes, and referring to Figure 2, the input vector of the non-binary polarization kernel 200 includes non-binary symbols 210. Each non-binary symbol 210 maps to q binary bits. In this example, the input vector of kernel 200 includes non-binary symbols [s1, s2], and the output vector generated by kernel 200 includes non-binary symbols [c1, c2] = [s1 + γs2, s2], where γ is a predefined operation parameter. The non-binary symbols s1, s2 and the predefined operation parameter γ are base-2. q The Galois domain (called GF(2)) q The elements of GF(2) are given by GF(2), where q is an integer. The circled "+" symbol in kernel 200 represents GF(2). q Addition in ).

[0052] It should be noted that multiplying s2 by γ equals a cyclic permutation of the field elements, and GF(2) q The addition in ) is a bitwise XOR logical operation on the q-ary binary representations of s1 and γs2. The recursive application of core 200 in Figure 2 can construct non-binary polar codes.

[0053] In use, non-binary symbols are received from the encoding module at the receiver's decoding module for decoding. Each non-binary symbol is received through a communication channel of the receiver module. The implementation of the decoding module will be described in more detail below. A predetermined set of communication channels is defined as reliable channels for carrying non-binary symbols, while the inputs of the remaining communication channels (referred to as "frozen" channels) are set to fixed values ​​known at the decoding module.

[0054] Referring to Figure 3, a schematic diagram illustrating the use of the polarization encoding / decoding pipeline 300 is shown. From left to right in Figure 3, the polarization encoding / decoding pipeline 300 functions as a polarization non-binary encoder. From right to left in Figure 3, the polarization encoding / decoding pipeline 300 functions as a polarization non-binary decoder.

[0055] Input vector 310 includes "information" symbols and four "frozen" symbols. The "information" symbols are non-binary symbols s3, s5, s6, and s7 corresponding to the four reliable channels. The four "frozen" symbols are non-binary symbols set to 0 in this example and corresponding to frozen channels. The input vector includes K = 4 information non-binary symbols and NK = 4 frozen non-binary symbols. Each of these information non-binary symbols can be represented by q bits. In other words, each information non-binary symbol maps q bits of information. For example, in the scenario where q = 2, the encoder input can be 00010111, which can be mapped to the four information non-binary symbols 0, 1, 1, and 3. These four symbols can then be encoded by the non-binary encoder 300.

[0056] The output of the non-binary encoder 300 (i.e., x0...x7) is the encoded non-binary symbol. The encoded non-binary symbol can be converted into a binary sequence of length 8q, called a polar code.

[0057] In the illustrative example in Figure 3, the freeze for non-binary symbols is set to 0. The freeze for non-binary symbols can be set to another predetermined value known at the decoding and encoding modules.

[0058] The operational parameter γ can be selected from GF(2 q Randomly select from the elements of GF(2), or equal to GF(2). q The primitive element of ) . Polarization can be generated using random or fixed operational parameters γ, but this may not be efficient in terms of decoding latency. In one aspect of this technology, a low-latency decoding module suitable for fast SC decoding and system coding is provided.

[0059] Unlike binary polar codes, where each bit has only two possibilities, each non-binary symbol has 2... qThere are 100 possibilities. Therefore, a single log-likelihood ratio (LLR) cannot represent all the possibilities of a non-binary symbol. Therefore, an LLR vector of length q is defined for each non-binary symbol.

[0060] In some implementations, the LLR vector of c1 can be represented as:

[0061] Where k∈[0,..,2] q -1] and of It is the probability of the maximum likelihood field element associated with position c1.

[0062] Similarly, the LLR vector of c2 can be represented as:

[0063] Where, k∈[0,..,2] q -1] and of It is the probability of the maximum likelihood field element associated with position c2.

[0064] Figures 4 and 5 provide examples of SC decoding for non-binary polar codes in GF(4). Based on SC scheduling, the message to s1 is first calculated, and then the message to s2 is calculated based on the estimate of s1.

[0065] First, the estimated value of s1 is determined. Referring to Figure 4, the LLR vectors of c1 and c2 are used. More specifically, a permutation based on the operational parameter γ is applied.

[0066] Among them, Π γ It is a permutation matrix, based on the value of γ for LLR vectors. The elements are replaced.

[0067] Therefore, the LLR vector of s1 is defined as in:

[0068]

[0069] The estimated value of s1 Alternatively, traditional decision-making techniques can be used to determine the LLR vector based on s1.

[0070] After confirming After obtaining the estimated value, the estimated value of s2 can be determined. Referring to Figure 5, based on the operational parameter γ and the estimated value... Another substitution was applied

[0071] in, It is Π γ The inverse permutation, and It is based on The value of is the permutation matrix that permutes the elements of the LLR vector.

[0072] Therefore, the LLR vector of s1 is defined as in:

[0073] Where, 14 = [1,1,1,1] t .

[0074] The decoding examples described in Figures 4 and 5 involve GF(4). For GF(2) with q>2 q Decoding can be performed recursively based on the same process.

[0075] Referring back to Figure 3, the operations of pipeline 300 can be grouped into multiple operation groups 320, represented by a binary tree 600 as shown in Figure 6. Operation groups 320 are mapped to nodes 610 of the binary tree 600. The binary tree 600 includes a root node 602, leaf nodes 604, and intermediate nodes 606. By definition, each of the intermediate nodes 606 and the root node 602 has a right child node and a left child node. For example, in Figure 6, intermediate node 6061 has a left child node 6062 and a right child node 6063. The leaf nodes can be called "synthetic channels" or "polarization channels," both located on the encoding / decoding side of the polarization encoding / decoding pipeline 300. In other words, each leaf node 604 corresponds to a communication channel of the decoding module.

[0076] The node length N of each node s This corresponds to the number of operations in the corresponding operation group. In some implementations, the node length of a binary tree 600 is N. s node N o The matrix α that receives LLR derivation values ​​from the parent node. o .

[0077]

[0078] The output of a given node is of size N. s A vector containing N s There are corresponding estimated non-binary symbols. It is important to note that N... s It is a power of 2.

[0079] In use, a given node output includes a symbol vector β corresponding to the estimated set of non-binary symbols, as described below.

[0080] Although 6 levels are represented on binary tree 600, it should be understood that for a binary tree used to decode a non-binary code of length N, the number of tree levels is log2(N). Here, the code length is N = 32, therefore, 5 levels are shown for binary tree 600.

[0081] In this example, binary tree 600 can be used to decode an input vector [u0, u1, ..., u5] of 6 non-binary symbols into an output vector of the corresponding estimated non-binary symbols (or simply "estimates"). In use, the estimated value Used to determine the estimated value estimated value and Used to determine the estimated value And so on. This decoding process can be called Successive-Cancellation (SC) decoding and is performed by traversing the entire binary tree 600. The decoding process for decoding a binary tree containing binary data symbols can be implemented as described in A. Alamdar-Yazdi and FRKschischang, “A simplified successive cancellation decoder for polar codes” (IEEE Communications Express, Vol. 15, No. 12, pp. 1378-1380, published December 2011), the entire contents of which are incorporated herein by reference.

[0082] Therefore, decoding non-binary polar codes can be a high-latency task because an estimate is determined before the next estimate can be determined. The developers of this technology have designed the definition of special nodes in non-binary trees and algorithms for decoding these special nodes. Implementing these special nodes in a hardware-based decoding module reduces the number of components required to perform the functionality of the decoding module, thereby reducing the computation time of the decoding operation.

[0083] Figure 6 is a representation of a binary tree 600, where each node is associated with the same predefined computational parameter γ. In this implementation, at least the computational parameter of the leaf node 604 is set to equal to 1. For example, Figure 7AA representation of a binary tree 710 according to some implementations of the present technology is shown. In this illustrative implementation, the root node of the binary tree 710 has a first predefined operation parameter γ1, the nodes of the first level of the binary tree 710 have the same second predefined operation parameter γ2, and other nodes at other levels have their corresponding predefined operation parameters equal to 1. This simplifies the identification of special nodes, simplifies the decoding of special nodes, and enables the removal of the permutation operation, i.e., Π, from the SC decoding at the lower part of the binary tree. γ and This reduces the number of operations and shortens the computation time.

[0084] Thus, in this implementation, the computational parameters of nodes at the same level in binary tree 710 are equal. In this example, for a binary tree with at least three levels, the computational parameter of leaf node 604 is equal to 1. However, even without setting these predefined computational parameters for leaf node 1, it is still possible to define and decode special nodes for non-binary codes.

[0085] In the context of this disclosure, for a node of length N s Given node N o Node N o leaf node N o,0 N o,1 ...N o,m Mapped to node vector d0 = [N o,0 N o,1 ,..,N o,m It should be noted that the names given to special nodes are similar to those given to special nodes in a binary tree within the context of binary polar codes, as described in M. Hanif and M. Ardakani's "Fast successive-cancellation decoding of polar codes: Identification and decoding of new nodes" (IEEE Communications Letters, Vol. 21, No. 11, pp. 2360-2363, November 2017), the entire contents of which are incorporated herein by reference. However, the decoding of special nodes within the context of this disclosure differs from the decoding of special nodes in a binary tree within the context of binary polar codes, as described below.

[0086] refer to Figure 7A and Figure 7B The binary tree 710 can be simplified or "pruned" by identifying the special nodes it includes. Each special node can be decoded using a corresponding routine or algorithm to generate a new pruned binary tree 720. In the implementation, if the parent node of the first special node is the second special node, the first special node is ignored.

[0087] Rate0 node

[0088] For mapping node N o The node vector of the leaf node is d0 = [0,..,0], and the node N is... o Named "Rate0", and node N o The output is of size N s A vector consisting entirely of zeros. For example, in a node size of N. S When N = 8, node N o The output symbol vector is β = [0,0,0,0,0,0,0,0,0].

[0089] Rate1 node

[0090] For mapping node N o The node vector of the leaf node is d0 = [1,..,1], and the node N is... o Named "Rate1", and node N o The output is at α o N corresponding to an LLR derivation value of zero in each column s A vector of symbols. It can be said that the algorithm used to decode the "Rate1" node is a hard decision within the extended min sum (EMS) algorithm.

[0091] For example, in a node size of N S =4 and input matrix α o for In this case,

[0092] The output of this node is in α o N columns corresponding to an LLR of zero s The symbol vector is a vector of symbols. In this implementation, the EMS algorithm is used for hard decision. Therefore, the size of the output symbol vector β is 4: β = [0, 2, 2, 3].

[0093] For mapping node N o The node vector of the leaf node is d0 = [0,..,0,1], and the node N is... o Named "Repeat", or simply "REP". To determine the node's output, α... o The columns are summed to obtain a single vector of LLR derivations. Then, the symbol corresponding to the smallest LLR derivation is selected as the hard decision. The output of each node is the estimated N symbols. s Repeated 2 times.

[0094] For example, in a matrix α of size Ns = 4 and at the top of the nodes oIt is a 4×4 matrix (represented as: In this case,

[0095] α o The columns are summed to obtain a single vector of LLRs for decoding the REP nodes. The symbol corresponding to the minimum LLR is selected as the hard decision. In the implementation, the output is the estimated N of the symbols. s Repeat. Add α per row. o By determining the signs of the columns, we can obtain the vector α. + ,Right now

[0096]

[0097] α + The smallest symbol is 25, which corresponds to the symbol in row 2 (the indexes of each row are from 0 to 3). Therefore, the output of this node will be 4 repetitions of symbol 2, i.e., β = [2,2,2,2].

[0098] SPC Node

[0099] For mapping node N o The node vector of the leaf node is d0 = [0, 1, ..., 1, 1], and node N... o This is named "Single Parity Check," or simply "SPC." To determine the node's output, α... o Make a hard decision. More specifically, if the obtained estimate satisfies the condition based on GF(2). q If the parity equation for addition is satisfied, the output of the node is the estimated non-binary symbol. Otherwise, starting from the first symbol, each code character is replaced with a symbol that satisfies the parity check, and its corresponding LLR is recorded. Finally, the code character with the minimum LLR after replacement is selected to satisfy the parity check.

[0100] For example, in a matrix α of size Ns = 4 with the top of the nodes being a 4×4 matrix (represented as: In the case of ),

[0101] The first stage of decoding the SPC node is similar to the decoding of the Rate1 node, that is, decoding α... o Make a hard decision. In this example, through the hard decision, one can obtain... Instead of β, for the reasons explained below.

[0102] In the second stage, GF(4) The sum of the signs is compared with zero to check. Does it satisfy the parity equation in GF(4) (i.e., the sum equals zero)? In this example, the sum is: 0 + 2 + 2 + 3 = (0,0) + (1,0) + (1,0) + (1,1) = (1,1) = 3

[0103] The above sum is obtained by bitwise XORing the binary representation of each symbol. As you can see, the sum is 3 instead of 0, meaning the parity equation is not satisfied.

[0104] If the parity check is satisfied, then the output β equals Since the parity check is not satisfied, each symbol is replaced with another symbol that does satisfy the parity check, and its corresponding LLR is recorded. This produces four different vectors that can become the output of the SPC node:

[0105]

[0106] The LLR of the modified symbols described above represents the cost of changing these symbols. To minimize the cost, choose... As output, i.e.

[0107] T1 node

[0108] For mapping node N o The node vector of the leaf node is d0 = [0,0,..,0,1,1], and the node N is... o Named "Type 1", or simply "T1". To determine the node's output, the decoding algorithm for the REP node is applied to α. o Columns with even indexes and α o The column has an odd index. In effect, a T1 node is equivalent to having two REP nodes, one for even positions and one for odd positions. In the context of this disclosure, if the index of the symbol to be the output of a special node is from 0 to Ns-1, then the symbol at an even position is the symbol at positions 0, 2, 4…Ns-2, and the symbol at an odd position is the symbol at positions 1, 3…Ns–1.

[0109] For example, in a matrix α of size Ns = 8 and at the top of the nodes o It is a 4×8 matrix (represented as:

[0110] In this case,

[0111] This node is equivalent to having two REP nodes between symbols located at even and odd positions. Therefore, the same decoding for the REP nodes can be applied to both even and odd indices. Thus, for both even and odd indices, α o It can be decomposed into two submatrices, namely

[0112]

[0113] Similar to REP nodes, add α by row. od and α e By determining the column signs, we obtain:

[0114]

[0115] and The smallest symbols in the array are associated with symbols 0 and 2, respectively. Therefore, β can be written as β = [0, 2, 0, 20, 2, 0, 2]. The output of node T1 is the concatenation of the first non-binary data symbol and the second non-binary data symbol (here, 0 and 2) into N. s Repeat

[0116] T2 node

[0117] For mapping node N o The node vector of the leaf node is d0 = [0,0,..,0,1,1,1], and node N... o Named "Type 2", or simply "T2". This node can be viewed as having multiple Rate0 nodes on the left and an SPC node of size 4 on the right. Assuming the symbol vector at the output of the SPC node is {β′0,β′1,β′2,β′3}, then the symbol vector β at the output of the T2 node has a pattern similar to β={β′0,…,β′3,β′0,…,β′3,β′0,…,β′3,β′0,…,β′3,β′0,…}.

[0118] Therefore, the decoding algorithm at node T2 adds the LLR derivations of the non-binary symbols associated with the four partitions of β. These LLR derivations are then input into the NB decoder at the SPC node to obtain the estimates in the SC algorithm.

[0119]

[0120] For example, in a matrix α of size Ns = 8 and at the top of the nodes o It is a 4×8 matrix (represented as:

[0121] In this case,

[0122] This node consists of a Rate0 node as the left descendant and an SPC node of size 4 as the rightmost descendant. Assuming the symbol vector at the output of the SPC node is {β′0,β′1,β′2,β′3}, then the symbol vector β at the output of this T2 node has a pattern similar to β={β′0,…,β′3,β′0,…,β′3}. Therefore, the optimal maximum likelihood decoder adds the LLRs of the bits associated with the four partitions of β. These LLRs are then input to the non-binary decoder of the SPC node to obtain the estimate in the SC algorithm. Therefore, the LLR used for SPC decoding can be calculated as:

[0123] Where k′=0,…,N s K = 0, ..., 3, j = 0, ..., 2 q -1.

[0124] The matrix form is as follows:

[0125]

[0126] A decoding routine with an SPC node of size 4 as input can now be used. Assuming the output of the SPC decoder is the vector {β′0,β′1,β′2,β′3}, then the output of the T2 node is equal to β={β′0,β′1,β′2,β′3,β′0,β′1,β′2,β′3}.

[0127] T3 node

[0128] For mapping node N o The node vector of the leaf node is d0 = [0,0,1,..,1], and the node N is... o Named "Type 3", or simply "T3", this node is equivalent to having two SPC nodes between the even-numbered and odd-numbered symbols. Therefore, the decoding algorithm for the SPC nodes is applied to α... o Columns with even indexes and α o Columns with odd indexes.

[0129] For example, in a matrix α of size Ns = 8 with the top of the nodes being a 4×8 matrix (represented as:

[0130] In this case,

[0131] This node is equivalent to having two SPC nodes between the symbols located at even and odd positions. Therefore, the same decoding for the SPC nodes can be applied to both even and odd indices. In this example, for both even and odd indices, α oIt can be decomposed into two submatrices, namely

[0132] The decoding routines for SPC nodes can be applied to α respectively. e and α od Suppose the outputs of the SPC even decoder and the SPC odd decoder can be written as β respectively. e ={β e,0 ,…,β e,3} and β o ={β o,0 ,…,β o,3}, then the total output of node T3 can be written as β = [β e,0 ,β o,0 ,β e,1 ,β o,1 ,β e,2 ,β o,2 ,β e,3 ,β o,3 Therefore, the output of node T3 is an alternating concatenation of the first and second vectors.

[0133] T4 node

[0134] For mapping node N o The node vector of the leaf node is d0 = [0,0,0,1,..,1], and the node N is... o Named "Type 4", or simply "T4". This node consists of repeating nodes on the lower left, and its remaining child nodes are Rate1 nodes. The decoding algorithm for the T3 node first uses the decoding algorithm for the REP node to decode the REP node on the left, and then further divides the descendant nodes of the T3 node into 4 independent SPC nodes for parallel decoding.

[0135] For example, in a matrix α with node size Ns = 16 and at the top of the node o It is a 4×16 matrix (represented as:

[0136] In this case,

[0137] It's important to note that the T4 node includes the REP node of size 4 on the left side of the binary tree. To decode the T4 node, we first decode the REP node of size 4 in the bottom left corner. In other words, we calculate the 4×4 matrix α2 after the SC decoding routine described above, and then decode the REP node after the REP decoding routine described above.

[0138] Let the output of the REP node be the vector β2 = [z,z,z,z], where z is the symbol in GF(4). Then, the T4 node can be decomposed into four SPC equations with symbol indices differing by 4 (i.e., symbols (0,4,8,12), (1,5,9,13), (2,6,10,14), and (3,7,11,15)). Therefore, using s i The symbols representing β, and the relationships between the symbols of β, can be represented as follows:

[0139] s0+s4+s8+s 12 =z s1+s5+s9+s 13 =z s2+s6+s 10 +s 14 =z s3+s7+s 11 +s 15 =z

[0140] These four equations can be solved separately and in parallel using the SPC decoding routine described above. The only difference is that z is equal to zero in the SPC node, while z can be 0, 1, 2 or 3 (i.e. all elements of GF(4)) in the T4 node.

[0141] T5 node

[0142] For mapping node N o The node vector of the leaf node is d0 = [0,..,0,0,0,1,1,1], and node N... o This is named "Type 5", or simply "T5". The LLR vectors of symbols whose indices differ by a multiple of 8 are summed, resulting in 8 LLR vectors. These LLRs can be used to decode the REP and SPC nodes, which are children of the T5 node, sequentially. Finally, the estimated symbols are repeated at indices that differ by a multiple of 8 to obtain the output of the T5 node.

[0143] For example, refer to Figure 15 Given a node size of Ns = 32 and a 4×32 matrix α at the top of the node, calculate the soft matrix α at the input of the source node. s In this implementation, the source node is the parent node of the SPC node corresponding to the three "1"s in vector d. More specifically, the source node is a combination of a REP node and an SPC node. Assume the output of this source node is β. s = [s0,s1,…,s7], then the output of node T5 can be written as β = [s0,s1,…,s7,s0,s1,…,s7,s0,s1,…,s7,s0,s1,…,s7,s0,s1,…,s7].

[0144] 4×8 matrix α sIt can also be calculated by adding the columns in α whose indices differ by a step size of 8. For example, adding columns 0, 8, 16, and 24 will give you α. s The first column in the array. Get α. s Then, the REP node and SPC node can be decoded sequentially, and then based on β... s The symbol retrieves the output of the type 5 node.

[0145] EG-PC node

[0146] Node N o Named "Extended Generalized Parity Check", or simply "EG-PC", it responds to a value of n on the lower left. r The REP / Rate0 node has all its child nodes as Rate1 nodes. Figure 16 This illustrates one possible implementation of an EG-PC node. After decoding the REP node or Rate0 node on the left, the child nodes of this special node can be divided into n. r An independent non-binary SPC node capable of parallel decoding. This node is a generalization of T4.

[0147] In other words, the EG-PC node is a generalization of the T4 node described above. There are two differences between the EG-PC node and the T4 node. In the EG-PC node, the bottom-left node can be either REP or Rate0, and its size can be 4, 8, or any other multiple of 2. In T4, the size of the REP node is 4. The size of the bottom-left node determines the symbol index that constitutes the SPC equation. Let n be the size of the bottom-left node that is either the REP node or the Rate0 node. r This indicates that EG-PC nodes can be decomposed into symbol indices differing by n. r n r SPC equations. These n r These equations can be solved separately and in parallel using the SPC decoding routine described below. It should be noted that if the lower left node is a Rate0 node, then z equals zero, while for a REP node, z can be any element in GF(4).

[0148] G-REP node

[0149] Node N o Named "Generalized Repetition," or simply "G-REP," in response to having multiple Rate0 nodes on the left and a size of n on the lower right. r The source node (can be any type of node). Decoding this node is similar to decoding the T2 node. First, calculate the LLR at the input of the source node, as follows:

[0150] Then, perform N operations on the output codeword of the source node. s / n r This process is repeated several times to obtain the output of the G-REP node. The node size is N. s α s The dimension is 4×n s In the case where the index difference step size in α is n s α is obtained by adding the columns together. s The column. Calculate α. s Next, the source node can be decoded (depending on the type of the source node, this can be done using one of the decoding routines described above), and then based on β... s To calculate the output of the G-REP node.

[0151] Simulation results

[0152] Figure 8 This is a graph showing the simulation results of the error rate performance (frame error rate, FER, or bit error rate, as a function of signal to noise ratio, SNR) of BPC and NBPC using fast SC and SC decoders in a bit-interleaved coded modulation (BICM) scheme employing a 16QAM constellation. Dashed curves represent BER values, and solid curves represent FER values. Lines 810 and 820 represent the FER and BER values ​​of SC decoding of binary polar codes (i.e., GF(2)), respectively. Lines 830 and 840 represent the FER and BER values ​​of SCL decoding of binary polar codes with a list size of L=2, respectively. Lines 850 and 860 represent the FER and BER values ​​of non-binary polar codes constructed in GF(16) and decoded without identifying special nodes, respectively. Lines 870 and 880 represent the FER and BER values ​​of the non-binary polar code constructed in GF(16) and decoded by identifying special nodes using the proposed fast SC decoder. In this illustrative example, the total number of special nodes (leaf nodes after pruning the binary tree) is 102.

[0153] It can be seen that the error rate performance of NBPC using SC decoding is similar to that of BPC using SC list (L=2) decoding. Furthermore, the BER curve of NBPC using special nodes overlaps with that of NBPC without special nodes. This is because there is a slight difference between the FER curves of NBPC using special nodes and NBPC without special nodes. This difference is due to the suboptimal decoding of SPC nodes, as low-complexity and hardware-friendly decoding of SPC nodes is chosen. Generally speaking, achieving a specific BER or FER value with a lower SNR indicates better decoding performance. For example, Figure 8 It is shown that, with a BER of 1e–5, the non-binary polar code in GF(16) decoded using SC is approximately 0.35 dB to 0.4 dB more accurate than the binary polar code decoded using SC decoder.

[0154] In one aspect, this technology provides a dedicated hardware device for executing decoding routines of binary trees and their specific nodes. A given dedicated hardware device may include memory units (e.g., random-access memory (RAM) units) and computation units for decoding received encoded non-binary data symbols. Examples of dedicated hardware devices will be described in more detail below.

[0155] Figure 9 It is a representation diagram of a binary tree 910 with 4 levels, and Figure 10 This is an illustrative implementation of a dedicated hardware device 915 used to decode received encoded non-binary data symbols via a binary tree 910. Figure 10 The specific uses of the compute block and memory block of the dedicated hardware device 915 are described in the document.

[0156] In comparison, Figure 11 This is a representation of binary tree 920, which is a pruned version of binary tree 910 defined using the special nodes described above. Figure 12 This is an illustrative implementation of a dedicated hardware device 925 used to decode received encoded non-binary data symbols via a binary tree 920. Figure 12 The specific uses of the compute block and memory block of the dedicated hardware device 925 are described in the document. Figure 12 The blocks denoted as "SPC" and "REP" are computational blocks that execute the decoding routines of the SPC node and the REP node, respectively, as described above.

[0157] Such as about Figure 10 and Figure 12As can be seen, the number of memory units and computing units in the dedicated hardware device 925 is greatly reduced, which provides a smaller footprint, faster computing speed, and cheaper implementation cost to decode the received encoded non-binary data symbols.

[0158] In a broader sense, this technology can thereby reduce latency in the decoding process in practical applications such as fiber optic communication and 5G. In addition to the definition of special nodes, a simplified structure for NBPC with specific decoding routines for said special nodes is proposed.

[0159] In some implementations, the dedicated hardware device 925 is part of a digital signal processor (DSP) chip in an encoding / decoding system or any electronic device used to encode and / or decode non-binary symbols. In the same or other implementations, the dedicated hardware device 925 is part of a forward error correction code (FEC) block in the encoding / decoding system or electronic device.

[0160] Figure 13 This is a block diagram illustrating a system 200 configured to receive and decode encoded non-binary data symbols. System 200 is communicatively connected to a communication medium 155 for receiving encoded non-binary data symbols therefrom, and includes a receiving module 210 and a decoding module 220 for outputting decoded data 250. However, it should be understood that in some embodiments of this art, system 200 may use a different approach than... Figure 13 The components shown can be implemented with more, fewer, and / or different components. For example, system 200 can be implemented as an optical communication system (e.g., an optical transceiver) to enable medium-rate, long-code communication via communication medium 155 or another optical communication medium. In a non-limiting implementation, communication medium 155 is an optical communication medium, such as optical fiber. It is envisioned that receiver module 210 can support optical terminal functionality and signal conversion between the electrical and optical domains to receive encoded non-binary data symbols via optical communication medium 155. For example, but not limited to, decoding module 220 can be implemented as a dedicated hardware device 925.

[0161] Among other factors, the structure and operation of each of these modules may also depend on the physical medium and the signaling mechanisms or protocols of the components of the system 200 executing these modules. Typically, each component includes at least some physical connection to the transmission medium and may also incorporate other hardware- and / or software-based elements, which, among other factors, depend on the specific transmission medium and / or specific mechanism and / or specific implementation of this technology.

[0162] refer to Figure 14 The diagram illustrates an electronic device 105 according to a non-limiting implementation of the present technology. In this embodiment, the system 200 is implemented as the electronic device 105, which is adapted to perform all the functions of the system 200, including the functions of the receiving module 210 and the decoding module 220.

[0163] Electronic device 105 includes computing unit 107. In some implementations, computing unit 107 may be implemented by any of a conventional personal computer, controller, and / or electronic device (e.g., server, controller unit, control device, monitoring device, etc.) and / or any combination thereof suitable for the relevant task at hand. In some embodiments, computing unit 107 includes various hardware components, including one or more single-core or multi-core processors represented by processor 120, solid-state drive 130, RAM 140, dedicated memory 150, and input / output interface 160. Computing unit 107 may be a general-purpose computer system.

[0164] In some other embodiments, computing unit 107 may be an "off-the-shelf" general-purpose computer system supplemented by adding dedicated hardware device 925. In some embodiments, computing unit 107 may also be distributed among multiple systems. Computing unit 107 may also be specifically designed to implement this technology. As those skilled in the art will appreciate, various variations on how computing unit 107 can be conceived without departing from the scope of this technology.

[0165] Communication between various components of the computing unit 107 can be achieved through one or more internal and / or external buses 180 (e.g., PCI bus, Universal Serial Bus, IEEE 1394 "Firewire" bus, SCSI bus, Serial ATA bus, ARINC bus, etc.), with various hardware components electrically coupled to these buses.

[0166] Input / output interface 160 can provide networking capabilities, such as wired or wireless access. For example, input / output interface 160 may include network interfaces, such as, but not limited to, one or more network ports, one or more network sockets, one or more network interface controllers, etc. Several examples of how a network interface can be implemented will become apparent to those skilled in the art. For example, but not limited to, the network interface can implement specific physical layer and data link layer standards, such as Ethernet, Fibre Channel, Wi-Fi, or Token Ring. Specific physical and data link layers can provide the foundation for a complete network protocol stack, facilitating communication between small groups of computers on the same local area network (LAN) and large-scale network communication via routable protocols such as the Internet Protocol (IP).

[0167] According to the implementation of this technology, the solid-state drive 130 stores program instructions suitable for loading into RAM 140 and being executed by processor 120. Although shown as solid-state drive 130, any type of memory can be used in place of solid-state drive 130, such as hard disk, optical disk, and / or removable storage media.

[0168] Processor 120 may be a general-purpose processor, such as a central processing unit (CPU), or a purpose-specific processor, such as a digital signal processor (DSP). In some embodiments, processor 120 may also rely on an accelerator 170 dedicated to certain given tasks. For example, accelerator 170 may be a dedicated hardware device 925. In some embodiments, processor 120 or accelerator 170 may be implemented as one or more field-programmable gate arrays (FPGAs). Furthermore, the explicit use of the term "processor" should not be construed as referring specifically to hardware capable of executing software, and may implicitly include, but is not limited to, application-specific integrated circuits (ASICs), read-only memory (ROM) for storing software, RAM, and non-volatile memory. Other conventional and / or custom hardware may also be included.

[0169] Furthermore, the electronic device 105 may include a Human-Machine Interface (HMI) 106. The HMI 106 may include a screen or display capable of presenting an interface and instructions for encoding and / or decoding data, and / or any other information suitable for performing the routines and techniques described herein. In this embodiment, the display of the HMI 106 includes and / or is equipped with a touchscreen so that a user can input data via a combination of a virtual keyboard, icons, menus, or other graphical user interface (GUI). Therefore, the HMI 106 may be referred to as the user interface 106. In some embodiments, the display of the user interface 106 may be implemented using a liquid crystal display (LCD) or a light-emitting diode (LED) display (e.g., an organic LED (OLED) display). The device may be (e.g., but not limited to) a handheld computer, a personal digital assistant, a cellular phone, a network device, a smartphone, a navigation device, an email device, a game console, or a combination of two or more of these data processing devices or other data processing devices. The user interface 106 may be as follows: Figure 14 The embodiments shown are embedded in the electronic device 105, or may be located in an external physical location accessible to the user. For example, the user can communicate with the computing unit 107 via a user interface 106 wirelessly connected to the computing unit 107 (i.e., send instructions to the computing unit 107 and receive information from the computing unit 107). The computing unit 107 may communicate with the user interface 106 via a network such as a Local Area Network (LAN) (not shown) and / or a wireless connection such as a Wireless Local Area Network (WLAN).

[0170] Electronic device 105 may include memory 102 communicatively connected to computing unit 107 to store received encoded data and / or generated decoded data. Memory 102 may be as follows: Figure 14 The embodiment shown is embedded in the electronic device 105, or may be located in an external physical location. The computing unit 107 may be configured to access the contents of the memory 102 via a network such as a Local Area Network (LAN) (not shown) and / or a wireless connection such as a Wireless Local Area Network (WLAN).

[0171] Needless to say, the computing unit 107 can be implemented with any other suitable hardware, software, and / or firmware, or a combination thereof. Figure 14 In the non-limiting embodiment of the present technology shown, the computing unit 107 is a single component. In alternative non-limiting embodiments of the present technology, the function of the computing unit 107 can be distributed and can be implemented via multiple components.

[0172] Those skilled in the art will understand that processor 120 generally represents processing power that can be provided by, for example, a central processing unit (CPU). In some embodiments, one or more dedicated processing cores may be provided to replace or supplement one or more conventional CPUs. For example, one or more graphics processing units (GPUs), tensor processing units (TPUs), accelerator processors (or processing accelerators), and / or any other processing units suitable for performing decoding protocols may be provided to supplement or replace one or more CPUs. In an alternative implementation, the dedicated memory 140 may be random access memory (RAM), video random access memory (VRAM), window random access memory (WRAM), multibank dynamic random access memory (MDRAM), double data rate (DDR) memory, graphics double data rate (GDDR) memory, high-bandwidth memory (HBM), fast-cycle random-access memory (FCRAM), or any other suitable type of computer memory.

[0173] Although the above implementation has been described and illustrated with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered without departing from the guidance of this technology. At least some of these operations can be performed in parallel or sequentially. Therefore, the order and grouping of these operations are not limitations of this technology.

[0174] Those skilled in the art will recognize that the descriptions of various embodiments are merely illustrative and not intended to be limiting in any way. Other embodiments will be self-evident to those skilled in the art who benefit from this disclosure. Furthermore, at least some of the disclosed embodiments can be tailored to provide valuable solutions to existing needs and problems related to FEC schemes. For clarity, not all conventional features of the implementation of at least some of the disclosed embodiments are shown or described.

[0175] Specifically, the combinations of features are not limited to those presented in the foregoing description, as combinations of elements listed in the appended claims form part of this disclosure. It should be understood, of course, that in developing any such practical implementation of at least some of the disclosed embodiments, many implementation-specific decisions may need to be made to achieve the developer’s specific objectives, such as compliance with constraints related to the application, system, and business, and these specific objectives will vary from implementation to implementation and from developer to developer. Furthermore, it should be understood that the development work may be complex and time-consuming, but it is a routine engineering task for those skilled in the art of digital error correction who will benefit from this disclosure.

[0176] Based on this disclosure, the components, process operations, and / or data structures described herein can be implemented using various types of operating systems, computing platforms, network devices, computer programs, and / or general-purpose machines. Furthermore, those skilled in the art will recognize that less general-purpose devices, such as hardwired devices, field-programmable gate arrays (FPGAs), or application-specific integrated circuits (ASICs), can also be used. When a routine comprising a series of operations is implemented by a computer, a processor operatively connected to memory, or a machine, these operations can be stored as a series of instructions readable by the machine, processor, or computer, and can be stored on a non-transitory tangible medium.

[0177] The systems and modules described herein may include software, firmware, hardware, or any combination of software, firmware, or hardware suitable for the purposes described herein. The software and other modules may be executed by a processor and reside on the memory of a server, workstation, personal computer, computerized tablet, personal digital assistant (PDA), and other devices suitable for the purposes described herein. The software and other modules may be accessed via local memory, via a network, via a browser or other application, or via other means suitable for the purposes described herein. The data structures described herein may include computer files, variables, programming arrays, programming structures, or any electronic information storage schemes, routines, and techniques suitable for the purposes described herein, or any combination thereof.

[0178] It should be clearly understood that not all of the technical effects mentioned herein can be enjoyed in every implementation of this technology.

[0179] Modifications and improvements to the above implementation of this technology will be apparent to those skilled in the art. The above description is intended to be exemplary and not restrictive. Therefore, the scope of this technology is intended to be limited only by the scope of the appended claims.

Claims

1. A dedicated hardware device for decoding data, said data comprising a plurality of encoded non-binary data symbols, said dedicated hardware device being configured to: The plurality of encoded non-binary data symbols are received, and each encoded non-binary data symbol is received through a corresponding channel; Determine the log-likelihood ratio vector for each encoded non-binary data symbol; The successive elimination decoding routine is applied to a plurality of log-likelihood ratio vectors, the successive elimination decoding routine comprising one or more sets of operations to be applied to a subset of the plurality of log-likelihood ratio vectors; as well as Multiple decoded non-binary data symbols are generated based on the results of the continuous elimination decoding routine.

2. The dedicated hardware device according to claim 1, wherein, The one or more operation groups comprise multiple operation groups, and subsets of the multiple operation groups are sequentially applied to subsets of the multiple log-likelihood ratio vectors, such that the output of a given operation group is used at least partially as the input of a successive operation group.

3. The dedicated hardware device according to claim 1, wherein, The initial iteration of the sequential elimination decoding routine includes: Applying the first set of operations to the subset of the plurality of log-likelihood ratio vectors, wherein the execution of each operation in the first set of operations includes: Perform a first permutation operation on the first log-likelihood ratio vector to define a first permutation log-likelihood ratio vector, the first permutation operation being defined based on the value of the first parameter; The first output is determined based on the first permutation log-likelihood ratio vector and the second log-likelihood ratio vector; A second permutation operation is performed on the first log-likelihood ratio vector to define a second permutation log-likelihood ratio vector, the second permutation operation being defined based on the value of the first parameter and the first output; The second output is determined based on the first permutation log-likelihood ratio vector and the second permutation log-likelihood ratio vector.

4. The dedicated hardware device according to claim 1, wherein, The final iteration of the sequential elimination decoding routine includes: Applying the final set of operations to the output of the previous set of operations, wherein the execution of each operation in the final set of operations includes: In the sequential elimination decoding routine, a first permutation operation is performed on the first output of the previous operation group to define a first permutation vector, the first permutation operation being defined based on the value of a first parameter; The first main output of the successive elimination decoding routine is determined based on the first permutation vector and the second output of the previous operation group; Perform a second permutation operation on the first output of the previous operation group to define a second permutation output, the second permutation operation being defined based on the value of the first parameter and the first main output; and The second main output is determined based on the second permutation vector and the second output of the previous operation group.

5. The dedicated hardware according to claim 1, wherein, The log-likelihood ratio vector includes 2 q The elements of the Galois field of q are integers corresponding to the number of bits mapped in each non-binary data symbol.

6. The dedicated hardware device according to claim 1, wherein, At least one operation in one or more operation groups includes performing an Extended Minimum Sum (EMS) operation.

7. The dedicated hardware device according to claim 1, wherein: Each of the one or more operation groups is mapped to a node of a binary tree, and each node has a corresponding node size N. s It receives a corresponding input matrix as input, the columns of which correspond to the log-likelihood ratio vector affected by the operations in the previous operation group, and each leaf node of the binary tree corresponds to one of the corresponding channels.

8. The dedicated hardware device according to claim 7, wherein, The corresponding channel includes a predetermined set of information channels, and the dedicated hardware device is further configured to: Identify one or more predetermined decoding routines to be executed on the binary tree.

9. The dedicated hardware device according to claim 8 is further configured to: Identify a given node of the binary tree, wherein the leaf nodes of the given node can be represented as a vector d = [a,...,a], where... Each of the corresponding channels is represented as "b" for the information channel and as "a" in other cases; as well as By setting the output of the given node to a size of N s The all-zero vector is used to perform a predetermined decoding routine on the given node.

10. The dedicated hardware device according to claim 8 is further configured to: Identify a given node of the binary tree, wherein the leaf nodes of the given node can be represented as a vector d = [b,...,b], where, Each of the corresponding channels is represented as "b" for the information channel and as "a" in other cases; and By outputting N s A vector of symbols is used to perform a predetermined decoding routine on the given node, wherein the corresponding correspondence likelihood ratio vector of the symbols in each column of the corresponding input matrix is ​​zero.

11. The dedicated hardware device according to claim 10 is further configured to: Identify a given node of the binary tree, wherein the leaf nodes of the given node can be represented as a vector d = [a,...,a,b], where, Each of the corresponding channels is represented as "b" for the information channel and as "a" in other cases; as well as The given node is subjected to a predetermined decoding routine by the following operations: Summing the columns of the corresponding input matrix to obtain a sum vector; The non-binary data symbol corresponding to the smallest element of the sum vector is selected, and the output of the third special node is N of the selected non-binary data symbol. s Repeated 2 times.

12. The dedicated hardware device according to claim 10 is further configured to: Identify a given node of the binary tree, wherein the leaf nodes of the given node can be represented as a vector d = [a, b, ..., b], where, Each of the corresponding channels is represented as "b" for the information channel and as "a" in other cases; as well as The given node is subjected to a predetermined decoding routine by the following operations: Generate N s A vector of N non-binary data symbols s The corresponding correspondence likelihood ratio vector for each non-binary data symbol in each column of the corresponding input matrix is ​​zero; and In response to the N s A vector of non-binary data symbols satisfies the GF(2)-based algorithm. q Parity check equation for addition, The N s A vector of non-binary data symbols is set as the output of the node, and In other cases, starting with the first non-binary data symbol, each non-binary data symbol is replaced with a non-binary data symbol that satisfies the parity equation.

13. The dedicated hardware device according to claim 10 is further configured to: Identify a given node of the binary tree, wherein the leaf nodes of the given node can be represented as a vector d = [a,...,a,b,b], where... Each of the corresponding channels is represented as "b" for the information channel and as "a" in other cases; as well as The given node is subjected to a predetermined decoding routine by the following operations: Summing the columns with even indices in the corresponding input matrix to obtain a first sum vector; Select the first non-binary data symbol corresponding to the smallest element of the first sum vector; Summing the columns with odd indices in the corresponding input matrix to obtain a second sum vector; Select the second non-binary data symbol corresponding to the smallest element of the second sum vector; The output of the node is N, which is the concatenation of the first non-binary data symbol and the second non-binary data symbol. s Repeated 2 times.

14. The dedicated hardware device according to claim 10 is further configured to: Identify a given node of the binary tree, wherein the leaf nodes of the given node can be represented as a vector d = [a,...,a,b,b,b], where... Each of the corresponding channels is represented as "b" for the information channel and as "a" in other cases; as well as The given node is subjected to a predetermined decoding routine by the following operations: pass Determine the second matrix. Where, α k′,j These are the coefficients of the input matrix; Generate N s A vector of N non-binary data symbols s The correspondence likelihood ratio vector of each non-binary data symbol in each column of the second matrix is ​​zero; and In response to the N s A vector of non-binary data symbols satisfies the GF(2)-based algorithm. q Parity check equation for addition, The N s A vector of non-binary data symbols is set as the output of the node, and In other cases, starting with the first non-binary data symbol, each non-binary data symbol is replaced with a non-binary data symbol that satisfies the parity check.

15. The dedicated hardware device according to claim 10 is further configured to: Identify a given node of the binary tree, wherein the leaf nodes of the given node can be represented as a vector d = [a, a, b, ..., b], where, Each of the corresponding channels is represented as "b" for the information channel and as "a" in other cases; as well as The given node is subjected to a predetermined decoding routine by the following operations: Generate N s The first vector consisting of / 2 non-binary data symbols, the N s The corresponding correspondence likelihood ratio vector for each of the two non-binary data symbols in each column with an even index in the corresponding input matrix is ​​zero; and In response to the first vector not satisfying GF(2) q The parity equation for addition, starting with the first non-binary data symbol, replaces each non-binary data symbol with a non-binary data symbol that satisfies the parity check. Generate N s The second vector consisting of / 2 non-binary data symbols, the N s The corresponding correspondence likelihood ratio vector for each of the two non-binary data symbols in each column of the corresponding input matrix with an odd index is zero; and In response to the second vector not satisfying GF(2) q The parity equation for addition replaces each non-binary data symbol with a non-binary data symbol that satisfies the parity check. The output of the node is an alternating concatenation of the first vector and the second vector.

16. The dedicated hardware device according to claim 10 is further configured to: Identify a given node of the binary tree, wherein the leaf nodes of the given node can be represented as a vector d = [a, a, a, b, ..., b], where, Each of the corresponding channels is represented as "b" for the information channel and as "a" in other cases; as well as The given node is subjected to a predetermined decoding routine by the following operations: Summing the columns of the corresponding input matrix to obtain a sum vector; Select the first non-binary data symbol corresponding to the smallest element of the sum vector; Generate N s A vector of -1 non-binary data symbols, wherein N s -1 non-binary data symbols have a corresponding correspondence likelihood ratio vector of zero in each column of the corresponding input matrix; and In response to the vector not satisfying GF(2) q The parity equation for addition replaces each non-binary data symbol with a non-binary data symbol that satisfies the parity check. The output of the node is the concatenation of the vector and the first non-binary data symbol.

17. The dedicated hardware device according to claim 10 is further configured to: Identify a given node of the binary tree, wherein the leaf node of the given node can be represented as a vector d = [a,...,a,a,a,b,a,b,b,b], where... Each of the corresponding channels is represented as "b" for the information channel and as "a" in other cases; as well as The given node is subjected to a predetermined decoding routine by the following operations: The columns in the input matrix whose indices differ by a multiple of 8 are summed to define eight LLR output vectors; The output of the node is a repeated concatenation of the eight LLR output vectors.

18. The dedicated hardware device according to claim 10 is further configured to: Identify a given node of the binary tree, wherein the leaf nodes of the given node can be represented as a vector d = [a,...,a,b,...,b], where the vector includes n r There are several "a"s, among which... The channel is denoted as "b" for information channels and as "a" in other cases; and The given node is subjected to a predetermined decoding routine by the following operations: Determine n r A set of equations; For each equation, the n equations are solved in parallel using the following operations. r Equations: Generate N s / n r A vector of N non-binary data symbols s / n r The corresponding correspondence likelihood ratio vector for each non-binary data symbol in each column of the corresponding input matrix is ​​zero; and In response to the N s / n r A vector of non-binary data symbols satisfies the GF(2)-based algorithm. q Parity check equation for addition, The N s / n r A vector of non-binary data symbols is set as the output of the node, and In other cases, starting with the first non-binary data symbol, each non-binary data symbol is replaced with a non-binary data symbol that satisfies the parity equation.

19. The dedicated hardware device according to claim 7, wherein, Each node is associated with computational parameters used to perform the operations in the corresponding operation group.

20. The dedicated hardware device according to claim 19, wherein, The computational parameters of nodes at the same level in the binary tree are equal.

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