Deposition apparatus and method of manufacturing display device using the same

Abstract

A deposition apparatus and a method of manufacturing a display device using the same are provided. The deposition apparatus includes: a deposition source; a mask disposed between the first substrate and the deposition source; a mask support disposed between the deposition source and the mask and supporting at least a portion of the mask; and a magnetic member disposed on the first substrate and fixing the mask support with a magnetic force. The magnetic member includes a plurality of magnets extending in a first direction. The mask support extends in a second direction perpendicular to the first direction.

Description

TECHNICAL FIELD

[0001] Embodiments relate to a deposition apparatus and a method of manufacturing a display device using the deposition apparatus. BACKGROUND

[0002] A wearable device in the form of glasses or a helmet that forms a focal point at a distance close to a user's eyes has been developed. For example, the wearable device can be a head-mounted display (HMD) or AR glasses. The wearable device provides a user with an augmented reality (hereinafter, referred to as "AR") screen or a virtual reality (hereinafter, referred to as "VR") screen.

[0003] A wearable device such as an HMD or AR glasses requires a display specification of approximately 3000 PPI (pixels per inch) or more so that a user can use it for a long time without dizziness. For this, an organic light emitting diode on silicon (OLEDoS), which is a high-resolution small organic light emitting display device, is emerging. The organic light emitting diode on silicon (OLEDoS) technology is a technology for disposing an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is disposed.

[0004] A high-resolution deposition mask is required to manufacture a high-resolution display panel of approximately 3000 PPI or more. As a deposition mask for manufacturing an OLEDoS display panel, a mask that deposits an inorganic film on a silicon substrate and patterns the deposited inorganic film to form a mask film is being studied. However, a gap between the mask and a deposition surface of a deposition substrate increases due to the weight of the mask film formed of the inorganic film. The gap is pointed out as a cause of a shadow defect or a color mixing defect. SUMMARY

[0005] Embodiments provide a deposition apparatus capable of reducing a shadow defect or a color mixing defect by reducing a gap between a deposition substrate and a mask and a method of manufacturing a display device using the deposition apparatus.

[0006] However, embodiments are not limited to the embodiments set forth herein. The above and other embodiments will be apparent from the disclosure given below by referring to the accompanying drawings.

[0007] According to embodiments, a deposition apparatus can include a deposition source, a mask disposed between the first substrate and the deposition source, a mask support disposed between the deposition source and the mask and supporting at least a portion of the mask, and a magnetic member disposed on the first substrate and fixing the mask support with a magnetic force. The magnetic member can include a plurality of magnets extending in a first direction. The mask support can extend in a second direction perpendicular to the first direction.

[0008] The mask can include a silicon substrate including a plurality of unit areas, an outer frame area disposed on an outermost edge of the plurality of unit areas, and a mask lip area disposed at a periphery of the plurality of unit areas, and a mask film disposed on the silicon substrate to correspond to the plurality of unit areas.

[0009] The mask film can include an inorganic film.

[0010] The inorganic film can include at least one of silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si), and aluminum oxide (AlO x ), and x can be a natural number other than zero.

[0011] The plurality of unit areas can be arranged in a matrix form. The mask support can include a plurality of first magnetic lifters disposed to intersect between the plurality of unit areas, and a plurality of second magnetic lifters disposed on both sides of the plurality of first magnetic lifters and supporting the outer frame area.

[0012] Each of the plurality of first magnetic lifters can have a first width in a first direction. Each of the plurality of second magnetic lifters can have the first width in the first direction.

[0013] Each of the plurality of first magnetic lifters can have a first width in a first direction. Each of the plurality of second magnetic lifters can have a second width smaller than the first width in the first direction.

[0014] The magnetic member can include a first magnet having a first polarity and extending in a first direction, and a second magnet having a second polarity and extending in the first direction.

[0015] The first magnet and the second magnet can be alternately arranged in a second direction.

[0016] The mask support can include a ferromagnetic substance.

[0017] A method of manufacturing a display device can include placing a first substrate on a surface of a mask inside a chamber of a deposition apparatus, placing a deposition source to face a surface of the first substrate, evaporating a deposition material included in the deposition source, passing the deposition material through the mask, and depositing the deposition material on the first substrate. The deposition apparatus can include a mask support disposed between the deposition source and the mask and supporting at least a portion of the mask, and a magnetic member disposed on the first substrate and fixing the mask support. The magnetic member can include a plurality of magnets extending in a first direction. The mask support can extend in a second direction perpendicular to the first direction.

[0018] The mask can include a silicon substrate including a plurality of unit areas, an outer frame area disposed on an outermost edge of the plurality of unit areas, and a mask lip area disposed at a periphery of the plurality of unit areas, and a mask film disposed on the silicon substrate to correspond to the plurality of unit areas.

[0019] The mask film can include an inorganic film.

[0020] The inorganic film can include at least one of silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si), and aluminum oxide (AlO x ), and x can be a natural number other than zero.

[0021] The plurality of unit areas can be arranged in a matrix form. The mask support can include a plurality of first magnetic lifters disposed to intersect between the plurality of unit areas, and a plurality of second magnetic lifters disposed at both sides of the plurality of first magnetic lifters and supporting the outer frame area.

[0022] Each of the plurality of first magnetic lifters can have a first width in a first direction. Each of the plurality of second magnetic lifters can have the first width in the first direction.

[0023] Each of the plurality of first magnetic lifters can have a first width in a first direction. Each of the plurality of second magnetic lifters can have a second width smaller than the first width in the first direction.

[0024] The magnetic member can include a first magnet having a first polarity and extending in a first direction, and a second magnet having a second polarity and extending in the first direction.

[0025] The first magnet and the second magnet can be alternately arranged in a second direction.

[0026] The mask support can include a ferromagnetic substance.

[0027] According to an embodiment, a shadow defect or a color mixture defect can be reduced by reducing a gap between a deposition substrate and a mask. BRIEF DESCRIPTION OF DRAWINGS

[0028] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiments and together with the description serve to explain the principles of the present disclosure. Figure 1 is an exploded perspective view illustrating a display device according to one embodiment; Figure 2is a schematic block diagram illustrating a display device according to an embodiment; Figure 3 is a schematic diagram of an equivalent circuit of a first sub-pixel according to an embodiment; Figure 4 is a schematic diagram illustrating a layout of a display panel according to an embodiment; Figure 5 and Figure 6 is a schematic diagram illustrating a layout of a display area of Figure 4 according to an embodiment; Figure 7 is a schematic cross-sectional view illustrating an embodiment of a display panel taken along a line II-II’ of Figure 5 Figure 8 is a perspective view illustrating a head-mounted display according to an embodiment; Figure 9 is an exploded perspective view illustrating an embodiment of a head-mounted display of Figure 8 Figure 10 is a perspective view illustrating a head-mounted display according to an embodiment; Figure 11 is a perspective view of a mask according to an embodiment; Figure 12 is a schematic plan view of a mask according to an embodiment; Figures 13 to 21 is a schematic cross-sectional view illustrating a method of manufacturing a mask according to an embodiment; Figure 22 is a schematic diagram schematically illustrating a deposition apparatus according to an embodiment; Figure 23 is an exploded perspective view of a deposition apparatus according to an embodiment; Figure 24 is a schematic diagram of a magnetic member and a mask support according to an embodiment; and Figure 25 is a schematic diagram of a magnetic member and a mask support according to another embodiment. DETAILED DESCRIPTION

[0029] Embodiments will now be described more fully hereinafter with reference to the accompanying drawings. Embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout the disclosure the same reference numerals are used for the same components. In the drawings, the thicknesses of layers and regions can be exaggerated for clarity.

[0030] For the description of the disclosed embodiments, some components (parts) among a plurality of components (parts) can not be provided, which are not relevant to the description.

[0031] ​​It will be further understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. It will be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms since such terms are only used to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section.

[0032] Furthermore, the phrase "in plan view" means when viewing a subject portion from above, and the phrase "in schematic cross-sectional view" means when viewing a schematic cross-section taken through a vertical cut of a subject portion from the side. The term "overlying" or "overlaid" means that a first object can be above or below or to the side of a second object or vice versa. Furthermore, the term "overlying" can include superposed, stacked, facing or facing toward, extending over (throughout) or under, covering or partially covering, or any other suitable term that will be appreciated and understood by one of ordinary skill in the art. The expression "not overlying" can include the meaning of "away from" or "offset from" or "offset away from" as well as any other suitable equivalent that will be appreciated and understood by one of ordinary skill in the art. The terms "facing" and "facing toward" can mean that a first object can be directly or indirectly opposite a second object. In case a third object is interposed between the first object and the second object, the first object and the second object can be understood as indirectly opposite each other, although they are still facing each other.

[0033] To facilitate description, spatially relative terms, such as "below," "under," "lower," "above," "upper" and the like, can be used herein for describing the relationship between one element or component and another element or component as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, in the case of an object being flipped over, a device that is "below" or "under" another device can be placed "above" the other device. Accordingly, the illustrative spatially relative terms can include top and bottom, upward and downward, and so on. Devices can also be oriented in other directions, and accordingly spatially relative terms can be interpreted differently depending on the orientation of the device.

[0034] When an element is referred to as being "connected" or "coupled" to another element, it can be "directly connected" or "directly coupled" to the other element or "electrically connected" or "electrically coupled" to the other element with one or more intervening elements therebetween. It will be understood that, when the term "includes" or "comprises" or "has" or "contains" is used in the specification, it can specify the presence of stated features, integers, steps, operations, elements, components, or a combination thereof, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or a combination thereof.

[0035] It will be understood that, although the terms "first," "second," "third," etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a "first element" could be termed a "second element," and, similarly, a "second element" could be termed a "first element," without departing from the teachings herein.

[0036] The terms "about" or "approximately" as used herein encompass the recited value and mean within an acceptable range of deviation for a particular value, taking into account measurement of the value and error associated with measurement of the particular quantity (e.g., limitations of the measurement system), as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within about ±30%, ±20%, ±10%, ±5% of the recited value.

[0037] In the description, the term "and / or," for the purpose of the meaning and interpretation of the term, is intended to include any and all combinations of one or more items in the list of items. For example, "A and / or B" can be understood as meaning "A, B, or A and B." The terms "and" and "or" can be used in the conjunctive sense or disjunctive sense and can be understood to be equivalent to "and / or." In the description, the phrase "at least one of (a kind(s) / plurality)" is intended to include the meaning of "at least one selected from a group of (a kind(s) / plurality)" for the purpose of the meaning and interpretation of the phrase. For example, "at least one of A and B" can be understood as meaning "A, B, or A and B."

[0038] Unless otherwise defined or implied, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless clearly defined herein.

[0039] Figure 1 FIG. 1 is an exploded perspective view showing a display device according to one embodiment. Figure 2 FIG. 2 is a schematic block diagram showing a display device according to one embodiment.

[0040] Referring to Figure 1 and Figure 2The display apparatus 10 according to an embodiment can be an apparatus that displays moving images or still images. The display apparatus 10 according to an embodiment can be applied to a portable electronic apparatus such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation system, an ultra mobile PC (UMPC), etc. For example, the display apparatus 10 according to an embodiment can be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) terminal. For example, the display apparatus 10 according to an embodiment can be applied to a smart watch, a watch phone, a head-mounted display (HMD) for implementing virtual reality and augmented reality, etc.

[0041] The display apparatus 10 according to an embodiment can include a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing controller 400, and a power supply circuit 500.

[0042] The display panel 100 can have a shape similar to a quadrilateral shape in a plan view. For example, the display panel 100 can have a planar shape similar to a quadrilateral shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, a corner where the short side in the first direction DR1 and the long side in the second direction DR2 meet can be a right angle or a rounded corner (or a fillet) having a curvature. The planar shape of the display panel 100 is not limited to the quadrilateral shape, and the display panel 100 can have a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display apparatus 10 can conform to the planar shape of the display panel 100, but the disclosure is not limited thereto.

[0043] The display panel 100 can include a display area DAA in which an image is displayed and a non-display area NDA in which an image is not displayed as shown in Figure 2

[0044] The display area DAA can include a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0045] The pixels PX can be arranged in a matrix form in the first direction DR1 and the second direction DR2. The scan lines SL and the emission control lines EL can extend in the first direction DR1 and be arranged in the second direction DR2. The data lines DL can extend in the second direction DR2 and be arranged in the first direction DR1.

[0046] The scan lines SL can include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The emission control lines EL can include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2. ​

[0047] The pixel PX includes a plurality of sub-pixels SP1, SP2, and SP3. The sub-pixels SP1, SP2, and SP3 can include a plurality of pixel transistors as shown in Figure 3 FIG. 6, and the pixel transistors can be formed by a semiconductor process and disposed on a semiconductor substrate S SUB (see FIG. 6). For example, the pixel transistors of the data driver 700 can be formed of complementary metal-oxide-semiconductor (CMOS). Figure 7

[0048] Each of the sub-pixels SP1, SP2, and SP3 can be connected to one of the write scan lines GWL, one of the control scan lines GCL, one of the bias scan lines GBL, one of the first emission control lines EL1, one of the second emission control lines EL2, and one of the data lines DL. Each of the sub-pixels SP1, SP2, and SP3 can receive a data voltage from the data line DL in response to a write scan signal from the write scan line GWL, and emit light from the light emitting element according to the data voltage.

[0049] The non-display area NDA can include the scan driver 610, the emission driver 620, and the data driver 700.

[0050] The scan driver 610 can include a plurality of scan transistors, and the emission driver 620 can include a plurality of light emitting transistors. The scan transistors and the light emitting transistors can be formed on a semiconductor substrate S SUB (see FIG. 6) by a semiconductor process. For example, the scan transistors and the light emitting transistors can be formed of CMOS. Although the scan driver 610 is shown to be disposed at the left side of the display area DAA and the emission driver 620 is shown to be disposed at the right side of the display area DAA in Figure 7 Figure 2 FIG. 6, the disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 can be disposed at both the left and right sides of the display area DAA.

[0051] ​​The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing controller 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS from the timing controller 400, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line GBL.

[0052] The transmit driver 620 may include a first transmit control driver 621 and a second transmit control driver 622. Each of the first transmit control driver 621 and the second transmit control driver 622 may receive a transmit timing control signal ECS from the timing controller 400. The first transmit control driver 621 may generate a first transmit control signal according to the transmit timing control signal ECS and sequentially output the first transmit control signal to a first transmit control line EL1. The second transmit control driver 622 may generate a second transmit control signal according to the transmit timing control signal ECS and sequentially output the second transmit control signal to a second transmit control line EL2.

[0053] The data driver 700 may include multiple data transistors, and the data transistors may be formed on a semiconductor substrate SSUB using semiconductor processes (see [link to SSUB]). Figure 7 For example, data transistors can be formed using CMOS.

[0054] The data driver 700 can receive digital video data DATA and data timing control signal DCS from the timing controller 400. The data driver 700 can convert the digital video data DATA into analog data voltage according to the data timing control signal DCS and output the analog data voltage to the data line DL. Sub-pixels SP1, SP2, and SP3 can be selected by the write scan signal of the scan driver 610, and the data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0055] The heat dissipation layer 200 can be stacked with the display panel 100 in a third direction DR3, which is a thickness direction of the display panel 100. The heat dissipation layer 200 can be disposed on a surface of the display panel 100, for example, on a rear surface of the display panel 100. The heat dissipation layer 200 can dissipate heat generated from the display panel 100. The heat dissipation layer 200 can include a graphite layer or a metal layer such as silver (Ag), copper (Cu), or aluminum (Al) having a high thermal conductivity.

[0056] The circuit board 300 can be electrically connected to a plurality of first pads PD1 (see Figure 4 ) of a first pad ("pad", also referred to as "land" or "bond pad") portion PDA1 (see Figure 4 ) of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 300 can be a flexible printed circuit board or a flexible film including a flexible material. Although the circuit board 300 is shown as being unfolded in Figure 1 , the circuit board 300 can be bendable. One end of the circuit board 300 can be disposed on a rear surface of the display panel 100 and / or a rear surface of the heat dissipation layer 200. The one end of the circuit board 300 can be an opposite end of the first pads PD1 (see Figure 4 ) of the first pad portion PDA1 (see Figure 4 ) of the display panel 100 connected to the circuit board 300 by using the conductive adhesive member.

[0057] The timing controller 400 can receive digital video data DATA and a timing signal input from the outside. The timing controller 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signal. The timing controller 400 can output the scan timing control signal SCS to the scan driver 610 and the emission timing control signal ECS to the emission driver 620. The timing controller 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0058] The power supply circuit 500 can generate a plurality of panel driving voltages according to a power voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT and supply them to the display panel 100. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be described below in connection with Figure 3 .

[0059] Each of the timing controller 400 and the power supply circuit 500 can be formed as an integrated circuit (IC) and attached to a surface of the circuit board 300. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing controller 400 can be supplied to the display panel 100 through the circuit board 300. Also, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0060] In another embodiment, each of the timing controller 400 and the power supply circuit 500 can be disposed in the non-display area NDA of the display panel 100, similar to the scan driver 610, the emission driver 620, and the data driver 700. The timing controller 400 can include a plurality of timing transistors, and each of the power supply circuits 500 can include a plurality of power transistors. The timing transistors and the power transistors can be formed on a semiconductor substrate SSUB (see Figure 7 ) by a semiconductor process. For example, the timing transistors and the power transistors can be formed by CMOS. Each of the timing controller 400 and the power supply circuit 500 can be disposed between the data driver 700 and the first pad portion PDA1 (see Figure 4 ).

[0061] Figure 3 is a schematic view of an equivalent circuit of a first sub-pixel according to an embodiment.

[0062] Referring to Figure 3 , the first sub-pixel SP1 can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. Also, the first sub-pixel SP1 can be connected to the first driving voltage line VSL to which the first driving voltage VSS corresponding to a low potential voltage is applied, the second driving voltage line VDL to which the second driving voltage VDD corresponding to a high potential voltage is applied, and the third driving voltage line VIL to which the third driving voltage VINT corresponding to an initialization voltage is applied. For example, the first driving voltage line VSL can be a low potential voltage line, the second driving voltage line VDL can be a high potential voltage line, and the third driving voltage line VIL can be an initialization voltage line. The first driving voltage VSS can be lower than the third driving voltage VINT. The second driving voltage VDD can be higher than the third driving voltage VINT.

[0063] The first sub-pixel SP1 can include a plurality of transistors T1 to T6, a light emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0064] The light emitting element LE can emit light in response to a driving current flowing through a channel of the first transistor T1. An emission amount of the light emitting element LE can be proportional to the driving current. The light emitting element LE can be disposed between the fourth transistor T4 and the first driving voltage line VSL. A first electrode of the light emitting element LE can be connected to a drain electrode of the fourth transistor T4, and a second electrode of the light emitting element LE can be connected to the first driving voltage line VSL. The first electrode of the light emitting element LE can be an anode electrode, and the second electrode of the light emitting element LE can be a cathode electrode. The light emitting element LE can be an organic light emitting diode including the first electrode, the second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but the disclosure is not limited thereto. For example, the light emitting element LE can be an inorganic light emitting element including the first electrode, the second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, and the light emitting element LE can be a micro light emitting diode.

[0065] The first transistor T1 can be a driving transistor that controls a source-drain current (hereinafter also referred to as "driving current") flowing between a source electrode and a drain electrode of the first transistor T1 according to a voltage applied to a gate electrode of the first transistor T1. The first transistor T1 can include the gate electrode connected to the first node N1, the source electrode connected to the drain electrode of the sixth transistor T6, and the drain electrode connected to the second node N2.

[0066] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 can be turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor CP1 to the data line DL. Accordingly, a data voltage of the data line DL can be applied to one electrode of the first capacitor CP1. The second transistor T2 can include the gate electrode connected to the write scan line GWL, the source electrode connected to the data line DL, and the drain electrode connected to one electrode of the first capacitor CP1.

[0067] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 can be turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. In the case where the gate electrode and the drain electrode of the first transistor T1 are connected, the first transistor T1 can operate like a diode. The third transistor T3 can include the gate electrode connected to the control scan line GCL, the source electrode connected to the second node N2, and the drain electrode connected to the first node N1.

[0068] The fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 can be turned on by a first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Accordingly, a driving current of the first transistor T1 can be supplied to the light emitting element LE. The fourth transistor T4 can include a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0069] The fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 can be turned on by a bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Accordingly, a third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light emitting element LE. The fifth transistor T5 can include a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0070] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 can be turned on by a second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Accordingly, a second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 can include a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0071] The first capacitor CP1 can be formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 can include one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0072] The second capacitor CP2 can be formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 can include one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0073] The first node N1 can be a junction between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and one electrode of the second capacitor CP2. The second node N2 can be a junction between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 can be a junction between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0074] Each of the first transistor T1 to the sixth transistor T6 can be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 can be a P-type MOSFET, but the disclosure is not limited thereto. In another embodiment, each of the first transistor T1 to the sixth transistor T6 can be an N-type MOSFET. In another embodiment, some of the first transistor T1 to the sixth transistor T6 can be a P-type MOSFET, and each of the remaining transistors can be an N-type MOSFET.

[0075] Although the first sub-pixel SP1 is shown to include six transistors T1 to T6 and two capacitors CP1 and CP2 in Figure 3 , it should be noted that the first sub-pixel SP1 is not limited to the embodiment shown in Figure 3 . For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to the embodiment shown in Figure 3 .

[0076] In addition, the circuit diagram of the second sub-pixel SP2 and the circuit diagram of the third sub-pixel SP3 can be substantially the same as the circuit diagram of the first sub-pixel SP1 described in conjunction with Figure 3 . Therefore, the description of the circuit diagram of the second sub-pixel SP2 and the circuit diagram of the third sub-pixel SP3 is not repeated in the disclosure.

[0077] Figure 4 is a schematic diagram showing a layout of a display panel according to one embodiment.

[0078] Referring to Figure 4 , the display area DAA of the display panel 100 according to one embodiment can include pixels PX arranged in a matrix form. The non-display area NDA of the display panel 100 according to one embodiment can include a scan driver 610, a emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0079] The scan driver 610 can be disposed at a first side of the display area DAA, and the emission driver 620 can be disposed at a second side of the display area DAA. For example, the scan driver 610 can be disposed at one side of the display area DAA in the first direction DR1, and the emission driver 620 can be disposed at the other side of the display area DAA in the first direction DR1. For example, the scan driver 610 can be disposed at a left side of the display area DAA, and the emission driver 620 can be disposed at a right side of the display area DAA. However, the disclosure is not limited thereto, and the scan driver 610 and the emission driver 620 can be disposed at both the first side and the second side of the display area DAA.

[0080] The first pad portion PDA1 can include the first pads PD1 connected to the pads or bumps of the circuit board 300 through the conductive adhesive members. The first pad portion PDA1 can be disposed at a third side of the display area DAA. For example, the first pad portion PDA1 can be disposed at one side of the display area DAA in the second direction DR2.

[0081] The first pad portion PDA1 can be disposed outside the data driver 700 in the second direction DR2. For example, the first pad portion PDA1 can be disposed closer to an edge of the display panel 100 than the data driver 700.

[0082] The second pad portion PDA2 can include a plurality of second pads PD2 corresponding to inspection pads for testing whether the display panel 100 operates normally. The second pads PD2 can be connected to a jig or a probe pin during an inspection process, or can be connected to a circuit board for inspection. The circuit board for inspection can be a rigid printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0083] The first distribution circuit 710 can distribute data voltages applied through the first pad portion PDA1 to the data lines DL. For example, the first distribution circuit 710 can distribute data voltages applied through the first pads PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or more) data lines DL, as a result, the number of the first pads PD1 can be reduced. The first distribution circuit 710 can be disposed at a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed at one side of the display area DAA in the second direction DR2. For example, the first distribution circuit 710 can be disposed at a lower side of the display area DAA.

[0084] The second distribution circuit 720 can distribute a signal applied through the second pad portion PDA2 to the scan driver 610, the emission driver 620, and the data line DL. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 can be disposed at a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed at another side of the display area DAA in the second direction DR2. For example, the second distribution circuit 720 can be disposed at an upper side of the display area DAA.

[0085] Figure 5 and Figure 6 is a schematic diagram illustrating a layout of a display area according to an embodiment. Figure 4

[0086] Referring to Figure 5 and Figure 6 , each of the pixels PX can include a first emission area EA1 that is an emission area of the first sub-pixel SP1, a second emission area EA2 that is an emission area of the second sub-pixel SP2, and a third emission area EA3 that is an emission area of the third sub-pixel SP3.

[0087] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 can have a polygonal shape, a circular shape, an elliptical shape, or a non-typical shape in a plan view.

[0088] A maximum length of the third emission area EA3 in the first direction DR1 can be less than a maximum length of the first emission area EA1 in the first direction DR1 and a maximum length of the second emission area EA2 in the first direction DR1. The maximum length of the first emission area EA1 in the first direction DR1 and the maximum length of the second emission area EA2 in the first direction DR1 can be substantially the same.

[0089] A maximum length of the third emission area EA3 in the second direction DR2 can be greater than a maximum length of the first emission area EA1 in the second direction DR2 and a maximum length of the second emission area EA2 in the second direction DR2. The maximum length of the first emission area EA1 in the second direction DR2 can be greater than the maximum length of the second emission area EA2 in the second direction DR2.

[0090] The first emission area EA1, the second emission area EA2, and the third emission area EA3 can have shapes as illustrated in Figure 5 and Figure 6 ​The hexagonal shape formed by the six straight lines as shown in FIG. 1A, but the disclosure is not limited thereto. The first emission area EA1, the second emission area EA2, and the third emission area EA3 can have a polygonal shape other than a hexagonal shape, a circular shape, an elliptical shape, or a non-typical shape in a plan view.

[0091] As shown in FIG. 1A, the first emission area EA1 and the second emission area EA2 can be adjacent to each other in the second direction DR2 in each of the pixels PX. In an embodiment, the first emission area EA1 and the third emission area EA3 can be adjacent to each other in the first direction DR1. In an embodiment, the second emission area EA2 and the third emission area EA3 can be adjacent to each other in the first direction DR1. The area of the first emission area EA1, the area of the second emission area EA2, and the area of the third emission area EA3 in a plan view can be different from each other. Figure 5 In another embodiment, as shown in FIG. 1B, the first emission area EA1 and the second emission area EA2 can be adjacent to each other in the first direction DR1, but the second emission area EA2 and the third emission area EA3 can be adjacent to each other in the first diagonal direction DD1, and the first emission area EA1 and the third emission area EA3 can be adjacent to each other in the second diagonal direction DD2. The first diagonal direction DD1 can be a direction between the first direction DR1 and the second direction DR2, and can be inclined by 45 degrees with respect to the first direction DR1 and the second direction DR2, and the second diagonal direction DD2 can be a direction perpendicular to the first diagonal direction DD1.

[0092] Figure 6 The first emission area EA1 can emit first light, the second emission area EA2 can emit second light, and the third emission area EA3 can emit third light. In an embodiment, the first light can be light of a blue wavelength band, the second light can be light of a green wavelength band, and the third light can be light of a red wavelength band. For example, the blue wavelength band can be a wavelength band of light having a dominant peak wavelength in the range of about 370 nm to about 460 nm, the green wavelength band can be a wavelength band of light having a dominant peak wavelength in the range of about 480 nm to about 560 nm, and the red wavelength band can be a wavelength band of light having a dominant peak wavelength in the range of about 600 nm to about 750 nm.

[0093] Each of the pixels PX includes three emission areas EA1, EA2, and EA3 as shown in

[0094] Each of the pixels PX includes three emission areas EA1, EA2, and EA3 as shown in Figure 5 Figure 6 Each of the pixels PX includes three emission areas EA1, EA2, and EA3 as shown in

[0095] The layout of the emission areas of the pixels PX is not limited to Figure 5 and​​Figure 6 The embodiment shown. For example, the emission region of pixel PX can be configured as a stripe structure with the emission region arranged in the first direction DR1, or a PenTile with the emission region arranged in a diamond shape. ® Structure, or emission region with a hexagonal shape in a plan view, such as Figure 6 The hexagonal structure is arranged as shown in the diagram.

[0096] Figure 7 It shows along Figure 5 A schematic cross-sectional view of an embodiment of the display panel, taken by line I1-I1'.

[0097] Reference Figure 7 The display panel 100 may include a semiconductor backplane (SBP), a light-emitting element backplane (EBP), a display element layer (EML), a packaging layer (TFE), an optical layer (OPL), a cover layer (CVL), and a polarizing plate (POL).

[0098] A semiconductor backplane (SBP) may include a semiconductor substrate (SSUB) containing multiple pixel transistors (PTRs), multiple semiconductor insulating films covering the pixel transistors (PTRs), and multiple contact terminals (CTEs) electrically connected to the pixel transistors (PTRs). The pixel transistors (PTRs) may be referenced... Figure 4 The first transistor T1 to the sixth transistor T6 are described.

[0099] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. Multiple well regions WA can be disposed on the top surface of the semiconductor substrate SSUB. The well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. For example, if the first type of impurity is a p-type impurity, the second type of impurity can be an n-type impurity. For example, if the first type of impurity is an n-type impurity, the second type of impurity can be a p-type impurity.

[0100] Each of the well regions WA may include a source region SA corresponding to the source electrode of the pixel transistor PTR, a drain region DA corresponding to the drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0101] The lower insulating film BIN can be disposed between the gate electrode GE and the well region WA. The side insulating film SINS can be disposed on the side surface of the gate electrode GE. The side insulating film SINS can be disposed on the lower insulating film BINS.

[0102] Each of the source regions SA and the drain regions DA can be a region doped with a first type impurity. The gate electrode GE of the pixel transistor PTR can overlap the well region WA in the third direction DR3. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be provided on one side of the gate electrode GE, and the drain region DA can be provided on the other side of the gate electrode GE.

[0103] Each of the well regions WA can further include a first low-concentration impurity region LDD1 provided between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 provided between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 can be a region having a lower impurity concentration than the source region SA due to the lower insulating film BINS. The second low-concentration impurity region LDD2 can be a region having a lower impurity concentration than the drain region DA due to the lower insulating film BINS. A distance between the source region SA and the drain region DA can be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, a length of the channel region CH of each of the pixel transistors PTR can be increased, so that punch-through and hot carrier phenomena that can be caused by a short channel can be reduced or prevented.

[0104] The first semiconductor insulating film SINS1 can be provided on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 can be formed of a silicon carbon nitride (SiCN) or a silicon oxide (SiO x ) type inorganic film, but the disclosure is not limited thereto.

[0105] The second semiconductor insulating film SINS2 can be provided on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 can be formed of a silicon oxide (SiO x ) type inorganic film, but the disclosure is not limited thereto.

[0106] The contact terminal CTE can be provided on the second semiconductor insulating film SINS2. Each of the contact terminals CTE can be connected to one of the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors PTR through a hole penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The contact terminal CTE can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0107] The third semiconductor insulating film SINS3 can be provided on a side surface of each of the contact terminals CTE. A top surface of each of the contact terminals CTE can be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 can be formed of a silicon oxide (SiO x( ) Formation of inorganic membranes, but the disclosure is not limited to this.

[0108] The semiconductor substrate SSUB can be replaced by a glass substrate or a polymer resin substrate including polyimide, and the thin-film transistor can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that does not bend, and the polymer resin substrate can be a flexible substrate that can be bent or folded.

[0109] The backplane (EBP) of the light-emitting element may include multiple conductive layers ML1 to ML8, multiple vias VA1 to VA9, and multiple insulating films INS1 to INS9. In an embodiment, the backplane (EBP) of the light-emitting element may further include second insulating films INS2 to INS8 disposed between the first conductive layers ML1 to the eighth conductive layers ML8.

[0110] The first conductive layer ML1 to the eighth conductive layer ML8 can be connected to the contact terminals CTE exposed from the semiconductor backplane SBP, thereby achieving Figure 3 The circuitry for the first sub-pixel SP1 is shown. For example, first transistors T1 to sixth transistors T6 can be formed in the semiconductor backplane SBP, and the connection between first transistors T1 to sixth transistors T6 and first capacitor CP1 and second capacitor CP2 can be achieved through first conductive layers ML1 to eighth conductive layers ML8. In an embodiment, the connection between the drain region corresponding to the drain electrode of fourth transistor T4, the source region corresponding to the source electrode of fifth transistor T5, and the first electrode of the light-emitting element LE can also be achieved through first conductive layers ML1 to eighth conductive layers ML8.

[0111] A first insulating film INS1 may be disposed on a semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first insulating film INS1 and connect to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first conductive layers ML1 may be disposed on the first insulating film INS1 and may connect to the first via VA1.

[0112] A second insulating film INS2 can be disposed on the first insulating film INS1 and the first conductive layer ML1. Each of the second vias VA2 can penetrate the second insulating film INS2 and connect to the exposed first conductive layer ML1. Each of the second conductive layers ML2 can be disposed on the second insulating film INS2 and can connect to the second via VA2.

[0113] A third insulating film INS3 can be disposed on the second insulating film INS2 and the second conductive layer ML2. Each of the third vias VA3 can penetrate the third insulating film INS3 and connect to the exposed second conductive layer ML2. Each of the third conductive layers ML3 can be disposed on the third insulating film INS3 and can be connected to the third via VA3.

[0114] A fourth insulating film INS4 can be provided over the third insulating film INS3 and the third conductive layer ML3. Each of fourth vias VA4 can penetrate the fourth insulating film INS4 and be connected to the exposed third conductive layer ML3. Each of fourth conductive layers ML4 can be provided over the fourth insulating film INS4 and can be connected to the fourth via VA4.

[0115] A fifth insulating film INS5 can be provided over the fourth insulating film INS4 and the fourth conductive layer ML4. Each of fifth vias VA5 can penetrate the fifth insulating film INS5 and be connected to the exposed fourth conductive layer ML4. Each of fifth conductive layers ML5 can be provided over the fifth insulating film INS5 and can be connected to the fifth via VA5.

[0116] A sixth insulating film INS6 can be provided over the fifth insulating film INS5 and the fifth conductive layer ML5. Each of sixth vias VA6 can penetrate the sixth insulating film INS6 and be connected to the exposed fifth conductive layer ML5. Each of sixth conductive layers ML6 can be provided over the sixth insulating film INS6 and can be connected to the sixth via VA6.

[0117] A seventh insulating film INS7 can be provided over the sixth insulating film INS6 and the sixth conductive layer ML6. Each of seventh vias VA7 can penetrate the seventh insulating film INS7 and be connected to the exposed sixth conductive layer ML6. Each of seventh conductive layers ML7 can be provided over the seventh insulating film INS7 and can be connected to the seventh via VA7.

[0118] An eighth insulating film INS8 can be provided over the seventh insulating film INS7 and the seventh conductive layer ML7. Each of eighth vias VA8 can penetrate the eighth insulating film INS8 and be connected to the exposed seventh conductive layer ML7. Each of eighth conductive layers ML8 can be provided over the eighth insulating film INS8 and can be connected to the eighth via VA8.

[0119] The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 can be formed of substantially the same material. The first to eighth conductive layers ML1 to ML8 and the first to eighth vias VA1 to VA8 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The first to eighth vias VA1 to VA8 can be made of substantially the same material. The first to eighth insulating films INS1 to INS8 can be formed of a silicon oxide (SiO x ) type inorganic film, but the disclosure is not limited thereto.

[0120] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 in the third direction DR3 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 in the third direction DR3, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately 1360 A. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately 1440 A. The thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6 can be approximately 1150 A.

[0121] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of each of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of each of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately 9000 A. The thickness of each of the seventh via VA7 and the eighth via VA8 can be approximately 6000 A.

[0122] The ninth insulating film INS9 can be provided on the eighth insulating film INS8 and the eighth conductive layer ML8. The ninth insulating film INS9 can be formed of a silicon oxide (SiO x ) type inorganic film, but the disclosure is not limited thereto.

[0123] Each of the ninth vias VA9 can penetrate the ninth insulating film INS9 and be connected to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The thickness of the ninth via VA9 can be approximately 16500A.

[0124] The display element layer EML can be provided on the light emitting element back plate EBP. The display element layer EML can include light emitting elements LE each including a reflective electrode layer RL, a tenth insulating film INS10 and an eleventh insulating film INS11, a tenth via VA10, a first electrode AND, a light emitting stack IL, and a second electrode CAT, and a pixel definition film PDL.

[0125] The reflective electrode layer RL can be provided on the ninth insulating film INS9. The reflective electrode layer RL can include at least one of a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and / or a fourth reflective electrode RL4. For example, the reflective electrode layer RL can include the first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4 as shown in FIG. 1B. Figure 7

[0126] Each of the first reflective electrode RL1 can be provided on the ninth insulating film INS9 and can be connected to the ninth via VA9. The first reflective electrode RL1 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), an alloy thereof, or a compound thereof. For example, the first reflective electrode RL1 can include titanium nitride (TiN).

[0127] Each of the second reflective electrode RL2 can be provided on the first reflective electrode RL1. The second reflective electrode RL2 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the second reflective electrode RL2 can include aluminum (Al).

[0128] Each of the third reflective electrode RL3 can be provided on the second reflective electrode RL2. The third reflective electrode RL3 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), an alloy thereof, or a compound thereof. For example, the third reflective electrode RL3 can include titanium nitride (TiN).

[0129] ​Each of the fourth reflective electrodes RL4 can be disposed on the third reflective electrodes RL3. The fourth reflective electrodes RL4 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the fourth reflective electrodes RL4 can include titanium (Ti).

[0130] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light emitting element LE, a thickness of the second reflective electrode RL2 in the third direction DR3 can be greater than a thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 in the third direction DR3. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately 100 Å, and the thickness of the second reflective electrode RL2 can be approximately 850 Å.

[0131] The tenth insulating film INS10 can be disposed on the ninth insulating film INS9. The tenth insulating film INS10 can be disposed between the reflective electrode layers RL adjacent to each other in the horizontal direction. The tenth insulating film INS10 can be formed of a silicon oxide (SiO x ) type inorganic film, but the disclosure is not limited thereto.

[0132] The eleventh insulating film INS11 can be disposed on the tenth insulating film INS10 and the reflective electrode layers RL. The eleventh insulating film INS11 can be formed of a silicon oxide (SiO x ) type inorganic film, but the disclosure is not limited thereto. The tenth insulating film INS10 and the eleventh insulating film INS11 can be an optical auxiliary layer through which light reflected by the reflective electrode layers RL among light emitted from the light emitting element LE passes.

[0133] To match a resonance distance of light emitted from the light emitting element LE in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the tenth insulating film INS10 or the eleventh insulating film INS11 can not be disposed under the first electrode AND. For example, the first electrode AND of the first sub-pixel SP1 can be disposed (e.g., directly disposed) on the reflective electrode layers RL. The eleventh insulating film INS11 can be disposed under the first electrode AND of the second sub-pixel SP2. The tenth insulating film INS10 and the eleventh insulating film INS11 can be disposed under the first electrode AND of the third sub-pixel SP3.

[0134] In summary, the distance between the first electrode AND and the reflective electrode layer RL can be different in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, in order to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the principal wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the tenth insulating film INS10 and the eleventh insulating film INS11 can be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. The disclosure is not limited to the above-described embodiments.

[0135] Although the tenth insulating film INS10 and the eleventh insulating film INS11 are shown in the disclosure, a twelfth insulating film that is disposed under the first electrode AND of the first sub-pixel SP1 can be added. The eleventh insulating film INS11 and the twelfth insulating film can be disposed under the first electrode AND of the second sub-pixel SP2, and the tenth insulating film INS10, the eleventh insulating film INS11, and the twelfth insulating film can be disposed under the first electrode AND of the third sub-pixel SP3.

[0136] Each of the tenth vias VA10 can penetrate the tenth insulating film INS10 and / or the eleventh insulating film INS11 in the second sub-pixel SP2 and the third sub-pixel SP3, and can be connected to the fourth reflective electrode RL4. The tenth via VA10 can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof. The thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0137] The first electrode AND of each of the light emitting elements LE can be provided on the tenth insulating film INS10 and connected to the tenth via hole VA10. The first electrode AND of each of the light emitting elements LE can be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via hole VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth via holes VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements LE can be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), an alloy thereof, or a compound thereof. For example, the first electrode AND of each of the light emitting elements LE can be titanium nitride (TiN).

[0138] The pixel defining film PDL can be provided on a portion of the first electrode AND of each of the light emitting elements LE. The pixel defining film PDL can cover an edge of the first electrode AND of each of the light emitting elements LE. The pixel defining film PDL can be used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0139] The first emission area EA1 can be an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 can be an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 can be an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0140] The pixel defining film PDL can include a first pixel defining film PDL1, a second pixel defining film PDL2, and a third pixel defining film PDL3. The first pixel defining film PDL1 can be provided on an edge of the first electrode AND of each of the light emitting elements LE, the second pixel defining film PDL2 can be provided on the first pixel defining film PDL1, and the third pixel defining film PDL3 can be provided on the second pixel defining film PDL2. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can be formed of a silicon oxide (SiO x ) based inorganic film, but the disclosure is not limited thereto. The first pixel defining film PDL1, the second pixel defining film PDL2, and the third pixel defining film PDL3 can each have a thickness of about 500 Å.

[0141] In a case where the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 are formed as one pixel definition film, the height of the one pixel definition film can increase, so that the first encapsulation inorganic film TFE1 can be cut off due to step coverage. Step coverage can be a ratio of a degree to which a thin film is coated on an inclined portion to a degree to which a thin film is coated on a flat portion. The lower the step coverage, the more likely the thin film will be cut off at the inclined portion.

[0142] Therefore, in order to reduce or prevent the possibility that the first encapsulation inorganic film TFE1 is cut off due to step coverage, the first pixel definition film PDL1, the second pixel definition film PDL2, and the third pixel definition film PDL3 can have a cross-sectional structure having a step portion. For example, the width of the first pixel definition film PDL1 can be greater than the width of the second pixel definition film PDL2 and the width of the third pixel definition film PDL3, and the width of the second pixel definition film PDL2 can be greater than the width of the third pixel definition film PDL3. The width of the first pixel definition film PDL1 can be a horizontal length of the first pixel definition film PDL1 defined in the first direction DR1 and the second direction DR2.

[0143] The light emitting stack IL can include a plurality of intermediate layers. The light emitting stack IL can include a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3 that emit different light. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 can be broken between adjacent sub-pixels SP1, SP2, and SP3.

[0144] The first stack layer IL1 can have a structure in which a first hole transport layer, a first organic light emitting layer that emits first light, and a first electron transport layer are sequentially stacked. The first stack layer IL1 can be disposed on the first electrode AND in the pixel definition film PDL and the first emission area EA1 of the first sub-pixel SP1.

[0145] The second stack layer IL2 can have a structure in which a second hole transport layer, a second organic light emitting layer that emits third light, and a second electron transport layer are sequentially stacked. The second stack layer IL2 can be disposed on the first electrode AND in the pixel definition film PDL and the second emission area EA2 of the second sub-pixel SP2.

[0146] The third hole transport layer, the third organic light emitting layer that emits second light, and the third electron transport layer can be sequentially stacked. The third stack layer IL3 can be disposed on the first electrode AND in the pixel definition film PDL and the third emission area EA3 of the third sub-pixel SP3.

[0147] The second electrode CAT can be disposed on the third stack layer IL3 and the pixel definition film PDL. The second electrode CAT can be formed of a transparent conductive material (TCO) such as ITO or IZO, which can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. In the case where the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency can be improved in each of the first, second, and third sub-pixels SP1, SP2, and SP3 by forming a microcavity effect.

[0148] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE can include at least one encapsulation inorganic film TFE1 and / or TFE2 to reduce or prevent penetration of oxygen or moisture into the display element layer EML. For example, the encapsulation layer TFE can include a first encapsulation inorganic film TFE1 and a second encapsulation inorganic film TFE2.

[0149] The first encapsulation inorganic film TFE1 can be disposed on the second electrode CAT. The first encapsulation inorganic film TFE1 can be formed to include one or more inorganic films of at least one of silicon nitride (SiN x ), silicon oxynitride (SiON), and silicon oxide (SiO x ) alternately stacked with each other in multiple layers. The first encapsulation inorganic film TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0150] The second encapsulation inorganic film TFE2 can be disposed on the first encapsulation inorganic film TFE1. The second encapsulation inorganic film TFE2 can be formed of titanium oxide (TiO x ) or aluminum oxide (AlO x ), but the disclosure is not limited thereto. The second encapsulation inorganic film TFE2 can be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic film TFE2 can be less than the thickness of the first encapsulation inorganic film TFE1.

[0151] The organic film APL can be a layer for increasing interfacial adhesion between the encapsulation layer TFE and the cover layer CVL. The organic film APL can be an organic film including an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0152] The cover layer CVL can be disposed on the organic film APL. The cover layer CVL can be a glass substrate or a polymer resin.

[0153] The polarizing plate POL can be disposed on a surface of the cover layer CVL. The polarizing plate POL can be a structure for reducing or preventing visibility degradation caused by reflection of external light. The polarizing plate POL can include a linear polarizing plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter wave plate), but the disclosure is not limited thereto.

[0154] Figure 8 is a perspective view showing a head-mounted display according to one embodiment. Figure 9 is an exploded perspective view showing an embodiment of the head-mounted display of Figure 8 .

[0155] Referring to Figure 8 and Figure 9 , the head-mounted display 1000 according to one embodiment can include a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0156] The first display device 10_1 can provide an image to the left eye of the user, and the second display device 10_2 can provide an image to the right eye of the user. Since each of the first display device 10_1 and the second display device 10_2 is substantially the same as the display device 10 described in connection with Figure 1 and Figure 2 , a description of the first display device 10_1 and the second display device 10_2 will be omitted.

[0157] The first optical member 1510 can be disposed between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 can be disposed between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 can include at least one convex lens.

[0158] The intermediate frame 1400 can be disposed between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The intermediate frame 1400 can support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0159] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display device housing 1100. The control circuit board 1600 can be connected to the first display device 10_1 and the second display device 10_2 through connectors. The control circuit board 1600 can convert an image source input from the outside into digital video data DATA and transmit the digital video data DATA to the first display device 10_1 and the second display device 10_2 through the connectors.

[0160] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the left eye of the user to the first display device 10_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the right eye of the user to the second display device 10_2. In another embodiment, the control circuit board 1600 can transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0161] The display device housing 1100 can accommodate the first display device 10_1, the second display device 10_2, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 can cover the open surface of the display device housing 1100. The housing cover 1200 can include a first eyepiece 1210 that positions the left eye of the user and a second eyepiece 1220 that positions the right eye of the user. Figure 8 and Figure 9 The first eyepiece 1210 and the second eyepiece 1220 are schematically shown to be separately provided, but the disclosure is not limited thereto. In another embodiment, the first eyepiece 1210 and the second eyepiece 1220 can be integrated with each other.

[0162] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical member 1520. Accordingly, the user can view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0163] The head-mounted band 1300 can fix the display device housing 1100 to the head of the user so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively maintained on the left eye and the right eye of the user. In the case where the housing cover 1200 is implemented to be light in weight and small in size, the head-mounted display 1000 can be provided with a spectacle frame instead of the head-mounted band 1300 as shown in FIG. 1B. Figure 10 In the case where the housing cover 1200 is implemented to be light in weight and small in size, the head-mounted display 1000 can be provided with a spectacle frame instead of the head-mounted band 1300 as shown in FIG. 1B.

[0164] In an embodiment, the head-mounted display 1000 can further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port can be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module can be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0165] Figure 10 is a perspective view showing a head-mounted display according to an embodiment.

[0166] Referring to Figure 10 , a head-mounted display 1000_1 according to an embodiment can be a glasses-type display device that implements a display device housing 1200_1 in a light-weight and small-sized manner. The head-mounted display 1000_1 according to an embodiment can include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temple pieces 1040 and 1050, an optical member 1060, an optical path changing member 1070, and the display device housing 1200_1.

[0167] The display device housing 1200_1 can include the display device 10_3, the optical member 1060, and the optical path changing member 1070. An image displayed on the display device 10_3 can be magnified by the optical member 1060 and can be provided to a right eye of a user through the right-eye lens 1020 after an optical path is changed by the optical path changing member 1070. As a result, the user can view an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image seen through the right-eye lens 1020 are combined through the right eye.

[0168] Figure 10 The display device housing 1200_1 is schematically shown as being disposed at a right end of the support frame 1030, but the disclosure is not limited thereto. For example, the display device housing 1200_1 can be disposed at a left end of the support frame 1030, and an image of the display device 10_3 can be provided to a left eye of the user. In another embodiment, the display device housing 1200_1 can be disposed at both the left end and the right end of the support frame 1030, and the user can view an image displayed on the display device 10_3 through both the left eye and the right eye.

[0169] Figure 11 is a perspective view of a mask according to an embodiment. Figure 12 is a schematic plan view of a mask according to an embodiment. Figure 11 is a perspective view showing a state in which one unit mask UM is separated from a plurality of unit masks. Figure 11 and Figure 12 The mask according to an embodiment shown in FIGS. 1A to 1C can be used in a process of depositing at least a portion of a light-emitting stack IL described with reference to Figure 7 For example, the light-emitting stack IL can be configured to emit light of different colors in each of the sub-pixels SP1, SP2, and SP3.

[0170] Referring to Figure 11 and Figure 12The mask MK according to an embodiment can be a shadow mask in which the mask film MM is disposed on the silicon substrate 1700. The mask MK according to an embodiment can be referred to as a "silicon mask".

[0171] According to an embodiment, the mask MK can include the silicon substrate 1700, and the mask film MM can be disposed on the silicon substrate 1700. The mask film MM can be disposed in unit areas 1710 arranged in a matrix form, and each unit area 1710 can be surrounded by a mask lip area 1721. The mask lip area 1721 can have a portion in which the silicon substrate is disposed, and can be used to support the mask film MM.

[0172] The mask film MM can be a portion of a unit mask UM disposed in each of the unit areas 1710.

[0173] The silicon substrate 1700 can include the unit areas 1710 and a mask frame area 1720 that does not include the unit areas 1710. The mask frame area 1720 can include the mask lip area 1721 surrounding each unit area 1710 and an outer frame area 1722 disposed at an outermost edge of the silicon substrate 1700. The mask frame MF can be disposed in the mask frame area 1720, and the mask frame MF can include a mask lip surrounding the unit areas 1710.

[0174] The mask lip area 1721 can be an area that separates the unit areas 1710. For example, the unit areas 1710 can be arranged in a matrix form, and a mask lip disposed in the mask lip area 1721 can surround an outer edge of the mask film MM disposed in each unit area 1710.

[0175] The unit opening COP and the unit mask UM for masking at least a portion of the unit opening COP can be disposed in each of the unit areas 1710 of the silicon substrate 1700.

[0176] The unit opening COP can penetrate the mask frame MF along a thickness direction (e.g., the third direction DR3) of the mask MK. The unit opening COP can be formed by etching a portion of the silicon substrate 1700 from the back.

[0177] Each unit mask UM can include the mask film MM, and the mask film MM can include a mask opening OP.

[0178] The mask opening OP of the mask film MM can be referred to as a "hole" or a "mask hole". The mask opening OP can penetrate the unit mask UM along a thickness direction (e.g., the third direction DR3) of the mask MK.

[0179] The unit mask UM can be used in a deposition process of the display panel 100. In the disclosure, the term "unit mask UM" can be replaced with a term such as mask unit UM.

[0180] Figures 13 to 21 is a schematic cross-sectional view illustrating a method of manufacturing a mask according to an embodiment. For example, Figure 21 may be a schematic cross-sectional view in which a portion of a mask according to an embodiment is cut, and Figures 13 to 21 may be a schematic view sequentially illustrating a process of manufacturing Figure 21 the mask illustrated in

[0181] Hereinafter, a method of manufacturing a mask according to an embodiment will be described with reference to Figures 13 to 15

[0182] Referring to Figure 13 , a substrate 1800 can be provided. The substrate 1800 can include silicon (Si). The substrate 1800 can be referred to as a "bulk substrate" or a "film substrate", but the disclosure is not limited thereto.

[0183] Referring to Figure 14 , a first inorganic film 1910 can be deposited to surround a surface of the substrate 1800. For example, the first inorganic film 1910 can include silicon oxide (SiO x ).

[0184] According to an embodiment, the first inorganic film 1910 can include a material other than silicon oxide (SiO x ). For example, the first inorganic film 1910 can include at least one of silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), titanium oxide (TiO x ), amorphous silicon (a-Si), and aluminum oxide (AlO x ).

[0185] Referring to Figure 15 , an alignment key 2010 can be formed on the first inorganic film 1910. For example, the alignment key 2010 can be patterned to be aligned in a portion of the mask frame region 1720 (see Figure 12 ). The alignment key 2010 can include tungsten (W), but the disclosure is not limited thereto.

[0186] Referring to Figure 16 , a second inorganic film 1920 can be deposited on the first inorganic film 1910 on which the alignment key 2010 is formed. The second inorganic film 1920 can include silicon nitride (SiN x ).

[0187] According to an embodiment, the second inorganic film 1920 can include a material other than silicon nitride (SiN​x Materials other than silicon (Si), silicon oxynitride (SiON), and silicon oxide (SiO2) may be used. x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of the following.

[0188] Despite Figures 13 to 23 The diagram illustrates the deposition of a first inorganic film 1910 and a second inorganic film 1920 on a substrate 1800, but the disclosure is not limited thereto. For example, the inorganic films may be deposited as a single layer on the substrate 1800, and the inorganic films may include silicon (Si), silicon nitride (SiN), etc. x ), silicon oxynitride (SiON), silicon oxide (SiO) x Titanium oxide (TiO) x ), amorphous silicon (a-Si) and aluminum oxide (AlO) x At least one of the following. However, in the following description, an embodiment in which a first inorganic film 1910 and a second inorganic film 1920 are deposited on a substrate 1800 will be described.

[0189] Reference Figure 17 A photoresist pattern 2110 can be formed on a portion of the front surface of the substrate 1800 where the second inorganic film 1920 is disposed, and the photoresist pattern 2110 can be used as a mask to etch the second inorganic film 1920. Thus, a plurality of openings penetrating the second inorganic film 1920 are formed.

[0190] Reference Figure 18 The photoresist pattern 2110 can be removed. Therefore, the inorganic film pattern from which a portion of the second inorganic film 1920 has been removed can remain on the front surface of the substrate 1800. The inorganic film pattern can be formed from the second inorganic film 1920 and becomes a mask film MM by including openings (see...). Figure 12 ).

[0191] Reference Figures 19 to 21 The second inorganic film 1920, the substrate 1800, and the first inorganic film 1910 can be etched from the rear surface of the substrate 1800 in a downward direction to expose the mask film MM, which includes a plurality of first openings and on which the second inorganic film 1920 is formed.

[0192] like Figure 19As shown in FIG. 19, the step of exposing the mask film MM can include a step of forming a first unit opening OP11 exposing a surface of the first inorganic film 1910 disposed on the rear surface of the substrate 1800 by etching the second inorganic film 1920 disposed on the rear surface of the substrate 1800. A first alignment opening OP12 aligned with the alignment key 2010 can also be formed. However, the process of forming the first alignment opening OP12 can not be an essential process. The process of forming the first alignment opening OP12 can be selectively performed or not performed depending on the wavelength of light used to identify the alignment key 2010.

[0193] As shown in FIG. 20, the step of exposing the mask film MM can include a step of forming a second unit opening OP21 exposing the rear surface of the substrate 1800 by etching the first inorganic film 1910 disposed on the rear surface of the substrate 1800 in the first unit opening OP11. A second alignment opening OP22 aligned with the alignment key 2010 can also be formed. However, the process of forming the second alignment opening OP22 can not be an essential process. The process of forming the second alignment opening OP22 can be selectively performed or not performed depending on the wavelength of light used to identify the alignment key 2010. Figure 20 As shown in FIG. 21, the step of exposing the mask film MM can include a step of forming a third unit opening OP31 exposing the second inorganic film 1920 (e.g., the mask film MM) disposed on the front surface of the substrate 1800. A third alignment opening OP32 aligned with the alignment key 2010 can also be formed. However, the process of forming the third alignment opening OP32 can not be an essential process. The process of forming the third alignment opening OP32 can be selectively performed or not performed depending on the wavelength of light used to identify the alignment key 2010.

[0194] Figure 21 As shown in FIG. 22, the step of exposing the mask film MM can include a step of forming a fourth unit opening OP41 exposing the second inorganic film 1920 (e.g., the mask film MM) disposed on the front surface of the substrate 1800. A fourth alignment opening OP42 aligned with the alignment key 2010 can also be formed. However, the process of forming the fourth alignment opening OP42 can not be an essential process. The process of forming the fourth alignment opening OP42 can be selectively performed or not performed depending on the wavelength of light used to identify the alignment key 2010.

[0195] Figure 21 The third unit opening OP31 shown in FIG. 19 can be a unit opening COP described with reference to FIG. 18. Figure 11 The unit opening COP described with reference to FIG. 18.

[0196] Figure 22 FIG. 23 is a schematic view schematically showing a deposition apparatus according to an embodiment.

[0197] Referring to FIG. 24, a deposition apparatus according to an embodiment can include a chamber 2310, a deposition source DS disposed inside the chamber 2310, a mask MK disposed inside the chamber 2310 between a first substrate 2320 and the deposition source DS, and a mask support 2340 disposed between the deposition source DS and the mask MK to support at least a portion of the mask MK. Figure 22

[0198] ​​In an embodiment, the deposition apparatus can include a magnetic member 2350 disposed on the first substrate 2320. The magnetic member 2350 can include a plurality of magnets 2351 and 2352 (see Figure 23 ) for fixing the mask support 2340 with a magnetic force. The magnetic member 2350 can be placed on top of a fixing member 2330 that fixes the first substrate 2320. For example, the fixing member 2330 including an electrostatic chuck for fixing the first substrate 2320 can be disposed on the first substrate 2320, and the magnetic member 2350 for fixing the mask support 2340 with a magnetic force can be disposed on top of the fixing member 2330.

[0199] According to an embodiment, the mask MK can include a silicon substrate 1700 (see Figure 12 ) including a plurality of unit areas 1710 (see Figure 12 ), and a mask frame area 1720 (see Figure 12 ) not including the unit areas 1710, and a mask film MM is disposed in each of the unit areas 1710.

[0200] Figure 22 The first substrate 2320 shown in FIG. 22 can be the display panel 100 described with reference to Figures 1 to 7 . Accordingly, the description of the first substrate 2320 can be replaced with the description of the display panel 100 with reference to Figures 1 to 7 .

[0201] Figure 22 The mask MK shown in FIG. 23 can be a second substrate, and can include the silicon substrate 1700 or the substrate 1800 described with reference to Figures 13 to 22 . The description of the second substrate can be replaced with the description of the silicon substrate 1700 or the substrate 1800 with reference to Figures 13 to 22 .

[0202] The mask support 2340 can be used to support and fix the mask MK, and can be disposed under the mask MK. Since such a mask support 2340 includes a ferromagnetic substance, the mask support 2340 can fix and support the lower portion of the mask MK with a magnetic force of the magnetic member 2350. The mask support 2340 can include at least one of iron, cobalt, nickel, and an alloy thereof as the ferromagnetic substance. According to an embodiment, the ferromagnetic substance can include an Invar alloy, for example, a nickel-iron alloy, having a very small coefficient of thermal expansion.

[0203] According to one embodiment, a method of manufacturing the display device 10 can include the following steps. For example, the method of manufacturing the display device 10 can include a step of disposing the first substrate 2320 on a surface of the mask MK inside the chamber 2310 of the deposition apparatus, a step of disposing the deposition source DS to face the surface of the first substrate 2320, and a step of evaporating a deposition material included in the deposition source DS and passing the evaporated deposition material through the mask MK to be deposited on the first substrate 2320.

[0204] Figure 23 is an exploded perspective view illustrating a deposition apparatus according to one embodiment. Figure 24 is a schematic view of a magnetic member and a mask support according to one embodiment.

[0205] Referring to Figure 23 and Figure 24 , the first substrate 2320, which is a deposition substrate, can be disposed on top (e.g., the third direction DR3) of the mask MK, and the magnetic member 2350, which provides a magnetic force to the mask support 2340, can be disposed on top of the first substrate 2320. The mask MK can be supported by the mask support 2340 including a ferromagnetic substance.

[0206] According to one embodiment, the magnetic member 2350 can include a plurality of magnets 2351 and 2352 extending in the first direction DR1, and the mask support 2340 can extend in a second direction DR2 perpendicular to the first direction DR1.

[0207] The mask MK can include a silicon substrate 1700 (see Figure 12 ) and a mask film MM (see Figure 12 ), the silicon substrate 1700 including a plurality of unit areas 1710 (see Figure 12 ), an outer frame area 1722 (see Figure 12 ) disposed at an outermost edge of the unit areas 1710, and a mask lip area 1721 disposed at a periphery of the unit areas 1710, the mask film MM being disposed on the silicon substrate 1700 to correspond to the unit areas 1710.

[0208] The unit areas 1710 can be disposed in a matrix form, and the mask support 2340 can include a plurality of first magnetic lifters 2341 disposed to intersect between the unit areas 1710 and a plurality of second magnetic lifters 2342 disposed on both sides of the first magnetic lifters 2341 and supporting the outer frame area 1722 (see Figure 12 ).

[0209] Each of the first magnetic elevators 2341 can extend in the second direction DR2 and can have a first width in the first direction DR1. Each of the second magnetic elevators 2342 can extend in the second direction DR2 and can have a first width in the first direction DR1. For example, the first width of the first magnetic elevators 2341 and the first width of the second magnetic elevators 2342 can be the same.

[0210] The magnetic member 2350 can include a first magnet 2351 having a first polarity (e.g., N-pole) and extending in the first direction DR1 and a second magnet 2352 having a second polarity (e.g., S-pole) and extending in the first direction DR1.

[0211] The first magnet 2351 and the second magnet 2352 can be alternately arranged in the second direction DR2.

[0212] According to one embodiment, in a case where the first magnet 2351 and the second magnet 2352 of the magnetic member 2350 are arranged to extend in the first direction DR1, the mask support 2340 supporting the mask MK and receiving a magnetic force from the magnetic member 2350 can extend in a direction perpendicular to the magnetic member 2350. For example, the first magnetic elevators 2341 and the second magnetic elevators 2342 of the mask support 2340 can extend in the second direction DR2 perpendicular to the first direction DR1 in which the first magnet 2351 and the second magnet 2352 extend.

[0213] According to one embodiment, it is possible to further increase the support force of the mask support 2340 with respect to the mask MK by arranging the direction in which the magnetic member 2350 extends and the direction in which the mask support 2340 extends to be perpendicular to each other. In the disclosure, by reducing the gap between the deposition base (i.e., the first base 2320) and the mask MK, it is possible to reduce sagging of the mask MK and it is possible to reduce a shadow defect or a color mixing defect.

[0214] The disclosure is not limited to the mask support 2340 in the form of a bar (stick, rod) as in the illustrated embodiment. For example, the mask support 2340 can include a frame not including a ferromagnetic substance. The frame of the mask support 2340 can be a circular frame or a square frame and can be designed to be larger than the deposition area of the mask MK. The frame can serve to maintain the first magnetic elevators 2341 and the second magnetic elevators 2342 in a taut state before the first magnetic elevators 2341 and the second magnetic elevators 2342 of the mask support 2340 are magnetized by a magnetic field. Accordingly, the frame can reduce variation by sagging of the mask MK.

[0215] Figure 25 is a schematic view of a magnetic member and a mask support according to another embodiment.

[0216] Unlike embodiments of Figure 24 , embodiments of Figure 25 may differ in that the width of the first magnetic lifters 2341 and the width of the second magnetic lifters 2342 are designed to be different.

[0217] Referring to Figure 25 , each of the first magnetic lifters 2341 can extend in the second direction DR2 and can have a first width in the first direction DR1. Each of the second magnetic lifters 2342 can extend in the second direction DR2 and can have a second width in the first direction DR1 that is smaller than the first width. For example, the first width of the first magnetic lifters 2341 and the second width of the second magnetic lifters 2342 can be different, and the first magnetic lifters 2341 can be designed to have a relatively larger width for the reason of supporting the mask MK.

[0218] The above description is an example of disclosed technical features, and those skilled in the art to which the disclosure pertains will be able to make various modifications and changes. Therefore, the above-described disclosed embodiments can be implemented alone or in combination with each other.

[0219] Therefore, the embodiments disclosed in the disclosure are not intended to limit the technical spirit of the disclosure, but to describe the technical spirit of the disclosure, and the scope of the technical spirit of the disclosure is not limited by these embodiments. The scope of protection of the disclosure should be interpreted by the attached claims, and it should be interpreted that all technical spirits within the equivalent scope are included within the scope of the disclosure.

Claims

1. A deposition apparatus, the deposition apparatus comprising: Sediment source; A mask is disposed between the first substrate and the deposition source; A mask support is disposed between the deposition source and the mask and supports at least a portion of the mask; as well as A magnetic component is disposed on the first substrate and the mask support is fixed by magnetic force, wherein... The magnetic component includes a plurality of magnets extending in a first direction, and The mask support extends in a second direction perpendicular to the first direction.

2. The deposition apparatus according to claim 1, wherein, The mask includes: A silicon substrate includes multiple unit regions, an outer frame region disposed on the outermost edge of the multiple unit regions, and a mask lip region disposed around the periphery of the multiple unit regions; and A mask film is formed on the silicon substrate corresponding to the plurality of unit regions.

3. The deposition apparatus according to claim 2, wherein, The mask film comprises an inorganic film, and The inorganic film includes Si and SiN. x SiON, SiO x TiO x , a-Si and AlO x At least one of them, and Where x is a non-zero natural number.

4. The deposition apparatus according to claim 2, wherein, The multiple unit regions are arranged in a matrix, and The mask support includes: A plurality of first magnetic lifters are configured to intersect between the plurality of unit regions; and Multiple second magnetic lifters are disposed on both sides of the multiple first magnetic lifters and support the outer frame area.

5. The deposition apparatus according to claim 4, wherein, Each of the plurality of first magnetic lifters has a first width in the first direction, and Each of the plurality of second magnetic lifters has the first width in the first direction.

6. The deposition apparatus according to claim 4, wherein, Each of the plurality of first magnetic lifters has a first width in the first direction, and Each of the plurality of second magnetic lifters has a second width in the first direction that is smaller than the first width.

7. The deposition apparatus according to claim 1, wherein, The magnetic component includes: A first magnet, having a first polarity and extending in the first direction; and The second magnet has a second polarity and extends in the first direction.

8. The deposition apparatus according to claim 7, wherein, The first magnet and the second magnet are arranged alternately in the second direction.

9. The deposition apparatus according to claim 1, wherein, The mask support comprises a ferromagnetic material.

10. A method for manufacturing a display device, the method comprising the following steps: The first substrate is placed on the surface of a mask inside the chamber of the deposition apparatus; The deposition source is positioned facing the surface of the first substrate; as well as Evaporation involves depositing material in the deposition source, passing the depositing material through the mask, and depositing the depositing material onto the first substrate, wherein... The deposition apparatus includes: a mask support disposed between the deposition source and the mask and supporting at least a portion of the mask; and a magnetic member disposed on the first substrate and fixing the mask support. The magnetic component includes a plurality of magnets extending in a first direction, and The mask support extends in a second direction perpendicular to the first direction.

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