Display output method and device, chip

Abstract

The display output method comprises the following steps: determining whether a first display interface is enabled; if the first display interface is not enabled at a first time, coupling a phase-locked loop of a first physical layer to a first video port as a pixel clock source of the first video port, the first physical layer corresponding to the first display interface and being used for transmission; and sending first display data from the first video port to a second display interface according to the phase-locked loop of the first physical layer, so that the first display data is output via the second display interface. The display output method can meet the display requirements of multi-screen different display, realize reasonable reuse of limited resources, and improve the display output efficiency.

Description

Technical Field

[0001] This disclosure belongs to the field of image processing technology, and in particular relates to display output methods, devices, and chips. Background Technology

[0002] With the development of multimedia technology, especially in fields such as video surveillance, virtual reality, digital advertising, and professional workstations, the demand for multi-screen independent display (MSI) technology is increasing. MSI allows multiple monitors to display different content simultaneously, greatly expanding the display area and improving work efficiency. MSI technology typically relies on traditional video interfaces such as HDMI, DisplayPort, and VGA. These interfaces are usually designed to transmit signals at fixed frequencies, making it difficult to meet the needs of transmitting arbitrary frequencies. In certain applications, the displayed content may require different frequency or resolution settings, such as in high dynamic range video, professional graphic design, or 3D rendering, requiring each monitor's signal frequency to be flexibly adjusted to adapt to different display needs. However, existing video interfaces, due to their fixed frequency settings, cannot effectively support this flexible, dynamically adjusted frequency transmission, limiting the applicability of MSI technology. Summary of the Invention

[0003] The purpose of this disclosure is to provide a display output method, apparatus, and chip to solve the problems of the prior art, such as the inability to achieve flexible transmission at arbitrary frequencies and low data transmission efficiency.

[0004] In a first aspect, this disclosure provides a display output method. The display output method includes: determining whether a first display interface is enabled; if the first display interface is not enabled at a first moment, coupling a phase-locked loop (PLL) of a first physical layer to a first video port as a pixel clock source for the first video port, the first physical layer corresponding to the first display interface and used for transmission; and having the first video port send first display data to a second display interface according to the PLL of the first physical layer, so as to output the first display data via the second display interface.

[0005] In one implementation of the first aspect, the display output method further includes: if the first display interface is enabled at a second time after the first time, decoupling the phase-locked loop of the first physical layer from the first video port, and coupling the phase-locked loop of the first physical layer to the second video port as a pixel clock source for the second video port; and having the second video port send second display data to the first display interface according to the phase-locked loop of the first physical layer, so as to output the second display data via the first display interface.

[0006] In one implementation of the first aspect, the display output method further includes: determining whether a third display interface is enabled; if the third display interface is not enabled at the second time, coupling a phase-locked loop of a third physical layer to the first video port as a pixel clock source for the first video port, the third physical layer corresponding to the third display interface and used for transmission; and having the first video port send third display data to the second display interface according to the phase-locked loop of the third physical layer, so as to output the third display data via the second display interface.

[0007] In one implementation of the first aspect, the display output method further includes: coupling a system phase-locked loop to the first video port as a pixel clock source for the first video port; and having the first video port send third display data to the second display interface according to the system phase-locked loop, so as to output the third display data via the second display interface.

[0008] In one implementation of the first aspect, the display output method further includes: if the first display interface is enabled at the first moment, coupling the phase-locked loop of the first physical layer to a third video port as a pixel clock source for the third video port; and having the third video port send fourth display data to the first display interface according to the phase-locked loop of the first physical layer, so as to output the fourth display data via the first display interface.

[0009] In one implementation of the first aspect, determining whether the first display interface is enabled includes: determining whether the first display interface receives an enable signal from any video port; coupling the phase-locked loop of the first physical layer to the first video port as a pixel clock source for the first video port includes: configuring the phase-locked loop of the first physical layer as a pixel clock source for the first video port.

[0010] In one implementation of the first aspect, receiving an enable signal from any video port includes: receiving an enable signal from the first video port and obtaining the operating frequency of the first video port transmitted from the first video port, wherein the first video port sends first display data to the second display interface according to the phase-locked loop of the first physical layer includes: packaging the transmitted data to obtain the first display data, and sending the first display data to the corresponding first display interface, wherein configuring the phase-locked loop of the first physical layer as the pixel clock source of the first video port includes: configuring the first video port with the pixel clock source having the same operating frequency.

[0011] In one implementation of the first aspect, configuring the phase-locked loop of the first physical layer as the pixel clock source of the first video port includes: configuring the parameters of the phase-locked loop of the first physical layer to a clock frequency that is the same as the operating frequency of the first video port.

[0012] In one implementation of the first aspect, the display output method further includes: if the corresponding first physical layer is occupied by other video ports when the first display interface is enabled, then disconnecting the occupation of the other video ports and configuring the first physical layer to an idle state.

[0013] In one implementation of the first aspect, the display output method further includes: if the second display interface is not enabled, configuring the phase-locked loop of the second physical layer corresponding to the second display interface as the pixel clock source of any video port.

[0014] In one implementation of the first aspect, the display output method further includes: if the corresponding first physical layer is occupied by another video port when the first display interface is enabled, then disconnect the occupation of the other video port and switch the pixel clock source of the other video port to the phase-locked loop or system phase-locked loop of the other physical layer.

[0015] Secondly, this disclosure provides a display output device. The display output device includes: a control module configured to: determine whether a first display interface is enabled; if the first display interface is not enabled at a first moment, couple a phase-locked loop of a first physical layer to a first video port as a pixel clock source for the first video port, the first physical layer corresponding to the first display interface and used for transmission; and have the first video port send first display data to a second display interface according to the phase-locked loop of the first physical layer, so as to output the first display data via the second display interface.

[0016] In one implementation of the second aspect, the display output device further includes: a plurality of video ports, each configured to transmit display data to a corresponding display interface according to a pixel clock source; a plurality of display interfaces, each configured to receive an enable signal from a corresponding video port among the plurality of video ports, and to transmit display data to the display device; and a plurality of physical layers, each corresponding to the plurality of display interfaces, each including a phase-locked loop and used for transmission, and configured to provide a clock frequency with the same operating frequency as the video port to the corresponding video port among the plurality of video ports through the phase-locked loop as a pixel clock source for the video port.

[0017] In one implementation of the second aspect, the phase-locked loop is configured to generate a clock frequency that is the same as the operating frequency of the video port, and the clock frequency is sent to the video port via the display interface as the pixel clock source of the video port.

[0018] Thirdly, this disclosure provides a chip. The chip includes: a plurality of display interfaces; and a video output processing module, including a controller and a plurality of video ports, the controller being configured to perform the display output method according to any one of the first aspects.

[0019] According to embodiments of this disclosure, when the first display interface is not enabled at a first moment, the phase-locked loop of the first physical layer is coupled to the first video port as the pixel clock source of the first video port. Furthermore, the first video port can also send first display data to the second display interface according to the phase-locked loop of the first physical layer, so that the first display data can be output via the second display interface. This display output method can meet the display requirements of multi-screen displays, achieve reasonable reuse of limited resources, and improve display output efficiency. Attached Figure Description

[0020] Figure 1 This diagram illustrates an application scenario of the display output method described in this disclosure.

[0021] Figure 2 The diagram shown is a flowchart illustrating the display output method described in an embodiment of this disclosure.

[0022] Figure 3 The diagram shown is a schematic representation of the display output method described in an embodiment of this disclosure.

[0023] Figure 4 The diagram shown is a flowchart illustrating the display output method described in an embodiment of this disclosure.

[0024] Figure 5 The diagram shown is a schematic representation of the display output device according to an embodiment of this disclosure.

[0025] Figure 6A The diagram shown is a schematic representation of a display output device according to an embodiment of this disclosure.

[0026] Figure 6B The diagram shown is a schematic representation of a display output device according to an embodiment of this disclosure.

[0027] Figure 6C The diagram shown is a schematic representation of a display output device according to an embodiment of this disclosure.

[0028] Figure 7 The diagram shown is a schematic representation of the chip described in an embodiment of this disclosure. Detailed Implementation

[0029] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0030] It should be noted that, in the embodiments of this disclosure, the word "for example" or similar terms signify an example, illustration, or description. Any embodiment or design described as "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "for example" or similar terms is intended to present the relevant concepts in a concrete manner.

[0031] In this disclosure, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0032] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. Therefore, the drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0033] During chip design, due to cost considerations, each video port's pixel clock is not dedicated to a single phase-locked loop (PLL) as its pixel clock source. Instead, it's shared with other devices under a single PLL. Taking the RK3588 chip as an example, only one V0 PLL is dedicated to the display subsystem as the video port's pixel clock source, allowing for arbitrary frequency division by changing its frequency. Other PLLs (GPLL, CPLL, AUPLL), when used as video port pixel clock sources, share the PLL with other pixel clock sources and cannot have their frequencies changed. This scenario leads to inaccurate pixel clock settings for scan timing requirements, forcing the configuration of only approximate frequencies, potentially causing display anomalies. For example, with the RK3588 chip, if multiple video ports of the display processor work together, only the video port pixel clock source using the V0 PLL can meet arbitrary frequency division requirements; other video port pixel clock sources cannot provide accurate output at any frequency, potentially resulting in display anomalies under certain scan timings.

[0034] At least to address the aforementioned problems, this disclosure provides a display output method. The display output method includes: determining whether a first display interface is enabled; if the first display interface is not enabled at a first moment, coupling a phase-locked loop (PLL) of a first physical layer to a first video port as a pixel clock source for the first video port, the first physical layer corresponding to the first display interface and used for transmission; and having the first video port send first display data to a second display interface according to the PLL of the first physical layer, so as to output the first display data via the second display interface.

[0035] In this embodiment, when the first display interface is not enabled at the first moment, the phase-locked loop of the first physical layer is coupled to the first video port as the pixel clock source of the first video port. Furthermore, the first video port can also send the first display data to the second display interface according to the phase-locked loop of the first physical layer, so that the first display data can be output via the second display interface. This display output method can meet the display requirements of multi-screen displays, achieve reasonable reuse of limited resources, and improve display output efficiency.

[0036] Figure 1 This diagram illustrates an application scenario of the display output method described in this disclosure. The display output system 1 can be used to implement the display output method provided in the embodiments of this disclosure, but the application scenarios of the display output method provided in the embodiments of this disclosure are not limited to this. Figure 1 The display output system 1 is shown. (As shown) Figure 1 As shown, the display output system 1 includes a storage device 11, a display processor 12, and a display device 13. The display output method provided in this embodiment can be applied to the display processor 12.

[0037] In this embodiment, Figure 1 The display processor 12 can be a single display processor, a cluster of multiple display processors, or a cloud computing center, etc., and is not specifically limited here. Although Figure 1 Only one storage device 11, one display processor 12, and one display device 13 are shown, but it should be understood that... Figure 1 The examples in this paper are only for understanding this solution. The actual number of display processors 12 and display devices 13 should be flexibly determined based on the actual situation.

[0038] In some other implementations, the display output system 1 may not include a display device 13, but only a display processor 12 with display functionality and a storage device 11. The display output method provided in this disclosure can be applied to the display processor 12. The display processor 12 may be included in tablet computers, PDAs, mobile phones, personal computers, and voice interaction devices, or it may be a monitoring device, a face recognition device, etc., without limitation here.

[0039] The technical solutions in the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0040] The following embodiments of this disclosure provide a display output method, which can be achieved through... Figure 1 The display processor 12 shown is used to implement this. Figure 2 The diagram shows a flowchart of the display output method described in an embodiment of this disclosure. Figure 2 As shown, the display output method includes the following steps S11 to S13.

[0041] Step S11: Determine whether the first display interface is enabled.

[0042] Step S12: If the first display interface is not enabled at the first moment, the phase-locked loop of the first physical layer is coupled to the first video port as the pixel clock source of the first video port. The first physical layer corresponds to the first display interface and is used for transmission.

[0043] The physical layer (PHY) within the chip supports transmitting (TX) and receiving (RX). It receives data from the protocol layer (IP) module, encodes and converts the received data from serial to parallel transmission, and then transmits it through the physical medium. The phase-locked loop (PLL) of the physical layer serves as the pixel clock source required for data transmission. Compared to other PLLs in the system, the physical layer PLL is generally dedicated to the physical layer and provides the operating frequency needed for data transmission. When the physical layer's data transmission frequency matches the video port's operating frequency, the physical layer PLL can serve as the pixel clock source for the video port. Furthermore, when the physical layer does not need to transmit data, the idle physical layer PLL can be configured to output the operating frequency required by other video ports, thus serving as the pixel clock source for those ports.

[0044] In step S13, the first video port sends the first display data to the second display interface according to the phase-locked loop of the first physical layer, so that the first display data can be output through the second display interface.

[0045] In some possible implementations, in the chip's display subsystem, the display output or video output processor (VOP) reads data from memory (Double Data Rate, DDR), processes it internally, and then transmits it to the display interface through the video port. The display interface encodes the data according to the interface protocol before displaying it.

[0046] Figure 3 The diagram shown is a schematic representation of the display output method described in an embodiment of this disclosure. Figure 3 As shown, a display processor includes multiple video ports, and data from one video port can be selected from multiple display interfaces. Data is transmitted between each video port and a display interface according to a specific scan timing sequence. This sequence includes a row scan timing sequence, a column scan timing sequence, and a pixel clock for that sequence. The row scan timing sequence includes the horizontal trailing edge, effective display area, horizontal leading edge, and horizontal sync pulse. The column scan timing sequence includes the vertical trailing edge, effective display area, vertical leading edge, and vertical sync pulse. Data transmission between each video port and display interface requires a pixel clock. Assuming only one pixel's worth of data is transmitted between the video port and display interface per clock cycle, the configured pixel clock size for data transmission must be consistent with the pixel clock size of the scan timing sequence. For example, to transmit display data at a resolution of 1920×1080 with a pixel clock of 148MHz, a 148MHz pixel clock needs to be configured.

[0047] Specifically, it is determined whether the first display interface is enabled. If the first display interface is not enabled at the first moment, the phase-locked loop (PLL) of the first physical layer is coupled to the first video port as the pixel clock source for the first video port. At this time, the first display interface corresponds to the first physical layer to display data. The first video port sends the first display data to the second display interface according to the PLL of the first physical layer, so that the first display data can be output through the second display interface. The PLL of the first physical layer is the physical layer corresponding to the first display interface, for example, the physical layer DPPHY corresponding to the DP display interface. The phase-locked loop (PLL) is used for synchronization signals and generating stable clock signals.

[0048] In this embodiment, when the first display interface is not enabled at the first moment, the phase-locked loop of the first physical layer is coupled to the first video port as the pixel clock source of the first video port. Furthermore, the first video port can also send the first display data to the second display interface according to the phase-locked loop of the first physical layer, so that the first display data can be output via the second display interface. This display output method can meet the display requirements of multi-screen displays, achieve reasonable reuse of limited resources, and improve display output efficiency.

[0049] Figure 4 The diagram shown is a flowchart illustrating the display output method described in an embodiment of this disclosure. Figure 4 As shown, the display output method may further include the following steps S14 to S15.

[0050] Step S14: If the first display interface is enabled at a second time after the first time, the phase-locked loop of the first physical layer is decoupled from the first video port, and the phase-locked loop of the first physical layer is coupled to the second video port as the pixel clock source of the second video port.

[0051] In step S15, the second video port sends the second display data to the first display interface according to the phase-locked loop of the first physical layer, so as to output the second display data through the first display interface.

[0052] In some possible implementations, the displayed data includes the operating frequency, row scan timing, and column scan timing of the video port. When the first display interface is enabled at a second time after the first time, the phase-locked loop (PLL) of the first physical layer is decoupled from the first video port, the PLL of the first physical layer is configured as the pixel clock source of the second video port, and its operating frequency is kept consistent with that of the second video port. The PLL of the first physical layer is then coupled to the second video port, and the second video port sends the second display data to the first display interface, which then outputs the second display data.

[0053] In one embodiment of this disclosure, the display output method may further include: determining whether a third display interface is enabled; if the third display interface is not enabled at the second time, coupling a phase-locked loop of a third physical layer to the first video port as a pixel clock source for the first video port, the third physical layer corresponding to the third display interface and used for transmission; and having the first video port send third display data to the second display interface according to the phase-locked loop of the third physical layer, so as to output the third display data via the second display interface.

[0054] In some possible implementations, it is determined whether the third display interface is enabled. If it is not enabled at the second moment, the phase-locked loop of the third physical layer is coupled to the first video port as the pixel clock source for the first video port. The third physical layer is coupled to the third display interface for displaying data on the first video port. The first video port displays the third display data via the second display interface based on the pixel clock source provided by the phase-locked loop of the third physical layer.

[0055] In one embodiment of this disclosure, the display output method may further include: coupling a system phase-locked loop to the first video port as a pixel clock source for the first video port; and having the first video port send third display data to the second display interface according to the system phase-locked loop, so as to output the third display data via the second display interface.

[0056] In some possible implementations, after the phase-locked loop (PLL) at the first physical layer is decoupled from the first video port and coupled to the second video port, the first video port can be coupled to the system PLL. The system PLL serves as the pixel clock source for the first video port, and based on the operating frequency provided by the system PLL, the first video port sends the third display data to the second display interface for display.

[0057] In one embodiment of this disclosure, the display output method further includes: if the first display interface is enabled at the first moment, coupling the phase-locked loop of the first physical layer to a third video port as a pixel clock source for the third video port; and having the third video port send fourth display data to the first display interface according to the phase-locked loop of the first physical layer, so as to output the fourth display data via the first display interface.

[0058] In some possible implementations, when the first display interface is enabled at the first moment, the phase-locked loop of the first physical layer is coupled to the third video port to provide a pixel clock source for the third video port. Based on the increased operating frequency of the phase-locked loop of the first physical layer, the third video port sends fourth display data to the first display interface to output the fourth display data.

[0059] In one embodiment of this disclosure, determining whether the first display interface is enabled includes: determining whether the first display interface receives an enable signal from any video port. Furthermore, coupling the phase-locked loop of the first physical layer to the first video port as a pixel clock source for the first video port includes: configuring the phase-locked loop of the first physical layer as a pixel clock source for the first video port.

[0060] In some possible implementations, the activation of the display interface is determined based on whether the display interface receives an enable signal from any video port. Specifically, if the first display interface receives an enable signal from the first video port, it is determined that the first display interface is activated, and the phase-locked loop of the first physical layer is configured as the pixel clock source of the first video port.

[0061] In one embodiment of this disclosure, receiving an enable signal from any video port includes: receiving an enable signal from the first video port and obtaining the operating frequency of the first video port transmitted from the first video port. Furthermore, sending first display data from the first video port to the second display interface according to the phase-locked loop of the first physical layer includes: packetizing the transmitted data to obtain the first display data, and sending the first display data to the corresponding first display interface. Additionally, configuring the phase-locked loop of the first physical layer as the pixel clock source of the first video port includes: configuring the first video port with the pixel clock source having the same operating frequency.

[0062] In some possible implementations, an enable signal from the first video port is received, the operating frequency of the first video port is determined, and the phase-locked loop of the first physical layer is configured as the pixel clock source of the first video port. The first video port packages the transmitted data to obtain first display data, and sends the first display data to the corresponding first display interface according to the phase-locked loop of the first physical layer.

[0063] In one embodiment of this disclosure, configuring the phase-locked loop of the first physical layer as the pixel clock source of the first video port includes: configuring the parameters of the phase-locked loop of the first physical layer to a clock frequency that is the same as the operating frequency of the first video port.

[0064] In some possible implementations, the phase-locked loop (PLL) of any physical layer is a dedicated PLL for that physical layer, providing the specific operating frequency required for the physical layer to transmit data. When the operating frequency of the physical layer's PLL is the same as the operating frequency of the video port, the physical layer's PLL can serve as the pixel clock source for the video port. Furthermore, when the physical layer does not need to transmit data, the parameters of the physical layer's PLL are configured to the operating frequency required by the video port, serving as the pixel clock source for the video port.

[0065] In one embodiment of this disclosure, the display output method may further include: if the corresponding first physical layer is occupied by other video ports when the first display interface is enabled, then disconnect the occupation of the other video ports and configure the first physical layer to an idle state.

[0066] In some possible implementations, if the corresponding first physical layer is occupied by a video port when the first display interface is enabled, it will be disconnected from other video ports, the first physical layer will be released, and the first physical layer will be configured to an idle state, not serving as a pixel clock source for any video port.

[0067] In one embodiment of this disclosure, the display output method may further include: if the second display interface is not enabled, configuring the phase-locked loop of the second physical layer corresponding to the second display interface as the pixel clock source of any video port.

[0068] In some possible implementations, when the second display interface is not enabled, the second physical layer corresponding to the second display interface is in an idle state. The phase-locked loop of the second physical layer corresponding to the second display interface can be configured as the pixel clock source of any video port, and the output frequency of the phase-locked loop of the second physical layer can be adjusted to the operating frequency required by any video port.

[0069] In one embodiment of this disclosure, the display output method may further include: if the corresponding first physical layer is occupied by another video port when the first display interface is enabled, then disconnect the occupation of the other video port and switch the pixel clock source of the other video port to the phase-locked loop or system phase-locked loop of the other physical layer.

[0070] In some possible implementations, when any display interface is enabled, if the physical layer corresponding to that display interface is occupied by another video port, the occupation of the other video port is disconnected, the physical layer corresponding to the display interface is released from coupling with the display interface, and the pixel clock source of the other video port is switched to another physical layer or the system phase-locked loop. This disclosure is not limited thereto.

[0071] Figure 5 The diagram shown is a structural schematic of the display output device described in an embodiment of this disclosure. Figure 5 As shown, the display output device 100 includes a control module 110.

[0072] The control module 110 is configured to: determine whether the first display interface is enabled; if the first display interface is not enabled at a first moment, couple the phase-locked loop of the first physical layer to the first video port as the pixel clock source of the first video port, the first physical layer corresponding to the first display interface and used for transmission; and send the first display data to the second display interface by the first video port according to the phase-locked loop of the first physical layer, so as to output the first display data via the second display interface.

[0073] In this embodiment, the display interface 110 receives an enable signal from the video port and configures the physical layer 120 as the pixel clock source of the video port. If the physical layer 120 is occupied by another video port, the physical layer 120 is switched back to be the pixel clock source of the video port. This display output system 100 can meet the display requirements of multi-screen display, realize the reasonable reuse of limited resources, and improve display output efficiency.

[0074] In one embodiment of this disclosure, please continue to participate. Figure 5 The display output device 100 further includes a plurality of video ports 120, a plurality of display interfaces 130, and a plurality of physical layers 140. The plurality of video ports 120 are each configured to transmit display data to a corresponding display interface 130 according to a pixel clock source. The plurality of display interfaces 130 are each configured to receive an enable signal from a corresponding video port among the plurality of video ports 120, and to transmit display data to the display device. The plurality of physical layers 140 correspond to the plurality of display interfaces 130, each physical layer 140 including a phase-locked loop (PLL) for transmission, and the plurality of physical layers 140 are configured to provide a clock frequency identical to the operating frequency of the corresponding video port among the plurality of video ports 120 via the PLL as a pixel clock source for the video port.

[0075] In one embodiment of this disclosure, the phase-locked loop is configured to generate a clock frequency that is the same as the operating frequency of the video port, and the clock frequency is sent to the video port via the display interface as the pixel clock source of the video port.

[0076] In some possible implementations, the physical layer is the physical layer corresponding to the display interface, for example, the DP PHY physical layer corresponding to the DP display interface. A phase-locked loop (PLL) is used for synchronization signals and generating a stable clock signal. The PLL of the physical layer configures its parameters to a clock frequency identical to the operating frequency of the video port based on the packetized data, serving as the pixel clock source for the video port.

[0077] In some other possible implementations, the chip may include two display interfaces and corresponding physical layers, namely display interfaces HDMI0 and HDMI1. Additionally, a system phase-locked loop (PLL) (VOPLL) is provided to configure the pixel clock source required for data transmission at the video ports.

[0078] Figure 6A The diagram shown illustrates a display output device according to an embodiment of this disclosure. When the HDMI physical layer's corresponding display interface (HDMI) is used, the phase-locked loop (PLL) of the HDMI physical layer is configured as the pixel clock source for the video port connected to the HDMI display interface. The video port output to HDMI0 uses the PLL of the physical layer corresponding to HDMI0 as its pixel clock source, and the video port output to HDMI1 uses the PLL of the physical layer corresponding to HDMI1 as its pixel clock source. For example... Figure 6A As shown, video port 0 transmits data to display interface HDMI0, using the phase-locked loop HDMIPHYPLL0 of the physical layer corresponding to display interface HDMI0 as the pixel clock source. Video port 1 transmits data to display interface HDMI1, using the phase-locked loop HDMIPHY PLL1 of the physical layer corresponding to display interface HDMI1 as the pixel clock source. Video port 2 transmits data to display interface DP0, and the system phase-locked loop V0PLL serves as the pixel clock source for video port 2, thus meeting the application requirements of any multi-screen display.

[0079] Figure 6B The diagram shown is a schematic representation of the display output device according to an embodiment of this disclosure. If the current display interface (HDMI) is in an idle state when it does not receive an enable signal from the video port, the physical layer HDMIPHY PLL corresponding to the display interface can be configured as the pixel clock source for any video port. For example... Figure 6B As shown, video port 0 transmits data to display interface DP0, using the physical layer phase-locked loop HDMIPHY PLL0 as the pixel clock source; video port 1 transmits data to display interface DP1, using the physical layer phase-locked loop HDMIPHY PLL1 as the pixel clock source; and video port 2 transmits data to display interface DSI0, using the system phase-locked loop V0PLL as the pixel clock source, thus meeting the application requirements of any multi-screen display.

[0080] Figure 6C The diagram shown is a schematic of the display output device described in an embodiment of this disclosure. If the current physical layer's phase-locked loop (HDMIPHY PLL) is occupied by a video port connected to a non-HDMI display interface, after other video ports send an enable signal to the HDMI display interface, the video port corresponding to the HDMIPHY PLL needs to be dynamically switched. For example... Figure 6CAs shown, after receiving the enable signal sent from video port 1 to display interface HDMI0, when the phase-locked loop HDMIPHY PLL0 of the physical layer corresponding to display interface HDMI0 is occupied by video port 0 connected to a non-HDMI display interface, the phase-locked loop HDMIPHY PLL0 of the physical layer is decoupled from video port 0, the phase-locked loop HDMIPHY PLL0 of the physical layer is configured as the pixel clock source of video port 1, and the pixel clock source of video port 0 connected to a non-HDMI display interface is switched to the phase-locked loop HDMIPHY PLL1 of the physical layer. Video port 2 transmits data to display interface DSI0, and the system phase-locked loop V0PLL is used as the pixel clock source to meet the application requirements of arbitrary multi-screen display.

[0081] It should be noted that the above Figure 6A , Figure 6B , Figure 6C This invention uses the RK3588 chip as an example to illustrate one implementation of this disclosure. The specific connection method of this disclosure is not limited to this.

[0082] Figure 7 The diagram shown is a structural schematic of the chip described in an embodiment of this disclosure. Figure 7 As shown, the chip 200 includes a display interface 210 and a video output processing module 220.

[0083] Display interface 210 may include multiple standard types of display interfaces 210.

[0084] The video output processing module 220 includes a controller and a plurality of video ports, the controller being configured to perform a display output method according to any embodiment of the present disclosure.

[0085] In some possible implementations, the video output processing module 220 reads data from memory, processes it internally, and then sends it to the display interface 210 through a video port. The display interface 210 then encodes the data according to the interface protocol and sends it out for display. The video output processing module 220 is configured to send an enable signal and transmit data to the display interface 210. The display interface 210 is configured to receive the enable signal and transmit data, and configure the phase-locked loop (PLL) of the physical layer corresponding to the enabled display interface as the pixel clock source of the video port that sent the enable signal. When the PLL of the physical layer corresponding to the display interface is occupied by other video ports, the other video ports are decoupled from the physical layer, and the corresponding PLL of the physical layer is reconfigured as the pixel clock source of the video port.

[0086] In the several embodiments provided in this disclosure, it should be understood that the disclosed systems, apparatuses, or methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules / units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or units may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of apparatuses or modules or units may be electrical, mechanical, or other forms.

[0087] The modules / units described as separate components may or may not be physically separate. The components shown as modules / units may or may not be physical modules; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules / units can be selected to achieve the objectives of the embodiments of this disclosure, depending on actual needs. For example, the functional modules / units in the various embodiments of this disclosure may be integrated into one processing module, or each module / unit may exist physically separately, or two or more modules / units may be integrated into one module / unit.

[0088] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0089] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0090] The descriptions of the processes or structures corresponding to the above figures each have their own emphasis. For parts of a process or structure that are not described in detail, please refer to the relevant descriptions of other processes or structures.

[0091] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the claims of this disclosure.

Claims

1. A display output method, characterized in that, include: Determine if the first display interface is enabled; If the first display interface is not enabled at the first moment, the phase-locked loop of the first physical layer is coupled to the first video port as the pixel clock source of the first video port. The first physical layer corresponds to the first display interface and is used for transmission. The first video port sends the first display data to the second display interface according to the phase-locked loop of the first physical layer, so that the first display data can be output through the second display interface; If the first display interface is enabled at the first moment, the phase-locked loop of the first physical layer is coupled to the third video port as the pixel clock source of the third video port. as well as The third video port sends the fourth display data to the first display interface according to the phase-locked loop of the first physical layer, so that the fourth display data can be output via the first display interface.

2. The display output method according to claim 1, characterized in that, Also includes: If the first display interface is enabled at a second time after the first time, the phase-locked loop of the first physical layer is decoupled from the first video port, and the phase-locked loop of the first physical layer is coupled to the second video port as the pixel clock source of the second video port. as well as The second video port sends the second display data to the first display interface according to the phase-locked loop of the first physical layer, so that the second display data can be output through the first display interface.

3. The display output method according to claim 2, characterized in that, Also includes: Determine if the third display interface is enabled; If the third display interface is not enabled at the second moment, the phase-locked loop of the third physical layer is coupled to the first video port as the pixel clock source of the first video port. The third physical layer corresponds to the third display interface and is used for transmission. as well as The first video port sends the third display data to the second display interface according to the phase-locked loop of the third physical layer, so that the third display data can be output via the second display interface.

4. The display output method according to claim 2, characterized in that, Also includes: The system phase-locked loop is coupled to the first video port to serve as the pixel clock source for the first video port; as well as The first video port sends the third display data to the second display interface according to the system phase-locked loop, so that the third display data can be output via the second display interface.

5. The display output method according to claim 1, characterized in that, Determining whether the first display interface is enabled includes: Determine whether the first display interface receives an enable signal from any video port. Couple the phase-locked loop of the first physical layer to the first video port as a pixel clock source for the first video port includes: configuring the phase-locked loop of the first physical layer as a pixel clock source for the first video port.

6. The display output method according to claim 5, characterized in that, Receiving enable signals from any video port includes: At the first moment, it is determined that the first display interface has not received an enable signal from any video port, and it is determined that the second display interface has received an enable signal from the first video port. Upon receiving the enable signal from the first video port, the operating frequency of the first video port transmitted from the first video port is obtained. The transmission of first display data from the first video port to the second display interface via the phase-locked loop of the first physical layer includes: packaging the transmitted data to obtain the first display data, and sending the first display data to the second display interface. Configuring the phase-locked loop of the first physical layer as the pixel clock source of the first video port includes configuring the first video port with the pixel clock source having the same operating frequency.

7. The display output method according to claim 6, characterized in that, Configuring the phase-locked loop of the first physical layer as the pixel clock source for the first video port includes: Configure the parameters of the phase-locked loop of the first physical layer to the same clock frequency as the operating frequency of the first video port.

8. The display output method according to claim 1, characterized in that, Also includes: If the first physical layer is occupied by other video ports when the first display interface is enabled, the occupation of the other video ports is disconnected and the first physical layer is configured to be in an idle state.

9. The display output method according to claim 1, characterized in that, Also includes: If the second display interface is not enabled, the phase-locked loop of the second physical layer corresponding to the second display interface will be configured as the pixel clock source for any video port.

10. The display output method according to claim 1, characterized in that, Also includes: If the corresponding first physical layer is occupied by other video ports when the first display interface is enabled, the occupation of the other video ports is disconnected, and the pixel clock source of the other video ports is switched to the phase-locked loop of other physical layers or the system phase-locked loop.

11. A display output device, characterized in that, include: The control module is configured as follows: Determine if the first display interface is enabled; If the first display interface is not enabled at the first moment, the phase-locked loop of the first physical layer is coupled to the first video port as the pixel clock source of the first video port. The first physical layer corresponds to the first display interface and is used for transmission. The first video port sends the first display data to the second display interface according to the phase-locked loop of the first physical layer, so that the first display data can be output through the second display interface; If the first display interface is enabled at the first moment, the phase-locked loop of the first physical layer is coupled to the third video port as the pixel clock source of the third video port. as well as The third video port sends the fourth display data to the first display interface according to the phase-locked loop of the first physical layer, so that the fourth display data can be output via the first display interface.

12. The display output device according to claim 11, characterized in that, Also includes: Multiple video ports are configured to transmit display data to the corresponding display interface based on the pixel clock source; Multiple display interfaces are configured to receive enable signals from corresponding video ports among the multiple video ports, and to transmit display data to the display device; as well as Multiple physical layers, each corresponding to the multiple display interfaces, each include a phase-locked loop (PLL) for transmission and are configured to provide a clock frequency, identical to the operating frequency of the video port, to a corresponding video port among the multiple video ports via the PLL as a pixel clock source for the video port.

13. The display output device according to claim 12, characterized in that, The phase-locked loop is configured to generate a clock frequency that is the same as the operating frequency of the video port, and the clock frequency is sent to the video port through the display interface as the pixel clock source of the video port.

14. A chip, characterized in that, include: Multiple display interfaces; as well as A video output processing module includes a controller and multiple video ports, the controller being configured to perform a display output method according to any one of claims 1 to 10.

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