Communication method and device between virtual processors, medium and equipment

Abstract

The embodiment of the invention discloses a communication method and device between virtual processors, a medium and equipment, and the method comprises the steps: responding to a first virtual processor to execute a first operation instruction for a preset interrupt register, enabling a first physical processor corresponding to the first virtual processor to enter a first operation state, the first physical processor determines a target interrupt identifier of an interrupt request corresponding to the first operation instruction and physical processor identifier information corresponding to a second virtual processor corresponding to the target interrupt identifier according to the first operation instruction and pre-configured virtual interrupt control information; and the first physical processor injects virtual interrupt information corresponding to the interrupt request into the second virtual processor through the physical processor corresponding to the physical processor identification information. According to the embodiment of the invention, the complexity of the processing flow of the interrupt virtualization can be reduced, the processing efficiency of the interrupt virtualization is improved, and the communication efficiency between the virtual processors is further improved.

Description

Technical Field

[0001] This disclosure relates to virtualization technology, and in particular to a method, apparatus, medium and device for communication between virtual processors. Background Technology

[0002] In microkernel-based virtualization, as much functional code (or application code, or simply code) as possible is executed in the processor's user mode (or user space). This user-mode functionality is implemented through the Virtual Machine Manager (VMM), while the processor's kernel mode (i.e., the microkernel) retains only essential functionalities such as memory management and task scheduling. Virtualization technology includes interrupt virtualization, which is typically implemented in user mode. User mode and kernel mode are two different execution levels of the processor designed by the operating system for security and resource management. Code running in user mode corresponds to a lower privilege level of the processor, while code running in kernel mode corresponds to the highest privilege level. Because user-mode and kernel-mode code have different privilege levels, during interrupt virtualization in user mode, user-mode code often needs to call kernel-mode code functions. This requires the processor to switch between user mode and kernel mode multiple times, making the entire interrupt virtualization process complex, inefficient, and affecting the communication efficiency between virtual processors. Summary of the Invention

[0003] The embodiments of this disclosure provide a communication method, apparatus, medium, and device between virtual processors, which can reduce the complexity of the interrupt virtualization process, improve the processing efficiency of interrupt virtualization, and thus improve the communication efficiency between virtual processors.

[0004] A first aspect of this disclosure provides a communication method between virtual processors, comprising: in response to a first virtual processor executing a first operation instruction on a preset interrupt register, a first physical processor corresponding to the first virtual processor enters a first running state; the first physical processor determines, according to the first operation instruction and pre-configured virtual interrupt control information, a target interrupt identifier of an interrupt request corresponding to the first operation instruction, and physical processor identifier information corresponding to a second virtual processor corresponding to the target interrupt identifier; the first physical processor injects virtual interrupt information corresponding to the interrupt request into the second virtual processor through the physical processor corresponding to the physical processor identifier information.

[0005] A second aspect of this disclosure provides a communication device between virtual processors, comprising: a first physical processor, configured to enter a first running state in response to the first virtual processor executing a first operation instruction on a preset interrupt register, and to determine, based on the first operation instruction and pre-configured virtual interrupt control information, a target interrupt identifier for an interrupt request corresponding to the first operation instruction, and physical processor identifier information corresponding to a second virtual processor corresponding to the target interrupt identifier; the first physical processor is further configured to inject virtual interrupt information corresponding to the interrupt request into the second virtual processor through the physical processor corresponding to the physical processor identifier information.

[0006] A third aspect of this disclosure is to provide a computer-readable storage medium storing a computer program that is executed by a processor to perform the virtual processor communication method described in any of the above embodiments of this disclosure.

[0007] A fourth aspect of this disclosure provides an electronic device, the electronic device comprising: a processor; a memory for storing executable instructions of the processor; the processor being configured to read the executable instructions from the memory, the processor executing the executable instructions to implement the virtual processor communication method described in any of the above embodiments of this disclosure.

[0008] A fifth aspect of this disclosure provides a computer program product that, when instructions in the computer program product are executed by a processor, performs the virtual processor communication method provided in any of the above embodiments of this disclosure.

[0009] Based on the communication method, apparatus, medium, and device between virtual processors provided in the above embodiments of this disclosure, when the first virtual processor executes a first operation instruction on a preset interrupt register, the first physical processor corresponding to the first virtual processor enters a first running state (i.e., kernel state). The first physical processor, according to the first operation instruction and pre-configured virtual interrupt control information, determines the target interrupt identifier of the interrupt request corresponding to the first operation instruction, and the physical processor identifier information corresponding to the second virtual processor corresponding to the target interrupt identifier. Then, the first physical processor can inject the virtual interrupt information corresponding to the interrupt request into the second virtual processor through the physical processor corresponding to the physical processor identifier information, effectively realizing interrupt virtualization. Since the first physical processor completes interrupt virtualization in kernel state, it effectively avoids or reduces the switching between kernel state (i.e., the first running state) and user state (referred to as the second running state) of the processor (i.e., the first physical processor), thereby reducing the complexity of the interrupt virtualization process, improving the processing efficiency of interrupt virtualization, and enhancing the communication efficiency between virtual processors. Attached Figure Description

[0010] Figure 1 This is an exemplary application scenario of the communication method between virtual processors provided in this disclosure;

[0011] Figure 2 This is a flowchart illustrating an exemplary embodiment of the present disclosure of a communication method between virtual processors.

[0012] Figure 3 This is a flowchart illustrating a communication method between virtual processors provided in another exemplary embodiment of this disclosure;

[0013] Figure 4 This is a flowchart illustrating a communication method between virtual processors provided in yet another exemplary embodiment of the present disclosure;

[0014] Figure 5 This is a schematic diagram of the process for configuring virtual interrupt control information provided in an exemplary embodiment of this disclosure;

[0015] Figure 6 This is a schematic diagram illustrating the principle of implementing interrupt virtualization in user space in related technologies;

[0016] Figure 7 This is a flowchart illustrating a process for implementing interrupt virtualization in user space within related technologies;

[0017] Figure 8 This is a schematic diagram illustrating the principle of interrupt virtualization implemented in kernel mode in related technologies;

[0018] Figure 9 This is a schematic diagram illustrating the process of implementing interrupt virtualization in kernel mode in related technologies;

[0019] Figure 10 This is a schematic diagram illustrating the principle of implementing interrupt virtualization provided by an exemplary embodiment of this disclosure;

[0020] Figure 11 This is a schematic diagram of the virtual interruption information injection process provided in an exemplary embodiment of this disclosure;

[0021] Figure 12 This is a schematic diagram of the structure of a communication device between virtual processors provided in an exemplary embodiment of this disclosure;

[0022] Figure 13 This is a schematic diagram of the structure of a communication device between virtual processors provided in another exemplary embodiment of this disclosure;

[0023] Figure 14 This is a schematic diagram of the structure of a communication device between virtual processors provided in yet another exemplary embodiment of the present disclosure;

[0024] Figure 15This is a structural diagram of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0025] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0026] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0027] This disclosure outlines

[0028] In developing this disclosure, the inventors discovered that in microkernel-based virtualization technology, as much functional code (or application code, or simply code) as possible is typically executed in the processor's user mode (or user space). User-mode functionality is implemented through a Virtual Machine Manager (VMM), while the processor's kernel mode (i.e., the microkernel) retains only essential functional code such as memory management and task scheduling. Virtualization technology includes interrupt virtualization, which is typically implemented in user mode. User mode and kernel mode are two different execution levels of the processor designed by the operating system for security and resource management. Code running in user mode corresponds to a lower privilege level of the processor, while code running in kernel mode corresponds to the highest privilege level. Because user-mode and kernel-mode code have different privilege levels, during interrupt virtualization in user mode, user-mode code often needs to call kernel-mode code functions. For example, the virtual machine manager needs to call service interfaces provided by the microkernel to implement higher-privilege functions through the microkernel. This results in the processor needing to switch between user mode and kernel mode multiple times, making the entire interrupt virtualization process complex, inefficient, and affecting the communication efficiency between virtual processors.

[0029] Exemplary Overview

[0030] In related technologies, when the first virtual processor executes a first operation instruction on a preset interrupt register, in response to this first operation instruction, the first physical processor corresponding to the first virtual processor enters kernel mode and transmits the first operation instruction to the virtual machine manager. That is, the first physical processor switches from kernel mode to user mode and executes the relevant functions corresponding to the virtual machine manager. The virtual machine manager executes the interrupt virtualization function according to the first operation instruction, and obtains the virtual interrupt-related information corresponding to the first operation instruction. The virtual interrupt-related information includes the virtual processor responding to the interrupt request, the virtual interrupt priority, etc. Based on the virtual interrupt-related information, it calls the microkernel service, triggering the first physical processor to switch from user mode to kernel mode again and write the virtual interrupt-related information into the preset interrupt register. After the first physical processor completes the virtual interrupt information injection in kernel mode, it switches back to user mode. The virtual machine manager checks whether the interrupt information injection was successful. If an overflow occurs, overflow handling is performed. If the injection is successful, the virtual machine manager sends an acknowledgment message to the microkernel, indicating that the interrupt virtualization process is complete. Thus, the first physical processor needs to switch between user mode and kernel mode multiple times to complete the interrupt virtualization process.

[0031] Figure 1 This is an exemplary application scenario of the inter-virtual processor communication method provided in this disclosure. For example... Figure 1As shown, the virtual processor corresponding to virtual machine 11 can be referred to as the first virtual processor. The virtual machine manager 12 (i.e., VMM) is responsible for managing virtual machine 11, including creating and starting virtual machine 11. Virtual machine manager 12 can call the service functions of microkernel 13 through the service interface provided by microkernel 13, thereby implementing higher-privilege-level functions. When the first physical processor 14 is in kernel mode, it can run higher-privilege-level code of microkernel 13 to implement the relevant functions of microkernel 13; when the first physical processor 14 is in user mode, it can run lower-privilege-level code corresponding to virtual machine manager 12 to implement the relevant functions of virtual machine manager 12. Privilege levels include, but are not limited to, EL0, EL1, and EL2. Different privilege levels have different functions and access permissions, with access permissions referring to access permissions to hardware resources. The virtual machine manager 12 and the microkernel 13 are intermediate software layers embedded between the operating system and the physical hardware. The virtual machine manager 12 is used to virtualize hardware resources and allocate virtual hardware resources to the virtual machine 11. These hardware resources include the CPU (Central Processing Unit), memory, I / O (input / output) devices, etc., ensuring that the virtual machine 11 has an independent virtual hardware environment and a corresponding operating system. The virtual machine 11 typically includes client user software (APP, i.e., user applications under the operating system) and the client operating system (OS). The client user software has a privilege level of EL0, the client operating system has a privilege level of EL1, the virtual machine manager 12 has a privilege level of EL0, and the microkernel 13 has the highest privilege level, i.e., EL2. The first virtual processor represents the CPU resources allocated to the virtual machine 11, used to execute the relevant tasks of the operating system and / or applications (i.e., user software) running on the virtual machine. Using the virtual processor communication method (also known as virtual machine communication method) provided in this embodiment, in response to the first virtual processor of virtual machine 11 executing a first operation instruction on the preset interrupt register 15, the first physical processor 14 corresponding to the first virtual processor enters a first running state, which can also be called kernel state. In the first running state, the first physical processor 14 executes the code corresponding to the microkernel 13, and determines the target interrupt identifier of the interrupt request corresponding to the first operation instruction and the physical processor identifier information corresponding to the second virtual processor corresponding to the target interrupt identifier according to the first operation instruction and the pre-configured virtual interrupt control information. The first physical processor 14 can inject the virtual interrupt information corresponding to the interrupt request into the second virtual processor through the physical processor corresponding to the physical processor identifier information.The second virtual processor can be a virtual processor other than the first virtual processor 14, in which case the physical processor corresponding to the physical processor identification information is the first physical processor; or, the second virtual processor can be a virtual processor 14 14, in which case the physical processor corresponding to the physical processor identification information is the second physical processor. Since virtual interrupt control information is pre-configured in the microkernel 13, the first physical processor 14 can complete the virtualization of the interrupt request corresponding to the first operation instruction in only the first running state. This effectively avoids or reduces the situation in related technologies where the first physical processor 14 needs to switch between kernel mode and user mode to complete interrupt virtualization processing. Therefore, this disclosure can reduce the complexity of interrupt virtualization processing and improve the processing efficiency of interrupt virtualization.

[0032] Exemplary methods

[0033] Figure 2 This is a flowchart illustrating a virtual processor communication method provided in an exemplary embodiment of this disclosure. The virtual processor communication method of this embodiment can be applied to electronic devices, such as in-vehicle computing platforms, systems on a chip (SoC), or vehicles, for example. Figure 2 As shown, the method of this disclosure embodiment may include the following steps:

[0034] Step 210: In response to the first virtual processor executing a first operation instruction on a preset interrupt register, the first physical processor corresponding to the first virtual processor enters the first running state.

[0035] The first virtual processor is the virtual processor corresponding to a virtual machine (which may be referred to as the first virtual machine). Each virtual machine may correspond to one or more virtual processors. The first virtual processor represents at least a portion of the CPU resources allocated to the virtual machine for executing tasks related to the operating system and / or applications (i.e., user software) running in the virtual machine.

[0036] The default interrupt register is a register in the Generic Interrupt Controller (GIC), which routes interrupt signals from one or more interrupt sources to the virtual processor or virtual machine that responds to the interrupt signal. An interrupt source is either the virtual processor or virtual machine that generates the interrupt signal, or a processing unit (or processing component) within a virtual processor or virtual machine that generates the interrupt signal.

[0037] The first operation instruction is a write operation instruction that writes interrupt information to a preset interrupt register. That is, the first operation instruction includes the interrupt information to be written. The interrupt information to be written may include information required by the format corresponding to the preset interrupt register, such as an interrupt identifier (or interrupt number) and / or relevant information of the second virtual processor used to determine the interrupt request corresponding to the interrupt information. The first physical processor corresponding to the first virtual processor refers to the physical processor where the CPU resources corresponding to the first virtual processor reside. The first running state can also be called kernel mode, that is, the first physical processor executes the functional code corresponding to the microkernel to implement the relevant functions of the microkernel. Because the first virtual processor is restricted by access permissions and does not have permission to directly access the preset interrupt register, the first virtual processor executing the first operation instruction on the preset interrupt register is equivalent to the first virtual processor initiating a system call request to the microkernel. The first physical processor responds to the system call request and enters the first running state, that is, switches from the current running state (e.g., user mode) to kernel mode. The first physical processor can be any physical processor in the SoC.

[0038] In some optional embodiments, when the first physical processor is in the second running state, the virtual machine manager has control over the first physical processor. The first physical processor can run code with a lower privilege level corresponding to the virtual machine manager to implement the relevant functions of the virtual machine manager, such as allocating virtual hardware resources, such as the first virtual processor, to the virtual machine, and running user software and operating system of the client through the first virtual processor with a lower privilege level. Since the first virtual processor does not have access to the preset interrupt register, if the first virtual processor executes the first operation instruction on the preset interrupt register, the microkernel needs to provide services. Therefore, it will initiate a system call request to the microkernel based on the first operation instruction, triggering the first physical processor to switch from the second running state to the first running state, so that the microkernel gains control of the first physical processor, that is, the first physical processor enters the first running state.

[0039] In some optional embodiments, the second running state can be referred to as user mode. In the second running state, the first physical processor can run functional code with lower privilege levels, such as the virtual machine manager, the client's operating system, and the client's user software. In practical applications, optionally, multiple different running states can be set for the physical processor according to the respective privilege levels of the client's user software, the client's operating system, and the virtual machine manager. For example, the running state corresponding to the client's user software, the running state corresponding to the client's operating system, and the running state corresponding to the virtual machine manager, etc. Then, the physical processor can run corresponding functional code after switching to different running states. Thus, the second running state can be one of multiple running states. This is only an exemplary running state setting, and practical applications are not limited to this example. It can be set according to actual needs.

[0040] For example, the preset interrupt register is a register capable of generating SGI (Software Generated Interrupt) interrupt requests. For instance, it may include a GICC (Generic Interrupt Controller CPU interface) register. The GICC register may include, but is not limited to, a software-generated Group0 register (ICC_SGI0R_EL1) and a software-generated Group1 register (ICC_SGI1R_EL1). Here, ICC_SGI represents a software-generated interrupt, 0R and 1R represent Group0 and Group1 registers respectively, EL1 represents the privilege level, and ICC_SGI0R_EL1 and ICC_SGI1R_EL1 are used to output the interrupt signal corresponding to the software-generated interrupt request. When the first virtual processor executes an interrupt request generated by the user software or operating system software corresponding to the virtual machine, it needs to write the virtual interrupt information corresponding to the interrupt request into the preset interrupt register through the microkernel, and read the virtual interrupt information from the preset interrupt register through the interrupt controller. Based on the virtual interrupt information, it generates virtual interrupt information and routes the virtual interrupt information to the corresponding second virtual processor.

[0041] Step 220: The first physical processor determines the target interrupt identifier of the interrupt request corresponding to the first operation instruction and the physical processor identifier information corresponding to the second virtual processor corresponding to the target interrupt identifier, based on the first operation instruction and the pre-configured virtual interrupt control information.

[0042] Virtual interrupt control information refers to information used to control interrupt requests of virtual processors, which is pre-configured in the corresponding configuration registers or other memory spaces in kernel mode. Virtual interrupt control information may include one or more of the following: virtual processor topology information, virtual interrupt configuration information, etc. Virtual processor topology information may include one or more of the following: the number of virtual processors, virtual processor identifier information corresponding to each virtual processor, physical processor information corresponding to each virtual processor, etc. Virtual interrupt configuration information is the interrupt configuration information corresponding to interrupt requests generated by software in the virtual machine. Virtual interrupt configuration information may include one or more of the following: interrupt identifier, interrupt identifier priority, enable status, etc.

[0043] After the first physical processor receives the first operation instruction, it can read the interrupt identifier from the first operation instruction and use the read interrupt identifier as the target interrupt identifier corresponding to the interrupt request of the first operation instruction. Then, based on the target interrupt identifier, it determines the second virtual processor corresponding to the target interrupt identifier and the physical processor identifier information corresponding to the second virtual processor from the virtual interrupt control information. For example, the target interrupt identifier can be matched with each interrupt identifier in the virtual interrupt control information, and based on the matching result, the second virtual processor corresponding to the target interrupt identifier and the physical processor identifier information corresponding to the second virtual processor can be obtained from the virtual interrupt control information.

[0044] Step 230: The first physical processor injects the virtual interrupt information corresponding to the interrupt request into the second virtual processor through the physical processor identification information corresponding to the physical processor.

[0045] The virtual interrupt information corresponding to the interrupt request is virtualized version of the interrupt request. There is a correspondence between the virtual interrupt information and the interrupt request; different interrupt requests correspond to different virtual interrupt information. This ensures that the interrupt request can be accurately routed to the corresponding virtual processor, and that the virtual processor can determine the corresponding interrupt handling task to be executed based on the virtual interrupt information. The specific content of the virtual interrupt information is set according to virtualization requirements, and this embodiment does not limit it.

[0046] In some optional embodiments, the physical processor corresponding to the physical processor identification information can be a first physical processor, or the physical processor corresponding to the physical processor identification information can be a second physical processor other than the first physical processor. That is, the second virtual processor can be a virtual processor belonging to the same first physical processor as the first virtual processor; or, the second virtual processor can be a virtual processor belonging to a different physical processor than the first virtual processor, i.e., the first virtual processor is a virtual processor virtualized and simulated from the first physical processor, and the second virtual processor is a virtual processor virtualized and simulated from the second physical processor. For example, when a SoC includes multiple physical processors, each physical processor can simulate one or more virtual machines through virtualization technology, and a corresponding virtual processor can be assigned to each virtual machine. Then, the virtual processors of the same physical processor can communicate with each other, and the virtual processors of different physical processors can also communicate with each other. The virtual processors can provide services through interrupt requests to achieve collaborative work.

[0047] In some optional embodiments, if the physical processor corresponding to the physical processor identification information is a first physical processor, then the first physical processor injects the virtual interrupt information corresponding to the interrupt request into the second virtual processor. In other optional embodiments, if the physical processor corresponding to the physical processor identification information is a second physical processor, then the first physical processor injects the virtual interrupt information corresponding to the interrupt request into the second virtual processor through the second physical processor. For example, the first physical processor can transmit the virtual interrupt information to the second physical processor through inter-core communication, and the second physical processor injects the virtual interrupt information into the second virtual processor. Inter-core communication methods may include, for example, IPC (Inter-Process Communication), Mailbox (hardware mailbox), shared memory, etc., and are not specifically limited.

[0048] The communication method between virtual processors provided in this embodiment involves the first physical processor entering a first running state (i.e., kernel state) when the first virtual processor executes a first operation instruction on a preset interrupt register. The first physical processor, based on the first operation instruction and pre-configured virtual interrupt control information, determines a target interrupt identifier, a second virtual processor corresponding to the target interrupt identifier, and physical processor identifier information corresponding to the second virtual processor. Then, the first physical processor can inject virtual interrupt information corresponding to an interrupt request into the second virtual processor through the physical processor corresponding to the physical processor identifier information, effectively realizing interrupt virtualization. Since the first physical processor completes interrupt virtualization in kernel state, it effectively avoids or reduces frequent switching between kernel state (i.e., the first running state) and user state (referred to as the second running state), thereby reducing the complexity of the interrupt virtualization process, improving the processing efficiency of interrupt virtualization, and ultimately improving the communication efficiency between virtual processors.

[0049] Figure 3 This is a flowchart illustrating a communication method between virtual processors provided in another exemplary embodiment of this disclosure.

[0050] In some alternative embodiments, in the above... Figure 2 Based on the embodiment shown, the virtual interrupt control information includes virtual processor topology information and virtual interrupt configuration information corresponding to each interrupt identifier among multiple interrupt identifiers; the virtual processor topology information includes the correspondence between each virtual processor identifier and the physical processor identifier in at least one virtual processor identifier.

[0051] The virtual processor topology information describes the topological relationships between the virtual processors simulated by each physical processor. This information can include one or more of the following: the number of virtual processors, the virtual processor identifier for each virtual processor, and the physical processor information for each virtual processor. For example, if a SoC includes M physical processors, and each physical processor simulates N virtual processors, then the virtual processor topology information includes the virtual processor identifiers for each of the M*N virtual processors, and the correspondence between these virtual processors and the physical processor identifiers for the M physical processors. This is just an example; in real-world applications, the number of virtual processors simulated by different physical processors can vary.

[0052] Virtual interrupt configuration information refers to the interrupt configuration information corresponding to interrupt requests generated by software within a virtual machine. The software within the virtual machine is the software running on the virtual processor. Each virtual processor has its own corresponding virtual interrupt configuration information; that is, each virtual processor can correspond to multiple interrupt identifiers, each with its own virtual interrupt configuration information. The virtual processor corresponding to the virtual interrupt configuration information can be identified through the virtual processor identifier information. Virtual interrupt configuration information can include one or more of the following: interrupt identifier, the priority of the interrupt identifier, enable status, and the identifier of the associated virtual processor. The interrupt identifier is the information that uniquely identifies an interrupt request. The priority of the interrupt identifier refers to the priority of the interrupt request corresponding to that interrupt identifier. The priority of the interrupt identifier can be used by the interrupt controller to determine the routing order of interrupt requests, or to determine the priority level of interrupt requests being responded to. For example, interrupt requests with higher priority are injected into the corresponding virtual processor first, so that they are responded to more quickly. The enable status of the interrupt identifier indicates whether the interrupt request corresponding to that interrupt identifier needs to be responded to. If the enable status is enabled, the interrupt request corresponding to that interrupt identifier will be responded to normally. If the enable status is disabled, it means that the interrupt request corresponding to that interrupt identifier is in a disabled state and does not need to be processed.

[0053] like Figure 3 As shown, in step 220, the first physical processor determines the target interrupt identifier of the interrupt request corresponding to the first operation instruction and the physical processor identifier information corresponding to the second virtual processor corresponding to the target interrupt identifier, based on the first operation instruction and the pre-configured virtual interrupt control information. This may include:

[0054] Step 2210: The first physical processor determines the target interrupt identifier according to the first operation instruction.

[0055] The first physical processor can read the interrupt identifier from the first operation instruction as the target interrupt identifier.

[0056] Step 2220: The first physical processor determines the identification information of the second virtual processor corresponding to the target interrupt identifier based on the target interrupt identifier and the virtual interrupt configuration information corresponding to each interrupt identifier among the multiple interrupt identifiers.

[0057] The first physical processor can match the target interrupt identifier with each interrupt identifier in the virtual interrupt control information to determine the interrupt identifier that matches the target interrupt identifier. The virtual interrupt control information includes the correspondence between each interrupt identifier and the virtual interrupt configuration information (which can be called the first correspondence), and the correspondence between the virtual interrupt configuration information and the virtual processor identifier information (which can be called the second correspondence). Therefore, based on the interrupt identifier that matches the target interrupt identifier and the first correspondence, the virtual interrupt configuration information corresponding to the target interrupt identifier can be determined. Based on the virtual interrupt configuration information corresponding to the target interrupt identifier and the second correspondence, the virtual processor identifier information corresponding to the virtual interrupt configuration information can be determined, which is the identifier information of the second virtual processor.

[0058] Step 2230: The first physical processor determines the physical processor identification information corresponding to the second virtual processor based on the identification information of the second virtual processor and the correspondence between the identification information of each virtual processor and the identification information of the physical processor.

[0059] The virtual interrupt control information includes the correspondence between the identification information of each virtual processor and the identification information of the physical processor (which can be called the third correspondence). The first physical processor can obtain the correspondence between the identification information of each virtual processor and the identification information of the physical processor from the virtual interrupt control information. After obtaining the identification information of the second virtual processor, the first physical processor can match the identification information of the second virtual processor with the identification information of each virtual processor in the third correspondence. Based on the matching result, the physical processor identification information corresponding to the second virtual processor is determined.

[0060] In the embodiments of this disclosure, by configuring virtual processor topology information and virtual interrupt configuration information in the microkernel of the first physical processor, the first physical processor can quickly determine the identification information of the physical processor corresponding to the second virtual processor requested by the interrupt request in kernel mode, so as to determine whether the second virtual processor belongs to the first physical processor. Then, the virtual interrupt information corresponding to the interrupt request is quickly injected into the second virtual processor through the physical processor corresponding to the second virtual processor, effectively avoiding frequent switching between kernel mode and user mode of the first physical processor.

[0061] Figure 4 This is a flowchart illustrating a virtual processor communication method provided in another exemplary embodiment of the present disclosure.

[0062] In some alternative embodiments, based on any of the above embodiments, such as Figure 4 As shown, step 230, where the first physical processor injects the virtual interrupt information corresponding to the interrupt request into the second virtual processor through the physical processor identification information, may include:

[0063] Step 2310: The first physical processor determines the matching status between the physical processor identification information and the identification information of the first physical processor.

[0064] The matching status can include two states: matched and mismatched (or not matched). If the processor identifier information matches the identifier information of the first physical processor, it means that the physical processor corresponding to the physical processor identifier information is the first physical processor. If the processor identifier information does not match the identifier information of the first physical processor, it means that the physical processor corresponding to the physical processor identifier information is not the first physical processor. In this case, the physical processor corresponding to the physical processor identifier information is called the second physical processor. The first physical processor can match its own physical processor identifier information to obtain a matching status.

[0065] Step 2320: In response to the matching status being matched, the first physical processor determines that the physical processor corresponding to the physical processor identification information is the first physical processor.

[0066] In this case, the first physical processor responds to the matching state as a match, indicating that the physical processor identification information is consistent with the identification information of the first physical processor. Therefore, it is determined that the physical processor corresponding to the physical processor identification information is the first physical processor.

[0067] Step 2330: The first physical processor reads the target virtual interrupt configuration information corresponding to the interrupt request from the virtual interrupt control information based on the target interrupt identifier.

[0068] Among them, the target interrupt identifier is the interrupt identifier corresponding to the interrupt request. The first physical processor can match the target interrupt identifier with each interrupt identifier in the virtual interrupt control information, and read the virtual interrupt configuration information corresponding to the target interrupt identifier from the virtual interrupt control information according to the matching result, which is the target virtual interrupt configuration information corresponding to the interrupt request.

[0069] Step 2340: The first physical processor injects the target virtual interrupt configuration information into the preset interrupt register in the interrupt controller.

[0070] The first physical processor can extract the information corresponding to the preset interrupt register from the target virtual interrupt configuration information according to the format of the preset interrupt register in the interrupt controller, and write the extracted information into the preset interrupt register according to the format of the preset interrupt register, thereby realizing the injection of virtual interrupt configuration information.

[0071] Step 2350: The interrupt controller generates virtual interrupt information based on the target virtual interrupt configuration information in the preset interrupt register, and transmits the virtual interrupt information to the second virtual processor.

[0072] The interrupt controller can detect the preset interrupt register in real time or at regular intervals, or monitor the preset interrupt register through other means. The interrupt controller responds by writing target virtual interrupt configuration information into the preset interrupt register, generating virtual interrupt information according to the target virtual interrupt configuration information in the preset interrupt register, and transmitting the virtual interrupt information to the second virtual processor.

[0073] In some alternative embodiments, the virtual interrupt information may be represented as an interrupt signal generated by an interrupt controller, which transmits the interrupt signal to a second virtual processor. The interrupt controller may interact with the second virtual processor in any implementable manner in the related art to transmit the virtual interrupt information to the second virtual processor.

[0074] In the embodiments of this disclosure, when the second virtual processor belongs to the first physical processor, the first physical processor injects the virtual interrupt information corresponding to the interrupt request into the interrupt controller in kernel mode. The interrupt controller then transmits the virtual interrupt information to the second virtual processor, avoiding interaction with the virtual machine manager. This achieves rapid injection of virtual interrupt information in kernel mode and improves the processing efficiency of the interrupt virtualization process.

[0075] In some optional embodiments, the virtual interrupt control information includes virtual interrupt configuration information corresponding to each interrupt identifier among multiple interrupt identifiers.

[0076] Step 2330, the first physical processor, reads the target virtual interrupt configuration information corresponding to the interrupt request from the virtual interrupt control information based on the target interrupt identifier, which may include:

[0077] The first physical processor reads the virtual interrupt configuration information corresponding to the target interrupt identifier from the virtual interrupt configuration information corresponding to each interrupt identifier among multiple interrupt identifiers, and uses it as the target virtual interrupt configuration information.

[0078] The first physical processor can match the target interrupt identifier with each interrupt identifier in the virtual interrupt control information, and determine the virtual interrupt configuration information corresponding to the target interrupt identifier based on the matching result, thereby obtaining the target virtual interrupt configuration information.

[0079] The embodiments of this disclosure configure virtual interrupt configuration information corresponding to each interrupt identifier in the microkernel, enabling the first physical processor to quickly determine the target virtual interrupt configuration information corresponding to the interrupt request in kernel mode, avoiding interaction between the microkernel and the virtual machine manager, and effectively improving the communication efficiency between virtual processors.

[0080] In some alternative embodiments, such as Figure 4 As shown, the method in this embodiment of the disclosure may further include:

[0081] Step 310: In response to the mismatch status, the first physical processor sends a first interrupt signal to the second physical processor corresponding to the physical processor identification information according to the target interrupt identifier.

[0082] The first interrupt signal includes the target interrupt identifier.

[0083] In some optional embodiments, if the physical processor identification information does not match the identification information of the first physical processor, it means that the physical processor identification information is inconsistent with the identification information of the first physical processor. That is, the physical processor corresponding to the physical processor identification information is a second physical processor other than the first physical processor. Then, the first physical processor sends a first interrupt signal to the second physical processor according to the target interrupt identifier. The first interrupt signal includes the target interrupt identifier so that the second physical processor can obtain the target interrupt identifier from the first interrupt signal.

[0084] In some optional embodiments, the first physical processor can generate a first interrupt signal according to the target interrupt identifier and the format of the communication protocol with the second physical processor. The first physical processor can send the first interrupt signal to the second physical processor via inter-core communication. Inter-core communication methods include, but are not limited to, IPC communication, shared memory, or Mailbox. IPC communication is a communication mechanism that allows data exchange and synchronization between different processes. Shared memory is a special IPC mechanism that allows multiple processes to access the same memory region, enabling efficient data exchange. Mailbox is a message passing mechanism used to pass messages between different components or modules.

[0085] Step 320: The second physical processor reads the target virtual interrupt configuration information corresponding to the target interrupt identifier from the pre-configured virtual interrupt control information based on the target interrupt identifier in the first interrupt signal.

[0086] Upon receiving the first interrupt signal, the second physical processor can obtain the target interrupt identifier from the first interrupt signal. Then, based on the target interrupt identifier, it reads the target virtual interrupt configuration information corresponding to the target interrupt identifier from the pre-configured virtual interrupt control information of the second physical processor. The pre-configured virtual interrupt control information of the second physical processor is consistent with the virtual interrupt control information of the first physical processor. That is, virtual interrupt control information can be configured for each physical processor that needs to participate in inter-virtual processor communication. The virtual interrupt control information may include virtual processor topology information and virtual interrupt configuration information corresponding to multiple interrupt identifiers, as detailed in the aforementioned embodiments.

[0087] In some optional embodiments, in the first operating state, the second physical processor reads the target virtual interrupt configuration information corresponding to the target interrupt identifier from the pre-configured virtual interrupt control information according to the target interrupt identifier in the first interrupt signal. The specific operation of the second physical processor reading the target virtual interrupt configuration information corresponding to the target interrupt identifier from the virtual interrupt control information according to the target interrupt identifier can be referred to the reading operation of the first physical processor described above, and will not be repeated here.

[0088] Step 330: The second physical processor injects the target virtual interrupt configuration information into the preset interrupt register in the interrupt controller.

[0089] In the first operating state, the second physical processor injects the target virtual interrupt configuration information into the preset interrupt register in the interrupt controller. The specific operation of the second physical processor injecting the target virtual interrupt configuration information into the preset interrupt register in the interrupt controller can be referred to the specific operation of the first physical processor in step 2340 above, and will not be repeated here.

[0090] Step 340: The interrupt controller generates virtual interrupt information based on the target virtual interrupt configuration information in the preset interrupt register, and transmits the virtual interrupt information to the second virtual processor.

[0091] For specific instructions on step 340, please refer to step 2350 above.

[0092] In this embodiment of the disclosure, when the physical processor corresponding to the second virtual processor is not the first physical processor, the first physical processor sends a first interrupt signal to the second physical processor corresponding to the second virtual processor via inter-processor interrupt (IPI) to initiate an interrupt request to the second physical processor. The second physical processor quickly injects the target virtual interrupt configuration information corresponding to the interrupt request into the preset interrupt register in the interrupt controller according to the target interrupt identifier and the pre-configured virtual interrupt control information in the first interrupt signal. This avoids the second physical processor switching between kernel mode and user mode, thereby improving the communication efficiency between virtual processors of different physical processors.

[0093] In some optional embodiments, after the first physical processor sends a first interrupt signal to the second physical processor corresponding to the physical processor identification information according to the target interrupt identifier in response to the mismatch state, the method further includes: the first physical processor updating the program pointer and switching from the first running state to the second running state, so that the first virtual processor executes other instructions after the first operation instruction.

[0094] The Program Counter (PC) is a special register used to store the address of the currently executing instruction. The PC's main function is to indicate the execution location of the next instruction. When an instruction is completed, the PC automatically increments to point to the next instruction. For example, before the first physical processor sends the first interrupt signal to the second physical processor, the program counter points to the address of the first operation instruction, meaning the first operation instruction is the currently executing instruction. After the first physical processor sends the first interrupt signal to the second physical processor, indicating that the first operation instruction has been completed, the first physical processor updates the program counter, making it point to another instruction following the first operation instruction (or the third operation instruction, or simply the third instruction). Furthermore, the first physical processor switches from a first running state to a second running state, such as user mode, meaning the first physical processor switches from kernel mode to user mode, allowing the first virtual processor to continue executing other instructions following the first operation instruction based on the program counter.

[0095] In the embodiments of this disclosure, after the first physical processor completes the injection of virtual interrupt information, the program pointer and state switching are maintained in real time to ensure that the virtual processor can continue to work.

[0096] Figure 5 This is a schematic diagram of the process for configuring virtual interrupt control information provided in an exemplary embodiment of this disclosure.

[0097] In some alternative embodiments, based on any of the above embodiments, such as Figure 5 As shown, the process of configuring virtual interrupt control information may include the following steps:

[0098] Step 410: The first physical processor responds to the first system call request from the virtual machine manager and configures the virtual processor topology information for the first virtual processor.

[0099] The first system call request is a request to configure the virtual processor topology information. The virtual machine manager is a user-mode application that manages virtual machines. The first physical processor runs the corresponding application of the virtual machine manager in user mode (i.e., the second running state) to implement the virtual machine manager's functions. When initializing the virtual machine corresponding to the first virtual processor, the virtual machine manager triggers a call to the interface provided by the microkernel to configure the virtual processor topology information for the first virtual processor.

[0100] In some optional embodiments, since the virtual machine manager is responsible for managing the lifecycle of each virtual machine and allocating corresponding virtual processors to each virtual machine, the virtual machine manager can obtain the correspondence between each virtual processor and the physical processor, as well as the virtual machine, and thus configure the virtual processor topology information for the first virtual processor according to the correspondence between the virtual processor and the physical processor, as well as the virtual machine.

[0101] In some alternative embodiments, the first physical processor responds to a first system call request from the virtual machine manager, enters a first running state, and in the first running state, configures the virtual processor topology information.

[0102] Step 420: In response to the first virtual processor executing the second operation instruction, the first physical processor enters the first running state.

[0103] The second operation instruction is the operation instruction for configuring virtual interrupt configuration information for the first virtual processor. This instruction can include the virtual interrupt configuration information to be configured. The virtual interrupt configuration information can include interrupt identifiers, enable states, priorities, etc. For example, during virtual machine initialization, the priorities and enable states of each interrupt request are configured. These configuration operations are called the second operation instructions. Due to the limited privilege level of the first virtual processor, executing the second operation instruction will trigger an exception, equivalent to initiating a system call to the microkernel. The first physical processor detects this exception and switches from the second running state to the first running state to execute the relevant microkernel functions. A system call is a way for a user-mode process on the physical processor to actively request a switch to kernel mode. The user-mode process uses a system call to request the use of service programs provided by the microkernel to complete tasks. For example, configuring virtual interrupt configuration information is a function of the virtual machine manager. The first virtual processor does not have the necessary privileges and uses a system call to communicate with the virtual machine manager using a service program provided by the microkernel to complete the virtual interrupt configuration information operation.

[0104] Step 430: The first physical processor sends the operation information corresponding to the second operation instruction to the virtual machine manager.

[0105] The operation information includes virtual interrupt configuration information corresponding to at least one interrupt identifier, enabling the virtual machine manager to simulate the execution of the operation corresponding to the second operation instruction and send a second system call request to the first physical processor based on the operation information. The virtual interrupt configuration information corresponding to the interrupt identifier can be found in the foregoing content.

[0106] After entering the first running state, the first physical processor determines the operation information corresponding to the second operation instruction based on the second operation instruction, and sends the operation information to the virtual machine manager. The operation information corresponding to the second operation instruction can be obtained from the second operation instruction. After obtaining the operation information corresponding to the second operation instruction, the virtual machine manager simulates the operation corresponding to the second operation instruction based on the operation information, and sends a second system call request to the first physical processor. The second system call request includes virtual interrupt configuration information corresponding to at least one interrupt identifier. By calling the microkernel service of the first physical processor, the configuration operation of the virtual interrupt configuration information is realized.

[0107] Step 440: The first physical processor configures the virtual interrupt configuration information corresponding to each interrupt identifier according to the second system call request.

[0108] In this process, the first physical processor responds to the second system call request, obtains the virtual interrupt configuration information corresponding to each interrupt identifier from the second system call request, and then configures the virtual interrupt configuration information corresponding to each interrupt identifier.

[0109] In some optional embodiments, the first physical processor, in the first running state, responds to the second system call request by running the application corresponding to the microkernel, obtains the virtual interrupt configuration information corresponding to each interrupt identifier from the second system call request, and then configures the virtual interrupt configuration information corresponding to each interrupt identifier.

[0110] Step 450: The first physical processor determines the virtual interrupt control information based on the virtual processor topology information and the virtual interrupt configuration information corresponding to each interrupt identifier.

[0111] In some optional embodiments, the first physical processor can construct virtual interrupt control information according to a preset format using the virtual processor topology information and the virtual interrupt configuration information corresponding to each interrupt identifier. Then, the virtual interrupt control information can be stored in a preset storage area to configure the virtual interrupt control information. When the first physical processor performs the above-mentioned virtual interrupt information injection operation, it can obtain the virtual interrupt control information from the preset storage area.

[0112] In the embodiments of this disclosure, the configuration operation of virtual interrupt control information is set on the virtual machine manager side, in user mode. The virtual machine manager initiates a system call request to the microkernel to configure the virtual interrupt control information into the microkernel. While ensuring the virtual machine manager's control function over the virtual machine, the microkernel can quickly determine the second virtual processor and target virtual interrupt configuration information corresponding to the interrupt request when the virtual interrupt information corresponding to the interrupt request is injected. This avoids frequent interactions between the microkernel and the virtual machine manager (i.e., frequent switching of the first physical processor between the first running state and the second running state) and avoids a significant increase in the amount of microkernel code, thus ensuring the security of the microkernel.

[0113] In some optional embodiments, the first physical processor receives a first system call request from the virtual machine manager via a virtualization system call interface. The virtualization system call interface is a service interface provided by the microkernel to the virtual machine manager. The virtual machine manager initiates the first system call request through the virtualization system call interface to configure the virtual processor topology information.

[0114] In some optional embodiments, the first physical processor receives a second system call request from the virtual machine manager through a virtualization system call interface to configure virtual interrupt configuration information.

[0115] In some optional embodiments, the microkernel provides various service interfaces to the virtual machine manager (VMM) for VMM to call, enabling higher-privilege (e.g., EL2 privilege) operations. Interactions between components within the SoC can be achieved through interfaces, which may include hardware interfaces and software interfaces, without specific limitations. Examples include the interface between the CPU and the microkernel, and the interface between the GIC, etc., which will not be elaborated upon further.

[0116] In related technologies, physical processors (CPUs) typically implement interrupt virtualization functionality in user mode or kernel mode. Figure 6 This is a schematic diagram illustrating the principle of implementing interrupt virtualization functionality in user space in related technologies. For example... Figure 6As shown, the Virtual Machine Manager (VMM) implements virtual machine management and interrupt virtualization functions. Virtual machine management functions include the creation and startup of virtual machines (VMs). Interrupt virtualization functions include virtualization related to VM interrupt requests. The Interrupt Controller (GIC) includes, but is not limited to, the CPU interface, the Redistributor, and the Distributor. VM interrupt request-related virtualization functions include virtual interrupt management sub-functions and GIC virtualization sub-functions (or virtual GICs). GIC virtualization sub-functions typically include CPU interface virtualization, and the Redistributor and Distributor virtualization is implemented through the GIC virtualization sub-functions within the VMM's interrupt virtualization functionality. VMs can execute specific operation instructions to enable, disable, configure priorities, and route interrupts. These operations by the VM will trigger an exception and cause it to enter the microkernel. Specifically, the execution of these operation instructions by the first virtual processor corresponding to the VM will trigger an exception and cause it to enter the microkernel. Entering the microkernel means that the first physical processor (CPU) corresponding to the VM enters kernel mode. In kernel mode, the CPU sends the interrupt request corresponding to the operation instruction to the VMM via IPC. The VMM triggers a system call request to the microkernel through the virtualization sub-function of the GIC. The microkernel injects virtual interrupt-related information corresponding to the interrupt request into the GIC through the services provided. The GIC generates virtual interrupt information based on the virtual interrupt-related information and transmits the virtual interrupt information to the second virtual processor that responds to the interrupt request. As shown in the figure, the virtual interrupt information is transmitted to the VM, indicating that the virtual interrupt information is responded to by the second virtual processor corresponding to the VM, or the second virtual processor can be the virtual processor corresponding to another VM. The arrow pointing from the GIC to the physical processor (CPU) indicates that the GIC can send interrupt requests to the physical processor (CPU). That is, all kinds of interrupt requests are routed and sent by the GIC. The virtualization sub-function of GIC simulates the operation of the hardware GIC through software. Since there is only one hardware GIC, but there are usually multiple virtual machines, it is not configured so that all virtual machines have the permission to operate the hardware GIC. The GIC that the virtual machine faces is the virtual GIC in the VMM. The virtualization sub-function of GIC can be used to update the registers in the hardware GIC, such as updating the priority of a certain interrupt request or other information.For example, if the mapping between virtual memory and physical resources is not established during VM initialization, VM operations on this register will generate an exception. This exception will trigger the physical processor corresponding to the VM to enter the microkernel, i.e., the physical processor enters kernel mode. The physical processor sends this exception information to the VMM via IPC. The VMM has the address of this register pre-configured and can determine the address of the virtual GIC based on this address. The VMM calls the virtual GIC based on the address of the virtual GIC, and the virtual GIC performs a priority modification operation based on the exception information, i.e., triggers a system call request. Through the services provided by the microkernel, the priority in the register of the hardware GIC is modified. The VMM manages the VM's virtual interrupt information through the virtual interrupt management sub-function, injecting virtual interrupt information belonging to the VM into the VM. Specifically, the virtual interrupt management sub-function manages the target VCPU, priority, VM virtual interrupt initialization, and injection of various types of virtual interrupt information. Among these, the VMM initiates a system call request to the microkernel, requesting to call the microkernel's interrupt injection service to inject virtual interrupt information into the VM.

[0117] Figure 7 This is a flowchart illustrating a process for implementing interrupt virtualization in user space within related technologies. For example... Figure 7As shown, the virtual machine (VM) sends an SGI interrupt to the virtual processor (VCPUn) by writing to the register ICC_SGI1R_EL1. This register ICC_SGI1R_EL1 can include multiple fields, each storing different information. These fields may include, for example, an interrupt identifier field (INTID) and information fields to identify the target VCPU (VCPUm in the figure). The operation of VCPUn writing to this register triggers the physical processor corresponding to VCPUn to trap into the kernel (S0 in the figure). KernelCPUn indicates that the physical processor CPUn corresponding to VCPUn is in kernel mode (or refers to the microkernel of CPUn). KernelCPUm indicates that the physical processor CPUm corresponding to the target VCPUm is in kernel mode (or refers to the microkernel of CPUm). KernelCPUn responds to the exception trap by performing exception trap handling and sending the exception trap to the user-space virtual machine manager (VMM) for processing via IPC (i.e., S1, IPC). Upon receiving the VSGI (Virtual Software Generated Interrupt) IPC, the VMM performs exception trap handling. By parsing the value of ICC_SGI1R_EL1 to be written, it calculates the target VCPU's identification information and VSGI interrupt number (i.e., the interrupt identifier). Then, the VMM calls the microkernel CPUn's interrupt injection service to inject the VSGI interrupt information into the target VCPU, as shown in Figure S2. During target VCPU analysis, the VMM needs to call the microkernel CPUn's system call function to obtain the values ​​of relevant registers. When processing this injection request, in response to the target VCPUm not running on the current CPU, the microkernel CPUn sends an inter-core interrupt (IPI) request to the physical processor CPUm where VCPUm resides, as shown in Figure S3. The injection is then completed by the kernel on CPUm, as shown in Figure S4.1. Kernel CPUn needs to wait for Kernel CPUm to complete the injection operation. After completing the interrupt injection operation, Kernel CPUn returns to the user-mode VMM, as shown in Figure S4.2. The VMM checks if the injection was successful. If an overflow occurs, it handles the overflow. Finally, it sends a reply to the microkernel to indicate that the VSGI exception trap handling is complete, as shown in step S5. Before the VMM sends the reply, since the instruction that triggered the exception has already completed, the VMM needs to request a microkernel service via a system call to update the VCPUn's PC pointer to point to the address of the next instruction.After receiving the VMM's reply, the kernel CPUn schedules VCPUn to continue running, as shown in S6 in the figure, switching CPUn to user mode, and VCPUn continues to execute the next instruction according to the PC pointer.

[0118] according to Figure 6 and Figure 7 As can be seen, interrupt virtualization is implemented in user space, requiring frequent interaction between the microkernel and the virtual machine manager. The entire process involves multiple switching of the physical processor between user and kernel modes, triggering numerous system calls, making the process complex and inefficient. Furthermore, some microkernels are serial, requiring the microkernel to acquire the global kernel lock each time it enters kernel mode. This lock contention is exacerbated, especially with frequent interrupt requests and multi-threaded VMM, reducing overall processing efficiency and impacting system performance (e.g., SoC). In addition, the process involves VCPU switching and VMM thread scheduling, which also affects processing efficiency. In summary, implementing interrupt virtualization in user space increases VSGI interrupt latency, severely impacting system performance when VSGI interrupts are frequent.

[0119] Figure 8 This is a schematic diagram illustrating the principle of interrupt virtualization implemented in kernel mode in related technologies. For example... Figure 8 As shown, the microkernel includes virtual machine management functions and interrupt virtualization functions, which can be found in the above description. Figure 6 The difference between the functions shown is that the virtual machine management function and the interrupt virtualization function are implemented in kernel mode. Since there is no virtual machine manager, there is no need for the microkernel to interact with the virtual machine manager. Figure 9 This is a schematic diagram illustrating the process of implementing interrupt virtualization in kernel mode in related technologies. For example... Figure 9 As shown, when VCPUn executes a partial operation that triggers an exception and traps into Kernel CPUn (i.e., S0 in the diagram), Kernel CPUn performs exception trap handling, determines the target VCPU and SGI interrupt number, and performs virtual interrupt management, injecting SGI interrupt information into the target VCPU. Specifically, Kernel CPUn sends an inter-core interrupt (IPI) request to Kernel CPUm, as shown in S1 in the diagram. Kernel CPUm then injects virtual interrupt information (VSGI interrupt information) into the target VCPUm, as shown in S2 in the diagram. After completing the virtual interrupt information injection, Kernel CPUm returns to VCPUn, allowing VCPUn to continue executing the next instruction.

[0120] according to Figure 8 and Figure 9The process of implementing interrupt virtualization in kernel mode is illustrated. It's evident that implementing interrupt virtualization in kernel mode increases the amount of kernel code (or code area), increasing the attack surface of the microkernel and reducing its security. Furthermore, since both virtual machine management and interrupt virtualization are implemented in kernel mode, their fault tolerance and isolation are poor. If the interrupt virtualization function in the microkernel malfunctions, it will not only affect the processing of interrupt requests from all virtual machines (VMs) but also other kernel-mode functions, thus impacting the entire system. In addition, because interrupt virtualization is tightly coupled with the microkernel, it is difficult to upgrade the interrupt virtualization component. Therefore, although implementing interrupt virtualization in kernel mode offers better VSGI injection performance and shorter latency, it compromises the security of the microkernel.

[0121] To address the various problems mentioned above in implementing interrupt virtualization in kernel mode and user mode, the virtual processor communication method of this disclosure provides a method to improve VSGI injection performance while ensuring microkernel security. Figure 10 This is a schematic diagram illustrating the principle of implementing interrupt virtualization according to an exemplary embodiment of this disclosure. For example... Figure 10 As shown, the Virtual Machine Manager (VMM) includes virtual machine management functions and interrupt virtualization functions. The interrupt virtualization functions include virtual interrupt management sub-functions and GIC virtualization sub-functions. Virtual interrupt control information and fast virtual interrupt injection functions are configured in the microkernel. VSGI virtualization is decomposed into control and data parts. The interrupt virtualization function in the VMM is responsible for the control part of VSGI virtualization, while the microkernel is responsible for the data part, i.e., the configuration and control operations related to interrupt requests, such as the enable state, disable state, and priority configuration of interrupt requests, are implemented in the VMM. The virtual interrupt information injection process is implemented in the microkernel. Figure 11 This is a schematic diagram illustrating the virtual interruption information injection process provided in an exemplary embodiment of this disclosure. For example... Figure 11As shown, VCPUn represents the first virtual processor, VCPUm represents the second virtual processor, CPUn represents the first physical processor, Kernel CPUn indicates that the first physical processor is in kernel mode or represents the microkernel of the first physical processor, and Kernel CPUm indicates that the second physical processor is in kernel mode or represents the microkernel of the second physical processor. When the first virtual processor executes an operation instruction that triggers an exception trap (S11, trap), Kernel CPUn performs exception trap handling. It determines the instruction type based on the operation instruction. A non-VSGI exception indicates that the currently trapped operation instruction is not the first operation instruction; for example, it could be the second operation instruction or other instructions related to the functions of the control part in interrupt virtualization. In the case of a non-VSGI exception, Kernel CPUn sends the exception information to the VMM via IPC (as shown in S12 in the figure), and the VMM performs exception trap handling. The specific process is the same as... Figure 7Similar to the above, it will not be elaborated here. A VSGI exception indicates that the operation instruction executed by VCPUn is a VSGI-related first operation instruction. Kernel CPUn then uses the virtual interrupt fast injection function to determine the target interrupt identifier corresponding to the interrupt request (i.e., determine the VSGI interrupt number) and the second virtual processor and the physical processor identifier corresponding to the second virtual processor (i.e., determine the target VCPU) based on the first operation instruction and the pre-configured virtual interrupt control information. It then determines the matching status between the physical processor identifier and the identifier of the first physical processor. If the matching status is "matched" (the diagram shows an example of a mismatch between the physical processor identifier and the first physical processor identifier; a match is not shown), the physical processor corresponding to the physical processor identifier is determined to be the first physical processor. Based on the target interrupt identifier, the target virtual interrupt configuration information corresponding to the interrupt request is read from the virtual interrupt control information. The target virtual interrupt configuration information is injected into the preset interrupt register in the interrupt controller. The interrupt controller reads the target virtual interrupt information from the preset interrupt register, generates virtual interrupt information based on the target virtual interrupt configuration information, and transmits the virtual interrupt information to the second virtual processor. In response to a mismatch, based on the target interrupt identifier, a first interrupt signal (i.e., interrupt injection IPI in S13) is sent to the second physical processor (i.e., CPUm where the target VCPU resides) corresponding to the physical processor identifier information. The second physical processor obtains the target virtual interrupt configuration information corresponding to the target interrupt identifier from the pre-configured virtual interrupt control information according to the target interrupt identifier in the first interrupt signal. The second physical processor injects the target virtual interrupt configuration information into the preset interrupt register in the interrupt controller. The interrupt controller generates virtual interrupt information according to the target virtual interrupt configuration information in the preset interrupt register and transmits the virtual interrupt information to the second virtual processor (VSGI interrupt injection as shown in S15). After the Kernel CPUn completes S13, it updates the program pointer (i.e., the PC pointer), and then CPUn returns to user mode, as shown in S14. The specific operations of each step are described in the aforementioned embodiments. For the virtual machine's configuration operations of the preset interrupt register in the interrupt controller and the configuration operations of the virtual interrupt control information within the microkernel, the following steps are followed: Figure 5The interaction process between the microkernel and the virtual machine manager is illustrated. By placing most of the functionality in user space and adding only a small amount of code to the microkernel, VSGI injection is achieved quickly, avoiding multiple switches between kernel and user space during virtual interrupt information injection. This reduces the interaction with the user-space VMM, thereby reducing the number of system calls to the microkernel. Furthermore, the entire process avoids VCPU and VMM context switching and scheduling, effectively reducing VSGI interrupt handling latency. While most interrupt virtualization functionality is still implemented in the user-space VMM, the fast virtual interrupt injection function only injects virtual interrupt information based on the configured virtual interrupt control information. Compared to related technologies that implement interrupt virtualization in kernel space, the processing logic of this embodiment is simpler, with a smaller code size and minimal impact on the microkernel's code size. Therefore, high-performance VSGI injection can be achieved while ensuring microkernel performance. The above embodiments of this disclosure can be implemented individually or in any combination without conflict, depending on actual needs. This disclosure does not impose any limitations.

[0122] Any of the virtual processor communication methods provided in this disclosure can be executed by any suitable electronic device with data processing capabilities, including but not limited to: terminal devices and servers. Alternatively, any of the virtual processor communication methods provided in this disclosure can be executed by a processor, such as by a processor executing any of the virtual processor communication methods mentioned in this disclosure by calling corresponding instructions stored in memory. Further details will not be elaborated below.

[0123] Exemplary device

[0124] Figure 12 This is a schematic diagram of a virtual processor communication device provided in an exemplary embodiment of the present disclosure. The virtual processor communication device 50 of this embodiment can be used to implement corresponding method embodiments of the present disclosure, such as… Figure 12 The virtual processor communication device 50 shown may include: a first physical processor 51.

[0125] The first physical processor 51 is configured to: enter a first running state in response to the first virtual processor executing a first operation instruction on a preset interrupt register; determine the target interrupt identifier of the interrupt request corresponding to the first operation instruction and the physical processor identifier information corresponding to the second virtual processor corresponding to the target interrupt identifier according to the first operation instruction and the pre-configured virtual interrupt control information; and inject the virtual interrupt information corresponding to the interrupt request into the second virtual processor through the physical processor corresponding to the physical processor identifier information.

[0126] Figure 13This is a schematic diagram of the structure of a communication device between virtual processors provided in another exemplary embodiment of this disclosure.

[0127] In some alternative embodiments, in the above... Figure 12 Based on the illustrated embodiments, as Figure 13 As shown, the virtual processor communication device 50 in this embodiment of the present disclosure may further include: an interrupt controller 52;

[0128] The first physical processor 51 includes: a virtual interrupt fast injection unit 511.

[0129] The virtual interrupt fast injection unit 511 is used for:

[0130] Based on the first operation instruction and the virtual interrupt control information pre-configured in the first physical processor 51, the target interrupt identifier corresponding to the interrupt request and the physical processor identifier information corresponding to the second virtual processor corresponding to the target interrupt identifier are determined; the matching status between the physical processor identifier information and the identifier information of the first physical processor 51 is determined; in response to the matching status being a match, the physical processor corresponding to the physical processor identifier information is determined to be the first physical processor 51; the target virtual interrupt configuration information corresponding to the interrupt request is read from the virtual interrupt control information according to the target interrupt identifier; the target virtual interrupt configuration information is injected into the preset interrupt register in the interrupt controller 52; the interrupt controller 52 is used to generate virtual interrupt information according to the target virtual interrupt configuration information in the preset interrupt register, and to transmit the virtual interrupt information to the second virtual processor.

[0131] In some optional embodiments, the virtual interrupt control information includes virtual interrupt configuration information corresponding to each interrupt identifier among multiple interrupt identifiers.

[0132] The virtual interrupt fast injection unit 511 is specifically used to: read the virtual interrupt configuration information corresponding to the target interrupt identifier from the virtual interrupt configuration information corresponding to each interrupt identifier among multiple interrupt identifiers, and use it as the target virtual interrupt configuration information.

[0133] Figure 14 This is a schematic diagram of the structure of a communication device between virtual processors provided in another exemplary embodiment of the present disclosure.

[0134] In some optional embodiments, the virtual processor communication device 50 of this disclosure embodiment further includes: a second physical processor 53.

[0135] The virtual interrupt fast injection unit 511 is also used to send a first interrupt signal to the second physical processor 53 corresponding to the physical processor identification information according to the target interrupt identifier in response to the mismatch status; the first interrupt signal includes the target interrupt identifier.

[0136] The second physical processor 53 is used to read the target virtual interrupt configuration information corresponding to the target interrupt identifier from the pre-configured virtual interrupt control information according to the target interrupt identifier in the first interrupt signal.

[0137] The second physical processor 53 is also used to inject the target virtual interrupt configuration information into the preset interrupt register in the interrupt controller 52.

[0138] The interrupt controller 52 is used to generate virtual interrupt information based on the target virtual interrupt configuration information in the preset interrupt register, and to transmit the virtual interrupt information to the second virtual processor.

[0139] In some optional embodiments, after the first physical processor 51 sends a first interrupt signal to the second physical processor corresponding to the physical processor identification information according to the target interrupt identifier in response to the matching state being mismatched, the first physical processor 51 or the virtual interrupt fast injection unit 511 is further used to update the program pointer and switch from the first running state to the second running state so that the first virtual processor executes other instructions after the first operation instruction.

[0140] In some optional embodiments, the virtual interrupt control information includes virtual processor topology information and virtual interrupt configuration information corresponding to each interrupt identifier among multiple interrupt identifiers; the virtual processor topology information includes the correspondence between each virtual processor identifier and physical processor identifier in at least one virtual processor identifier.

[0141] The virtual interrupt fast injection unit 511 in the first physical processor 51 is specifically used for: determining the target interrupt identifier according to the first operation instruction; determining the identifier information of the second virtual processor corresponding to the target interrupt identifier according to the target interrupt identifier and the virtual interrupt configuration information corresponding to each interrupt identifier among the multiple interrupt identifiers; and determining the physical processor identifier information corresponding to the second virtual processor according to the identifier information of the second virtual processor and the correspondence between the identifier information of each virtual processor and the identifier information of the physical processor.

[0142] In some optional embodiments, the first physical processor 51 is further configured to configure virtual processor topology information for the first virtual processor in response to a first system call request from the virtual machine manager; and to enter a first running state in response to the first virtual processor executing a second operation instruction. The first physical processor 51 is further configured to send operation information corresponding to the second operation instruction to the virtual machine manager. The operation information includes virtual interrupt configuration information corresponding to at least one interrupt identifier, so that the virtual machine manager can simulate the execution of the operation corresponding to the second operation instruction and send a second system call request to the first physical processor 51 according to the operation information. The first physical processor 51 is further configured to configure the virtual interrupt configuration information corresponding to each interrupt identifier according to the second system call request. The first physical processor 51 is further configured to determine virtual interrupt control information based on the virtual processor topology information and the virtual interrupt configuration information corresponding to each interrupt identifier.

[0143] In some alternative embodiments, the first physical processor 51 receives a first system call request from the virtual machine manager via a virtualization system call interface.

[0144] The embodiments described above can be implemented individually or in any combination without conflict. The specific implementation can be set according to actual needs, and this disclosure does not limit them.

[0145] The beneficial technical effects corresponding to the exemplary embodiments of this device can be found in the corresponding beneficial technical effects of the exemplary method section above, and will not be repeated here.

[0146] Exemplary electronic devices

[0147] Figure 15 This is a structural diagram of an electronic device provided in an embodiment of the present disclosure, including at least one processor 91 and a memory 92.

[0148] The processor 91 may be a central processing unit (CPU) or other form of processing unit with data processing and / or instruction execution capabilities, and may control other components in the electronic device 90 to perform desired functions.

[0149] The memory 92 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 91 may execute one or more computer program instructions to implement the methods and / or other desired functions of the various embodiments of this disclosure described above.

[0150] In one example, the electronic device 90 may also include an input device 93 and an output device 94, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0151] The input device 93 may also include, for example, a touch screen, a microphone, various sensors, etc.

[0152] The output device 94 can output various information to the outside, including, for example, a display, a speaker, a communication network and its connected remote output devices, etc.

[0153] Of course, for the sake of simplicity, Figure 15 Only some of the components of the electronic device 90 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 90 may include any other suitable components depending on the specific application.

[0154] Exemplary computer program products and computer-readable storage media

[0155] In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods in the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0156] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0157] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps of the methods in the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0158] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0159] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0160] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A communication method between virtual processors, comprising: In response to the first virtual processor executing a first operation instruction on a preset interrupt register, the first physical processor corresponding to the first virtual processor enters a first running state. The first physical processor determines the target interrupt identifier of the interrupt request corresponding to the first operation instruction and the physical processor identifier information corresponding to the second virtual processor corresponding to the target interrupt identifier based on the first operation instruction and the pre-configured virtual interrupt control information. The first physical processor injects the virtual interrupt signal corresponding to the interrupt request into the second virtual processor through the physical processor identification information.

2. The method according to claim 1, wherein, The first physical processor injects the virtual interrupt signal corresponding to the interrupt request into the second virtual processor through the physical processor identification information, including: The first physical processor determines the matching status between the physical processor identification information and the identification information of the first physical processor; In response to the matching status being a match, the first physical processor determines that the physical processor corresponding to the physical processor identification information is the first physical processor. The first physical processor reads the target virtual interrupt configuration information corresponding to the interrupt request from the virtual interrupt control information based on the target interrupt identifier; The first physical processor injects the target virtual interrupt configuration information into a preset interrupt register in the interrupt controller; The interrupt controller generates the virtual interrupt information based on the target virtual interrupt configuration information in the preset interrupt register, and transmits the virtual interrupt information to the second virtual processor.

3. The method according to claim 2, wherein, The virtual interrupt control information includes virtual interrupt configuration information corresponding to each interrupt identifier among multiple interrupt identifiers; The first physical processor reads the target virtual interrupt configuration information corresponding to the interrupt request from the virtual interrupt control information based on the target interrupt identifier, including: The first physical processor reads the virtual interrupt configuration information corresponding to the target interrupt identifier from the virtual interrupt configuration information corresponding to each of the multiple interrupt identifiers, and uses it as the target virtual interrupt configuration information.

4. The method according to claim 2, further comprising: In response to the mismatch status, the first physical processor sends a first interrupt signal to the second physical processor corresponding to the physical processor identification information according to the target interrupt identifier; the first interrupt signal includes the target interrupt identifier. The second physical processor reads the target virtual interrupt configuration information corresponding to the target interrupt identifier from the pre-configured virtual interrupt control information based on the target interrupt identifier in the first interrupt signal; The second physical processor injects the target virtual interrupt configuration information into the preset interrupt register in the interrupt controller; The interrupt controller generates the virtual interrupt information based on the target virtual interrupt configuration information in the preset interrupt register, and transmits the virtual interrupt information to the second virtual processor.

5. The method according to claim 4, wherein, After the first physical processor, in response to the mismatch status, sends a first interrupt signal to the second physical processor corresponding to the physical processor identification information based on the target interrupt identifier, the method further includes: The first physical processor updates the program pointer and switches from the first running state to the second running state, so that the first virtual processor executes other instructions after the first operation instruction.

6. The method according to any one of claims 1-5, wherein, The virtual interrupt control information includes virtual processor topology information and virtual interrupt configuration information corresponding to each of the multiple interrupt identifiers; the virtual processor topology information includes the correspondence between each of the virtual processor identifiers and the physical processor identifiers in at least one virtual processor identifier; The first physical processor determines, based on the first operation instruction and pre-configured virtual interrupt control information, the target interrupt identifier of the interrupt request corresponding to the first operation instruction, and the physical processor identifier information corresponding to the second virtual processor corresponding to the target interrupt identifier, including: The first physical processor determines the target interrupt identifier according to the first operation instruction; The first physical processor determines the identification information of the second virtual processor corresponding to the target interrupt identifier based on the target interrupt identifier and the virtual interrupt configuration information corresponding to each interrupt identifier among the plurality of interrupt identifiers; The first physical processor determines the physical processor identification information corresponding to the second virtual processor based on the identification information of the second virtual processor and the correspondence between the identification information of each virtual processor and the identification information of the physical processor.

7. The method according to any one of claims 1-5, further comprising: The first physical processor responds to a first system call request from the virtual machine manager and configures virtual processor topology information for the first virtual processor. In response to the first virtual processor executing the second operation instruction, the first physical processor enters the first running state, and the first physical processor sends operation information corresponding to the second operation instruction to the virtual machine manager; the operation information includes virtual interrupt configuration information corresponding to at least one interrupt identifier, so that the virtual machine manager simulates the operation corresponding to the second operation instruction according to the operation information and sends a second system call request to the first physical processor; The first physical processor configures the virtual interrupt configuration information corresponding to each interrupt identifier according to the second system call request; The first physical processor determines the virtual interrupt control information based on the virtual processor topology information and the virtual interrupt configuration information corresponding to each interrupt identifier.

8. The method according to claim 7, wherein, The first physical processor receives the first system call request from the virtual machine manager through the virtualization system call interface.

9. A communication device between virtual processors, comprising: The first physical processor is configured to enter a first running state in response to the first virtual processor executing a first operation instruction on a preset interrupt register, and to determine the target interrupt identifier of the interrupt request corresponding to the first operation instruction and the physical processor identifier information corresponding to the second virtual processor corresponding to the target interrupt identifier based on the first operation instruction and the pre-configured virtual interrupt control information. The first physical processor is further configured to inject virtual interrupt information corresponding to the interrupt request into the second virtual processor through the physical processor corresponding to the physical processor identification information.

10. The apparatus according to claim 9, wherein, The device further includes: an interrupt controller; The first physical processor includes: The virtual interrupt fast injection unit is used for: Based on the first operation instruction and the virtual interrupt control information pre-configured in the first physical processor, determine the target interrupt identifier corresponding to the interrupt request and the physical processor identifier information corresponding to the second virtual processor corresponding to the target interrupt identifier; Determine the matching status between the physical processor identification information and the identification information of the first physical processor; In response to the matching status being a match, it is determined that the physical processor corresponding to the physical processor identification information is the first physical processor; Based on the target interrupt identifier, the target virtual interrupt configuration information corresponding to the interrupt request is read from the virtual interrupt control information; The target virtual interrupt configuration information is injected into the preset interrupt register of the interrupt controller; The interrupt controller is used to generate the virtual interrupt information according to the target virtual interrupt configuration information in the preset interrupt register, and to transmit the virtual interrupt information to the second virtual processor.

11. A computer-readable storage medium storing a computer program that is executed by a processor to perform the method described in any one of claims 1-8.

12. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory, and to execute the executable instructions to implement the method described in any one of claims 1-8.

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