Testing device and testing method for mainboard device

Abstract

The invention discloses a testing device and a testing method for a mainboard device. The mainboard device comprises a power key end and a first reference voltage end. The testing device comprises a microprocessor, a first switch and a second switch. The microprocessor comprises a general purpose input / output pin. And the microprocessor provides a control signal through the universal input / output pin. The control end of the first switch is coupled with the universal input / output pin. The control end of the second switch is coupled to the first end of the first switch. The first end of the second switch is coupled with the power button end. The second end of the second switch is coupled to the first reference voltage end. The microprocessor controls connection or disconnection between the first end and the second end of the second switch based on the control signal and the first switch.

Description

Technical Field

[0001] This invention relates to a functional testing technique for computer systems, and more particularly to a testing apparatus and method for motherboard devices. Background Technology

[0002] Many components of a computer system are mounted on the motherboard. Therefore, the power management and power button functions on the motherboard are crucial. Before a computer system leaves the factory, it is desirable to test all its functions.

[0003] Modern power switches can perform corresponding functions depending on the power state and the number of seconds the button is pressed. For example, in the off state, pressing the power button can turn on the motherboard device; in the on state, pressing the power button can turn off the motherboard device; pressing the power button for a longer period of time can force the motherboard device to shut down, and so on. However, the aforementioned functions of the power button are likely tested manually before leaving the factory to ensure their complete functionality. Summary of the Invention

[0004] This invention provides a testing apparatus and method for motherboard devices, which reduces the need for manual verification of the power button function on the motherboard device.

[0005] In a test apparatus for a motherboard device according to an embodiment of the present invention, the motherboard device includes a power button terminal and a first reference voltage terminal. The test apparatus includes a microprocessor, a first switch, and a second switch. The microprocessor includes general-purpose input / output (GPIO) pins, through which the microprocessor provides control signals. The control terminal of the first switch is coupled to the GPIO pins. The control terminal of the second switch is coupled to a first terminal of the first switch, the first terminal of the second switch is coupled to the power button terminal, and the second terminal of the second switch is coupled to the first reference voltage terminal. The microprocessor controls the conduction or cutoff between the first terminal and the second terminal of the second switch based on the control signals and the first switch.

[0006] In a test method for a motherboard device according to an embodiment of the present invention, the motherboard device includes a power button terminal and a first reference voltage terminal. The test method includes: setting up a test device, wherein a first terminal of the test device is coupled to the power button terminal, and a second terminal of the test device is coupled to the first reference voltage terminal; and controlling the conduction or cutoff between the first terminal and the second terminal of the test device based on a control signal provided by the test device.

[0007] Based on the above, the motherboard device testing apparatus and method described in this embodiment of the invention utilize the testing apparatus to generate a control signal for testing the power button. This control signal is used to connect or disconnect the power button terminal and a reference voltage terminal (e.g., ground terminal), thereby verifying the function of the power button on the motherboard device. In other words, this embodiment of the invention reduces the need for manual verification of the motherboard device's functionality through the testing apparatus. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a computer system, motherboard device, and testing device according to an embodiment of the present invention.

[0009] Figure 2 This is a flowchart of a test method for a motherboard device according to an embodiment of the present invention.

[0010] Explanation of reference numerals in the attached figures:

[0011] 10: Computer System

[0012] 100: Testing equipment

[0013] 105: Motherboard Device

[0014] 107: Connector device

[0015] 110: Microprocessor

[0016] 120: First switch

[0017] 130: Voltage divider circuit

[0018] 140: Electrostatic Discharge Protection Circuit

[0019] 145: Fuse

[0020] 150: Signal Delay Circuit

[0021] GND: Ground terminal

[0022] PWRBT#: Power button end

[0023] RU: Pull-up resistor

[0024] R1, R2, RL1, RL2: Resistors

[0025] Vs3V: First voltage terminal

[0026] Vs12V: Second voltage terminal

[0027] MC1: Control transistor

[0028] MN1: First transistor

[0029] MN2: Second transistor

[0030] G: Gate terminal

[0031] S: Source Extreme

[0032] D: Leakage extreme

[0033] DC1: Capacitor

[0034] DR1, DR2: Resistors

[0035] ZD1, ZD2: Zener diodes

[0036] GPIO: General Purpose Input / Output Pins

[0037] CN: Control terminal of the second switch

[0038] N1: The first end of the testing device

[0039] N2: The second end of the testing device

[0040] S210~S220: Steps of the test method for the motherboard device Detailed Implementation

[0041] Figure 1 This is a schematic diagram of a computer system 10, a motherboard device 105, and a testing device 100 according to an embodiment of the present invention. The computer system 10 may include the motherboard device 105 and the testing device 100. The motherboard device 105 mainly includes a power button terminal PWRBT# and a first reference voltage terminal (in this embodiment, the ground terminal GND is used as an example).

[0042] When the computer system 10 is manufactured or its casing is installed, the casing of the computer system 10 has a power button. The two ends of this power button are respectively coupled to the power button terminal PWRBT# and the first reference voltage terminal. When the power button is pressed, the power button terminal PWRBT# and the first reference voltage terminal are made conductive to realize the corresponding function of the power button. In this embodiment, a test device 100 is set on the motherboard device 105 before the computer system 10 is manufactured to verify the corresponding function of the power button. That is, the test device 100 is set by coupling the first terminal N1 of the test device 100 to the power button terminal PWRBT# and coupling the second terminal N2 of the test device 100 to the first reference voltage terminal (ground terminal GND).

[0043] The testing device 100 includes a microprocessor 110, a first switch 120, and a second switch. In this embodiment, the first switch 120 is implemented using a control transistor MC1, and the second switch is implemented using a first transistor MN1 and a second transistor MN2. Users of this embodiment can adjust the circuit structure of the first switch 120 and the second switch according to their needs, and are not limited to... Figure 1 The circuit structure of the switch shown.

[0044] Microprocessor 110 includes general purpose input / output (GPIO) pins. Microprocessor 110 provides control signals to the control terminal of first switch 120 (e.g., the gate G of control transistor MC1) via GPIO pins. The control terminal of first switch 120 (e.g., the gate G of control transistor MC1) is coupled to GPIO pins. The control terminal CN of second switch (e.g., the gate G of first transistor MN1 and second transistor MN2) is coupled to a first terminal of first switch 120 (e.g., the drain D of control transistor MC1). The second terminal of first switch 120 (e.g., the source S of control transistor MC1) is coupled to a reference voltage terminal (e.g., ground GND). The first terminal of second switch (e.g., the drain D of first transistor MN1) is coupled to the power button terminal PWRBT# via a first terminal N1. The second terminal of second switch (e.g., the drain D of second transistor MN1) is coupled to a first reference voltage terminal (ground GND) via a second terminal N2.

[0045] The microprocessor 110 controls the conduction or cutoff between the first terminal (drain terminal D of the first transistor MN1) and the second terminal (drain terminal D of the second transistor MN2) of the second switch based on the control signal and the first switch 120. Specifically, the control signal in this embodiment can be a pulse signal. The pulse width of the pulse signal is when the control signal is at a first value (e.g., logic "1"). Other times in the control signal that are not the pulse width of the pulse signal are when the control signal is at a second value (e.g., logic "0"). The pulse width of the pulse signal can be set to N seconds by the microprocessor 110, where N is a positive integer. For example, in this embodiment, when the motherboard device 105 is powered off, setting the aforementioned N to 2, that is, turning on the power button terminal PWRBT# and the first reference voltage terminal (ground terminal GND) for 2 seconds, can power on the motherboard device 105. When the motherboard device 105 is powered on, setting N to 2, i.e., turning on the power button terminal PWRBT# and the first reference voltage terminal (GND ground) for 2 seconds, will power off the motherboard device 105. When the motherboard device 105 is powered on, setting N to 4, i.e., turning on the power button terminal PWRBT# and the first reference voltage terminal (GND ground) for 4 seconds, will force the motherboard device 105 to power off. The setting of N can be adjusted according to the different motherboard devices 105 and the different functions of the power button, allowing users of this embodiment to set the appropriate value.

[0046] When the control signal provided by the microprocessor 110 is a first value (logic "1"), the first and second terminals of the second switch are connected to each other, thereby connecting the power button terminal PWRBT# and the first reference voltage terminal (GND). Conversely, when the control signal provided by the microprocessor 110 is a second value (logic "0"), the first and second terminals of the second switch are not connected and are cut off, thereby de-connecting the power button terminal PWRBT# and the first reference voltage terminal (GND).

[0047] The control transistor MC1 is an N-type transistor. The first terminal of the control transistor MC1 (e.g., the drain terminal D) is coupled to the control terminal CN of the second switch. The second terminal of the control transistor MC1 (e.g., the source terminal S) is coupled to ground GND. When the gate terminal G of the control transistor MC1 receives a first voltage (3V), the first terminal (drain terminal D) and the second terminal (source terminal S) of the control transistor MC1 are mutually connected, causing one end of the resistor RL1 in the voltage divider circuit 130 to be coupled to ground.

[0048] The test device 100 also includes a connector device 107. The first end of the connector device 107 serves as the first end N1 of the test device 100, the second end of the connector device 107 serves as the second end N2 of the test device 100, the third end of the connector device 107 is not used, and the fourth end of the connector device 107 is coupled to the grounding terminal GND.

[0049] The test apparatus 100 also includes a pull-up resistor RU, a voltage divider circuit 130, an electrostatic discharge protection circuit 140, and a signal delay circuit 150. The two ends of the pull-up resistor RU are coupled to a general purpose input / output (GPIO) pin and a first voltage terminal Vs3V, respectively. When the control signal is a first value (logic "1"), the pull-up resistor RU provides a first voltage (e.g., 3V) on the first voltage terminal Vs3V to the control terminal of the first switch 120 (the gate G of the control transistor MC1).

[0050] The voltage divider circuit 130 includes a first voltage divider resistor RL1 and a second voltage divider resistor RL2. The two ends of the first voltage divider resistor RL1 are coupled to the second voltage terminal Vs12V and the control terminal CN of the second switch, respectively. The two ends of the second voltage divider resistor RL2 are coupled to the control terminal CN of the second switch and the first terminal (drain terminal D) of the first switch 120, respectively. When the first terminal (drain terminal D) and the second terminal (source terminal S) of the first switch 120 are mutually conductive, the control terminal CN of the second switch obtains a divided voltage through the voltage divider circuit 130 and the second voltage terminal Vs12V (e.g., 12V voltage).

[0051] The second switch includes a first transistor MN1 and a second transistor MN2. The control terminal (e.g., gate terminal G) of the first transistor MN1 is coupled to the control terminal CN of the second switch. The first terminal (e.g., drain terminal D) of the first transistor MN1 is coupled to the power button terminal PWRBT# of the motherboard device 105 via the first terminal N1 of the test device 100. The control terminal (e.g., gate terminal G) of the second transistor MN2 is coupled to the control terminal CN of the second switch. The first terminal (e.g., drain terminal D) of the second transistor MN2 is coupled to the first reference voltage terminal (ground terminal) of the motherboard device 105 via the second terminal N2 of the test device 100. The second terminal (e.g., source terminal S) of the first transistor MN1 is coupled to the second terminal (e.g., source terminal S) of the second transistor MN2.

[0052] The electrostatic discharge protection circuit 140 includes a fuse 145, a first Zener diode ZD1, and a second Zener diode ZD2. The fuse 145 serves as a current-limiting protection device and will trip when the current flowing through it exceeds 0.1A. The two ends of the fuse 145 are coupled to the power button terminal PWRBT# and the first terminal of the second switch (the drain terminal D of the first transistor MC1), respectively.

[0053] The first ZN diode ZD1 and the second ZN diode ZD2 are used for voltage protection. They are designed to withstand a signal input range of up to 12V for the power button terminal PWRBT# and can protect against surges exceeding 13V. Specifically, the first terminal of the first ZN diode ZD1 is coupled to the power button terminal PWRBT#, and its second terminal is coupled to ground GND. The first terminal of the second ZN diode ZD2 is coupled to the first reference voltage terminal (ground GND), and its second terminal is coupled to ground GND.

[0054] The signal delay circuit 150 includes resistors DR1 and DR2 and capacitor DC1. The signal delay circuit 150 primarily uses a resistor-capacitor circuit structure to delay the input of a 12V signal from the control terminal CN of the second switch. Specifically, one end of resistor DR1 is coupled to the control terminal CN of the second switch, and the other end of resistor DR1 is coupled to the source terminals S of transistors MC1-MC2. One end of capacitor DC1 is coupled to the control terminal CN of the second switch, and the other end of capacitor DC1 is coupled to the source terminals S of transistors MC1-MC2. One end of resistor DR1 is coupled to ground GND, and the other end of resistor DR1 is coupled to the source terminals S of transistors MC1-MC2. The test apparatus 100 also includes matching resistors R1 and R2. One end of resistors R1 and R2 is coupled to ground, and the other ends of resistors R1 and R2 are respectively coupled to the drain terminals D of the first transistor MC1 and the second transistor MC2.

[0055] Figure 2 This is a flowchart of a test method for a motherboard device according to an embodiment of the present invention. (Refer to...) Figure 1 and Figure 2 In step S210, a test device 100 is installed on the motherboard device 105 of the computer system 10. The first terminal N1 of the test device 100 is coupled to the power button terminal PWRBT#, and the second terminal N2 of the test device 100 is coupled to the first reference voltage terminal (ground terminal GND). In step S220, the conduction or cutoff between the first terminal N1 and the second terminal N2 of the test device 100 is controlled based on a control signal provided by the test device 100. The control signal can be a pulse signal, and the pulse width of this pulse signal is set to N seconds by the test device 100. Figure 2 For details of each step, please refer to the foregoing embodiments.

[0056] In summary, the motherboard device testing apparatus and method described in this embodiment of the invention utilize the testing apparatus to generate a control signal for testing the power button. This control signal is used to connect or disconnect the power button terminal and a reference voltage terminal (e.g., ground terminal), thereby verifying the function of the power button on the motherboard device. In other words, this embodiment of the invention reduces the need for manual verification of the motherboard device's functionality through the testing apparatus.

[0057] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A test apparatus for a host board device, wherein the host board device comprises a power button terminal and a first reference voltage terminal, the test apparatus comprising: a microprocessor comprising a general purpose input / output pin, wherein the microprocessor provides a control signal through the general purpose input / output pin; a first switch having a control terminal coupled to the general purpose input / output pin; and a second switch having a control terminal coupled to a first terminal of the first switch, a first terminal coupled to the power button terminal, and a second terminal coupled to the first reference voltage terminal, wherein the microprocessor controls conduction or non-conduction between the first terminal and the second terminal of the second switch based on the control signal and the first switch. when the control signal is a first value, the first terminal and the second terminal of the second switch are in conduction with each other, 2. The test device of claim 1, wherein, when the control signal is a second value, the first terminal and the second terminal of the second switch are in non-conduction with each other.

3. The test apparatus of claim 1, further comprising: a pull-up resistor having two terminals coupled to the general purpose input / output pin and a first voltage terminal, respectively, when the control signal is the first value, the pull-up resistor provides a first voltage on the first voltage terminal to the control terminal of the first switch based on the first voltage terminal.

4. The test apparatus of claim 1, further comprising: a voltage dividing circuit comprising: a first voltage dividing resistor having two terminals coupled to a second voltage terminal and the control terminal of the second switch, respectively; and a second voltage dividing resistor having two terminals coupled to the control terminal of the second switch and the first terminal of the first switch, respectively, wherein, when the first terminal and the second terminal of the first switch are in conduction with each other, the control terminal of the second switch obtains a divided voltage via the voltage dividing circuit and a second voltage on the second voltage terminal.

5. The test apparatus of claim 4, wherein the first switch comprises: a control transistor having a control terminal coupled to the general purpose input / output pin, and a first terminal coupled to the control terminal of the second switch through the voltage dividing circuit.

6. The test apparatus of claim 1, wherein the second switch comprises: a first transistor having a control terminal coupled to the control terminal of the second switch, and a first terminal coupled to the power button terminal of the host board device; and a second transistor having a control terminal coupled to the control terminal of the second switch, and a first terminal coupled to the first reference voltage terminal of the host board device, wherein a second terminal of the first transistor is coupled to a second terminal of the second transistor.

7. The test apparatus of claim 1, further comprising: an electrostatic discharge protection circuit comprising: a fuse having two terminals coupled to the power button terminal and the first terminal of the second switch, respectively; a first zener diode having a first terminal coupled to the power button terminal; and a second zener diode having a first terminal coupled to the first reference voltage terminal. ​ ​ 8. The testing device of claim 1, wherein the control signal is a pulse signal, a pulse width of the pulse signal is set to N seconds via the microprocessor, N is a positive integer.

9. A testing method of a host board device, wherein the host board device comprises a power button end and a first reference voltage end, the testing method comprising: providing a testing device, wherein a first end of the testing device is coupled to the power button end, and a second end of the testing device is coupled to the first reference voltage end; and controlling on or off between the first end and the second end of the testing device based on a control signal provided by the testing device.

10. The testing method of claim 9, wherein the control signal is a pulse signal, a pulse width of the pulse signal is set to N seconds via the testing device, N is a positive integer. ​

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