Adaptive slt testing method, apparatus, device, and medium

Abstract

The adaptive SLT test method, device, equipment and medium provided by the embodiments of the present disclosure comprise: determining type information of a to-be-tested memory particle according to characteristic information of the to-be-tested memory particle; obtaining a physical address mapping rule of the to-be-tested memory particle under the type information and generating a corresponding address conversion function according to the type information of the to-be-tested memory particle; correcting standard timing parameters of the to-be-tested memory particle to obtain target timing parameters according to a test target of the to-be-tested memory particle; obtaining a specific defect mode test sequence of the to-be-tested memory particle; obtaining temperature information of the to-be-tested memory particle in a test process and determining a target refresh frequency of the to-be-tested memory particle according to a temperature-charge retention characteristic curve model of the to-be-tested memory particle; and testing the to-be-tested memory particle according to an actual address, the target timing parameters, the specific defect mode test sequence and the target refresh frequency to obtain a test result.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory and related technical fields, in particular, to a self-adaptive SLT test method, system, device and medium supporting different types of memory particles. BACKGROUND

[0002] With the development of computing technology, memory (DRAM) as the core component of computer systems, its performance and reliability are crucial to the overall system. DRAM production involves complex processes, and in the process of manufacturing, packaging, and assembling into memory, various defects may occur. These defects may be due to small differences in materials, processes, or design, and are often closely related to the complex physical structure and electrical characteristics inside the DRAM. In order to ensure the quality of the memory, it is necessary to test the memory strictly. At present, memory testing is mainly divided into several stages: wafer test, component test, module test and system level test (SLT). Among them, SLT is a test conducted in a simulated or real system environment, aiming to discover complex defects that only appear under specific system load, including but not limited to intermittent failures caused by power integrity, signal integrity, thermal stress or complex access patterns, which is the final hurdle to ensure memory reliability.

[0003] The existing system level test method usually includes: general standard test and customized test of specific manufacturers, and the traditional general standard test usually cannot fully expose the specific internal defects and failure modes of different DRAM manufacturer particles. Memory particle manufacturers (such as SK Hynix, Samsung, Micron, etc.) will produce unique defect modes (for example, different manufacturers' RowHammer sensitivity, refresh characteristics, power / signal integrity problems, etc.) that only appear under specific stress due to differences in internal architecture, physical layout, addressing method and material process of DRAM. In order to discover these defects, some manufacturers will develop proprietary test methods or adjust parameters. But these methods are usually closed and not public, and often only suitable for their own products, lacking cross-manufacturer universality.

[0004] Based on the problems existing in the prior art, there is an urgent need for a self-adaptive SLT test method supporting different types of memory particles. SUMMARY

[0005] The embodiments described herein provide a self-adaptive SLT test method, device, equipment and medium supporting different types of memory particles, which solves the problems existing in the prior art.

[0006] In a first aspect, according to the disclosure, an adaptive SLT test method supporting different types of memory particles is provided, comprising:

[0007] According to the characteristic information of the to-be-tested memory particle, type information of the to-be-tested memory particle is determined, wherein the characteristic information at least includes manufacturer identification information, DRAM part number information, density information, bit width information and DRAM revision version information;

[0008] According to the type information of the to-be-tested memory particle, a physical address mapping rule of the to-be-tested memory particle under the type information is obtained, and a corresponding address conversion function is generated to convert a virtual address of the to-be-tested memory particle into an actual address through the address conversion function;

[0009] According to a test target of the to-be-tested memory particle, a standard timing parameter of the to-be-tested memory particle is corrected to obtain a target timing parameter;

[0010] A specific defect mode test sequence of the to-be-tested memory particle is obtained;

[0011] Temperature information of the to-be-tested memory particle in a test process is obtained, and according to a temperature-charge retention characteristic curve model of the to-be-tested memory particle, a target refresh frequency of the to-be-tested memory particle is determined;

[0012] According to the actual address, the target timing parameter, the specific defect mode test sequence and the target refresh frequency, the to-be-tested memory particle is tested to obtain a test result.

[0013] In some embodiments of the disclosure, according to the type information of the to-be-tested memory particle, the physical address mapping rule of the to-be-tested memory particle under the type information is obtained, and the corresponding address conversion function is generated to convert the virtual address of the to-be-tested memory particle into the actual address through the address conversion function, comprising:

[0014] According to the type information of the to-be-tested memory particle, a physical address mapping rule corresponding to the type information of the to-be-tested memory particle is obtained from a configuration file library;

[0015] According to the physical address mapping rule corresponding to the type information of the to-be-tested memory particle, an address conversion function is determined;

[0016] According to the address conversion function, a virtual address of the to-be-tested memory particle is converted to obtain an actual address of the to-be-tested memory particle.

[0017] In some embodiments of the present disclosure, the method further comprises:

[0018] In some embodiments of the present disclosure, the method further comprises:

[0019] In some embodiments of the present disclosure, the method further comprises:

[0020] In some embodiments of the present disclosure, the method further comprises:

[0021] In some embodiments of the present disclosure, the method further comprises:

[0022] In some embodiments of the present disclosure, the method further comprises:

[0023] In some embodiments of the present disclosure, the method further comprises:

[0024] In some embodiments of the present disclosure, the method further comprises:

[0025] In some embodiments of the present disclosure, the method further comprises:

[0026] In some embodiments of the present disclosure, the method further comprises:

[0027] In some embodiments of the present disclosure, the method further comprises:

[0028] In some embodiments of the present disclosure, the method further comprises:

[0029] In some embodiments of the present disclosure, the method further comprises:

[0030] According to a preset defect classification rule, the test error information of the to-be-tested memory particle is analyzed to determine an error type, an error address, and an error severity;

[0031] According to the error type, the error address, and the error severity, the to-be-tested memory particle is physically repaired.

[0032] In some embodiments of the present disclosure, before the to-be-tested memory particle is tested according to the actual address, the target timing parameter, the specific defect mode test sequence, and the target refresh frequency to obtain a test result, the method further includes:

[0033] The Bank layout of the to-be-tested memory particle under the type information is obtained, wherein the Bank layout includes a Bank physical layout, a Bank group organization mode, and a difference in a Bank interconnection structure.

[0034] In a second aspect, according to the present disclosure, an adaptive SLT testing device supporting different types of memory particles is provided, including:

[0035] A type information determination module is configured to determine type information of a to-be-tested memory particle according to characteristic information of the to-be-tested memory particle, wherein the characteristic information at least includes manufacturer identification information, DRAM part number information, density information, bit width information, and DRAM revision version information.

[0036] An address conversion function generation module is configured to obtain a physical address mapping rule of the to-be-tested memory particle under the type information according to the type information of the to-be-tested memory particle, and generate a corresponding address conversion function to convert a virtual address of the to-be-tested memory particle into an actual address through the address conversion function.

[0037] A target timing parameter determination module is configured to correct a standard timing parameter of the to-be-tested memory particle to obtain a target timing parameter according to a test target of the to-be-tested memory particle.

[0038] A test sequence generation module is configured to obtain a specific defect mode test sequence of the to-be-tested memory particle.

[0039] A target refresh frequency determination module is configured to obtain temperature information of the to-be-tested memory particle in a test process, and determine a target refresh frequency of the to-be-tested memory particle according to a temperature-charge retention characteristic curve model of the to-be-tested memory particle.

[0040] A test result generation module is configured to test the to-be-tested memory particle according to the actual address, the target timing parameter, the specific defect mode test sequence, and the target refresh frequency to obtain a test result.

[0041] In a third aspect, according to the content of the present disclosure, a computer device is provided, comprising:

[0042] one or more processors;

[0043] a storage device configured to store one or more programs,

[0044] When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of the first aspect.

[0045] In a fourth aspect, according to the content of the present disclosure, a computer readable storage medium is provided, which stores a computer program, and the program is executed by a processor to implement the method according to any one of the first aspect.

[0046] The adaptive SLT test method, device, equipment and medium supporting different types of memory particles provided by the embodiments of the present disclosure first determine the type information of the to-be-tested memory particle according to the characteristic information of the to-be-tested memory particle; then, according to the type information of the to-be-tested memory particle, the physical address mapping rule of the to-be-tested memory particle under the type information is obtained, and the corresponding address conversion function is generated to convert the virtual address of the to-be-tested memory particle into the actual address through the address conversion function; and according to the test target of the to-be-tested memory particle, the standard timing parameter of the to-be-tested memory particle is corrected to obtain the target timing parameter; then, the specific defect mode test sequence of the to-be-tested memory particle is obtained; and the temperature information of the to-be-tested memory particle in the test process is obtained, and according to the temperature-charge retention characteristic curve model of the to-be-tested memory particle, the target refresh frequency of the to-be-tested memory particle is determined; finally, according to the actual address, the target timing parameter, the specific defect mode test sequence and the target refresh frequency, the to-be-tested memory particle is tested to obtain the test result. It is ensured that the test of the to-be-tested memory particle is closer to the working frequency, voltage and temperature conditions of the real system of the to-be-tested memory particle, and the possibility of discovering potential defects is maximized.

[0047] The above description is only a summary of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, the embodiments of the present application can be implemented according to the content of the specification, and in order to make the above and other purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but not limit the present disclosure, wherein:

[0049] Figure 1 is a flowchart of a self-adaptive SLT test method supporting different types of memory particles provided by an embodiment of the present disclosure;

[0050] Figure 2 is a structural diagram of a self-adaptive SLT test device supporting different types of memory particles provided by an embodiment of the present disclosure;

[0051] Figure 3 is a structural diagram of a computer device provided by an embodiment of the present disclosure.

[0052] In the drawings, reference numbers between “-” and “ / ” correspond to elements having the same function. It should be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0053] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort also belong to the scope of protection of the present disclosure.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together will mean that the parts are joined together either directly or through one or more intermediate parts.

[0055] Reference herein to "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily all directed to the same embodiment, or to a single alternative embodiment. It is explicitly contemplated that embodiments described herein can be combined with each other.

[0056] The term "and / or", used in the present document, only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A existing, A and B existing, and B existing. In addition, the character " / " in the present document generally represents an "or" relationship between the front and rear associated objects.

[0057] In addition, in all embodiments of the present disclosure, terms such as "first" and "second" are only used to distinguish one component (or part of a component) from another component (or another part of a component).

[0058] In the description of the present application, unless otherwise specified, "a plurality of" means two or more (including two), and similarly, "a plurality of groups" means two or more groups (including two groups).

[0059] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings.

[0060] Based on the problems existing in the prior art, the present disclosure provides a self-adaptive SLT test method supporting different types of memory particles, Figure 1 is a flowchart of a self-adaptive SLT test method supporting different types of memory particles provided by the present disclosure, as Figure 1 shown, the specific process of the self-adaptive SLT test method supporting different types of memory particles includes:

[0061] S110, according to the characteristic information of the to-be-tested memory particle, determining the type information of the to-be-tested memory particle.

[0062] Among them, the characteristic information at least includes manufacturer identification information, DRAM component number information, density information, bit width information and DRAM revision version information.

[0063] The self-adaptive SLT test method supporting different types of memory particles provided by the present disclosure is applied to a self-adaptive SLT test device supporting different types of memory particles. When the self-adaptive SLT test device starts testing, the SPD (Serial Presence Detect) information of the to-be-tested memory particle is read through the standard JEDEC interface SMBus, and the key byte field is parsed to obtain the characteristic information of the to-be-tested memory particle, such as manufacturer identification information, DRAM component number information, density information, bit width information and DRAM revision version information.

[0064] The type information of the memory particle corresponding to different characteristic information is not the same. After obtaining the characteristic information of the to-be-tested memory particle, the type information of the to-be-tested memory particle can be determined according to the characteristic information of the to-be-tested memory particle.

[0065] In the above embodiments, the characteristic information of the memory chip to be tested is based on the third-party manufacturer.

[0066] S120, according to the type information of the memory chip to be tested, obtaining the physical address mapping rule of the memory chip to be tested under the type information, and generating a corresponding address conversion function to convert the virtual address of the memory chip to be tested into the actual address through the address conversion function.

[0067] After determining the type of the memory chip to be tested, according to the internal physical address mapping rule and the internal bus topology structure provided by the manufacturer, a corresponding address conversion function is generated to convert the virtual address of the memory chip to be tested into the actual address in the adaptive SLT test device, and the memory chip to be tested is tested based on the SLT test device. Through the addressing logic of the adaptive SLT test device, it is ensured that the logical address can fully apply the internal layout of the memory chip to be tested in the physical, and expose the mode sensitive fault.

[0068] In a specific implementation, according to the type information of the memory chip to be tested, the physical address mapping rule of the memory chip to be tested under the type information is obtained, and a corresponding address conversion function is generated to convert the virtual address of the memory chip to be tested into the actual address, including: according to the type information of the memory chip to be tested, obtaining the physical address mapping rule corresponding to the type information of the memory chip to be tested from the configuration file library; according to the physical address mapping rule corresponding to the type information of the memory chip to be tested, determining the address conversion function; according to the address conversion function, the virtual address of the memory chip to be tested is converted to obtain the actual address of the memory chip to be tested.

[0069] Specifically, first, the physical address mapping rule corresponding to the type information of the memory chip to be tested is obtained, for example, the physical address mapping rule (such as: Bank / Row / Column bit distribution, Bank Group interleaving mode) is extracted from the manufacturer datasheet or configuration file library, then according to the physical address mapping rule corresponding to the type information of the memory chip to be tested, the address conversion function is determined, and finally the virtual address of the memory chip to be tested is converted according to the address conversion function to obtain the actual address of the memory chip to be tested, the address conversion function satisfies: PhysicalAddr = f(LogicalAddr), wherein LogicalAddr is the virtual address, PhysicalAddr is the actual address, and f is the address conversion function. The virtual address conversion function realizes the conversion of the memory virtual address to the actual address of the memory in the adaptive SLT test device, which is usually realized by position conversion.

[0070] S130, according to the test target of the to-be-tested memory particle, the standard timing parameter of the to-be-tested memory particle is corrected to obtain a target timing parameter.

[0071] According to the test target of the to-be-tested memory particle, the standard timing parameter (such as write recovery time tWR, refresh interval tREFI, read-to-write delay tRW, write-to-read delay tWRD, etc.) of the to-be-tested memory particle is dynamically adjusted to obtain the target timing parameter of the to-be-tested memory particle. The adjustment of these timing parameters can simulate a more stringent electrical environment, or expose the sensitivity of a specific manufacturer's particle to timing fluctuations, such as insufficient timing margin problems.

[0072] In a specific implementation, according to the test target of the to-be-tested memory particle, the standard timing parameter of the to-be-tested memory particle is corrected to obtain a target timing parameter, including: according to the test target of the to-be-tested memory particle, the standard timing parameter of the to-be-tested memory particle is timing modified to obtain a test timing parameter; obtaining the test result of the to-be-tested memory particle under the test timing parameter; when the test result of the to-be-tested memory particle meets a preset threshold, the test timing parameter is the target timing parameter of the to-be-tested memory particle.

[0073] The to-be-tested memory particle has a standard timing parameter (such as tRCD, tRP, tRAS, tREFI, tRFC, tWR, tWTR, tRTP, etc.). The manufacturer of the to-be-tested memory particle will give more accurate or more challenging timing values according to its specific manufacturing process, materials, circuit design, and internal test results. These values may be more stringent than the standard timing parameters, as they represent the boundaries at which the memory particle can work stably under optimal conditions. This information is usually included in the detailed technical documents or special test guidelines provided by the manufacturer.

[0074] The adjustment of the standard timing parameter of the to-be-tested memory particle is to find the limit of the stable operation of the to-be-tested memory particle and expose potential problems near this limit. One implementation tightens the timing (reduces the margin) or relaxes the timing (increases the margin). Tightening the timing (reducing the margin) is the most common strategy, used to simulate a more stringent electrical environment or to expose the sensitivity of the chip to timing fluctuations. By reducing (making the value smaller) the time interval of, for example, tWR, tRCD, or tRP, or increasing (making the value larger) the refresh frequency of, for example, tREFI, the to-be-tested memory particle can be forced to complete operations in a shorter time, thereby exposing potential signal integrity problems, charge leakage, or crosstalk. Relaxing the timing (increasing the margin) may also be required in some cases to cover a wider operating range or to verify stability under specific conditions.

[0075] Based on the standard timing parameters provided by the vendor, and combined with the test target (for example, "the stability of the memory particle to be tested needs to meet the preset threshold under the condition that tWR is shortened by 10%"), a set of test timing parameters is obtained, and the memory particle to be tested is tested based on the test timing parameters. When the stability test result of the memory particle to be tested meets the preset threshold, the test timing parameter is the target timing parameter of the memory particle to be tested. If the stability test result of the memory particle to be tested does not meet the preset threshold, the standard timing parameters are modified again to obtain another set of test timing parameters, and the test is performed again until the target timing parameter is determined.

[0076] It should be noted that in the above implementation process, the test result of the memory particle to be tested meeting the preset threshold means whether the test stability of the memory particle to be tested meets the preset threshold. If the test stability of the memory particle to be tested does not meet the preset threshold, the test target is changed (for example, "the stability of the memory particle to be tested needs to meet the preset threshold under the condition that tWR is shortened by 8%"), and a set of test timing parameters is obtained again according to the test target, and the memory particle to be tested is tested based on the set of test timing parameters. In this way, the target timing parameter is determined.

[0077] S140, obtaining a specific defect mode test sequence of the memory particle to be tested.

[0078] The special test sequence is designed for known or predicted vendor-specific complex defect modes (such as specific Row Hammer attack modes vulnerable to specific vendors, specific dynamic refresh characteristics, or sensitive write recovery stability). These test sequences may include specific read-write sequences, data backgrounds (such as all 0, all 1, alternating 10, random, etc.), access steps, and cycle times to trigger complex defects such as charge leakage, bit-to-bit or row-to-row crosstalk, and unstable write recovery.

[0079] The specific defect mode test sequence of the memory particle to be tested is obtained based on the vendor's known problem reports, historical test data, market feedback, technical literature, and theoretical analysis based on the memory architecture.

[0080] S150, obtaining temperature information of the memory particle to be tested during the test process, and determining a target refresh frequency of the memory particle to be tested according to a temperature-charge retention characteristic curve model of the memory particle to be tested.

[0081] The temperature information of the memory chip under test is acquired by a temperature sensor, and a temperature-charge retention characteristic curve model is established based on the pre-set data of the charge retention characteristics of DRAM chips at different temperatures from a specific manufacturer, and the target refresh frequency is dynamically calculated, which ensures that the charge retention capability and anti-interference capability of the chip can be accurately and effectively evaluated at different temperatures. This process uses temperature to accelerate or slow down the decay of charge retention capability, thereby efficiently evaluating the refresh requirements of the memory chip under test at different temperatures.

[0082] In a specific implementation, the temperature information of the memory chip under test during the test is acquired, and the target refresh frequency of the memory chip under test is determined according to the temperature-charge retention characteristic curve model of the memory chip under test, including: acquiring the temperature information of the memory chip under test during the test; determining the maximum refresh interval required for the memory chip under test to maintain the charge according to the temperature-charge retention characteristic curve model of the memory chip under test; and determining the target refresh frequency of the memory chip under test according to the maximum refresh interval required for the memory chip under test to maintain the charge.

[0083] Specifically, one implementation of determining the target refresh frequency of the memory chip under test is to adjust the refresh pause time of the memory chip under test. The refresh pause time of the memory chip under test can be determined based on the maximum refresh interval required for the memory chip under test to maintain the charge. If the "maximum allowed charge retention time" corresponding to the current temperature information of the memory chip under test is T_retention_max, and the normal refresh interval of the memory chip under test is T_refresh_normal, if T_refresh_normal is greater than T_retention_max (meaning that the charge retention capability of the memory chip under test is insufficient to support the normal refresh interval at the current temperature), the refresh pause time needs to be shortened to avoid data loss during the pause period; if T_refresh_normal is less than T_retention_max, the refresh pause time can be appropriately extended to increase the severity of the test and further verify the charge retention capability.

[0084] Another implementation to determine the target refresh frequency of the memory under test is to adjust the perturbation count in the dynamic refresh test. A perturbation (e.g. a read operation) in the dynamic refresh test consumes a certain amount of charge. If T_refresh_normal is close to T_retention_max, then the more perturbations inserted, the more charge leakage accumulated. By calculating a maximum allowed perturbation count N_perturb_max. This count is related to T_retention_max and T_refresh_normal and the amount of charge consumed by each perturbation. For example, if T_retention_max = 64ms, T_refresh_normal = 32ms (DRAM needs to be refreshed every 32ms). Then the total "charge margin" is about 32ms. If each perturbation consumes an amount of charge equivalent to 0.5ms of leakage, then 32ms / 0.5ms = 64 perturbations can be inserted. To increase the severity, one can design to reduce the allowed perturbation count when T_retention_max is close to T_refresh_normal, or increase the perturbation count when T_retention_max is much larger than T_refresh_normal.

[0085] That is, the real-time temperature information of the memory under test is taken as input, and the accurate modeling of the temperature-charge retention characteristic curve by the manufacturer is combined to dynamically calculate the refresh capability limit of the memory under test at the current temperature. Then, according to the limit, the target refresh frequency of the memory under test is obtained to ensure that the test can fully apply the charge retention capability of the target refresh frequency and find potential refresh-related faults within a reasonable test time.

[0086] S160, test the memory under test according to the actual address, the target timing parameter, the specific defect mode test sequence and the target refresh frequency, and obtain a test result.

[0087] All customized parameters based on the test result output are configured into the CPGC or other hardware test engine of the SLT platform, including: loading the actual address of the memory under test, setting the accurate target timing parameter, configuring the specific defect mode test sequence, and the target refresh frequency, and converting these strategies into a hardware executable CPGC instruction set or configuration register value to realize accurate control of the test of the memory under test.

[0088] Wherein, on the SLT platform, the DRAM particles are read and written and data is checked according to the highly customized test sequence by using the configured CPGC, and the test process can include but is not limited to: 1, static refresh test (including temperature self-adaptive adjustment); 2, dynamic refresh test (including specific intrusion mode, such as Row Hammer); 3, write recovery test (including tWR dynamic adjustment); 4, mode sensitive test (including customized address confusion); 5, power integrity test and signal integrity test; 6, stress test, such as edge voltage test, high temperature and high pressure test, etc. Ensure that the test of the to-be-tested memory particles is closer to the working frequency, voltage and temperature conditions of the real system of the to-be-tested memory particles, and the possibility of discovering potential defects is maximized.

[0089] It should be noted that in the above implementation process, after the corresponding address conversion function is generated, the address conversion function is written into the address remapping register of the CPGC (Controller Pattern Generator / Checker) in the adaptive SLT test device, after the target timing parameter and the target refresh frequency are obtained, the timing parameter and the refresh frequency of the CPGC are adjusted to the target timing parameter and the target refresh frequency, and finally the CPGC runs the specific defect mode test sequence to obtain the corresponding test result.

[0090] The adaptive SLT test method supporting different types of memory particles provided by the embodiments of the present disclosure first determines the type information of the to-be-tested memory particles according to the characteristic information of the to-be-tested memory particles; then acquires the physical address mapping rule of the to-be-tested memory particles under the type information according to the type information of the to-be-tested memory particles, and generates a corresponding address conversion function to convert the virtual address of the to-be-tested memory particles into an actual address through the address conversion function; and modifies the standard timing parameter of the to-be-tested memory particles to obtain a target timing parameter according to the test target of the to-be-tested memory particles; further acquires a specific defect mode test sequence of the to-be-tested memory particles; and acquires temperature information of the to-be-tested memory particles in the test process, and determines a target refresh frequency of the to-be-tested memory particles according to a temperature-charge retention characteristic curve model of the to-be-tested memory particles; finally, tests the to-be-tested memory particles according to the actual address, the target timing parameter, the specific defect mode test sequence and the target refresh frequency, and obtains a test result. Ensure that the test of the to-be-tested memory particles is closer to the working frequency, voltage and temperature conditions of the real system of the to-be-tested memory particles, and the possibility of discovering potential defects is maximized.

[0091] After the test result of the to-be-tested memory particle is obtained, the method further comprises: analyzing the test result of the to-be-tested memory particle according to the test result of the to-be-tested memory particle to obtain test error information of the to-be-tested memory particle; analyzing the test error information of the to-be-tested memory particle according to a preset defect classification rule to determine an error type, an error address and an error severity; and performing physical repair on the to-be-tested memory particle according to the error type, the error address and the error severity.

[0092] Real-time collection and analysis of test error information, identification of error type, error address and error severity according to a preset defect classification rule, identification of the physical location of the fault according to the error address if a repairable error is found (such as repair by redundant row / column), and triggering or guiding the PPR mechanism according to a preset repair rule (such as the availability of redundant row / column, error density threshold) to perform physical repair on the to-be-tested memory particle, improve the final yield, and realize an efficient defect repair process.

[0093] In addition, on the basis of the above-mentioned embodiments, as a preferred implementation manner, before step S160 is performed, the method further comprises: obtaining a Bank layout of the to-be-tested memory particle under the type information, wherein the Bank layout comprises a Bank physical layout, a Bank group organization manner and an inter-Bank interconnection structure.

[0094] At this time, the implementation manner of step S160 is to test the to-be-tested memory particle according to the actual address, the target timing parameter, the specific defect mode test sequence and the target refresh frequency, and the implementation process of obtaining the test result is: testing the to-be-tested memory particle according to the actual address, the target timing parameter, the specific defect mode test sequence, the target refresh frequency and the Bank layout to obtain the test result.

[0095] In this process, the Bank L2P mapping register of the CPGC is configured according to the differences between the Bank physical layout, the Bank group organization manner and the inter-Bank interconnection structure, and the core of this process is to map the “logical Bank” and “logical Bank Group” seen by the CPGC to the “physical Bank” and “physical Bank Group” actually existing inside the to-be-tested memory particle, and to consider the connection relationship therebetween.

[0096] Specifically, the DRAM structure is parsed: 16 physical Banks, 4 physical BGs, the physical Bank address bit is 4 bits, and Bit2, 3 are used for BG.

[0097] The CPGC perspective is determined: 2 logical BGs, 8 logical Banks.

[0098] The L2P mapping rule is generated:

[0099] Bank Group mapping, one possible implementation is LBG0 -> BG0 & BG1 aggregation, LBG1 -> BG2 & BG3 aggregation, when CPGC sends LBG0 (logical Bank Group 0), CPGC's L2P register needs to know that this corresponds to DRAM's physical BG0 and BG1. When CPGC sends LBG1 (logical Bank Group 1), CPGC's L2P register needs to know that this corresponds to DRAM's physical BG2 and BG3.

[0100] Bank mapping, for LBG0 (mapped to BG0, BG1), one possible implementation is that LBG0's first Bank (LB0) maps to BG0's first Bank (PB0), LBG0's second Bank (LB1) maps to BG0's second Bank (PB1)... LBG0's fifth Bank (LB4) maps to BG1's first Bank (PB4).

[0101] Thus, LB0 (logical address 0000) -> PB0 (physical address 0000), LB1 (logical address 0001) -> PB1 (physical address 0001),..., LB4 (logical address 0100) -> PB4 (physical address 0100).

[0102] For LBG1 (mapped to BG2, BG3), similar mapping is done.

[0103] L2P register configuration: CPGC's L2P register is programmed so that when it receives an address of logical Bank Group X and logical Bank Y, it can output the actual physical Bank Group and physical Bank address that DRAM needs according to the pre-set mapping rule. For example, one L2P register can store a lookup table, the input is (logical Bank Group, logical Bank), and the output is (physical Bank Group, physical Bank).

[0104] With this precise configuration, CPGC can perform targeted testing on the memory particles under test in the manner of the physical Bank topology expected by the DRAM designer, so as to find deeper faults related to the Bank structure and interconnection.

[0105] In addition, in the implementation process described above, for a memory particle to be tested of a non-JEDEC standard capacity (such as 24 Gb), according to the characteristics of the internal non-traditional Bank organization or storage cell array layout, the number of test cycles or addressing logic is automatically adjusted to ensure the comprehensiveness of the test and avoid the test blind area caused by the capacity difference.

[0106] JEDEC standards usually have a clear number of Banks (for example, 8 or 16 Banks) and a number of Bank Groups. Non-standard capacity may use more Banks (for example, 32 Banks) or more complex Bank Group division, and may even contain a special "super Bank" concept. The memory particle to be tested of non-standard capacity will affect how the address bits are mapped to the Bank and the parallel access rules between Banks.

[0107] The memory particle to be tested of non-traditional storage cell array layout may be different from the standard particle. It will affect the number and mapping of column addresses (Column Address) and row addresses (Row Address).

[0108] For example, if a standard 16 Gb DRAM has 16 Banks (4-bit Bank address), a 24 Gb DRAM may expand to 32 Banks (5-bit Bank address), therefore, the difference needs to be identified, and the extra bit of the logical address is allocated to the Bank address.

[0109] Bank Group mapping: According to the Bank Group rules of the manufacturer (for example, which Banks belong to the same Group), adjust the mapping of the Bank address to the physical Bank Group.

[0110] Row / Column address mapping: If the storage cell array layout changes (for example, the number of storage cells per row changes), the bit allocation of the row address and the column address needs to be adjusted, as well as their mapping to the physical Row / Column.

[0111] Generate / select address conversion functions: Based on these new address bit allocation rules, dynamically generate or select a new set of address conversion functions for the CPGC to convert the logical address to the physical address.

[0112] On the basis of the above-mentioned embodiments, the embodiments of the present disclosure further provide a self-adaptive SLT test device supporting different types of memory particles, Figure 2 is a structural schematic diagram of a self-adaptive SLT test device supporting different types of memory particles provided by the embodiments of the present disclosure, as Figure 2 shown, the self-adaptive SLT test device supporting different types of memory particles comprises:

[0113] The type information determination module 210 is configured to determine type information of the memory particle to be tested according to characteristic information of the memory particle to be tested, wherein the characteristic information at least includes manufacturer identification information, DRAM part number information, density information, bit width information, and DRAM revision version information.

[0114] The address conversion function generation module 220 is configured to obtain a physical address mapping rule of the memory particle to be tested under the type information according to the type information of the memory particle to be tested, and generate a corresponding address conversion function to convert a virtual address of the memory particle to be tested into an actual address through the address conversion function.

[0115] The target timing parameter determination module 230 is configured to correct a standard timing parameter of the memory particle to be tested to obtain a target timing parameter according to a test target of the memory particle to be tested.

[0116] The test sequence generation module 240 is configured to obtain a specific defect mode test sequence of the memory particle to be tested.

[0117] The target refresh frequency determination module 250 is configured to obtain temperature information of the memory particle to be tested in a test process, and determine a target refresh frequency of the memory particle to be tested according to a temperature-charge retention characteristic curve model of the memory particle to be tested.

[0118] The test result generation module 260 is configured to test the memory particle to be tested according to the actual address, the target timing parameter, the specific defect mode test sequence, and the target refresh frequency to obtain a test result.

[0119] The self-adaptive SLT test device supporting different types of memory particles provided by the embodiments of the present disclosure first determines type information of the memory particle to be tested according to characteristic information of the memory particle to be tested, then obtains a physical address mapping rule of the memory particle to be tested under the type information according to the type information of the memory particle to be tested, and generates a corresponding address conversion function to convert a virtual address of the memory particle to be tested into an actual address through the address conversion function, and corrects a standard timing parameter of the memory particle to be tested to obtain a target timing parameter according to a test target of the memory particle to be tested, further obtains a specific defect mode test sequence of the memory particle to be tested, and obtains temperature information of the memory particle to be tested in a test process, and determines a target refresh frequency of the memory particle to be tested according to a temperature-charge retention characteristic curve model of the memory particle to be tested, and finally tests the memory particle to be tested according to the actual address, the target timing parameter, the specific defect mode test sequence, and the target refresh frequency to obtain a test result. The test of the memory particle to be tested is closer to the working frequency, voltage, and temperature conditions of the real system of the memory particle to be tested, and the possibility of discovering potential defects is maximized.

[0120] In specific embodiments, the obtaining, according to the type information of the memory particle to be tested, a physical address mapping rule of the memory particle to be tested under the type information, and generating a corresponding address conversion function to convert a virtual address of the memory particle to be tested into an actual address through the address conversion function, comprises:

[0121] According to the type information of the memory particle to be tested, obtaining a physical address mapping rule corresponding to the type information of the memory particle to be tested from a configuration file library;

[0122] According to the physical address mapping rule corresponding to the type information of the memory particle to be tested, determining an address conversion function;

[0123] Converting a virtual address of the memory particle to be tested according to the address conversion function to obtain an actual address of the memory particle to be tested.

[0124] In specific embodiments, the correcting a standard timing parameter of the memory particle to be tested according to the test target of the memory particle to be tested to obtain a target timing parameter, comprises:

[0125] According to the test target of the memory particle to be tested, performing timing modification on the standard timing parameter of the memory particle to be tested to obtain a test timing parameter;

[0126] Obtaining a test result of the memory particle to be tested under the test timing parameter;

[0127] When the test result of the memory particle to be tested meets a preset threshold, the test timing parameter is the target timing parameter of the memory particle to be tested.

[0128] In specific embodiments, the obtaining temperature information of the memory particle to be tested during the test process, and determining a target refresh frequency of the memory particle to be tested according to a temperature-charge retention characteristic curve model of the memory particle to be tested, comprises:

[0129] Obtaining temperature information of the memory particle to be tested during the test process;

[0130] According to a temperature-charge retention characteristic curve model of the memory particle to be tested, determining a maximum refresh interval required by the memory particle to be tested to maintain charge;

[0131] According to the maximum refresh interval required by the memory particle to be tested to maintain charge, determining a target refresh frequency of the memory particle to be tested.

[0132] In specific embodiments, the testing the memory chip to be tested according to the actual address, the target timing parameter, the specific defect mode test sequence and the target refresh frequency to obtain a test result comprises:

[0133] performing static refresh test, dynamic refresh test, write recovery test, mode sensitive test, power integrity test and signal integrity test and stress test on the memory chip to be tested according to the actual address, the target timing parameter, the specific defect mode test sequence and the target refresh frequency.

[0134] obtaining the test result of the memory chip to be tested under different test modes.

[0135] In specific embodiments, the method further comprises:

[0136] analyzing the test result of the memory chip to be tested according to the test result of the memory chip to be tested to obtain test error information of the memory chip to be tested;

[0137] analyzing the test error information of the memory chip to be tested according to a preset defect classification rule to determine error type, error address and error severity;

[0138] performing physical repair on the memory chip to be tested according to the error type, the error address and the error severity.

[0139] In specific embodiments, before the testing the memory chip to be tested according to the actual address, the target timing parameter, the specific defect mode test sequence and the target refresh frequency to obtain a test result, the method further comprises:

[0140] obtaining the Bank layout of the memory chip to be tested under the type information, wherein the Bank layout comprises Bank physical layout, Bank group organization mode and difference of Bank interconnection structure.

[0141] The present application also provides a computer device, please refer to Figure 3 , Figure 3 for the basic structure block diagram of the computer device of the present application.

[0142] The computer device includes a memory 510 and a processor 520 which are communicatively connected through a system bus. It is noted that only the computer device with components 510-520 is shown in the figure, but it is understood that not all of the shown components are required to be implemented, and more or less components can be alternatively implemented. Among them, those skilled in the art can understand that the computer device herein is a device capable of automatically performing numerical calculation and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), embedded devices, etc.

[0143] The computer device can be a desktop computer, a notebook computer, a palm computer, a cloud server and the like. The computer device can interact with the user through a keyboard, a mouse, a remote controller, a touchpad or a voice control device and the like.

[0144] The memory 510 includes at least one type of readable storage medium, including non-volatile memory or volatile memory, for example, flash memory, a hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory, etc.), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disk, etc. The RAM can include static RAM or dynamic RAM. In some embodiments, the memory 510 can be an internal storage unit of the computer device, for example, a hard disk or a memory of the computer device. In other embodiments, the memory 510 can also be an external storage device of the computer device, for example, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, or a flash card, etc. equipped on the computer device. Of course, the memory 510 can include both an internal storage unit and an external storage device of the computer device. In this embodiment, the memory 510 is generally used to store an operating system and various application software installed on the computer device, for example, program codes of the above-described method, etc. In addition, the memory 510 can also be used to temporarily store various data that has been output or will be output.

[0145] The processor 520 is generally used to perform the overall operation of the computer device. In this embodiment, the memory 510 is used to store program codes or instructions, including computer operation instructions, and the processor 520 is used to execute the program codes or instructions stored in the memory 510 or process data, for example, run the program codes of the above-described method.

[0146] In this article, the bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus system can be divided into address bus, data bus, control bus, etc. For the convenience of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0147] Another embodiment of the present application also provides a computer readable medium, which can be a computer readable signal medium or a computer readable medium. The processor in the computer reads the computer readable program code stored in the computer readable medium, so that the processor can perform the function actions specified in each step or combination of steps in the above method; generate the device implementing the function actions specified in each block or combination of blocks in the block diagram.

[0148] The computer readable medium includes but is not limited to electronic, magnetic, optical, electromagnetic, infrared, semiconductor system, device or apparatus, or any appropriate combination of the foregoing, for storing program code or instructions, which include computer operation instructions, and processor for executing the program code or instructions of the above method stored in the memory.

[0149] The definition of the memory and the processor can refer to the description of the foregoing computer device embodiment, which will not be repeated here.

[0150] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiment described above is only schematic, for example, the division of modules or units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be through some interface, indirect coupling or communication connection between the devices or units, which can be electrical, mechanical or other forms.

[0151] The function units or modules in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of software function unit.

[0152] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the embodiments of the method of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0153] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular form "a," "an," and "the" include plural references unless the context clearly dictates otherwise. Accordingly, the use of "a" or "an" herein and in the following claims is intended to be interpreted to include the plural, unless the context clearly indicates otherwise. Similarly, the words "comprise," "comprises," and "comprising" are to be interpreted inclusively rather than exclusively. Likewise, the terms "include," "including," and "or" should be construed as inclusive, unless otherwise indicated herein. Where the term "example" is used occurring in this document, particularly with respect to a term or phrase, the "example" is merely an example and is not to be construed as exclusive or exhaustive.

[0154] Further aspects and scope of adaptation become apparent from the description provided herein. It should be appreciated that individual aspects of the present application can be implemented alone or in combination with one or more other aspects. It should also be appreciated that the description and specific examples herein are intended to be for illustrative purposes only and are not intended to limit the scope of the present application.

[0155] The above has been described in detail for several embodiments of the present disclosure, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. An adaptive SLT testing method supporting different types of memory chips, characterized in that, include: Based on the characteristic information of the memory chip to be tested, the type information of the memory chip to be tested is determined, wherein the characteristic information includes at least manufacturer identification information, DRAM part number information, density information, bit width information and DRAM revision information; Based on the type information of the memory chip to be tested, obtain the physical address mapping rule of the memory chip to be tested under the type information, and generate the corresponding address translation function to convert the virtual address of the memory chip to be tested into the actual address through the address translation function; Based on the test target of the memory chip under test, the standard timing parameters of the memory chip under test are corrected to obtain the target timing parameters; Obtain a specific defect pattern test sequence for the memory chip under test; The temperature information of the memory chip under test during the test is obtained, and the target refresh frequency of the memory chip under test is determined according to the temperature-charge retention characteristic curve model of the memory chip under test. The memory chip under test is tested based on the actual address, the target timing parameters, the specific defect mode test sequence, and the target refresh frequency to obtain test results. The step of acquiring the temperature information of the memory chip under test during the test process, and determining the target refresh frequency of the memory chip under test based on the temperature-charge retention characteristic curve model of the memory chip under test, includes: Obtain the temperature information of the memory chip under test during the test process; Based on the temperature-charge retention characteristic curve model of the memory chip under test, determine the maximum refresh interval required for the memory chip under test to maintain its charge; The target refresh frequency of the memory chip under test is determined based on the maximum refresh interval required for the memory chip under test to maintain its charge.

2. The method according to claim 1, characterized in that, The step of obtaining the physical address mapping rule of the memory chip under the type information based on the type information of the memory chip to be tested, and generating the corresponding address translation function to convert the virtual address of the memory chip to be tested into the actual address through the address translation function includes: Based on the type information of the memory chip to be tested, obtain the physical address mapping rules corresponding to the type information of the memory chip to be tested from the configuration file library; Determine the address translation function based on the physical address mapping rules corresponding to the type information of the memory chip to be tested; The virtual address of the memory chip under test is converted using the address translation function to obtain the actual address of the memory chip under test.

3. The method according to claim 1, characterized in that, The step of correcting the standard timing parameters of the memory chip under test to obtain the target timing parameters based on the test target of the memory chip under test includes: Based on the test objectives of the memory chip under test, the standard timing parameters of the memory chip under test are modified to obtain the test timing parameters; Obtain the test results of the memory chip under test under the test timing parameters; When the test results of the memory chip under test meet the preset threshold, the test timing parameters are the target timing parameters of the memory chip under test.

4. The method according to claim 1, characterized in that, The test involves evaluating the memory chip under test based on the actual address, the target timing parameters, the specific defect mode test sequence, and the target refresh frequency, to obtain test results, including: Based on the actual address, the target timing parameters, the specific defect mode test sequence, and the target refresh frequency, the memory chip under test is subjected to static refresh test, dynamic refresh test, write recovery test, mode-sensitive test, power integrity test, signal integrity test, and stress test. Obtain the test results of the memory chip under test in different test modes.

5. The method according to claim 1, characterized in that, The method further includes: Based on the test results of the memory chip under test, the test results of the memory chip under test are analyzed to obtain the test error information of the memory chip under test; According to the preset defect classification rules, the test error information of the memory chip under test is analyzed to determine the error type, error address and error severity; Based on the error type, error address, and error severity, physical repairs are performed on the memory chips under test.

6. The method according to claim 1, characterized in that, Before obtaining the test results by testing the memory chip under test based on the actual address, the target timing parameters, the specific defect mode test sequence, and the target refresh frequency, the method further includes: Obtain the Bank layout of the memory chip to be tested under the aforementioned type information, wherein the Bank layout includes differences in Bank physical layout, Bank group organization method, and inter-Bank interconnection structure.

7. An adaptive SLT testing device supporting different types of memory chips, characterized in that, include: The type information determination module is used to determine the type information of the memory chip to be tested based on the characteristic information of the memory chip to be tested. The characteristic information includes at least manufacturer identification information, DRAM part number information, density information, bit width information and DRAM revision information. The address translation function generation module is used to obtain the physical address mapping rules of the memory chip under the type information according to the type information of the memory chip to be tested, and generate the corresponding address translation function so as to convert the virtual address of the memory chip to be tested into the actual address through the address translation function; The target timing parameter determination module is used to correct the standard timing parameters of the memory chip under test according to the test target of the memory chip under test to obtain the target timing parameters. The test sequence generation module is used to obtain a specific defect pattern test sequence of the memory chip to be tested; The target refresh rate determination module is used to acquire the temperature information of the memory chip under test during the test process, and determine the target refresh rate of the memory chip under test according to the temperature-charge retention characteristic curve model of the memory chip under test. The test result generation module is used to test the memory chip under test based on the actual address, the target timing parameters, the specific defect mode test sequence, and the target refresh frequency, and obtain the test results. The step of acquiring the temperature information of the memory chip under test during the test process, and determining the target refresh frequency of the memory chip under test based on the temperature-charge retention characteristic curve model of the memory chip under test, includes: Obtain the temperature information of the memory chip under test during the test process; Based on the temperature-charge retention characteristic curve model of the memory chip under test, determine the maximum refresh interval required for the memory chip under test to maintain its charge; The target refresh frequency of the memory chip under test is determined based on the maximum refresh interval required for the memory chip under test to maintain its charge.

8. A computer device, characterized in that, include: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1 to 6.

Images