A test case dynamic priority scheduling method for automotive electronic chips

Abstract

The present application relates to the field of task queue scheduling of automobile chips, and particularly to a test case dynamic priority scheduling method for automobile electronic chips. The method comprises the following steps: analyzing standard test data of automobile electronic chips, organizing structured data sets associated with physical layout of the chips; applying a data clustering algorithm to identify failure clusters and noise points on the structured data sets; extracting geometric and positional features of the failure clusters, using a classifier to classify them into known failure modes, correlating the failure modes with upstream key process steps and device logs for correlation analysis to establish causal relationships; calculating a functional safety risk score for each chip; when the functional safety risk score is higher than a preset risk threshold, generating and executing dynamic task rearrangement instructions to dynamically improve the execution priority of the test cases. The present application dynamically selects priority according to the functional safety risk score through dynamic task rearrangement instructions, which not only saves test time, but also improves the coverage depth and quality of the test.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip test scheduling management, and particularly to a test case dynamic priority scheduling method for automotive electronic chips. BACKGROUND

[0002] In the production test of modern automotive electronic chips, in order to ensure that the product meets the stringent quality and functional safety standards, a large test set containing tens of thousands of test cases must be executed. However, there is a contradiction between ensuring test coverage and maximizing production throughput, and the cost of completely executing all test cases is too high. To solve this problem, the industry generally uses test case priority sorting (TCP) technology, the core idea of which is to optimize the execution order of test cases to discover critical defects as soon as possible within a limited time, thereby maximizing fault detection rate.

[0003] Although test case priority sorting (TCP) aims to improve test efficiency, the current commonly used technical methods have several inherent and universal defects, especially when dealing with large-scale and highly dynamic production environments, many existing TCP technologies are inefficient. When the test suite is large and contains a large number of test cases with the same initial priority, these technologies are difficult to effectively sort, often leading to improper scheduling and cost overruns. Moreover, the sorting algorithm is often rigid and may ignore actual weight factors or use inefficient weight algorithms. This "one-size-fits-all" model cannot adapt to dynamic changes in the production process, and its sorting basis is usually historical data or preset assumptions, which may no longer be applicable to the specific wafer batch currently being processed. Or generating a fixed execution sequence at one time before test execution may not be able to respond to sudden trends that occur in the production process.

[0004] In summary, there is a need for a method that can receive and analyze inputs from a manufacturing data system and map these inputs as dynamic adjustment factors for test case priority, thereby generating an adaptive and optimized test execution sequence for each batch of chips to be tested.

[0005] To this end, a test case dynamic priority scheduling method for automotive electronic chips is proposed. SUMMARY

[0006] The present application aims to provide a test case dynamic priority scheduling method for automotive electronic chips to solve the problems raised in the background art.

[0007] To achieve the above-mentioned purpose, the present application provides the following technical solution: a test case dynamic priority scheduling method for automotive electronic chips, comprising:

[0008] Collect and parse standard test data of automotive electronic chips; extract structured data sets including wafer ID, physical coordinates of each chip and software bin number; apply data clustering algorithm to identify aggregated failure clusters;

[0009] Extract geometric and positional features of the failure clusters, and use a classifier to classify them into known failure modes; query the manufacturing execution system and equipment automation system through the wafer ID to associate the failure modes with process steps and equipment logs, and match them with the failure root cause knowledge base to establish causal relationships; analyze historical test results, calculate the frequency of failure modes, and perform statistical significance test with the failure rate of the production line baseline to obtain a diagnostic confidence score, and store the diagnostic confidence score and causal relationships in the failure root cause knowledge base;

[0010] For each chip, calculate the Euclidean distance between the physical coordinates and the centroid of all failure clusters; combine the severity weight of the failure mode associated with the failure cluster and the spatial influence factor obtained by principal component analysis of the physical coordinates of the chips in the failure cluster to quantify the risk coverage range of the failure cluster; and obtain a functional safety risk score by combining a weighted summation function with Gaussian attenuation.

[0011] Compare the functional safety risk score with a preset risk threshold, when the functional safety risk score is higher than the risk threshold, analyze the composition of the functional safety risk score, identify the most dangerous failure cluster that contributes most to the risk, generate and execute dynamic task rearrangement instructions, dynamically improve the execution priority of the most sensitive test cases of the associated failure mode, and perform testing; when a defect is detected, terminate all subsequent testing of the chip and classify it into a high-risk isolated batch.

[0012] Preferably, the specific generation process of the structured data set comprises:

[0013] Collect and parse standard test data of automotive electronic chips, extract wafer ID, physical coordinates of chips on the wafer and software bin number, and form key data tuples; according to the preset mapping rule, perform data conversion on the software bin number, map the test results to binary data labels; create a two-dimensional matrix according to the physical size of the wafer; traverse all chip data of the wafer, fill the binary data label of each chip into the position corresponding to the physical coordinates in the matrix, and form a structured data set.

[0014] Preferably, the specific process of identifying the aggregated failure clusters and isolated noise points on the structured data set comprises:

[0015] The density-based unsupervised clustering algorithm is selected, the neighborhood radius and the minimum number of points are set according to the physical size of the chip and the process experience, and the physical coordinates of all failed chips in the structured data set are taken as the input point set; each failed chip is traversed, and according to the density of the failed chips in the neighborhood radius, it is divided into three categories: core point: the number of contained failed chips is not less than the preset minimum point number; boundary point: the number of contained failed chips is less than the minimum point number, but within the neighborhood radius of the core point; noise point: neither core point nor boundary point; starting from the core point that has not been visited, a new failed cluster is created, and all connectable core points and their associated boundary points are assigned to the same failed cluster through recursion.

[0016] Preferably, the specific process of using the classifier to classify into known failure modes includes:

[0017] A set of geometric and positional features is calculated and extracted from the failed cluster; the geometric and positional features are taken as the input of the pre-trained classifier, and the classifier outputs the failure mode label from the predefined car chip label library; the geometric and positional features include cluster size, cluster density, centroid coordinates, relative position and elongation obtained by principal component analysis.

[0018] Preferably, the specific generation process of establishing causal relationship includes:

[0019] When the failed cluster is assigned a failure mode label, a concurrent query is initiated to the manufacturing execution system and the equipment automation system through the wafer ID; the full life cycle manufacturing data associated with the wafer ID is retrieved from the manufacturing execution system database; the process parameter log in the time window of processing the wafer is called according to the full life cycle manufacturing data in the equipment automation system database; the process parameter log is compared with the preset control limit to detect the existence of specification deviation, and when the process parameter abnormality is detected, it is matched with the preset failure root cause knowledge base; the causal relationship established with the process step and the equipment log is stored in the database, and the failure root cause knowledge base is dynamically updated through the judgment of process experts.

[0020] Preferably, the specific generation process of the functional safety risk score includes:

[0021] The centroid coordinates of all failure clusters are obtained by traversing each chip on the wafer, and the Euclidean distance between the physical coordinates of any chip and the centroid coordinates of each failure cluster is calculated.

[0022] Preferably, the specific process of dynamically promoting the execution priority of the test case most sensitive to the associated failure mode includes:

[0023] The functional safety risk score is queried from the database using the chip identifier as the database query key, and is compared with the preset risk threshold. If the functional safety risk score is higher than the risk threshold, the chip is determined to be high-risk, and a dynamic task rearrangement instruction is generated and executed to dynamically promote the execution priority of the test case most sensitive to the associated failure mode. The data structure of the original task queue is reordered to generate a new task queue, and the test case with high priority is placed at the front end of the task queue. When a defect is detected, all subsequent tests on the chip are immediately terminated and are classified into a high-risk isolation batch.

[0024] Preferably, the specific process of generating and executing the dynamic task rearrangement instruction includes:

[0025] When the chip is determined to be high-risk, the composition of the functional safety risk score is analyzed, the dangerous failure cluster with the greatest risk contribution is identified, and the failure mode label associated with the dangerous failure cluster is retrieved. Through the preset database storing the mapping relationship between the test case and the failure mode, the test case with high detection sensitivity to the failure mode label is screened out, and the execution priority of the test case is dynamically promoted to the highest.

[0026] Compared with the prior art, the present application has the following advantages:

[0027] 1. After identifying the failure clusters on the structured dataset using density-based unsupervised clustering algorithm, further analysis of the failure modes and their associated upstream critical process steps and equipment logs by querying the manufacturing execution system and equipment automation system through wafer ID, provides precise clues for process engineers to quickly locate the problematic equipment or process steps, shortens the time from problem discovery to problem resolution, effectively contains the spread of systemic defects, and improves overall production line yield from the source. When more data confirms or refutes the causal relationship, the confidence score will be dynamically updated. This confidence score provides engineers with an intuitive judgment of diagnostic reliability, making the entire risk assessment system more data-driven and intelligent.

[0028] 2. By calculating the Euclidean distance between each chip in the wafer and all failure cluster centroids, combining root cause severity, and performing principal component analysis on the physical coordinates of all chips within the failure cluster to determine a spatial impact factor, and then combining a weighted sum function with Gaussian decay to obtain a functional safety risk score, chips that have passed CP testing but are likely to carry potential defects due to their presence in high-risk physical proximity areas can be identified, helping to prevent flawed chips from entering the final product, thereby greatly improving product safety and reliability. Risk assessment incorporates analysis of failure root cause severity, enabling identification of chips that have passed preliminary testing but are likely to carry potential defects due to their presence in high-risk manufacturing environments, playing a crucial role in meeting zero-defect requirements in automotive electronics and other fields.

[0029] 3. When a chip with a functional safety risk score higher than the risk threshold enters the FT testing station, trace the failure cluster and its associated failure mode that is the main source of risk, and query the preconfigured failure mode and test case mapping database to dynamically improve the execution priority of the most sensitive test cases for the associated failure mode. This means that the testing process is transformed from a fixed test sequence to a queue with dynamically adjustable priority. This testing strategy improves the probability of detecting critical defects early in the testing process, allowing the test to terminate immediately upon detecting a failure, thereby saving a significant amount of testing time for high-risk chips, and ensuring that the most effective stress testing for potential defects is performed first, thereby improving the depth and quality of testing, effectively preventing chips carrying potential defects from entering the market, and ensuring the reliability of the final product. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A flowchart of a test case dynamic priority scheduling method for automotive electronic chips according to an embodiment of the present application;

[0031] Figure 2A schematic diagram of a structured data set proposed for the embodiments of the present application;

[0032] Figure 3 A functional safety risk score distribution thermodynamic diagram proposed for the embodiments of the present application;

[0033] Figure 4 A flowchart of an optimized test task queue proposed for the embodiments of the present application. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0035] Please refer to Figures 1-4 The present application provides a test case dynamic priority scheduling method for automotive electronic chips, and the specific steps are as follows:

[0036] Collect and analyze the standard test data of the automotive electronic chips; extract a structured data set including wafer ID, physical coordinates of each chip and software bin number; apply a data clustering algorithm to identify the aggregated failure clusters;

[0037] Extract geometric and positional features from the failure clusters, and use a classifier to classify them into known failure modes; query the manufacturing execution system and the equipment automation system through the wafer ID, associate the failure modes with process steps and equipment logs, and match them with the failure root cause knowledge base to establish causal relationships; analyze the historical test results, calculate the frequency of the failure modes, perform statistical significance test with the failure rate of the production line baseline, obtain the diagnostic confidence score, and store the diagnostic confidence score and the causal relationship in the failure root cause knowledge base;

[0038] For each chip, calculate the Euclidean distance between the physical coordinates and the center of all failure clusters; and combine the severity weight of the failure mode associated with the failure cluster and the spatial influence factor for quantifying the risk coverage range of the failure cluster obtained by performing principal component analysis on the physical coordinates of the chips in the failure cluster, to obtain the functional safety risk score through the weighted summation function combined with the Gaussian attenuation.

[0039] The functional safety risk score is compared with a preset risk threshold, when the functional safety risk score is higher than the risk threshold, the composition of the functional safety risk score is analyzed, the dangerous failure cluster with the largest risk contribution is identified, dynamic task rearrangement instructions are generated and executed, the execution priority of the test case most sensitive to the associated failure mode is dynamically improved, and testing is performed; when a defect is detected, all subsequent tests on the chip are immediately terminated and are classified into a high-risk isolated batch.

[0040] The technical solutions of the application will be further described in detail below with specific embodiments.

[0041] Embodiment one

[0042] The embodiment of the application discloses a test case dynamic priority scheduling method for an automotive electronic chip, referring to Figure 1 The specific steps include: S1, collecting and analyzing standard test data of the automotive electronic chip; extracting a structured data set including wafer ID, physical coordinates of each chip and software bin number; S2, applying a data clustering algorithm to identify aggregated failure clusters; S3, extracting geometric and positional features of the failure clusters, and using a classifier to classify them into known failure modes; querying a manufacturing execution system and a device automation system through the wafer ID, analyzing the failure modes and process steps and device logs, and matching them with a failure root cause knowledge base to establish causal relationships; analyzing historical test results, calculating the frequency of the failure modes, and performing statistical significance test with the failure rate of the production line baseline to obtain a diagnostic confidence score, and storing the diagnostic confidence score and the causal relationship in the failure root cause knowledge base; S4, for each chip, calculating the Euclidean distance between the physical coordinates and the centroid of all failure clusters; and combining the severity weight of the failure mode associated with the failure cluster and the spatial influence factor for quantifying the risk coverage range of the failure cluster obtained by principal component analysis on the physical coordinates of the chips of the failure cluster, obtaining a functional safety risk score through a weighted summation function with Gaussian attenuation; S5, comparing the functional safety risk score with a preset risk threshold, when the functional safety risk score is higher than the risk threshold, analyzing the composition of the functional safety risk score, identifying the dangerous failure cluster with the largest risk contribution, generating and executing dynamic task rearrangement instructions, dynamically improving the execution priority of the test case most sensitive to the associated failure mode, and testing; when a defect is detected, immediately terminating all subsequent tests on the chip and classifying them into a high-risk isolated batch.

[0043] Further, the standard test data of the automotive electronic chip is collected and analyzed; a structured data set including wafer ID, physical coordinates of each chip and software bin number is extracted; corresponding to the above S1 step; referring to Figure 2 ; the specific implementation process includes:

[0044] When an automatic test equipment (ATE) completes the wafer probe (CP) test of a wafer, a standard binary test data file, i.e. standard test data, is generated. The generation of the file serves as a trigger signal to automatically start a parsing program to read the standard test data:

[0045] WIR (Wafer Information Record): Extract the wafer ID (WAFER ID); PRR (Part Results Record): This record is for each independent chip (Die), from which the physical coordinates (X_COORD, Y_COORD) of the chip on the wafer and its final software bin number (SOFT BIN) are extracted.

[0046] After the key data tuples (WAFER ID, X_COORD, Y_COORD, SOFT BIN) are preliminarily cleaned and integrated, they are sent to the database of the data analysis center (DAC) to form a standardized wafer test result data set.

[0047] For a specific wafer ID, the physical coordinates and software bin numbers of all chips on the wafer are retrieved from the database of the data analysis center. Then, according to the pre-set mapping rules, logical judgment is made on the software bin number results of each chip. Generally, SOFT BIN of 1 represents a pass, and all other non-1 values represent different types of failures. According to the above definition, the test results of each chip are mapped to binary data labels: 0 represents normal, and 1 represents failure. Finally, a two-dimensional matrix is created according to the physical size of the wafer, and the binary data label (0 or 1) of each chip is filled into the matrix at the position corresponding to its physical coordinates. This completely filled two-dimensional matrix constitutes the digital structured data set of the wafer.

[0048] By parsing the standard test data generated by the automatic test equipment after CP test, which contains the wafer ID, and extracting the physical coordinates and software bin results of each chip, the data integrity and traceability are ensured. By mapping these data into a two-dimensional matrix, a structured data set is generated, which realizes the key step of spatializing discrete test results and accurately reproduces the physical distribution of all failed chips on the wafer, laying a solid data foundation for stable, reliable and automated failure mode analysis.

[0049] Further, a data clustering algorithm is applied to identify clustered failure clusters; corresponding to the S2 step; the specific process includes:

[0050] This example selects a density-based unsupervised clustering algorithm, such as DBSCAN (Density-Based Spatial Clustering of Applications with Noise). DBSCAN does not require the number of clusters to be specified in advance, and can effectively identify clusters of arbitrary shape. It is very suitable for discovering various patterns of systematic defects in semiconductor manufacturing. In the data analysis center, according to the physical size of the chip and the process experience, two key parameters are set:

[0051] neighborhood radius: defines a physical distance to determine the "neighborhood" range around a failed chip.

[0052] minimum point number: defines the minimum number of failed chips required to form a dense region (i.e. the core of a cluster) within the neighborhood radius of a failed chip.

[0053] DBSCAN takes the physical coordinates of all failed chips in the structured data set as input point set. Then each failed chip point is traversed, and according to the density of failed points in its neighborhood, it is automatically divided into three categories:

[0054] core point: the number of failed chips contained in its neighborhood radius is greater than or equal to the minimum point number. The core point is considered as the internal point of the systematic failure cluster.

[0055] boundary point: the number of failed chips contained in its neighborhood radius is less than the minimum point number, but the point itself falls within the neighborhood of a core point. The boundary point is considered as the edge of the failure cluster.

[0056] noise point: neither a core point nor a boundary point. These points usually correspond to random defects (Type-A defects) in semiconductor manufacturing and will be identified as isolated noise points.

[0057] DBSCAN starts from any unvisited core point and creates a new cluster. Through recursion or iteration, all core points and associated boundary points that can be connected by a series of core point neighborhoods from this core point are assigned to the same cluster. When a cluster cannot be expanded, the next unvisited core point is selected and the above process is repeated until all core points are assigned to a cluster.

[0058] After the first stage of clustering algorithm is completed, the physical coordinates of all the failed chips labeled as noise points are collected to form a residual dataset; a density variation sensitive clustering algorithm is applied to the residual dataset to identify weak signal clusters that are ignored due to low density and uneven distribution. Features are extracted for them and classification and root cause analysis are attempted. This two-stage analysis process retains the ability to identify high-density "strong signal" failure clusters while increasing the ability to detect low-density "weak signal" clusters, thereby building a more comprehensive and forward-looking failure mode monitoring system.

[0059] Through the above steps, the failure points on the structured dataset are divided into one or more failure clusters (composed of core points and boundary points) with physical aggregation, and at the same time, random failure points that do not meet the systematic aggregation characteristics are effectively distinguished.

[0060] By applying a density-based unsupervised clustering algorithm, statistically significant aggregated failure clusters can be automatically identified from the structured dataset. This allows subsequent analysis resources to focus on tracing and solving the root causes of systematic problems that truly affect the stability of the production line and the overall yield, improving the efficiency and accuracy of fault diagnosis and avoiding the waste of valuable engineering resources on random failures.

[0061] Further, geometric and positional features of the failure clusters are extracted, and a classifier is used to classify them into known failure modes; by querying the manufacturing execution system and the device automation system through the wafer ID, the failure modes are analyzed and matched with the process steps and device logs, and are matched with the failure root cause knowledge base to establish causal relationships; historical test results are analyzed to calculate the frequency of the failure mode, and statistical significance test is performed with the failure rate of the production line baseline to obtain a diagnostic confidence score, which is stored in the failure root cause knowledge base; corresponding to the S3 step; the specific implementation process includes:

[0062] For each independent failure cluster, a set of feature vectors that can quantify its physical form and distribution characteristics is calculated and extracted. The process includes:

[0063] Cluster size: the total number of failed chips constituting the cluster is calculated.

[0064] Cluster density: the ratio of the size of the cluster to the area of its minimum bounding box is calculated to quantify its compactness.

[0065] Centroid coordinates: the arithmetic mean of the physical coordinates of all failed chips in the cluster is calculated to determine its geometric center.

[0066] Relative position: according to the distance between the centroid coordinates and the center of the wafer, the position of the cluster is classified into predefined areas such as "center", "edge" or "corner".

[0067] Elongation: All the physical coordinates of failed chips in a cluster are regarded as a two-dimensional point set, and principal component analysis is applied to the point set to obtain the ratio of the eigenvalues corresponding to the first principal component (representing the longest axis direction of the cluster) and the second principal component (representing the shortest axis direction).

[0068] After obtaining the feature vector, a pre-trained classifier (for example, a support vector machine SVM) is input to process the input feature vector. The support vector machine is trained based on a large amount of historical wafer map data labeled by process experts in the data analysis center, and can identify the mapping relationship between the feature vector and the known failure mode, automatically and accurately classify the input feature vector into a known failure mode, and assign the most matching failure mode label. Specifically, the training data set of the pre-trained support vector machine (SVM) classifier can be selected from at least 10,000 wafer maps accurately labeled by failure analysis engineers in historical production data as a training data set. To ensure the generalization ability of the model, the data set needs to cover at least 15 typical systematic failure modes in semiconductor manufacturing, including but not limited to center clustering, edge ring, local area, scratch, repeated occurrence, etc., and using oversampling or undersampling technology to ensure that the number of samples of each failure mode in the data set is not less than 200. Select a support vector machine model with strong universality and stable effect of Gaussian radial basis function (RBF) kernel, and use grid search combined with five-fold cross-validation method to automatically determine the hyperparameters of the model. Among them, the search range of the penalty coefficient C is set to [0.1, 100], and the search range of the gamma value is set to [0.001, 10]. Finally, define and apply the label library. The pre-defined label library relied on by the classifier contains a standardized mapping list of failure mode ID and description, which serves as the output standard of the classifier. For example: {1: center clustering, 2: edge ring, 3: scratch,..., 15: specific device cavity contamination}. When a new failure cluster feature vector is input, the trained SVM model will output the most matching failure mode label.

[0069] While the classifier outputs the failure mode label, the confidence score is also obtained. The absolute value of the confidence score is compared with a preset confidence threshold. When the confidence score is lower than the confidence threshold, the failure mode label will be automatically marked as "low confidence", and a human-machine loop process is triggered; all failure mode labels marked as low confidence are pushed to a special review queue, and process experts reconfirm the failure mode labels according to their professional knowledge; if the failure mode is a new type, the process expert creates a new failure mode category; the failure mode label confirmed by the expert is automatically added back to the training data set of the classifier, and accumulated until the incremental retraining of the SVM classifier is triggered. Through this closed-loop feedback mechanism, new or difficult-to-identify failure mode cases can be actively identified and learned, continuously improving the ability to identify new failure modes and the accuracy of distinguishing ambiguous patterns.

[0070] When the failure cluster is assigned a failure mode label (such as "edge ring"), a query request is automatically initiated to the upstream manufacturing execution system and equipment automation system through the wafer ID (WAFER ID) and test completion timestamp as the key index. From the database of the manufacturing execution system, the full life cycle manufacturing data associated with the wafer ID is retrieved, including but not limited to: the wafer batch number it belongs to, the mask layer number used, the etching machine, the film deposition equipment number, and the process recipe followed by each key step.

[0071] From the database of the equipment automation system, the process parameter logs collected and recorded in real time by the above-mentioned key equipment during the processing of the wafer batch are retrieved. For example, these parameters specifically include: the radio frequency power and gas flow of the plasma etching machine, the temperature and pressure during film deposition, the polishing pressure of chemical mechanical polishing, etc.

[0072] The retrieved process parameter logs are compared with the control limits preset in the process recipe to detect abnormal fluctuations. The detected process abnormalities are matched with a pre-set failure root cause knowledge base. The construction and updating process of the knowledge base includes: a) importing initial FMEA (Failure Mode and Effects Analysis) data developed by experts from multiple fields such as design, process, and equipment; b) automatically mining historical production data to verify and correct existing causal relationships and discover new associations; c) establishing an automated entry interface for new root cause analysis (RCA) reports to ensure continuous learning and iteration. For example, when a wafer presents an "edge ring" failure mode and an abnormal radio frequency power is found in the EAP log of its etching step, a high-confidence causal relationship is established: "the 'edge ring' failure of the current wafer is likely caused by power fluctuations of the etching machine".

[0073] The causal relationship established with the process steps and equipment logs is taken as a hypothesis to be verified, and the historical production database is automatically queried to retrieve all wafer batches that have been processed by the equipment and in which the parameters have changed. The wafer test results of the wafer batches are analyzed, and the frequency of occurrence of failure modes is calculated. Through statistical significance testing with the failure rate of the production line baseline, a comprehensive diagnostic confidence score is calculated based on the results of the statistical significance testing, the frequency of occurrence of failure modes, and the initial weight preset by the process expert for the causal relationship. The diagnostic confidence score and the causal relationship are stored in the failure root cause knowledge base. When subsequent data confirm or disprove the causal relationship, the confidence score will be dynamically updated. This confidence score provides engineers with an intuitive judgment of diagnostic reliability, making the entire risk assessment system more data-driven and intelligent.

[0074] By extracting geometric and positional features from the failure clusters, a set of points without specific meaning is quantified into a set of feature vectors available for analysis. By using a classifier to classify into known failure modes, the failure cluster is given a standardized, engineer-understandable label. Subsequent root cause tracing is no longer a purposeless data mining, but can be based on classified patterns for more targeted correlation analysis, significantly improving the efficiency and accuracy of diagnosis. And by querying the manufacturing execution system and equipment automation system through wafer ID, the barrier between test data and upstream manufacturing data is broken down, realizing the integration of full-process data. On this basis, the failure mode is correlated with the upstream key process steps and equipment logs to establish a causal relationship, providing a high-confidence diagnostic report for process engineers. This shortens the cycle from discovering yield problems to locating problem sources, enabling rapid and accurate feedback on the production process, so that corrective measures can be taken in time to effectively curb the generation of defects and improve product yield from the source.

[0075] Further, for each chip, the Euclidean distance between the physical coordinates and the centroid of all failure clusters is calculated; and the severity weight of the failure mode associated with the failure cluster and the spatial influence factor for quantifying the risk coverage range of the failure cluster obtained by principal component analysis on the physical coordinates of the chips of the failure cluster are combined, and a functional safety risk score is obtained by combining a weighted summation function with Gaussian attenuation; corresponding to the S4 step; refer to Figure 3 ; the specific implementation process includes:

[0076] Traverse each chip to obtain physical coordinates, and at the same time call the centroid coordinates of all identified failure clusters. For any chip, the Euclidean distance between its physical coordinates and the centroid coordinates of each identified failure cluster is calculated.

[0077] A quantitative severity weight is assigned to each failure mode associated with a failure cluster. The weight is dynamically set based on the root cause severity derived from analysis. A secondary query is initiated to the database with wafer ID to retrieve the process capability index values of key process parameters associated with the specific process step within the time window when the wafer was processed; a pre-set non-linear mapping function is adopted to ensure that the severity weight drops rapidly as the process capability index value increases, implemented by an inverse exponential decay function containing configurable constants.

[0078] A spatial impact factor is determined for each failure cluster to control the speed of risk decay with distance. Principal component analysis is performed on the physical coordinates of all chips within the failure cluster to calculate two orthogonal principal component directions (eigenvectors) and the data variance along these two directions. The standard deviations σ_pc1 and σ_pc2 along the first principal component (PC1) and the second principal component (PC2) directions are calculated, respectively equal to the square root of the corresponding eigenvalues. The spatial impact factor σ is the root mean square of the two standard deviations. In this way, a failure cluster with a larger size or a more elongated shape will naturally obtain a larger spatial impact factor σ, making its risk assessment coverage wider.

[0079] The Euclidean distance, the severity weight of the associated failure mode, and the spatial impact factor extracted from the failure cluster are input into a weighted summation function combined with a Gaussian decay function to sum up the risk contributions of all identified failure clusters to the chip. The risk contribution of each failure cluster is determined by the severity weight of the cluster multiplied by a factor that decays exponentially with increasing distance; the decay rate of the decay factor is controlled by the spatial impact factor of the cluster and inversely proportional to the square of the Euclidean distance from the chip to the cluster centroid. The functional safety risk score is obtained and associated with its unique chip identifier (combined with wafer ID and physical coordinates) and stored in the database of the data analysis center.

[0080] By calculating the Euclidean distance from each chip on the wafer to all failure cluster centroids and utilizing the severity weight of the associated failure mode and the spatial impact factor, the risk assessment incorporates the analysis of failure root cause severity, enabling accurate identification of chips that have passed preliminary tests but are highly likely to carry potential defects due to being in a high-risk manufacturing environment, playing a crucial role in meeting zero-defect requirements in the automotive electronics and other fields.

[0081] Further, the functional safety risk score is compared with a preset risk threshold, when the functional safety risk score is higher than the risk threshold, the composition of the functional safety risk score is analyzed, the dangerous failure cluster with the largest risk contribution is identified, the dynamic task rearrangement instruction is generated and executed, the execution priority of the test case most sensitive to the associated failure mode is dynamically improved, and the test is performed; when the unqualified is detected, all subsequent tests on the chip are terminated immediately, and are classified into a high-risk isolated batch; corresponding to the S5 step; refer to Figure 4 ; the specific implementation process includes:

[0082] When a chip enters the final test (FT) station, the functional safety risk score of the chip is queried from the database of the data analysis center through the unique identification of the chip. The queried risk score is compared with a preset risk threshold which can be configured by an engineer. If the score is higher than the threshold, the chip is determined as a high-risk chip, and a dynamic task rearrangement logic is triggered to generate a dynamic task rearrangement instruction; if the score is lower than or equal to the threshold, the chip is determined as a low-risk chip, and a default test sequence is executed.

[0083] The setting of the risk threshold first selects a plurality of wafer batches with stable yield and high product reliability in history as a reference data set; the functional safety risk scores of all chips in the reference data set are calculated by the method of the application; statistical analysis is performed on these risk scores, for example, the value of the 95th percentile of the risk score distribution plus three standard deviations is set as the initial risk threshold. The threshold can be dynamically adjusted according to the actual defect detection rate and test cost of the production line.

[0084] For high-risk chips, further analyze the composition of the risk score, identify one or more failure clusters that contribute most to the risk, and retrieve the failure mode labels (such as “edge ring”, “scratch type”, etc.) associated with these failure clusters. Access a pre-established test failure mode knowledge base, which is defined by test and process experts in the form of a mapping table, which clearly defines the physical failure mechanisms or their corresponding failure modes that can be effectively detected by each independent test case in the test program library. The mapping table at least includes the following fields: failure mode label (such as edge ring), possible physical root cause (such as timing performance degradation), high sensitivity test case ID list (such as TC_AC_001, TC_AC_005), and optional sensitivity score. The establishment process of the table includes: combining the failure mode and impact analysis in the design stage and the process failure mode and impact analysis, preliminarily associating the failure mode with the test item; by analyzing the test data of the historical specific failure mode batch, the test case with the highest detection rate for the mode is counted and filled into the table, thereby continuously enriching and optimizing the knowledge base.

[0085] The failure mode label is matched with the test failure mode knowledge base to screen all test cases with high detection sensitivity for the specific failure mode. For example, if the traced failure mode is "edge ring", and the mode is associated with the physical root cause of "timing performance decline" caused by photolithography layer misalignment or uneven etching, all test cases related to timing performance, such as "maximum operating frequency test", "setup / hold time test", and other communication parameter tests, are screened in the knowledge base. The execution priority of one or more test cases most sensitive to the associated failure mode screened in the previous step is dynamically promoted to the highest. A new test execution sequence is generated, and the high-priority test cases are placed at the front end of the test queue, and the remaining standard test cases are arranged in the default order.

[0086] The reconstructed dynamic test sequence is sent to the controller of the automatic test equipment, and the automatic test equipment tests the high-risk chip according to the new optimized sequence. In this way, the test most likely to find potential defects is executed first, and when a functional failure is detected during the execution of any test case, all subsequent tests on the chip are immediately terminated, and the chip is classified into a high-risk isolated batch.

[0087] By dynamically promoting the execution priority of the test case most sensitive to the associated failure mode, the test most likely to find potential defects is ensured to be executed first, the early fault detection rate is improved, and the test is terminated as soon as a failure is found, thereby saving a large amount of test time for the high-risk chip. Secondly, by performing more targeted stress testing on the high-risk area, the coverage depth and quality of the test are improved, and the chips carrying potential defects are effectively prevented from flowing into the market.

[0088] The application can capture the systemic yield loss pattern caused by specific process or equipment problems in real time and accurately by collecting and analyzing the standard test data of the automotive electronic chip and applying the density-based unsupervised clustering algorithm to identify the failure clusters aggregated on the structured data set. More importantly, the application correlates and analyzes the failure mode with the upstream key process steps and equipment logs by querying the manufacturing execution system and equipment automation system through wafer ID, establishes a causal relationship, deeply integrates test data and manufacturing data, realizes the leap from phenomenon correlation to root cause diagnosis, and provides precise clues for process engineers to quickly locate and solve the root problem. On this basis, a quantitative functional safety risk score is calculated for each chip, which not only considers the physical proximity, but also integrates the severity weight determined by the manufacturing root cause, realizing "individualized" risk assessment. Finally, for the chips with a functional safety risk score higher than the preset risk threshold, the execution priority of the test case most sensitive to the associated failure mode can be dynamically improved for accurate testing. In summary, the application improves the early defect detection rate, shortens the test time and reduces the test cost; through root cause analysis feedback, the overall production line yield is improved; and a screening mechanism is provided for automotive electronics to eliminate potential failure risk chips, thereby improving the quality and functional safety level of the product.

[0089] Embodiment Two

[0090] This embodiment two shows the specific test process of the application method applied in the automotive electronic chip factory, referring to Figure 2 and Figure 3 ; the specific implementation is as follows:

[0091] For a wafer probe (CP) test completed wafer, the unique identifier (WAFER_ID) is "HNA2025-L0T34A-W21", and a series of chip test result records are extracted from the standard test data thereof. Each record contains the physical coordinates and software bin number of the chip. For example, the following two records are extracted:

[0092] Chip One: physical coordinates (10, 25), software bin number 1.

[0093] Chip Two: physical coordinates (32, 58), software bin number 101.

[0094] The extracted data tuples are loaded and integrated into a structured database. According to the mapping rule, logical judgment and mapping are performed on the extracted software bin number. Software bin number 1 is defined as pass and mapped to binary state 0. Software bin number 101 (for example, representing high leakage current failure) and all other software bin numbers that are not "1" are defined as failure and mapped to binary state 1. A two-dimensional matrix is created according to the physical size of the wafer. Then, all chip data of the wafer are traversed, and the binary state of each chip is filled into the position corresponding to its physical coordinates in the matrix. The value 0 is filled in the (10, 25) position of the matrix, and the value 1 is filled in the (32, 58) position of the matrix.

[0095] This process is repeated for all chips on the wafer "HNA2025-L0T34A-W21", and a complete, digitized structured data set is finally generated.

[0096] The DBSCAN algorithm is selected, and according to the physical size of the tested chip and process experience, the neighborhood radius is set to 2 to 4 times the diagonal length of the chip, and in this embodiment, it is 2.5 times. The minimum number of points is set to an integer range of 3 to 10, and in this embodiment, it is 5. The algorithm traverses each failure chip point in the structured data set, such as point P (32, 58), and according to the density of failure points in its neighborhood, it is automatically divided into three categories: core point, boundary point and noise point.

[0097] Then the algorithm starts with an arbitrarily selected core point that has not been visited from the structured data set, creates a new cluster (for example, Cluster 1), and recursively or iteratively assigns all core points and associated boundary points connected by a series of core point neighborhoods to the same cluster. When a cluster cannot be expanded any further, the algorithm selects the next unvisited core point and repeats the above process until all core points are assigned to a cluster.

[0098] After the algorithm is executed, a labeled data set is output. The data set adds a classification label, i.e. a unique cluster ID or a noise label, to each failure chip point based on the original structured data set. For example:

[0099] (WAFER ID: HNA2025-L0T34A-W21, X: 32, Y: 58, Fail: 1, Cluster ID: 1)

[0100] (WAFER ID: HNA2025-L0T34A-W21, X: 32, Y: 59, Fail: 1, Cluster ID: 1)

[0101] (WAFER ID: HNA2025-L0T34A-W21, X: 15, Y: 40, Fail: 1, Cluster ID: -1).

[0102] For each failed cluster, a set of feature vectors quantifying its physical morphology and distribution characteristics are automatically calculated and extracted. For example, for Cluster ID: 1: Size: the total number of failed dies is calculated to be 157. Centroid: the geometric center is calculated to be (32.8, 85.1). Relative Position: according to the distance between the centroid and the wafer center, the position is classified as "Center". Shape Feature: principal component analysis (PCA) is applied to the 157 coordinate points within the cluster, and the elongation is calculated to be 1.1, indicating that the cluster shape is close to a circle.

[0103] The feature vectors generated for each failed cluster (e.g., [157, Center, 1.1,...]) are input into a pre-trained support vector machine in the data analysis center, and a standardized failure mode label is output. For example: Cluster ID: 1 is classified as "Center Cluster". Cluster ID: 2 is classified as "Edge Ring". With the wafer's unique identifier "HNA2025-L0T34A-W21" and the test completion timestamp as the key index, a query request is initiated to the upstream manufacturing execution system and equipment automation system to retrieve the complete manufacturing history of the wafer, obtaining a large amount of process and equipment data related to the wafer. For example, it is found that the wafer was processed by the plasma etching machine with device number "ETCH_Tool_08" at "14:32:05", using the process recipe "Recipe_Poly_Etch_v2.3". Using the above device number and timestamp, the high-frequency process parameter log containing thousands of data points collected by "ETCH_Tool_08" during processing of the wafer is retrieved from the equipment automation system database, and the retrieved EAP parameter data is compared with the control limit preset by the process recipe "Recipe_Poly_Etch_v2.3", detecting that the radio frequency power (RF_Power) has an abnormal decrease of 4%. Then, the failure root cause knowledge base is queried, and a rule is matched: "Edge Ring" failure mode is highly correlated with "plasma etching uniformity problem", and the typical cause is "radio frequency power fluctuation", and a causal relationship is established accordingly.

[0104] The attribute data of all failed clusters generated for the wafer is retrieved. For example, there are two failed clusters on the wafer:

[0105] Failed Cluster 1: Cluster ID: 1, Failure Mode: "Center Cluster", Centroid: (32.8, 85.1), Severity Weight (Fail: 1, Cluster ID: -1). ): 0.8, spatial impact factor ( ): 15.0.

[0106] Failure Cluster 2: Cluster_ID: 2, Failure Pattern: "Edge-Ring", Centroid Coordinate: (85.0, 15.2), Severity Weight ( ): 0.5, spatial impact factor ( ): 25.0.

[0107] Traverse all failure clusters, calculate the Euclidean distance between the target chip (45, 62) and the centroid of each failure cluster. The distance to failure cluster 1 is , and the distance to failure cluster 2 is .

[0108] For each failure cluster, calculate its risk contribution to the target chip according to its severity weight, spatial impact factor, and distance to the target chip. The calculation process is: multiply the severity weight by an exponentially decaying factor as the distance increases, and the decay rate of the decay factor is controlled by the spatial impact factor, and is inversely proportional to the square of the Euclidean distance from the chip to the centroid of the cluster.

[0109] Risk contribution of failure cluster 1 = 0.8 x exp[- (26.12 2 / (2 x 15 2 ))]= 0.8 x exp(-1.516)= 0.176,

[0110] Risk contribution of failure cluster 2 = 0.5 x exp(-3.032)= 0.024,

[0111] Sum the risk contributions of all failure clusters to the target chip to get the final functional safety risk score of the chip = 0.176+0.024= 0.200

[0112] After the calculation, output a record containing the unique identifier of the chip and its corresponding risk score. For example: {Chip_UID: HNA2025-L0T34A-W21_45_62, Risk_Score: 0.200}, the record is stored in the database of the data analysis center, associated with other information of the chip.

[0113] When the chip enters the final test (FT) station, the test system controller queries the functional safety risk score from the database of the data analysis center. The result is {Chip_UID: HNA2025-L0T34A-W21_45_62, Risk_Score: 0.200}. The queried risk score 0.200 is compared with a pre-set, engineer-configurable risk threshold (e.g., 0.150). Since 0.200 > 0.150, the chip is determined to be a high-risk chip, and the dynamic task rearrangement logic is triggered to generate dynamic task rearrangement instructions.

[0114] Further analysis of the risk score composition of the chip identifies the failure cluster that contributes most to its risk as failure cluster 2, and retrieves the classified failure mode label associated with this cluster from the database: “edge ring”. The database is accessed. The associated physical root cause “timing performance degradation” is matched against the database, and all test cases with high detection sensitivity to this specific failure mode are filtered out. For example, from the test program containing thousands of test cases, the following high-sensitivity test cases are filtered out:

[0115] TC_AC_001: Fmax_Test @ VDD_nom, Temp_hot

[0116] TC_AC_005: Setup_Time_Test_Core_A @ VDD_min, Temp_cold

[0117] TC_AC_006: Hold_Time_Test_Core_A @ VDD_max, Temp_hot

[0118] TC_AC_012: Fmax_Test_DDR_Interface @ VDD_nom, Temp_hot

[0119] The execution priority of the selected, most targeted test cases (TC_AC_001, TC_AC_005, TC_AC_006, TC_AC_012) is dynamically promoted to the highest. Meanwhile, a new test execution sequence is generated, placing these high-priority test cases at the very front of the test queue, while the rest of the standard test cases are arranged in their default order behind. The reconfigured dynamic test sequence is issued to the controller of the automated test equipment, which then proceeds to test the high-risk chip according to this new, optimized order. The chip fails during execution of TC_AC_005, and the remaining thousands of test cases will not be executed. The final results of the test, including pass / fail status, specific failed test item (e.g. TC_AC_005), and detailed parameter measurements, are all recorded. This data is fed back to the data analysis center through the real-time monitoring system, for subsequent yield analysis and continuous optimization of the scheduling method model.

[0120] While embodiments of the application have been shown and described, it is to be understood that the embodiments described are merely exemplary of the principles and application of the present application. Numerous modifications and adaptions can be made without departing from the spirit and scope of the present application, which is defined by the following claims and their equivalents.

Claims

1. A method for dynamic priority scheduling of test cases for automotive electronic chip, characterized in that, The application comprises: Collecting and analyzing standard test data of automotive electronic chips; extracting a structured data set including wafer ID, physical coordinates of each chip, and software bin number; Applying data clustering algorithm to identify aggregated failure clusters; Extracting geometric and positional features of the failure clusters and using a classifier to classify them into known failure modes; When the failure cluster is assigned a failure mode label, querying the manufacturing execution system and equipment automation system through the wafer ID to retrieve the full life cycle manufacturing data associated with the wafer ID from the manufacturing execution system database; in the equipment automation system database, according to the full life cycle manufacturing data, the process parameter log in the time window of processing wafer is retrieved; the failure mode is analyzed in association with the process step and equipment log, the process parameter log is compared with the preset control limit to detect the existence of specification deviation; when the process parameter is abnormal, the failure root cause knowledge base is matched to establish a causal relationship with the process step and equipment log; Analyzing historical test results, calculating the frequency of failure modes, and performing statistical significance test with the failure rate of the production line baseline to obtain a diagnostic confidence score, and storing the diagnostic confidence score and causal relationship in the failure root cause knowledge base; For each chip, calculate the Euclidean distance between the physical coordinates and the centroid of all failure clusters; Combine the severity weight of the failure mode associated with the failure cluster and the spatial influence factor for quantifying the risk coverage range of the failure cluster obtained by principal component analysis of the physical coordinates of the chips in the failure cluster, and obtain the functional safety risk score by combining the weighted sum function of Gaussian attenuation; Compare the functional safety risk score with the preset risk threshold value, when the functional safety risk score is higher than the risk threshold value, analyze the composition of the functional safety risk score, identify the most dangerous failure cluster that contributes most to the risk, generate and execute dynamic task rearrangement instructions, dynamically improve the execution priority of the most sensitive test cases of the associated failure mode, and perform testing; when unqualified is detected, terminate all subsequent testing of the chip and enter the high-risk isolation batch.

2. The test case dynamic priority scheduling method for automotive electronic chip according to claim 1, wherein, The specific generation process of the structured data set comprises: collecting and analyzing standard test data of automotive electronic chips, extracting wafer ID, physical coordinates of chips on wafer, and software bin number to form key data tuples; according to the preset mapping rule, data conversion is performed on the software bin number, and the test result is mapped to binary data label; a two-dimensional matrix is created according to the physical size of the wafer; traverse all chip data of the wafer, fill the binary data label of each chip into the position corresponding to the physical coordinates in the matrix, and construct a structured data set.

3. The method of claim 1, wherein, The specific process of identifying the aggregated failure cluster includes: selecting a density-based unsupervised clustering algorithm, setting a neighborhood radius and a minimum point number according to the physical size of the chip and process experience, and taking the physical coordinates of all failed chips in the structured data set as an input point set; traversing each failed chip, and according to the density of failed chips within the neighborhood radius, dividing into three categories: core point: the number of failed chips contained is not less than the preset minimum point number; boundary point: the number of failed chips contained is less than the minimum point number, but within the neighborhood radius of the core point; noise point: neither core point nor boundary point; starting from the core point that has not been visited, creating a new failure cluster, and through recursion, all connectable core points and their associated boundary points are assigned to the same failure cluster.

4. The method of claim 1, wherein, The specific process of classifying using the classifier to the known failure mode includes: calculating and extracting a set of geometric and position features from the failure cluster; taking the geometric and position features as the input of the pre-trained classifier, and the classifier outputs the failure mode label from the predefined car chip label library; the geometric and position features include cluster size, cluster density, centroid coordinates, relative position and elongation obtained by principal component analysis.

5. The method of claim 1, wherein, The specific generation process of the functional safety risk score includes: traversing each chip on the wafer, obtaining the centroid coordinates of all failure clusters, calculating the Euclidean distance between the physical coordinates of any chip and the centroid coordinates of each failure cluster; according to the failure mode associated with each failure cluster, a quantitative severity weight is given, and principal component analysis is performed on the physical coordinates of all chips in the failure cluster to determine a spatial influence factor; input the Euclidean distance, severity weight and spatial influence factor into a weighted summation function combined with Gaussian attenuation to calculate the functional safety risk score; the functional safety risk score is associated with the chip identifier combined with the wafer ID and physical coordinates, and stored in the database.

6. The method of claim 1, wherein, The specific process of dynamically improving the execution priority of the test case most sensitive to the associated failure mode includes: taking the chip identifier as the database query key, querying the functional safety risk score from the database, and comparing it with the preset risk threshold; if the functional safety risk score is higher than the risk threshold, the chip is determined to be high-risk, and a dynamic task rearrangement instruction is generated and executed to dynamically improve the execution priority of the test case most sensitive to the associated failure mode; the data structure of the original task queue is reordered to generate a new task queue, and the test case with high priority is placed at the front end of the task queue; when a defect is detected, all subsequent tests on the chip are immediately terminated and are classified into a high-risk isolation batch.

7. The method of claim 6, wherein the method further comprises: The specific process of generating and executing a dynamic task rearrangement instruction includes: when the chip is determined to be high-risk, analyzing the composition of the functional safety risk score, identifying the dangerous failure cluster with the largest risk contribution, and retrieving the failure mode label associated with the dangerous failure cluster; through the preset database storing the mapping relationship between test cases and failure modes, the test case with high detection sensitivity to the failure mode label is screened out, and the execution priority of the test case is dynamically improved to the highest.

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