Chip task writing method and device and storage medium

Abstract

The invention discloses a chip task writing method, chip task writing equipment and a storage medium, and is applied to a chip task writing system, the chip task writing system comprises a master end, a slave end and a buffer unit, the method comprises the following steps: determining the starting condition of the buffer unit through a Master, when determining to start the buffer unit, generating task writing information according to a task ID and a task state, and transmitting the task writing information to the buffer unit; the write task information is stored through a buffer unit, a write task application is sent to the Slave, and when application feedback of the Slave is received, the write task information is sent to the Slave; and processing the write task information based on the task ID through the Slave and feeding back the write task information. The starting condition of the buffer unit is determined through the Master, whether the buffer unit is started or not can be flexibly determined according to system requirements, and the efficiency and flexibility of resource utilization are improved. The efficiency, accuracy and stability of chip writing tasks can be improved, the system performance is optimized, and reliable writing and processing of data are ensured.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a chip writing task method, device and storage medium. Background Technology

[0002] In the rapid development of modern information technology, chips, as core components, are crucial to the operation of various electronic devices and systems in terms of performance and efficiency. Among the many operations of a chip, the efficiency of write tasks directly affects the speed of data storage, processing, and transmission.

[0003] Currently, write tasks are processed through interaction between the Master and Slave. Typically, the Master sends the address and data information required for the write task to the Slave, while the Slave returns the result to the Master after completing the write task. Throughout this process, a channel handshake is required between the Master and Slave to ensure accurate and effective data transmission; only when the handshake is successful can the information be sent smoothly.

[0004] However, in the traditional method, when the write address is unavailable, the write address channel remains in a handshake-attempt state. During this time, relevant resources on both the Master and Slave are continuously occupied and cannot be released for other tasks or operations. This prolonged resource occupation not only wastes resources but also affects the chip's data write efficiency, thus limiting the performance of the entire chip system. Summary of the Invention

[0005] This invention provides a chip write task method, device, and storage medium to improve the data write efficiency of chips.

[0006] According to one aspect of the present invention, a chip write task method is provided, applied to a chip write task system, comprising: a master, a slave, and a buffer unit, the method comprising: The Master determines whether the buffer unit is enabled. When the buffer unit is enabled, write task information is generated based on the task ID and task status, and the write task information is transmitted to the buffer unit. The write task information includes write task ID information, write task data information, and write task address information. Write task information is stored in a buffer unit, and a write task request is sent to the slave. When the slave's request feedback is received, write task information is sent to the slave. The Slave processes and provides feedback on write task information based on the task ID.

[0007] Optionally, the Master determines the enabling status of the buffer unit, including: sending a handshake request to the Slave via the write task channel, where the write task channel includes a write task ID channel, a write data channel, a write address channel, and a write feedback channel; sending a handshake request to the buffer unit via the write data channel, the write address channel, and the write feedback channel; the Slave checking whether its own resources meet preset conditions based on the handshake request, and if so, replying with a first handshake response, otherwise not replying; the buffer unit checking whether its own resources meet preset conditions based on the handshake request, and if so, replying with a second handshake response, otherwise not replying; the Master accepting the first and second handshake responses, and determining that the buffer unit is not enabled if the first handshake response is less than a preset time or earlier than the second handshake response, otherwise, determining that the buffer unit is enabled.

[0008] Optionally, after determining the enabling status of the buffer unit through the Master, the method further includes: when it is determined that the buffer unit is not enabled, directly sending write task information to the Slave through the Master.

[0009] Optionally, after storing the write task information through the buffer unit, the method further includes: feeding back the first write result information to the Master through the buffer unit; and changing the task status from busy to suspended by the Master based on the first write result information.

[0010] Optionally, the Slave processes and feeds back the write task information based on the task ID, including: the Slave sequentially determines the target write task from the write task information according to the write task ID; the Slave processes the target write task and generates a second write result information to feed back to the Master and the buffer unit.

[0011] Optionally, after the Slave processes and responds to the write task information based on the task ID, the method further includes: changing the task status from suspended to available by the Master based on the second write result information; and releasing resources by the buffer unit based on the second write result information.

[0012] Optionally, the buffer unit includes: a data buffer, an address buffer, a data manager, and an address manager.

[0013] Optionally, write task information can be stored in a buffer unit, including: storing write task data information in a data buffer and managing the data buffer through a data manager; storing write task address information in an address buffer and managing the address buffer through an address manager.

[0014] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute a chip write task method according to any embodiment of the present invention.

[0015] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement a chip write task method according to any embodiment of the present invention.

[0016] The technical solution of this invention, by determining the activation status of the buffer unit through the Master, can flexibly decide whether to activate the buffer unit according to system requirements, improving the efficiency and flexibility of resource utilization. Transmitting write task information to the buffer unit achieves initial storage and centralized management of information, preparing for subsequent transmission and processing. Processing based on task ID by the Slave enables accurate classification and processing of different write tasks, improving processing accuracy and efficiency. This improves the efficiency, accuracy, and stability of chip write tasks, optimizes system performance, and ensures reliable data writing and processing.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a chip write task method provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a write task information structure provided in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the structure of a write task ID management unit according to Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of information transmission in a chip write task system according to Embodiment 1 of the present invention; Figure 5This is a schematic diagram of a handshake operation provided in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of information transmission in another chip write task system provided according to Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of the structure of an electronic device that implements a chip writing task method according to an embodiment of the present invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Example 1 Figure 1 The flowchart illustrates a chip write task method according to Embodiment 1 of the present invention. This method can be applied to a chip write task system, including a master, a slave, and a buffer unit. This chip write task system can be configured in a computer controller. Figure 1 As shown, the method includes: S110. The Master determines the activation status of the buffer unit. When the buffer unit is determined to be activated, write task information is generated based on the task ID and task status, and the write task information is transmitted to the buffer unit. The write task information includes write task ID information, write task data information, and write task address information.

[0023] It should be noted that the buffer unit is an intermediate storage and coordination component in the chip write task system. It serves to temporarily store the write task information transmitted from the master end, and is also responsible for communicating and coordinating with the slave end, sending write task requests to it, and forwarding the stored write task information to the slave end after receiving feedback from the slave end. This buffers and coordinates the data interaction rhythm between the master and slave ends, avoiding problems caused by differences in processing speed between the two ends.

[0024] The write task information is a set of data related to the chip write task, which includes write task ID information, write task data information, and write task address information. Figure 2 This invention provides a schematic diagram of a write task information structure in Embodiment 1. Figure 2 In the process, the Master sends out information including write task ID, write task address, and write task data. The write task data specifies the exact content to be written to the chip's storage area. The write task address specifies the physical or logical address where the write task data should be stored. The task ID is a unique symbol, code, or value used to identify each write task. In the entire chip write task system, the task ID accurately distinguishes different write tasks, facilitating the search, management, and tracking of their processing flow by various components. The task status reflects the current processing stage of the write task. Task status includes four states: Valid, Busy, Hang-up, and Zombie. Valid indicates that the ID can be used for write task allocation; Busy indicates that the Master is writing or requesting to write to a Slave or buffer unit; Hang-up indicates that the buffer unit has completed receiving information from the Master and is writing or requesting to write to a Slave; Zombie indicates that the write task has not been completed for a long time.

[0025] Specifically, the Master is responsible for monitoring the operational status of the entire chip write task system to determine whether to enable the buffer unit. The decision to enable the buffer unit can be based on multiple factors. For example, the system's real-time data traffic can be considered. If the current data transmission rate is close to or exceeds a certain threshold of the system bandwidth, such as 80%, enabling the buffer unit can prevent data loss or blockage during transmission due to untimely processing. The Master's own processing load can also be considered, i.e., the number and complexity of tasks being executed. If too many tasks are being processed, the response time for processing new write tasks may be prolonged. In this case, enabling the buffer unit can temporarily store write tasks, allowing the Master to handle other urgent or important tasks first. Furthermore, the working status of the slave can be considered. If the slave is busy, such as performing large-scale data reading or complex computation tasks, the Master can obtain its busyness information according to the communication protocol with the slave. When the slave's busyness exceeds a set value, the buffer unit is enabled to wait for a suitable time to interact with the slave for write tasks, thereby improving the overall system's resource utilization and task processing flexibility.

[0026] Furthermore, once the buffer unit is enabled, the Master needs to generate task IDs for the write task information. The generation principle of the task ID is based on ensuring its uniqueness and identifiability, so that tasks can be accurately tracked and managed throughout the entire chip write task system. For example, a combination of timestamps and task sequence numbers can be used. Using the initial time at system startup as a reference, a timestamp is generated by recording the current time. Then, an incrementing task sequence number is assigned according to the order in which the write tasks are initiated. These two are combined and processed using a hash algorithm to obtain a fixed-length and unique task ID.

[0027] Specific application scenario: The Master will have a write task ID management unit. Figure 3 This embodiment provides a schematic diagram of the structure of a write task ID management unit, as shown below. Figure 3 As shown, the write task ID management unit manages all write task IDs in a unified manner. It has an internal write task ID resource pool in which all write task ID information is contained, and the task ID is unique.

[0028] Optionally, the Master determines the enabling status of the buffer unit, including: sending a handshake request to the Slave via the write task channel, where the write task channel includes a write task ID channel, a write data channel, a write address channel, and a write feedback channel; sending a handshake request to the buffer unit via the write data channel, the write address channel, and the write feedback channel; the Slave checking whether its own resources meet preset conditions based on the handshake request, and if so, replying with a first handshake response, otherwise not replying; the buffer unit checking whether its own resources meet preset conditions based on the handshake request, and if so, replying with a second handshake response, otherwise not replying; the Master accepting the first and second handshake responses, and determining that the buffer unit is not enabled if the first handshake response is less than a preset time or earlier than the second handshake response, otherwise, determining that the buffer unit is enabled.

[0029] in, Figure 4 This invention provides a schematic diagram of information transmission in a chip write task system according to Embodiment 1. The Master and Slave are connected through a write task ID channel, a write address channel, a write data channel, and a write feedback channel; the buffer unit and Slave are connected through a write address channel, a write data channel, and a write feedback channel; and the Master and the buffer unit are connected through a write address channel, a write data channel, and a write feedback channel. The arrows indicate the direction of information flow in each channel.

[0030] It is known that the write task channel is divided into a write task ID channel, a write data channel, a write address channel, and a write feedback channel. These four channels each carry different key information and work together to serve the write task process. Information transmission between channels requires a handshake operation; only after a successful handshake can information be transmitted. Each channel must contain at least three signal lines: Valid, Ready, and Message. Figure 5 A handshake operation diagram is provided for Embodiment 1 of the present invention. Figure 5 In this process, the sending end sends a Valid signal to the receiving end. Upon receiving the Valid signal, the receiving end checks its own status. If it can receive information, it sends a Ready signal to the sending end. If the sending end's Valid signal is valid and it has received the corresponding Ready signal, the handshake is considered successful.

[0031] In this implementation, the Master sends a handshake request to the Slave simultaneously through the write task ID channel, write address channel, and write data channel. The purpose is to initiate a communication interaction to understand the current resource status of the other party, thereby determining whether to enable the buffer unit and ensuring the smooth execution of subsequent write tasks.

[0032] Specifically, after receiving the handshake request from the Master through the write task channel, the Slave immediately performs a comprehensive check of its own resource status. This includes current processing capacity, such as CPU utilization, the number and complexity of tasks currently being executed; available storage resources, such as remaining cache space, the amount of memory available for temporary storage of write task-related data, and bandwidth usage for communication with other components. Preset conditions may include a CPU utilization limit of 70% and a requirement of 10KB of remaining cache space.

[0033] Furthermore, if, after inspection, the Slave finds that its resources meet the preset conditions, it indicates that it has the capacity to process new write tasks. In this case, the Slave will reply with the first handshake response, informing the Master that it can receive and process subsequent write task-related operations. Conversely, if the resources do not meet the preset conditions, the Slave will not reply with a handshake response, essentially conveying to the Master that it is currently unable to process new tasks. Similarly, the resource checking and response principle of the buffer unit based on the handshake request is similar to that of the Slave, and will not be described in detail in this embodiment.

[0034] Specifically, after sending a handshake request, the Master waits for and receives responses from the Slave and the buffer unit, namely the first handshake response and the second handshake response. If the first handshake response is less than a preset time or earlier than the second handshake response, the Master determines not to enable the buffer unit. If the first handshake response is less than the preset time, it indicates that the Slave responded quickly, meaning the Slave currently has sufficient resources and responds rapidly, potentially handling write tasks efficiently without buffer unit intervention, and can directly interact with the Master. Conversely, if the first handshake response is earlier than the second handshake response, it means the Slave is ready to receive write tasks faster than the buffer unit, also implying that in the current situation, the buffer unit is not necessary, and write tasks can be directly passed from the Master to the Slave for processing.

[0035] Conversely, when the first handshake response is greater than or equal to the preset time and the second handshake response is no later than the first handshake response, it indicates that the Slave may be relatively short of resources or respond slowly. In this case, enabling the buffer unit can temporarily store the write task information, which plays a role in buffering and coordination, allowing the system to complete the write task process more smoothly and avoiding data blocking or loss caused by the Slave's inability to process in time.

[0036] In one specific implementation, when the Master initiates a write task and transmits write task information to the buffer unit, the Master's task ID management unit assigns a task ID to the current task and sets the task status to "busy," indicating that the write task is being processed and is in the data transmission and temporary storage phase. After being assigned a write task ID, the Master's write task ID channel sends a WID_Valid signal to the Slave and keeps it high, indicating that the write task ID information is ready. Upon receiving the WID_Valid signal, the Slave checks its own status and, if the reception conditions are met, sends a WID_Ready signal to the Master. Similarly, after being assigned a write task ID and the write address information is ready, the Master's write address channel sends a WAddr_Valid signal to both the Slave and the buffer unit and keeps it high, indicating that the write task address information is ready. Upon receiving the WAddr_Valid signal, the Slave and the buffer unit check their own status and, if the reception conditions are met, each sends a WAddr_Ready signal to the Master. After a write task ID is assigned and the write data is ready, the Master's write data channel sends a WDate_Valid signal to the Slave and the buffer unit, keeping it high and valid, indicating that the write task data is ready. Upon receiving the WDate_Valid signal, the Slave and the buffer unit check their own status; if the reception conditions are met, they each send a WDate_Ready signal to the Master. When the buffer unit is determined to be enabled, the Master sends the write task ID information to the Slave, the write task address information, and the write task data information to the buffer unit. After sending the write task ID information, the Master immediately pulls the WDate_Valid signal low.

[0037] Optionally, after determining the enabling status of the buffer unit through the Master, the method further includes: when it is determined that the buffer unit is not enabled, directly sending write task information to the Slave through the Master.

[0038] When it is determined that the buffer unit is not enabled, it indicates that the system is in good condition based on the current resource status of each component. In this case, it is more efficient to directly transmit write task information between the Master and Slave, without the need for the buffer unit to coordinate data storage and forwarding operations. Figure 6 This invention provides another schematic diagram of information transmission in a chip write task system, as shown in Embodiment 1. Figure 6 It uses three channels: write address channel, write data channel, and write feedback channel. The arrows indicate the direction of information flow in each channel.

[0039] It should be noted that the Master sends write task ID information to the Slave depending on whether the buffer unit is enabled. The Master will only send write task ID information to the Slave when the buffer unit is enabled.

[0040] S120. Store write task information through the buffer unit and send a write task request to the Slave. When the Slave's request feedback is received, send write task information to the Slave.

[0041] Furthermore, to ensure storage security and integrity, the buffer unit also performs some basic verification operations on the written data. For example, it performs a cyclic redundancy check (CRC) on the write task data information.

[0042] First, a suitable CRC generator polynomial can be selected, such as the CRC-32 polynomial: In binary, it is represented as Then, let the task information data sequence be... Its length is Position. Consider it as a sequence of coefficients of a polynomial, for example ,in A value of 0 or 1 indicates the value of the data bit. Then, in the data sequence... Add 32 zeros to the end to get a new data sequence. ,at this time The length is Then use Divide by This can be achieved using shift registers and XOR logic circuits. The specific operation involves... Starting from the highest bit, take 32 bits each time and AND them. Perform an XOR operation. If the highest bit is 1, then AND with... XOR; if the highest bit is 0, no XOR operation is performed, and the next bit of data is shifted into the register. The judgment and operation continue until all bits have been processed. Bit data, the final remainder It is the CRC checksum, which is 32 bits long.

[0043] During CRC verification, after the buffer unit receives information from the Master or the Slave receives information from the buffer unit, it processes the received raw write task information and the accompanying CRC checksum as a whole, and performs CRC calculation on the received data again to obtain the result. The recalculated result With the received CRC checksum The two signals are compared. If they match, the data transmission is correct; if they do not match, an error occurred during transmission. When a data transmission error is detected, the receiving end can send an error signal or a retransmission request signal to the sending end. Upon receiving the signal, the sending end decides whether to retransmit the data based on the specific protocol and strategy. For example, an automatic retransmission request mechanism can be used, whereby the sending end retransmits the write task information after receiving the retransmission request until the receiving end receives it correctly.

[0044] Optionally, after storing the write task information through the buffer unit, the method further includes: feeding back the first write result information to the Master through the buffer unit; and changing the task status from busy to suspended by the Master based on the first write result information.

[0045] In one specific implementation, after receiving the write address information and write data information for the same task ID, the buffer unit sends a WRepo_Valid signal to the Master and keeps it high, indicating that a write task has been completed and is ready to send the specific information of the completed task. After receiving the WRepo_Valid signal, the Master checks its own status. If the receiving conditions are met, it sends a WRepo_Ready signal to the buffer unit, indicating that it is ready to receive the specific information. After receiving the WRepo_Ready signal, the buffer unit immediately sends the specific information of the currently completed write task to the Master.

[0046] Specifically, after receiving the first write result information from the buffer unit, the Master parses it according to the communication protocol specifications. First, it extracts the status code to determine whether the buffer unit's operation of storing the write task information was successful. If the status code indicates successful storage, the Master knows that the write task information has been safely stored in the buffer unit, awaiting further processing by the Slave. However, if the status code indicates problems such as data loss or storage timeout, the Master needs to take corresponding measures, such as resending the write task information to the buffer unit or performing error troubleshooting.

[0047] In addition, the Master will change the task status from busy to suspended based on the first write result. The "suspended" state indicates that the write task is temporarily put on hold, waiting for a suitable time to continue, that is, waiting for the buffer unit to send a write task request to the Slave and successfully transmit the write task information before further processing. At the same time, the Master will release the resources occupied by the corresponding task.

[0048] Optionally, the buffer unit includes: a data buffer, an address buffer, a data manager, and an address manager.

[0049] Optionally, write task information is stored in a buffer unit, including: storing write task data information into a data buffer and managing the data buffer through a data manager; storing write task address information into an address buffer and managing the address buffer through an address manager.

[0050] The data buffer is a dedicated area within the buffer unit for temporarily storing the write data information from the write task information. The address buffer is used to temporarily store the write address information from the write task information.

[0051] Specifically, the data manager is a functional module that effectively manages the data buffer. For example, in data writing, when write data is passed to the buffer unit and prepared to be stored in the data buffer, the data manager determines the specific location in the data buffer to write the new data based on the current storage state of the data buffer, such as the remaining available space and the distribution of stored data. The data manager uses an appropriate storage allocation algorithm. For example, the first-fit algorithm starts searching from the beginning of the data buffer, finds the first free space block that can accommodate the size of the write data, and then stores the data in that space block. In data reading, when the slave is ready to receive write task information and needs to retrieve the corresponding write data from the data buffer, the data manager can quickly locate the corresponding write data based on task identifiers and other relevant clues, accurately read it, and transmit it to the slave. In addition, the data manager is also responsible for maintaining the data stored in the data buffer, such as periodically cleaning up expired data and performing data integrity checks to ensure that the data in the data buffer is always in a correct and usable state.

[0052] Specifically, the address manager, corresponding to the data manager, is a functional module that effectively manages the address buffer. During the write address information storage phase, the address manager arranges the storage location of the write address information based on the structural characteristics of the address buffer and the current storage status. The address manager ensures that the write address information of different write tasks is stored in an orderly manner and maintains a correct association with the corresponding data information in the data buffer. For example, by establishing an address index table, using the task identifier as the index key, it records the storage address of each write task's write address information in the address buffer, facilitating quick lookup and retrieval later. During the address information usage phase, when write task information needs to be sent to the slave, the address manager accurately retrieves the corresponding write address information from the address buffer according to predetermined rules and the task identifier, and matches and combines it with the write data information retrieved from the data buffer. This ensures that the slave receives complete and accurate write task information and can write data into the chip according to the correct address. Simultaneously, the address manager also performs maintenance work such as validity checks on the address information in the address buffer to prevent address errors or confusion, ensuring that the address pointers for the entire write task are accurate.

[0053] S130: The Slave processes and provides feedback on the write task information based on the task ID.

[0054] Optionally, the Slave processes and feeds back the write task information based on the task ID, including: the Slave sequentially determines the target write task from the write task information according to the write task ID; the Slave processes the target write task and generates a second write result information to feed back to the Master and the buffer unit.

[0055] Specifically, when a slave can receive multiple messages from a buffer unit, it will process them in order of the write task IDs received from the master.

[0056] In one specific implementation, after receiving the write address information and write data information for the same task ID, the buffer unit also sends WAddr_Valid and WDate_Valid signals to the Slave simultaneously, keeping them high. Upon receiving the signals, the Slave checks its own status and the write task ID information received from the Master. If the receiving conditions are met, it prioritizes processing the first received write task and sends WAddr_Ready and WDate_Ready signals to the buffer unit. After receiving the WAddr_Ready signal, the buffer unit sends the write task address information to the Slave, and after receiving the WAddr_Ready and WDate_Ready signals, it sends the write task data information to the Slave. After completing a write task, the Slave releases the resources occupied by that task and sends a WRepo_Valid signal to the Master and the buffer unit, keeping it high and valid to indicate that a write task has been completed and is ready to send detailed information about the task completion. Upon receiving WRepo_Valid, the Master checks its own status; if it meets the acceptance conditions, it sends a WRepo_Ready signal to the Slave, indicating it is ready to receive detailed information. Similarly, upon receiving WRepo_Valid, the buffer unit checks its own status; if it meets the acceptance conditions, it sends a WRepo_Ready signal to the Slave, indicating it is ready to receive detailed information. Upon receiving the WRepo_Ready signal, the Slave immediately sends detailed information about the completed write task to either the Master or the buffer unit.

[0057] Optionally, after the Slave processes and responds to the write task information based on the task ID, the method further includes: changing the task status from suspended to available by the Master based on the second write result information; and releasing resources by the buffer unit based on the second write result information.

[0058] After receiving the second write result information from the Slave, the Master parses it to extract key information to determine the actual completion status of the write task. The second write result information may include a status code indicating the write task processing result. For example, a status code of "00" signifies successful task completion, meaning that from the initial write task initiated by the Master, through the buffer unit's temporary coordination, to the Slave's specific processing operations, the entire process proceeded smoothly and achieved the expected goal: the data has been accurately written to the corresponding storage location on the chip. Status codes other than "00," such as "01" and "10," correspond to different types of processing problems, such as abnormal data format conversion or invalid write addresses. In these cases, the Master can take further corrective or exception handling measures.

[0059] Furthermore, once the Master confirms from the second write result information that the task has been successfully processed, it will also change the task status accordingly, changing it from "suspended" to "available". This status change allows the Master to precisely control the lifecycle of each write task, clearly knowing which tasks have been completed and which are still in progress. This enables the Master to rationally allocate system resources and orderly schedule new write tasks into the processing flow according to predetermined task priorities, system load, and other factors, ensuring the efficient and continuous operation of the entire chip write task system.

[0060] Furthermore, when the buffer unit receives the second write result information from the Slave, it will also parse it first. If the status code shows that the task has been successfully completed, it means that the mission of the write task in the entire system has ended, and the various resources occupied in the buffer unit can be released.

[0061] Specifically, the buffer unit can locate and reclaim the buffer space allocated to a task based on the task identifier, according to the previously established resource management records, and mark it as idle so that it can be reused for storage when receiving new write task information. Simultaneously, it clears the memory resources occupied by the resource management control structure related to the task, releasing the corresponding memory space and preventing memory leaks from affecting the performance of the buffer unit and the entire system. Regarding communication link resources, since the write task has been completed, the link bandwidth, communication interfaces, and other resources previously used to coordinate communication for that task can also be released, restoring them to a state available for other tasks. By releasing resources, the buffer unit can ensure the efficient recycling of its own resources, maintaining a good resource reserve to cope with the continuous demands of subsequent write tasks, avoiding system lag and task processing delays due to resource exhaustion, and further improving the overall stability and reliability of the chip write task system.

[0062] In one specific implementation, the Master's tasks include: actively initiating write operations; transmitting the parameters required for the write operation to the Slave / buffer unit, such as address, control signals, and operation type; transmitting the data to be written to the Slave / buffer unit, including documents, multimedia files, and programs; sending relevant control commands to the Slave / buffer unit, such as starting, pausing, and stopping the write operation; managing the storage units related to the write operation, including requesting, allocating, operating, cleaning up, and reclaiming; configuring the working status parameters of the Slave / buffer unit; and configuring the status information of the write task ID.

[0063] In one specific implementation, the Slave's specific tasks include: receiving write operations initiated by the Master / buffer unit; receiving parameters required for the write operation from the Master / buffer unit; receiving control commands related to the write operation from the Master; managing the implementation of the write operation on the Slave side; and sending a signal indicating that the write operation is complete to the Master / buffer unit.

[0064] In one specific implementation, the buffer unit's specific functions include: receiving write operations initiated by the Master; receiving parameters required for the write operation from the Master; receiving control commands related to the write operation from the Master; receiving a write operation completion signal from the Slave; managing the implementation of write operations in the buffer unit; sending a write operation completion signal to the Master; sending a write operation request to the Slave; sending parameters required for the write operation to the Slave; sending data to be written to the Slave; and managing the write operation-related storage units in the buffer unit, including requesting, allocating, operating, cleaning up, and reclaiming them.

[0065] Specific application scenario: When the Master initiates a write operation, it performs a series of necessary processes to ensure that data is correctly written to the storage device. This includes checking permissions, allocating necessary resources (including the allocation of write task IDs), and state management. After the Master is ready, it first sends a handshake request to the Slave / buffer unit through the write task ID channel, write address channel, and write data channel, maintaining the request state until a response is received. After receiving the handshake request, the Slave / buffer unit checks whether its own resources meet the response conditions. If they do, it responds; otherwise, it does not. After receiving the response signal, the Master first determines whether to enable the buffer unit, following these conditions: if the Slave's write address channel handshake is completed within the specified time, or if the specified time has passed but the Slave's write address channel handshake succeeds earlier than the buffer module's write address channel handshake, then the data is written directly from the Master to the Slave; otherwise, it needs to be relayed through the buffer unit. When the buffer unit is disabled, data is written directly from the Master to the Slave. After writing, the Slave destroys its own port's write task ID and sends a write completion signal to the Master via the write feedback channel. Upon receiving the write completion signal, the Master destroys the task and changes the write task ID status to Valid. When data is written to the Slave via the buffer unit, the Master sends the write task ID information to the Slave and releases the write address and write data channel resources occupied by the current task from Master to Slave. The address and data are then written to the buffer unit. After writing, the buffer unit sends a write completion message to the Master. The Master suspends the task and changes the write task ID status to Hang-up. Simultaneously, the buffer unit sends a write request (address and data) to the Slave. After the data is written to the Slave, the Slave sends a write completion signal to both the Master and the buffer unit. Upon receiving this signal, the Master destroys the task and changes the write task ID status to Valid. Upon receiving this signal, the buffer unit clears the space occupied by the task and all configuration information.

[0066] The technical solution of this invention, by determining the activation status of the buffer unit through the Master, can flexibly decide whether to activate the buffer unit according to system requirements, improving the efficiency and flexibility of resource utilization. Transmitting write task information to the buffer unit achieves initial storage and centralized management of information, preparing for subsequent transmission and processing. Processing based on task ID by the Slave enables accurate classification and processing of different write tasks, improving processing accuracy and efficiency. This improves the efficiency, accuracy, and stability of chip write tasks, optimizes system performance, and ensures reliable data writing and processing.

[0067] Example 2 Figure 7 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0068] like Figure 7 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0069] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0070] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as a chip write task method.

[0071] In some embodiments, a chip write task method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the chip write task method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform a chip write task method by any other suitable means (e.g., by means of firmware).

[0072] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0073] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0074] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0075] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0076] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0077] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0078] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0079] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A chip write task method, characterized in that, This method is applied to a chip write task system, which includes a master, a slave, and a buffer unit. The Master determines the activation status of the buffer unit. When the buffer unit is determined to be activated, write task information is generated based on the task ID and task status, and the write task information is transmitted to the buffer unit. The write task information includes write task ID information, write task data information, and write task address information. The write task information is stored in the buffer unit, and a write task request is sent to the Slave. When the Slave's request feedback is received, the write task information is sent to the Slave. The Slave processes the write task information based on the task ID and provides feedback.

2. The method according to claim 1, characterized in that, The process of determining the enabling status of the buffer unit through the Master includes: The Master sends a handshake request to the Slave via the write task channel, which includes a write task ID channel, a write data channel, a write address channel, and a write feedback channel. The Master sends handshake requests to the buffer unit based on the write data channel, write address channel, and write feedback channel. The Slave checks whether its own resources meet the preset conditions based on the handshake request. If they do, it replies with the first handshake response; otherwise, it does not reply. The buffer unit checks whether its own resources meet the preset conditions based on the handshake request. If they do, it replies with a second handshake response; otherwise, it does not reply. The Master receives the first handshake response and the second handshake response. If the first handshake response is less than a preset time or the first handshake response is earlier than the second handshake response, it is determined that the buffer unit is not enabled; otherwise, it is determined that the buffer unit is enabled.

3. The method according to claim 2, characterized in that, After determining the buffer unit's activation status via the Master, the method further includes: When it is determined that the buffer unit is not enabled, write task information is sent directly from the Master to the Slave.

4. The method according to claim 1, characterized in that, After storing the write task information through the buffer unit, the method further includes: The first write result information is fed back to the Master through the buffer unit; The Master changes the task status from busy to suspended based on the first write result information.

5. The method according to claim 1, characterized in that, The process of processing and feeding back the write task information based on the task ID via the Slave includes: The Slave determines the target write task sequentially from the write task information according to the write task ID information; The Slave processes the target write task and generates a second write result message which is then fed back to the Master and the buffer unit.

6. The method according to claim 5, characterized in that, After the Slave processes the write task information based on the task ID and provides feedback, the method further includes: The Master changes the task status from suspended to available based on the second write result information. The buffer unit releases resources based on the second write result information.

7. The method according to claim 1, characterized in that, The buffer unit includes: a data buffer, an address buffer, a data manager, and an address manager.

8. The method according to claim 7, characterized in that, The step of storing the write task information through a buffer unit includes: The write task data information is stored in a data buffer, and the data buffer is managed by a data manager. The write task address information is stored in the address buffer, and the address buffer is managed by the address manager.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

10. A computer storage medium, characterized in that, The computer storage medium stores computer instructions that are used to cause a processor to execute the method of any one of claims 1-8.

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